Array substrate, display panel, preparation method of array substrate and display device

Abstract

The application provides an array substrate, a display panel and a preparation method thereof, and a display device. The array substrate comprises a substrate and a plurality of conductor layers which are arranged on one side of the substrate in a stacked manner, and conductor structures are arranged in the plurality of conductor layers. The array substrate has a first area and a second area. The area of the first area in the orthographic projection of the substrate is equal to the area of the second area in the orthographic projection of the substrate. In the first direction, the distance between the center of the array substrate and the second area is greater than the distance between the center of the array substrate and the first area, and the first direction is parallel to the plane in which the substrate is located. The area of the conductor structures in the orthographic projection of the substrate in the second area is greater than the area of the conductor structures in the orthographic projection of the substrate in the first area. The embodiments of the application can reduce the actual temperature difference of the array substrate at the first area and the second area, so that the actual temperatures at the first area and the second area are the same or similar, thereby improving the bonding yield and quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display devices, in particular to an array substrate, a display panel and a preparation method therefor, and a display device. BACKGROUND

[0002] With the continuous development of micro light emitting diode (Micro LED) technology, Micro LED is increasingly applied to display devices. Laser bonding is one of the main bonding methods for Micro LED, and one of the basic processes is to align and press a temporary substrate on which Micro LED chips are arranged to a corresponding position on a substrate, and then heat the substrate by laser irradiation to electrically connect the Micro LED and the substrate. On this basis, how to improve the bonding yield of Micro LED has become the research direction of many manufacturers. SUMMARY

[0003] Embodiments of the present application provide an array substrate, a display panel and a preparation method therefor, and a display device, which can improve the bonding yield.

[0004] In a first aspect, embodiments of the present application provide an array substrate, which includes a substrate and a plurality of conductor layers stacked on one side of the substrate, and conductor structures are arranged in the plurality of conductor layers.

[0005] The array substrate has a first region and a second region, the first region has a projection area on the substrate equal to the projection area of the second region on the substrate, and the distance between the center of the array substrate and the second region is greater than the distance between the center of the array substrate and the first region along a first direction parallel to the plane on which the substrate is located. The projection area of the conductor structures in the second region on the substrate is greater than the projection area of the conductor structures in the first region on the substrate.

[0006] In a second aspect, embodiments of the present application provide a display panel, which includes the array substrate of any of the preceding embodiments and a plurality of light emitting elements, part of the light emitting elements are bonded to the first region of the array substrate, and part of the light emitting elements are bonded to the second region of the array substrate.

[0007] In a third aspect, embodiments of the present application provide a display device, which includes the display panel of any of the preceding embodiments.

[0008] In a fourth aspect, embodiments of the present application provide a preparation method of a display panel, which includes:

[0009] providing the array substrate and the light emitting elements of any of the preceding embodiments;

[0010] The light emitting element is arranged on one side of the array substrate, and a moving laser source is used to irradiate the light emitting element and the array substrate to bond and fix the light emitting element and the array substrate, and the moving laser source moves along a third direction, and the first direction and the third direction intersect and are both parallel to the plane where the substrate is located.

[0011] In a fifth aspect, the embodiments of the present application provide a preparation method of a display panel, comprising:

[0012] The array substrate and the light emitting element in any of the foregoing embodiments are provided.

[0013] The light emitting element is arranged on one side of the array substrate, and a fixed laser source is used to irradiate the light emitting element and the array substrate to bond and fix the light emitting element and the array substrate, and the fixed laser source is focused on the center of the array substrate.

[0014] The embodiments of the present application provide an array substrate, a display panel, a preparation method of the display panel, and a display device. The structure layout of the conductor structure in the first region and the second region is adjusted, so that the conductor structure in the second region has a larger normal projection area on the substrate than the conductor structure in the first region. The normal projection area of the conductor structure at a specific region is often positively correlated with the absorption capacity of the array substrate at the region for external heat. In other words, the second region of the array substrate has a stronger heat absorption capacity than the first region. On this basis, even if the bonding temperature at the second region is lower than the bonding temperature at the first region, the actual temperature difference of the array substrate at the first region and the second region can be reduced due to the stronger heat absorption capacity at the second region, so that the actual temperatures at the first region and the second region can be the same or similar, thereby improving the bonding yield and quality. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced. For those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0016] Figure 1 is a schematic diagram of the corresponding relationship between an array substrate and a line light spot laser provided by the embodiments of the present application;

[0017] Figure 2 is another schematic diagram of the corresponding relationship between an array substrate and a line light spot laser provided by the embodiments of the present application;

[0018] Figure 3 is a schematic diagram of the corresponding structure of the conductor structure in the first region of an array substrate provided by the embodiments of the present application;

[0019] Figure 4is a structure schematic diagram of a conductor structure in a second area of an array substrate provided by an embodiment of the present application;

[0020] Figure 5 is Figure 3 is a sectional structure schematic diagram at A-A in the array substrate;

[0021] Figure 6 is Figure 4 is a sectional structure schematic diagram at B-B in the array substrate;

[0022] Figure 7 is a sectional structure schematic diagram of a display panel provided by an embodiment of the present application;

[0023] Figure 8 is a structure schematic diagram of a first conductor layer in a first area of an array substrate provided by an embodiment of the present application;

[0024] Figure 9 is a structure schematic diagram of a first conductor layer in a second area of an array substrate provided by an embodiment of the present application;

[0025] Figure 10 is a structure schematic diagram of a first conductor layer in a first area of an array substrate provided by an embodiment of the present application;

[0026] Figure 11 is a structure schematic diagram of a first conductor layer in a first area of an array substrate provided by an embodiment of the present application;

[0027] Figure 12 is a structure schematic diagram of a first conductor layer in a first area of an array substrate provided by an embodiment of the present application;

[0028] Figure 13 is a sectional structure schematic diagram of an array substrate in a first area provided by an embodiment of the present application;

[0029] Figure 14 is a sectional structure schematic diagram of an array substrate in a second area provided by an embodiment of the present application;

[0030] Figure 15 is a structure schematic diagram of a first conductor layer in a first area of an array substrate provided by an embodiment of the present application;

[0031] Figure 16 is a structure schematic diagram of a first conductor layer in a second area of an array substrate provided by an embodiment of the present application;

[0032] Figure 17 is a structure schematic diagram of a first conductor layer in a second area of an array substrate provided by an embodiment of the present application;

[0033] Figure 18 is a structure schematic diagram of a first conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0034] Figure 19 is a structure schematic diagram of a first conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0035] Figure 20 is a structure schematic diagram of a first conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0036] Figure 21 is a structure schematic diagram of a first conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0037] Figure 22 is a structure schematic diagram of a first conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0038] Figure 23 is a structure schematic diagram of a first conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0039] Figure 24 is a structure schematic diagram of a third conductor layer in an array substrate provided by an embodiment of the present application;

[0040] Figure 25 is a structure schematic diagram of a fourth conductor layer and a fifth conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0041] Figure 26 is a structure schematic diagram of a fourth conductor layer and a fifth conductor layer in a second region of an array substrate provided by an embodiment of the present application;

[0042] Figure 27 is a structure schematic diagram of a fourth conductor layer and a fifth conductor layer in a first region of an array substrate provided by an embodiment of the present application;

[0043] Figure 28 is a structure schematic diagram of an array substrate provided by an embodiment of the present application;

[0044] Figure 29 is a structure schematic diagram of a conductor structure in a third region of an array substrate provided by an embodiment of the present application;

[0045] Figure 30 is a structure schematic diagram of an array substrate provided by an embodiment of the present application;

[0046] Figure 31 is a structure schematic diagram of a conductor structure in a fourth region of an array substrate provided by an embodiment of the present application;

[0047] Figure 32 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

[0048] Figure 33 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0049] Figure 34 is a schematic structural diagram of another display panel provided by an embodiment of the present application;

[0050] Figure 35 is a schematic structural diagram of a display device provided by an embodiment of the present application;

[0051] Figure 36 is a schematic structural diagram of another display device provided by an embodiment of the present application;

[0052] Figure 37 is a flowchart of a preparation method of a display panel provided by an embodiment of the present application;

[0053] Figure 38 is a flowchart of another preparation method of a display panel provided by an embodiment of the present application.

[0054] Labeling description:

[0055] 100, array substrate; 200, display panel; 300, display device;

[0056] 10, substrate;

[0057] 20, conductor layer; 21, conductor structure; 22, first conductor layer; 221, first conductive part; 2211, first part; 222, second conductive part; 2221, second part; 2222, third part; 223, hollow part; 224, first power supply structure; 225, first pad; 226, second pad; 23, second conductor layer; 24, third conductor layer; 241, hollow structure; 25, fourth conductor layer; 251, third conductive part; 26, fifth conductor layer; 261, fourth conductive part;

[0058] 30, active layer;

[0059] 40, light emitting element;

[0060] 50, laser;

[0061] D1, first sub-section; D2, second sub-section; D3, main section structure; D4, branch section structure;

[0062] T, thin film transistor; T1, first electrode; T2, second electrode; T3, control end;

[0063] W1, first hole; W2, second hole;

[0064] A1, first area; A2, second area; A3, third area; A4, fourth area; A5, fifth area; A6, sixth area; A7, seventh area;

[0065] C1, center of array substrate; C2, center of first area; C3, center of second area; C4, center of third area; C5, center of fourth area; C6, center of fifth area;

[0066] X, first direction; Y, second direction; Z, thickness direction; M, third direction. DETAILED DESCRIPTION

[0067] In order to make the purposes, technical solutions and advantages of the present application clearer, the following further describes the present application in detail with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of the specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0068] It should be noted that, in this document, relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the listed element.

[0069] Laser bonding is one of the main bonding methods for Micro LED, one of the basic processes is to align and press the temporary substrate with the arranged Micro LED to the corresponding position of the substrate, then heat the metal traces, pads, bonding layer and pads on the Micro LED on the substrate by laser irradiation, so that the metal on the bonding layer of the substrate pad melts, thereby realizing the connection between the Micro LED and the substrate.

[0070] The current laser bonding mode includes three modes of point spot bonding, surface spot bonding and line spot bonding. Among them, the bonding efficiency corresponding to the point spot bonding is poor, and the bonding efficiency corresponding to the line spot bonding and the surface spot bonding is high. However, for the line spot bonding and the surface spot bonding, when the laser is irradiated, the bonding temperature of the center region of the spot is often higher than that of the edge region, thereby causing the Micro LED at the edge region to have the risk of poor bonding. Specifically, for the line spot bonding, the laser will pass through the substrate along a certain scanning direction, and at the two edge regions in the direction intersecting the scanning direction, there is a problem of poor bonding of the Micro LED. And for the surface spot bonding, there may be a problem of poor bonding of the Micro LED at the edge region around the substrate.

[0071] Further, for the Micro LED, the suitable bonding temperature is within a certain range, and if the bonding strength is increased to increase the bonding temperature, the risk of abnormal bonding or substrate damage at the center region of the spot is easy to occur, so how to improve the bonding yield without damaging the substrate is the problem that needs to be focused on at present.

[0072] In view of the above problems, in a first aspect, referring to Figures 1 to 7 The array substrate 100 includes a substrate 10 and a plurality of conductor layers 20 stacked on one side of the substrate 10, and the plurality of conductor layers 20 are provided with conductor structures 21.

[0073] The array substrate 100 has a first area A1 and a second area A2, the first area A1 has a projection area on the substrate 10 equal to the projection area of the second area A2 on the substrate 10, and along the first direction X, the distance between the center C1 of the array substrate 100 and the second area A2 is greater than the distance between the center C1 of the array substrate 100 and the first area A1, and the first direction X is parallel to the plane where the substrate 10 is located. Among them, the conductor structure 21 located in the second area A2 has a projection area on the substrate 10 greater than the projection area of the conductor structure 21 in the first area A1 on the substrate 10.

[0074] The array substrate 100 is used for subsequent formation of a display panel 200, and the light emitting element 40 can be fixed on the array substrate 100 by means of laser bonding, and driven to emit light through the array substrate 100. Among them, the array substrate 100 is provided with a plurality of conductors and semiconductor structures, and the plurality of conductors and semiconductor structures 21 can collectively form a circuit structure to meet the different needs of the display panel 200. Optionally, part of the conductors and semiconductor structures in the array substrate 100 can be used to form a pixel circuit, and the light emitting element 40 is provided with an electrode, and the pixel circuit is electrically connected to the electrode to realize control of whether the light emitting element 40 emits light or not.

[0075] The first area A1 and the second area A2 are two different areas on the array substrate 100, and the first area A1 and the second area A2 have the same area in the orthographic projection of the substrate 10. The first area A1 and the second area A2 can have various shapes, for example, the orthographic projection of the first area A1 and the second area A2 on the substrate 10 can be regular or irregular shapes such as a circle or a square, or the orthographic projection shapes of the first area A1 and the second area A2 on the substrate 10 can be different, and the embodiments of the present application do not limit this as long as the orthographic projection areas of the two on the substrate 10 remain the same. Among them, Figure 1 and Figure 2 The case where the orthographic projection of the first area A1 and the second area A2 on the substrate 10 is a square is shown in FIG.

[0076] In the first direction X, the distance between the center C1 of the array substrate 100 and the second area A2 is greater than the distance between the center C1 of the array substrate 100 and the first area A1. Specifically, the distance L2 between the center of the second area A2 and the center C1 of the array substrate 100 in the first direction X is greater than the distance L1 between the center C2 of the first area A1 and the center C1 of the array substrate 100 in the first direction X. The center C2 of the first area A1 can coincide with the center C1 of the array substrate 100 in the first direction X, and in this case, the distance L1 between the center C2 of the first area A1 and the center C1 of the array substrate 100 in the first direction X is the distance of the connecting line between the two. Or the center C2 of the first area A1 and the center C1 of the array substrate 100 can not overlap in the first direction X, and in this case, the distance L1 between the center C2 of the first area A1 and the center C1 of the array substrate 100 in the first direction X is less than the distance of the connecting line between the two. The distance L2 between the center C3 of the second area A2 and the center C1 of the array substrate 100 in the first direction X is the same, and the embodiments of the present application will not be described again. Among them, Figure 1 The case where the center C3 of the second area A2 and the center C1 of the array substrate 100 overlap in the first direction X is shown in FIG. Figure 2 The case where the center C3 of the second area A2 and the center C1 of the array substrate 100 do not overlap in the first direction X is shown in FIG.

[0077] It should be noted that due to the influence of factors such as the shape of the array substrate 100 itself and the difference in local structure, the "center of the array substrate 100" mentioned here is not necessarily the exact center position of the array substrate 100, and there can be a certain deviation, and the center of the first area A1 and the center of the second area A2 are the same. And the first area A1 and the second area A2 can have various positional relationships with respect to the center C1 of the array substrate 100, for example, as shown in Figure 1 The orthographic projection of the center C1 of the array substrate 100 on the substrate 10 can be located within the orthographic projection of the first area A1 on the substrate 10, or as Figure 2As shown, the center C1 of the array substrate 100 in the orthographic projection of the substrate 10 is located outside the orthographic projection of the first area A1 and the second area A2 on the substrate 10. Further, when the center C1 of the array substrate 100 in the orthographic projection of the substrate 10 is located outside the orthographic projection of the first area A1 and the second area A2 on the substrate 10, the first area A1 and the second area A2 can be located on the same side of the center C1 of the array substrate 100 along the first direction X, or can also be located on different sides.

[0078] In addition, the first direction X is a direction parallel to the plane on which the substrate 10 is located, and the first direction X has various forms according to different bonding methods. For example, if the line spot bonding method is adopted, the first direction X is a direction intersecting the laser scanning direction, and further optionally, the first direction X is perpendicular to the laser scanning direction. If the surface spot bonding method is adopted, the first direction X can be any direction parallel to the plane on which the substrate 10 is located. Among them, Figure 1 and Figure 2 The case of line spot bonding is shown in FIGS. 1A and 1B, and the scanning direction of the laser 50 is the third direction M, and the first direction X is perpendicular to the third direction M.

[0079] The array substrate 100 includes a plurality of film layer structures stacked, and the substrate 10 is a film layer in the array substrate 100 for supporting, and other film layers are stacked on one side of the substrate 10. Here, the stacked refers to that the other film layers are stacked along the thickness direction Z of the substrate 10. Among them, the thickness direction Z of the substrate 10 is usually parallel to the thickness direction Z of the other film layers in the array substrate 100, so in order to facilitate the illustration, the thickness direction Z of each film layer is represented by the same direction in the drawings of the embodiments of the present application.

[0080] The substrate 10 is provided with a plurality of conductor layers 20, each of which is provided with a conductor, and an insulating layer is provided between adjacent conductor layers 20. Among them, the conductors in different conductor layers 20 can have the same or different material composition. The plurality of conductor layers 20 are provided with a conductor structure 21. Here, the plurality of conductor layers 20 can be all the conductor layers 20 in the array substrate 100, or can be part of the conductor layers 20 in the array substrate 100. Further, the conductor structure 21 referred to here refers to the set of conductors in the plurality of conductor layers 20. Among them, Figure 3 and Figure 4 respectively show the corresponding top view structure schematic diagram of the conductor structure 21 in the first area A1 and the second area A2, and Figure 5 and Figure 6 are cross-sectional structure schematic diagrams corresponding to Figure 3 and Figure 4 In Figures 3 to 6 , the conductors in different conductor layers 20 are schematically shown by different cross-sectional lines, and the different conductors in the same conductor layer are schematically shown by the same cross-sectional line.

[0081] The conductor structure 21 located in the second region A2 and the conductor structure 21 located in the first region A1 both have corresponding orthographic projection areas on the substrate 10. Taking the conductor structure 21 in the second region A2 as an example, when calculating its corresponding orthographic projection area, the total orthographic projection area of ​​the portion of the conductor structure 21 in the second region A2 on the substrate 10 is calculated. For the overlapping portions of the conductors in the conductor structures 21, the orthographic projection area generated by the overlap is not calculated repeatedly when calculating the orthographic projection area. The orthographic projection area corresponding to the conductor structure 21 in the first region A1 is calculated in the same way, and will not be described again in the embodiments of this application.

[0082] Based on the foregoing, for both line spot bonding and area spot bonding, the bonding temperature near the center C1 region of the array substrate 100 is generally higher than that further away from the center C1 region. Within the array substrate 100, the first region A1 is closer to the center C1 in the first direction X than the second region A2. Therefore, during the bonding process, the bonding temperature in the second region A2 is generally lower than that in the first region A1. Here, the bonding temperature refers to the irradiation temperature of the laser 50 at a specific region during the bonding process, indicating an inherent characteristic of the laser 50 during irradiation.

[0083] Therefore, this application embodiment adjusts the structural layout of the conductor structure 21 in the first region A1 and the second region A2, such that the projected area of ​​the conductor structure 21 in the second region A2 on the substrate 10 is larger than that of the conductor structure 21 in the first region A1. The projected area of ​​the conductor structure 21 in a specific region is often positively correlated with the heat absorption capacity of the array substrate 100 in that region. In other words, the second region A2 of the array substrate 100 has a stronger heat absorption capacity than the first region A1. Based on this, even if the bonding temperature in the second region A2 is lower than that in the first region A1, the stronger heat absorption capacity of the second region A2 reduces the actual temperature difference between the array substrate 100 in the first region A1 and the second region A2, allowing the actual temperatures in the first region A1 and the second region A2 to be the same or similar, thereby improving bonding yield and quality.

[0084] It should be noted that the actual temperature mentioned here refers to the real temperature of the array substrate 100 in a specific region during the bonding process, which is the temperature state of the array substrate 100. The specific layout of the conductor structure 21 in the first region A1 and the second region A2 is not limited in this embodiment. For example, the conductor size of a single conductor layer 20 in the second region A2 can be increased, thereby making the projected area of ​​the conductor structure 21 in the second region A2 on the substrate 10 larger than the projected area of ​​the conductor structure 21 in the first region A1 on the substrate 10. Alternatively, the conductor size of multiple conductor layers 20 in the second region A2 can be increased, or the size of the overlapping portion of different conductor layers 20 in the second region A2 can be reduced, or an additional conductor layer 20 can be added to the array substrate 100, thereby increasing the projected area of ​​the conductor structure 21 in the second region A2 on the substrate 10.

[0085] Furthermore, considering the characteristic that the bonding temperature decreases from the center region to the edge region, in some optional embodiments, the projected area of ​​the conductor structure 21 in a unit region can gradually increase in the direction from the center C2 of the first region A1 to the center C3 of the second region A2. This makes the layout of the conductor structure 21 more compatible with the trend of bonding temperature change, thereby further improving the bonding yield and quality.

[0086] In some embodiments, such as Figures 3 to 6 As shown, the plurality of conductor layers 20 include a first conductor layer 22, the first conductor layer 22 includes a first conductive portion 221 located in a first region A1 and a second conductive portion 222 located in a second region A2, the projected area of ​​the second conductive portion 222 on the substrate 10 is greater than the projected area of ​​the first conductive portion 221 on the substrate 10.

[0087] The first conductor layer 22 is one of a plurality of conductor layers 20. The specific positional relationship of the first conductor layer 22 relative to the other conductor layers 20 is not limited in the embodiments of this application. For example, the first conductor layer 22 may be a conductor layer 20 that is relatively close to the substrate 10, or the first conductor layer 22 may be a conductor layer 20 that is relatively far away from the substrate 10.

[0088] The first conductive part 221 is a conductor in the first conductor layer 22 at the first area A1, and the second conductive part 222 is a conductor in the second conductor layer 23 at the second area A2. The first conductive part 221 can include only one continuous conductor, or can include multiple conductors arranged at intervals, depending on the area covered by the first area A1, the size of a single conductor in the first conductive part 221, and the size of the spacing between adjacent conductors, and the like, and embodiments of the present application do not limit this. The same applies to the second conductive part 222. Among them, Figure 5 and Figure 6 The case where the first conductive part 221 includes multiple conductors and the second conductive part 222 includes multiple conductors is shown in FIGS.

[0089] On this basis, at least part of the first conductive part 221 and at least part of the second conductive part 222 can be different components in the same continuous conductor, or the first conductive part 221 and the second conductive part 222 can be completely spaced apart. At least one of the first conductive part 221 and the second conductive part 222 can be used to transmit a specific signal, or at least one of the two can have no potential signal inside. Further, when the first conductive part 221 and the second conductive part 222 are both used to transmit a specific signal, at least part of the structure in the two can be arranged to be electrically connected to each other, or at least part of the structure in the two can be arranged to be insulated from each other, and embodiments of the present application do not limit this.

[0090] The second conductive part 222 has a larger area in the orthographic projection on the substrate 10 than the first conductive part 221. The orthographic projection area corresponding to the second conductive part 222 can have multiple adjustment methods, for example, the extension length of a single or multiple conductors in the second conductive part 222 can be increased, or the width of the second conductive part 222 at at least some positions can be increased, or the number of conductors in the second conductive part 222 can be increased.

[0091] In embodiments of the present application, the size or layout of the second conductive part 222 in the first conductor layer 22 can be changed, that is, the structure of the conductor structure 21 in the second area A2 is adjusted to have a larger area in the orthographic projection on the substrate 10 than the conductor structure 21 in the first area A1, so as to reduce the actual temperature difference between the first area A1 and the second area A2 of the array substrate, and improve the bonding yield and quality.

[0092] It should be noted that, according to different actual needs, only the size and number of conductors in the first conductor layer 22 can be adjusted, and the size and number of conductors in other conductor layers 20 are not adjusted. Of course, in other embodiments, the size and number of conductors in the first conductor layer 22 and other conductor layers 20 can be adjusted at the same time, and the embodiments of the present application do not limit this.

[0093] In some embodiments, as shown in Figure 5 and Figure 6 The array substrate includes an active layer 30, and the first conductor layer 22 is located on the side of the active layer 30 away from the substrate 10.

[0094] The active layer 30 is a film layer including a semiconductor structure in the array substrate. For example, the array substrate can include a thin film transistor T, which includes a first electrode T1, a second electrode T2, and a control terminal T3. The control terminal T3 is used to control whether the first electrode T1 and the second electrode T2 are turned on, and the control terminal T3 is arranged in the orthographic projection of the active layer 30 on the substrate 10.

[0095] The first conductor layer 22 is located on the side of the active layer 30 away from the substrate 10. The first conductor layer 22 can have various positions. For example, the control terminal T3 in the thin film transistor T can be located in the first conductor layer 22, or the first electrode T1 and the second electrode T2 in the thin film transistor T can be located in the first conductor layer 22, or the first conductor layer 22 can be located on the side of the first electrode T1 away from the substrate 10 in the thickness direction Z, or the first conductor layer 22 can be located between the first electrode T1 and the control terminal T3 in the thickness direction Z. Among them, Figure 4 and Figure 5 The first conductor layer 22 is located on the side of the first electrode T1 away from the substrate 10 in the thickness direction Z.

[0096] Generally, in the thickness direction Z, the closer the conductor layer 20 is to the light emitting element, the stronger the absorption ability of the conductor layer 20 to the heat generated by the bonding process. In other words, the closer the conductor layer 20 is to the light emitting element, the greater the influence of the conductor layer 20 on the bonding effect. In view of this, the first conductor layer 22 is arranged on the side of the active layer 30 away from the substrate 10, that is, the first conductor layer 22 can be closer to the light emitting element relative to the active layer 30. On this basis, by adjusting the orthographic projection area of the first conductive part 221 and the second conductive part 222 in the first conductor layer 22, the actual temperature difference and the corresponding bonding difference at the first area A1 and the second area A2 are reduced, and the bonding yield and quality are improved.

[0097] In some embodiments, as shown in Figure 5 and Figure 6As shown, the plurality of conductor layers 20 further comprises a second conductor layer 23, which is located between the first conductor layer 22 and the active layer 30.

[0098] The second conductor layer 23 is one of the plurality of conductor layers 20 other than the first conductor layer 22, and the first conductor layer 22 is located on the side of the second conductor layer 23 away from the substrate 10. The first conductor layer 22 and the second conductor layer 23 can have various forms. For example, the second conductor layer 23 is the film layer in which the control terminal T3 of the thin film transistor T is located. In this case, the first conductor layer 22 can be the film layer in which the first electrode T1 and the second electrode T2 are located, or the film layer on the side of the first electrode away from the substrate 10. Alternatively, the array substrate can include a storage capacitor (not shown in the figure), one of the plates of the storage capacitor is located in the second conductor layer 23 together with the control terminal, and the other plate is located in the first conductor layer 22.

[0099] The first conductor layer 22 can be closer to the light emitting element relative to the second conductor layer 23. Further, the first conductor layer 22 has a greater influence on the bonding effect of the light emitting element relative to the second conductor layer 23. On this basis, the embodiments of the present application further reduce the actual temperature difference and the corresponding bonding difference at the first region A1 and the second region A2 by adjusting the corresponding orthographic projection areas of the first conductive part 221 and the second conductive part 222 in the first conductor layer 22, thereby improving the bonding yield and quality.

[0100] It should be noted that, for the second conductor layer 23, the corresponding orthographic projection area of the second conductor layer 23 at the first region A1 can be greater than, less than, or equal to the corresponding orthographic projection area of the second conductor layer 23 at the second region A2, according to different actual needs. That is, in the embodiments of the present application, in order to improve the bonding yield at the second region A2, at least the conductors in the first conductor layer 22 need to be adjusted, and the conductors in the second conductor layer 23 can be selected to be adjusted or not to be changed corresponding to the first region A1 and the second region A2.

[0101] In some embodiments, the first conductive part 221 and the second conductive part 222 both transmit a power supply signal.

[0102] The power supply signal is a constant voltage, and the power supply signal can include a PVDD signal and a PVEE signal. Illustratively, the array substrate 100 can further include a plurality of pixel circuits, which are circuit structures for controlling the light emitting element 40 in the array substrate 100, wherein the light emitting element 40 is provided with two electrodes, the PVDD signal can be electrically connected to the pixel circuit, the pixel circuit is electrically connected to one of the electrodes of the light emitting element 40, and the PVEE signal is electrically connected to the other electrode of the light emitting element 40.

[0103] On this basis, the first conductive part 221 and the second conductive part 222 can be used to transmit the PVDD signal, or the first conductive part 221 and the second conductive part 222 are used to transmit the PVEE signal, or one of the first conductive part 221 and the second conductive part 222 is used to transmit the PVDD signal, and the other is used to transmit the PVEE signal. Or at least one of the first conductive part 221 and the second conductive part 222 can also be partially used to transmit the PVDD signal and partially used to transmit the PVEE signal. In other words, the type of power signal corresponding to the transmission of the first conductive part 221 and the second conductive part 222 depends mainly on the size, shape and position of the first area A1 and the second area A2 and other factors. The embodiments of the present application do not limit this. Among them, Figure 5 and Figure 6 It is shown that the first conductive part 221 and the second conductive part 222 are partially used to transmit the PVDD signal and partially used to transmit the PVEE signal.

[0104] In the embodiments of the present application, the first conductive part 221 and the second conductive part 222 transmit the power signal, and in order to meet the transmission needs of the power signal, the first conductive part 221 and the second conductive part 222 need to be arranged at a position close to the light emitting element 40. On this basis, by increasing the size of the second conductive part 222, the second conductive part 222 is greater than the first conductive part 221 in the area of the substrate 10, thereby helping to further improve the actual temperature of the array substrate at the second area A2, and improve the bonding yield and quality at the second area A2.

[0105] In some embodiments, please refer to Figure 8 and Figure 9 The first conductor layer 22 is a planar structure.

[0106] It should be noted that the planar structure mentioned here refers to the orthographic projection of the first conductor layer 22 on the substrate can cover most of the area in the first conductor layer 22. For example, the orthographic projection of the first conductor layer 22 on the substrate covers 50% or more of the area in the substrate.

[0107] In the embodiments of the present application, the first conductor layer 22 is a planar structure, on this basis, the different structures of the first conductor layer 22 in the first area A1 and the second area A2 can be designed differently, so that the second conductive part 222 is greater than the first conductive part 221 in the area of the substrate, thereby improving the bonding yield and quality.

[0108] It should be noted that the specific manner of the difference design of the first conductor layer 22 corresponding to the first area A1 and the second area A2 is not limited in the embodiments of the present application. Exemplarily, taking the example that the first conductive part 221 and the second conductive part 222 both transmit the power supply signal, in order to meet the transmission needs of the PVDD signal and the PVEE signal in the first conductor layer 22, the first conductor layer 22 at least includes a plurality of conductors arranged in insulation with each other, and on this basis, the size of the spacing between the two conductors can be adjusted for the first area A1 and the second area A2, so that the second conductive part 222 has a larger area of the orthographic projection on the substrate 10 than the first conductive part 221, or by providing a hole structure on at least one of the two conductors, the second conductive part 222 can also have a larger area of the orthographic projection on the substrate 10 than the first conductive part 221.

[0109] In some embodiments, as shown in Figure 8 and Figure 9 The first conductor layer 22 is provided with a hollow part 223, and the hollow part 223 is at least partially located in the first area A1.

[0110] The hollow part 223 is a hollow structure formed by patterning of the first conductor layer 22, and the hollow part 223 is arranged through the first conductor layer 22 along the thickness direction. The hollow part 223 has a plurality of forms, taking the example that the first conductor layer 22 includes a plurality of conductors arranged in insulation with each other, at least part of the hollow part 223 can be a gap space between the two conductors, or at least part of the hollow part 223 can also be a hole structure arranged on any one of the two conductors.

[0111] The hollow part 223 can have a plurality of position forms, for example, the hollow part 223 is at least partially located in the first area A1, and the second area A2 is free of the hollow part 223, that is, the first conductor layer 22 is in a complete and continuous structure at the first area A1. Or the hollow part 223 can be partially located in the first area A1 and partially located in the second area A2, as long as the hollow part 223 is at least partially located in the first area A1. Among them, Figure 8 and Figure 9 It is shown that the hollow part 223 is partially located in the first area A1 and partially located in the second area A2, and the corresponding orthographic projection size of the hollow part 223 at the first area A1 is greater than the corresponding orthographic projection size of the hollow part 223 at the second area A2.

[0112] In the embodiments of the present application, the hollow parts 223 are at least partially located in the first area A1, and the total area of the orthographic projection of all the hollow parts 223 in at least one of the first area A1 and the second area A2 on the substrate is adjusted, so as to adjust the orthographic projection area of at least one of the first conductive part 221 and the second conductive part 222 on the substrate, so that the orthographic projection area of the second conductive part 222 on the substrate is greater than the orthographic projection area of the first conductive part 221 on the substrate, which has strong flexibility and practicality.

[0113] In some embodiments, referring to Figures 8 to 10 , the number of hollow parts 223 in the first area A1 is greater than the number of hollow parts 223 in the second area A2; and / or, the orthographic projection area of the hollow parts 223 in the first area A1 on the substrate is greater than the orthographic projection area of the hollow parts 223 in the second area A2 on the substrate.

[0114] According to different actual needs, the number of hollow parts 223 can be multiple, and at least part of the multiple hollow parts 223 are arranged in the first area A1. On this basis, as shown in Figure 9 and Figure 10 , the number of hollow parts 223 in the first area A1 is greater than the number of hollow parts 223 in the second area A2, so that the total area of the orthographic projection of all the hollow parts 223 in the first area A1 on the substrate is greater than the total area of the orthographic projection of all the hollow parts 223 in the second area A2 on the substrate, so as to realize that the orthographic projection area of the second conductive part 222 on the substrate is greater than the orthographic projection area of the first conductive part 221 on the substrate.

[0115] It should be noted that the second area A2 can be provided with hollow parts 223, or can not be provided with hollow parts 223. When the second area A2 is not provided with hollow parts 223, the number of hollow parts 223 in the second area A2 is 0.

[0116] As shown in Figure 8 and Figure 9 , in addition to adjusting the number of hollow parts 223 distributed in different areas, the size of a single hollow part 223 in different areas can also be adjusted, so that the orthographic projection area of a single hollow part 223 in the first area A1 on the substrate is greater than the orthographic projection area of a single hollow part 223 in the second area A2 on the substrate, so as to also realize that the orthographic projection area of the second conductive part 222 on the substrate is greater than the orthographic projection area of the first conductive part 221 on the substrate.

[0117] Of course, in some other embodiments, the number of the hollowed parts 223 in the first area A1 can be adjusted to be greater than the number of the hollowed parts 223 in the second area A2, while the area of the orthographic projection of the hollowed parts 223 in the first area A1 on the substrate is set to be greater than the area of the orthographic projection of the hollowed parts 223 in the second area A2 on the substrate, which helps to further increase the difference between the area of the orthographic projection of the second conductive part 222 on the substrate and the area of the orthographic projection of the first conductive part 221 on the substrate.

[0118] In the embodiments of the present application, the number of the hollowed parts 223 in different areas can be selectively adjusted, and the size of the single hollowed part 223 in different areas can also be selectively adjusted, so as to realize that the area of the orthographic projection of the second conductive part 222 on the substrate is greater than the area of the orthographic projection of the first conductive part 221 on the substrate, thereby improving the bonding yield and quality, and having strong practicability and flexibility.

[0119] In some embodiments, the first conductor layer 22 comprises a first power supply structure 224, which is used to provide a first power supply voltage.

[0120] The first power supply structure 224 is a conductor used to provide a first power supply voltage. Optionally, as shown in Figures 8 to 10 , the first power supply structure 224 is used to transmit a PVDD signal. Alternatively, as shown in Figure 11 , the first power supply structure 224 can also be used to transmit a PVEE signal. Further, the first power supply structure 224 has a planar structure, so the first conductive part 221 can comprise part of the first power supply structure 224, and the second conductive part 222 can also comprise part of the first power supply structure 224.

[0121] On this basis, the embodiments of the present application can set the hollowed parts 223 in the first power supply structure 224, and adjust the number and size of the hollowed parts 223 in different areas, so that the area of the orthographic projection of the first power supply structure 224 in the second area A2 is greater than the area of the orthographic projection of the first power supply structure 224 in the first area A1, and then the area of the orthographic projection of the second conductive part 222 on the substrate is greater than the area of the orthographic projection of the first conductive part 221 on the substrate, thereby improving the bonding yield and quality.

[0122] In addition, since the first power supply structure 224 has a planar structure, the overall size of the first power supply structure 224 can be increased, so as to reduce the resistance of the first power supply structure 224, thereby reducing the voltage drop of the signal transmitted by the first power supply structure 224, reducing the power consumption loss of the first power supply structure 224, improving the display unevenness problem, and improving the display effect.

[0123] In some embodiments, as shown in Figures 7 to 11As shown, the first conductor layer 22 further comprises a first pad 225 which is arranged in isolation from the first power supply structure 224.

[0124] The first pad 225 can be a structure in the array substrate 100 for bonding connection with the light emitting element 40. Alternatively, the light emitting element 40 comprises two electrodes, and the first conductor layer 22 further comprises a second pad 226. As shown in FIG. 2B, the first pad 225 and the second pad 226 are arranged in isolation from the first power supply structure 224, and the first pad 225 and the second pad 226 are respectively bonded to the two electrodes of the light emitting element 40. Figures 8 to 10 As shown in FIG. 2A, the first power supply structure 224 is used to transmit a PVDD signal, at this time, the first pad 225 and the second pad 226 are arranged in isolation from the first power supply structure 224, and the first pad 225 and the second pad 226 are respectively bonded to the two electrodes of the light emitting element 40. Figure 11 As shown in FIG. 2B, the first power supply structure 224 is used to transmit a PVEE signal, at this time, the first power supply structure 224 is arranged in electrical connection with the second pad 226, and in isolation from the first pad 225. Alternatively, the second pad 226 and the first power supply structure 224 can be an integral structure.

[0125] Further, in combination with the foregoing, it can be known that the first power supply structure 224 is in a planar structure, on this basis, in order to meet the insulation requirement between the first power supply structure 224 and the first pad 225, the first power supply structure 224 needs to be provided with a first hole W1 for accommodating the first pad 225, and the first pad 225 needs to be arranged in isolation from the first power supply structure 224. Among them, the second pad 226 can be located in the first hole W1 together with the first pad 225, or the second pad 226 can be located outside the first hole W1, and the embodiments of the present application do not limit this. Figures 8 to 10 As shown in FIG. 2B, the first pad 225 and the second pad 226 are both located in the first hole W1, Figure 11 As shown in FIG. 2A, only the first pad 225 is located in the first hole W1.

[0126] Under this design, the gap space between the first pad 225 and the first power supply structure 224 is the hollow part 223. On this basis, the gap size between the first pad 225 and the first power supply structure 224 in the first area A1 can be selected to be increased, so as to increase the size of a single hollow part 223 in the first area A1, so as to make the area of the second conductive part 222 in the substrate 10 greater than the area of the first conductive part 221 in the substrate 10.

[0127] Alternatively, as shown in FIG. 2B, the first power supply structure 224 is used to transmit a PVEE signal, at this time, the first power supply structure 224 is arranged in electrical connection with the second pad 226, and in isolation from the first pad 225. Alternatively, the second pad 226 and the first power supply structure 224 can be an integral structure. Figure 10As shown, alternatively, an additional second hole W2 can be added in the first power structure 224 within the first region A1, at positions other than the corresponding position of the first pad 225. The second hole W2 is also a cutout portion 223. With this design, the total orthographic projection area corresponding to all the cutout portions 223 within the first region A1 can be increased, thereby making the orthographic projection area of ​​the second conductive portion 222 on the substrate 10 larger than the orthographic projection area of ​​the first conductive portion 221 on the substrate 10.

[0128] It should be noted that, for the technical solution of adding an additional second hole W2 in other positions besides the position corresponding to the first pad 225 in the first power structure 224, in addition to adding a second hole W2 in the first area A1, a second hole W2 can also be added in the second area A2. Based on this, the number of corresponding second holes W2 or the size of a single hole in the first area A1 and the second area A2 can be adjusted to control the corresponding orthographic projection area of ​​the first conductive part 221 and the second conductive part 222.

[0129] Furthermore, since the adjacent insulating layers on both sides of the thickness direction Z of the first power supply structure 224 are usually made of inorganic materials, the perforation structure can improve the adhesion between the first power supply structure 224 and its adjacent insulating layers, reduce the risk of the first power supply structure 224 peeling off from the adjacent film layers, and improve reliability.

[0130] Apart from Figures 8 to 11 Besides the structure shown, the first power supply structure 224 can also have other structural forms, for example, please refer to Figure 12 ,exist Figure 12 In the middle, the first power supply structure 224 also has a planar structure, and... Figure 10 The difference is that the second hole W2 formed on the first power structure 224 is connected to the first hole W1 for accommodating the first pad 225. Furthermore, besides the shape shown in the figure, the first hole W1 and the second hole W2 can have various other shapes, and this embodiment does not limit this.

[0131] In some embodiments, please refer to Figure 13 and Figure 14 The array substrate 100 also includes an active layer 30, and a first conductor layer 22 is located on the side of the active layer 30 facing the substrate 10.

[0132] In combination with the foregoing embodiments, the first conductor layer 22 can be located on the side of the active layer 30 away from the substrate 10 or on the side of the active layer 30 facing the substrate 10. In other words, in order to improve the bonding yield, the conductors in the conductor layer 20 on the side of the active layer 30 away from the substrate 10 can be adjusted, or the conductors in the conductor layer 20 on the side of the active layer 30 facing the substrate 10 can be adjusted. Of course, in other embodiments, the conductors in the conductor layer 20 on the side of the active layer 30 facing the substrate 10 and the conductors in the conductor layer 20 on the side of the active layer 30 away from the substrate 10 can be adjusted at the same time, which has strong flexibility and can meet the needs of different situations.

[0133] It should be noted that the first conductive part 221 in the first conductor layer 22 can be arranged corresponding to the active layer 30 or can not be arranged corresponding to the active layer 30, that is, the orthographic projection of the first conductive part 221 on the substrate 10 can overlap the orthographic projection of the active layer 30 on the substrate 10 or can not overlap. The relationship between the second conductive part 222 and the active layer 30 is the same.

[0134] In addition, the conductors in the conductor layer 20 on the side of the active layer 30 facing the substrate 10 are usually not used to realize specific functions such as light emission and touch control, so even if part of the conductors in the conductor layer 20 are cancelled, it will not affect the normal use of the subsequently formed display panel. In view of this, in other optional embodiments, the active layer 30 is provided with a conductor layer 20 on the side facing the substrate 10, the conductors in the conductor layer 20 have orthographic projections on the substrate 10 located within the orthographic projection of the second area A2 on the substrate 10 and outside the orthographic projection of the first area A1 on the substrate 10, that is, on the basis of the foregoing embodiments, the first conductive part 221 can be cancelled, so that the orthographic projection area corresponding to the conductor structure 21 in the second area A2 is greater than the orthographic projection area corresponding to the conductor structure 21 in the first area A1.

[0135] In some embodiments, as shown in Figs. 1A and 1B, the orthographic projections of the first conductive part 221 and the second conductive part 222 on the substrate 10 do not overlap the orthographic projection of the active layer 30 on the substrate 10. Figure 13 and Figure 14 In some embodiments, as shown in Figs. 1A and 1B, the orthographic projections of the first conductive part 221 and the second conductive part 222 on the substrate 10 do not overlap the orthographic projection of the active layer 30 on the substrate 10.

[0136] The array substrate usually has a thin film transistor T, part of the structure of the thin film transistor T can be located in the active layer 30, the first conductor layer 22 is located on the side of the active layer 30 facing the substrate 10, and on this basis, the orthographic projections of the first conductive part 221 and the second conductive part 222 on the substrate 10 overlap the orthographic projection of the active layer 30 on the substrate 10. In this way, the first conductive part 221 and the second conductive part 222 can absorb part of the reflected light in the display panel, thereby reducing the amount of light reflected into the active layer 30 and improving the operation reliability of the thin film transistor.

[0137] It should be noted that, according to different actual needs, at least one of the first conductive part 221 and the second conductive part 222 can be used to transmit a specific signal, for example, can be configured with a constant voltage potential. In this way, at least one of the first conductive part 221 and the second conductive part 222 can also reduce the formation of a capacitor between the existing charge in the substrate 10 and the active layer 30, reduce the risk of leakage of the thin film transistor, and thus improve the operation reliability of the thin film transistor.

[0138] In some embodiments, referring to Figure 15 and Figure 16 , the first conductive part 221 includes a first part 2211, the second conductive part 222 includes a second part 2221 and a third part 2222, the first part 2211 and the second part 2221 transmit the same type of signal, and the third part 2222 is insulated from the first part 2211 and the second part 2221.

[0139] The first part 2211 and the second part 2221 are both conductors that exist in the first conductor layer, and the third part 2222 is a newly added conductor in the first conductor layer to improve the bonding yield. Among them, the first part 2211 and the second part 2221 transmit the same type of signal, and the third part 2222 can be used to transmit a specific signal, or the third part 2222 can not transmit a signal, that is, the third part 2222 can be configured with a potential, or can not be configured with a potential. Further, when the third part 2222 is used to transmit a specific signal, the type of signal it transmits can be the same as the first part 2211 or can be different.

[0140] In the embodiments of the present application, by additionally providing the third part 2222 in the first conductor layer corresponding to the second area A2, the projection area of the second conductive part 222 on the substrate can be increased, so that the projection area of the second conductive part 222 on the substrate is greater than the projection area of the first conductive part 221 on the substrate, thereby improving the bonding yield and quality.

[0141] In some embodiments, referring to Figure 17 , the extension direction of the third part 2222 is parallel to the extension direction of the second part 2221. Among them, the "direction of the third part 2222" mentioned here refers to the direction corresponding to the overall extension trend of the third part 2222, wherein the third part 2222 can be in a straight line shape, or referring to Figure 18 , the third part 2222 can also be in a polyline shape or a curve shape, etc., in which case the extension direction corresponding to the third part 2222 is the direction N shown in the figure. The extension direction of the second part 2221 is the same.

[0142] The second part 2221 is a conductor existing in the second conductive part 222 by itself, and the third part 2222 is a conductor added for increasing the corresponding orthogonal projection area of the second conductive part 222. The second part 2221 and the third part 2222 are both integrated in the second area A2. Further, in order to improve the layout rationality of the second part 2221 and the third part 2222 and reduce the risk of intersection of the two, the extension direction of the third part 2222 is set to be parallel to the extension direction of the second part 2221, which can reduce the difficulty of conductor layout of the first conductor layer 22 in the second area A2 and reduce the risk of intersection of the second part 2221 and the third part 2222.

[0143] It should be noted that the length corresponding to the third part 2222 can be greater than, less than, or equal to the length corresponding to the second part 2221, which is not limited in the embodiments of the present application. In addition, the third part 2222 can be connected with other conductors outside the second area A2, or the third part 2222 can be spaced from other conductors outside the second area A2, and the second part 2221 is the same. Figure 15 In the above case, the second part 2221 is connected with other conductors outside the second area A2, and the third part 2222 is spaced from other conductors outside the second area A2.

[0144] In some embodiments, referring to Figure 19 , the third part 2222 transmits a constant voltage signal, and the orthogonal projection of the third part 2222 on the substrate overlaps at least part of the orthogonal projection of other conductors in the conductor structure on the substrate.

[0145] The third part 2222 has a voltage signal therein, and the voltage in the third part 2222 is a constant voltage. Further, the orthogonal projection of the third part 2222 on the substrate 10 overlaps at least part of the orthogonal projection of other conductors in the conductor structure on the substrate 10. Here, the “other conductors in the conductor structure 21” refer to the conductors in the conductor layers 20 other than the first conductor layer 22. In other words, the third part 2222 can have an overlapping area in the orthogonal projection on the substrate 10 with at least part of the structure of the conductors in the conductor layers 20 other than the first conductor layer 22, so that the constant voltage signal transmitted in the third part 2222 can shield the signal of the part of the conductors, thereby improving the reliability of signal transmission in the array substrate.

[0146] In some embodiments, referring to Figure 15 , Figure 20 and Figure 21The first conductive part 221 includes a first portion 2211, and the second conductive part 222 includes a second portion 2221. The first portion 2211 and the second portion 2221 transmit the same type of signal. The length of the second portion 2221 is greater than the length of the first portion 2211. The width of at least part of the structure of the second portion 2221 is greater than the width of the first portion 2211. Figure 15 、 Figure 21 and Figure 22 In the length direction, F1 is used for illustration, and in the width direction, F2 is used for illustration.

[0147] The first portion 2211 and the second portion 2221 are both conductors that exist in the first conductor layer. In order to increase the corresponding orthographic projection area of the second conductive part 222, in addition to adding new conductors, the size parameters of the second portion 2221 can also be adjusted. Specifically, the length of the second portion 2221 can be adjusted to increase the orthographic projection area of the second conductive part 222, or the width of the second portion 2221 at some or all positions can be adjusted to increase the orthographic projection area of the second conductive part 222. Among them, Figure 21 shows a case where the width of the second portion 2221 is increased at all positions, and Figure 22 shows a case where the width of the second portion 2221 is increased only at some positions.

[0148] It should be noted that the scheme of adjusting the length of the second portion 2221 can have multiple implementation forms. For example, if the second portion 2221 itself is in a straight line shape, the size in the extension direction can be increased while maintaining the straight line shape, thereby increasing the length of the second portion 2221. Alternatively, the second portion 2221 can be changed to other shapes, thereby increasing the length of the second portion 2221.

[0149] In addition, in the embodiments of the present application, a third portion 2222 can be added in the first conductor layer, or the third portion 2222 can not be provided. The embodiments of the present application do not limit this. Figure 17 and Figure 18 show a case where the third portion 2222 is not provided in the first conductor layer.

[0150] In summary, in the embodiments of the present application, the length and width of part of the conductors in the second area A2 can be increased based on the original conductor layout, so that the first conductor layer 22 has size differences between the first area A1 and the second area A2, thereby increasing the orthographic projection area of the second conductive part 222 and improving the bonding yield and quality.

[0151] It should be noted that in the embodiments of the present application, only one of the length and width of the conductors in different regions can be adjusted, or both the length and width can be adjusted. Further, the length or width of the conductors in one film layer in different regions can be adjusted, or the length or width of the conductors in multiple film layers in different regions can be adjusted.

[0152] In some embodiments, referring to Figure 20 and Figure 23 , the second part 2221 includes first sub-sections D1 and second sub-sections D2 arranged alternately, the first sub-sections D1 and the second sub-sections D2 are intersected in the extending direction; and / or, the second part 2221 includes a main section structure D3 and a branch section structure D4 extending from the middle of the main section structure D3, the main section structure D3 and the branch section structure D4 are intersected in the extending direction.

[0153] In order to increase the length of the second part 2221, the extending manner of the second part 2221 can be adjusted. Specifically, the second part 2221 can be arranged to include first sub-sections D1 and second sub-sections D2 arranged alternately and not parallel in the extending direction. The first sub-sections D1 and the second sub-sections D2 can be linear or curved, and the number of the first sub-sections D1 and the second sub-sections D2 can be one or more. Figure 20 The case where the first sub-sections D1 and the second sub-sections D2 are linear and the number of the first sub-sections D1 and the second sub-sections D2 is more than one is shown in FIG. 12. It can be seen from the drawings that in this design, the second part 2221 is overall a broken line, and the length of the second part 2221 can be greater than that of the first part 2211 which is linear.

[0154] Alternatively, in other embodiments, the second part 2221 can also include a main section structure D3 and a branch section structure D4. The main section structure D3 is the basic component of the second part 2221, and can be the same as or similar to the extending manner and length of the first part 2211.

[0155] The branch section structure D4 is a branch extending from the middle of the main section structure D3. Here, the middle of the main section structure D3 does not specifically refer to the central position of the main section structure D3, but refers to any position of the main section structure D3 except the two ends. The number of the branch section structure D4 can be one or more. When the number of the branch section structure D4 is more than one, at least part of the branch section structure D4 can be arranged on the same side of the main section structure D3, or arranged on different sides of the main section structure D3. Further, at least part of the branch section structure D4 can extend from the same position of the main section structure D3, or extend from different positions of the main section structure D3. Figure 23It is shown that the plurality of branch segment structures D4 extend from different positions of the main segment structure D3 and are arranged on the same side of the main segment structure D3.

[0156] It should be noted that when the second part 2221 includes the main segment structure D3 and the branch segment structure D4, the length of the second part 2221 is the sum of the length of the main segment structure D3 and the length of all the branch segment structures D4. This design can also increase the corresponding length of the second part 2221, so that the area of the second conductive part 222 in the orthographic projection of the substrate 10 is greater than the area of the first conductive part 221 in the orthographic projection of the substrate 10, thereby improving the bonding yield and quality.

[0157] In addition, for a plurality of conductor layers, the structure of only one of the conductor layers can be adjusted, or the structures of a plurality of conductor layers can be adjusted. For example, the conductors in the second region A2 of one of the conductor layers can be selected to include the first sub-segment D1 and the second sub-segment D2, and the conductors in the second region A2 of the other conductor layers can be selected to include the main segment structure D3 and the branch segment structure D4.

[0158] In some embodiments, referring to Figure 24 , the plurality of conductor layers includes a third conductor layer 24, and the third conductor layer 24 includes a hollow structure 241 covering the first region A1.

[0159] The third conductor layer 24 is one of the plurality of conductor layers, and the third conductor layer 24 can have various positions, for example, the third conductor layer 24 can be located on the side of the active layer facing the substrate, or the third conductor layer 24 can be located on the side of the active layer away from the substrate.

[0160] The third conductor layer 24 includes the hollow structure 241, and the hollow structure 241 has various forms. For example, the third conductor layer 24 can have a planar structure, and the hollow structure 241 is a hole in the planar structure. Alternatively, the third conductor layer 24 can include a plurality of wiring structures, and the hollow structure 241 is a region structure formed by avoiding the plurality of wiring structures. Among them, Figure 20 A case where the third conductor layer 24 has a planar structure is shown.

[0161] In the embodiments of the present application, the hollow structure 241 covers the first region A1, that is, the third conductor layer 24 does not have a conductor at the first region A1, the orthographic projection of the third conductor layer 24 on the substrate is located outside the orthographic projection of the first region A1 on the substrate, and the orthographic projection of the third conductor layer 24 on the substrate overlaps with the orthographic projection of the second region A2 on the substrate. This also helps to make the corresponding orthographic projection area of the conductor structure in the second region A2 greater than the corresponding orthographic projection area of the conductor structure in the first region A1, thereby improving the bonding yield and quality.

[0162] In some embodiments, refer to Figure 25 and Figure 26 The array substrate includes a fourth conductor layer 25 and a fifth conductor layer 26 which are stacked and insulated, the fourth conductor layer 25 includes a third conductive part 251 located in the second area A2, the fifth conductor layer 26 includes a fourth conductive part 261 located in the second area A2, the fourth conductor layer 25 and the fifth conductor layer 26 correspond to a second projection area Y2 at the second area A2, the third conductive part 251 has a projection area Z1 of the orthographic projection on the substrate, and the fourth conductive part 261 has a projection area Z2 of the orthographic projection on the substrate. When the third conductive part 251 and the fourth conductive part 261 are arranged in overlapping orthographic projection on the substrate, and the orthographic projection on the substrate has a first overlapping area J1, Y2 = Z1 + Z2 - J1. Alternatively, when the orthographic projection of the third conductive part 251 on the substrate 10 and the orthographic projection of the fourth conductive part 261 on the substrate are not arranged in overlapping, Y2 = Z1 + Z2.

[0163] The fourth conductor layer 25 and the fifth conductor layer 26 are two of the plurality of conductor layers, wherein the fourth conductor layer 25 and the fifth conductor layer 26 can be two adjacent conductor layers, or there can be other conductor layers between the fourth conductor layer 25 and the fifth conductor layer 26, which is not limited in the embodiments of the present application.

[0164] The third conductive part 251 is a conductor in the fourth conductor layer 25 located in the second area A2, and the fourth conductive part 261 is a conductor in the fifth conductor layer 26 located in the second area A2. The fourth conductor layer 25 and the fifth conductor layer 26 correspond to a first projection area Z1 at the first area and a second projection area Z2 at the second area A2. Among them, the third conductive part 251 and the fourth conductive part 261 can be arranged in overlapping orthographic projection on the substrate, or can not be arranged in overlapping orthographic projection on the substrate, and for these two cases, the calculation method of the second projection area Y2 will be different.

[0165] Specifically, when the orthographic projection of the third conductive part 251 on the substrate and the orthographic projection of the fourth conductive part 261 on the substrate are not arranged in overlapping, the second projection area Y2 is equal to the sum of the orthographic projection area Z1 corresponding to the third conductive part 251 and the orthographic projection area Z2 corresponding to the fourth conductive part 261, that is, Y2 = Z1 + Z2.

[0166] When the third conductive part 251 is arranged in the overlapping area of the orthographic projection of the substrate and the orthographic projection of the fourth conductive part 261, the second projection area Y2 is equal to the sum of the orthographic projection area Z1 corresponding to the third conductive part 251 and the orthographic projection area Z2 corresponding to the fourth conductive part 261, minus the first overlapping area J1 corresponding to the third conductive part 251 and the fourth conductive part 261, that is, Y2 = Z1 + Z2 - J1, in other words, in the process of calculating the orthographic projection area corresponding to the third conductive part 251 and the fourth conductive part 261, the orthographic projection area in the overlapping area is not calculated repeatedly.

[0167] It should be noted that the calculation method of the orthographic projection area corresponding to the conductor structure 21 is the same as that of the conductor structure 21. Further, when the plurality of conductor layers 20 only includes the fourth conductor layer 25 and the fifth conductor layer 26, the orthographic projection area of the conductor structure 21 at the second area A2 is the second projection area Y2. When the plurality of conductor layers 20 includes other conductor layers 20 in addition to the fourth conductor layer 25 and the fifth conductor layer 26, the calculation method of the orthographic projection area of the conductor structure 21 at the second area A2 is similar to the calculation method provided in the embodiments of the present application, that is, the orthographic projection area in the overlapping area is not calculated repeatedly.

[0168] In some embodiments, referring to Figure 26 and Figure 27 , the orthographic projection area of the part of the fourth conductor layer 25 located in the second area A2 on the substrate is greater than the orthographic projection area of the part of the fourth conductor layer 25 located in the first area A1 on the substrate; and / or, the orthographic projection area of the part of the fifth conductor layer 26 located in the second area A2 on the substrate is greater than the orthographic projection area of the part of the fifth conductor layer 26 located in the first area A1 on the substrate; and / or, the orthographic projection overlapping area of the part of the fourth conductor layer 25 and the fifth conductor layer 26 in the first area A1 is greater than the orthographic projection overlapping area of the part of the fourth conductor layer 25 and the fifth conductor layer 26 in the second area A2.

[0169] When the plurality of conductor layers 20 includes at least two conductor layers of the fourth conductor layer 25 and the fifth conductor layer 26, in order to make the orthographic projection area of the conductor structure in the second area A2 on the substrate greater than the orthographic projection area of the conductor structure in the first area A1 on the substrate, the size of the conductor in at least one of the fourth conductor layer 25 and the fifth conductor layer 26 in different areas can be adjusted, or the relative position of the conductor in the fourth conductor layer 25 and the fifth conductor layer 26 can be adjusted, which has strong flexibility. Next, the embodiments of the present application will be introduced respectively for different cases.

[0170] In one case, the size of the conductors in the fourth conductor layer 25 can be adjusted, specifically, the area of the conductor structure in the fourth conductor layer 25 in the second area A2 in the orthographic projection of the substrate can be set to be greater than the area of the conductor structure in the fourth conductor layer 25 in the first area A1 in the orthographic projection of the substrate, so that the area of the conductor structure in the second area A2 in the orthographic projection of the substrate is greater than the area of the conductor structure in the first area A1 in the orthographic projection of the substrate.

[0171] In another case, the size of the conductors in the fifth conductor layer 26 can also be adjusted, specifically, the area of the conductor structure in the fifth conductor layer 26 in the second area A2 in the orthographic projection of the substrate can be set to be greater than the area of the conductor structure in the fifth conductor layer 26 in the first area A1 in the orthographic projection of the substrate, so that the area of the conductor structure in the second area A2 in the orthographic projection of the substrate is greater than the area of the conductor structure in the first area A1 in the orthographic projection of the substrate.

[0172] In other cases, the overlap between the fourth conductor layer 25 and the fifth conductor layer 26 can also be adjusted. Specifically, by changing the layout of the conductors in at least one of the fourth conductor layer 25 and the fifth conductor layer 26, the overlap area of the fourth conductor layer 25 and the fifth conductor layer 26 in the second area A2 can be reduced. In this case, even if the size of the conductors in the fourth conductor layer 25 and the fifth conductor layer 26 is not changed, it is also helpful to increase the area of the conductor structure in the second area A2 in the orthographic projection of the substrate, so that the area of the conductor structure in the second area A2 in the orthographic projection of the substrate is greater than the area of the conductor structure in the first area A1 in the orthographic projection of the substrate. Wherein Figure 26 and Figure 27 It is shown that, without changing the size of the conductors in the fourth conductor layer 25 and the fifth conductor layer 26, by adjusting the overlap relationship between the two film layers, the corresponding orthographic projection areas are different.

[0173] In some embodiments, referring to Figure 4 , Figure 28 and Figure 29 , the array substrate 100 also has a third area A3, the orthographic projection area of the third area A3 on the substrate 10 is equal to the orthographic projection area of the second area A2 on the substrate 10, and in the first direction X, the third area A3 is located on the side of the second area A2 away from the center C1 of the array substrate 100. Wherein, the area of the conductor structure 21 in the third area A3 in the orthographic projection of the substrate is greater than the area of the conductor structure 21 in the second area A2 in the orthographic projection of the substrate.

[0174] The third area A3 is an area at a different position from the first area A1 and the second area A2, the third area A3 is located on the same side of the center C1 of the array substrate 100 as the second area A2 along the first direction X, and the first area A1, the second area A2 and the third area A3 have the same area in the orthographic projection of the substrate 10. Among them, the third area A3 can have various shapes, for example, the orthographic projection of the third area A3 on the substrate 10 can be regular or irregular shapes such as a circle or a square, and the like, wherein, Figure 28 The orthographic projections of the first area A1, the second area A2 and the third area A3 on the substrate are all squares.

[0175] In the first direction X, the third area A3 is located on the side away from the center C1 of the array substrate 100 as the second area A2. That is, the distance L3 between the center of the third area A3 and the center C1 of the array substrate 100 in the first direction X is greater than the distance L2 between the center C3 of the second area A2 and the center C1 of the array substrate 100 in the first direction X. Among them, the center C4 of the third area A3 can coincide with the center C1 of the array substrate 100 in the first direction X, at this time, the distance between the center C4 of the third area A3 and the center C1 of the array substrate 100 in the first direction X is the distance of the connecting line of the two. Or the center C4 of the third area A3 and the center C1 of the array substrate 100 can also not overlap in the first direction X, at this time, the distance between the center C4 of the third area A3 and the center C1 of the array substrate 100 in the first direction X is less than the distance of the connecting line of the two.

[0176] In combination with the foregoing, for linear spot bonding and surface spot bonding, the bonding temperature at the edge area is often lower than the bonding temperature at the center area, and in the array substrate 100, the second area A2 is closer to the center of the array substrate 100 in the first direction X than the third area A3, so in the bonding process, the bonding temperature at the third area A3 is often lower than the bonding temperature at the second area A2.

[0177] Therefore, in the embodiments of the present application, the structure layout of the conductor structure 21 in the second area A2 and the third area A3 is adjusted, so that the orthographic projection area of the conductor structure 21 located in the third area A3 on the substrate is greater than the orthographic projection area of the conductor structure 21 in the second area A2. The orthographic projection area of the conductor structure 21 in a certain area is often positively correlated with the absorption capacity of the array substrate 100 in that area to external heat, in other words, the third area A3 of the array substrate 100 has stronger heat absorption capacity than the second area A2. On this basis, even if the bonding temperature at the third area A3 is lower than the bonding temperature at the second area A2, because the third area A3 has stronger heat absorption capacity, the actual temperature difference of the array substrate 100 at the second area A2 and the third area A3 can be reduced, so that the actual temperature at the second area A2 and the third area A3 can be the same or similar, thereby improving the bonding yield and quality.

[0178] In some embodiments, referring to Figure 3 , Figure 30 and Figure 31 , the array substrate 100 further has a fourth area A4, the fourth area A4 is located on the two sides of the first area A1 and the center C1 of the array substrate 100 in the first direction X with the second area A2, and the area of the orthographic projection of the substrate 10 of the fourth area A4 is equal to the area of the orthographic projection of the substrate 10 of the first area A1. Wherein, the area of the orthographic projection of the substrate 10 of the conductor structure 21 located in the fourth area A4 is greater than the area of the orthographic projection of the substrate 10 of the conductor structure 21 located in the first area A1.

[0179] The fourth area A4 and the second area A2 are located on different sides of the center C1 of the array substrate 100 in the first direction X, and the areas of the orthographic projections of the substrate 10 of the first area A1, the second area A2 and the fourth area A4 are all the same. Wherein, the fourth area A4 can have various shapes, for example, the orthographic projection of the fourth area A4 on the substrate 10 can all be regular or irregular shapes such as circles or squares, wherein, Figure 30 The case where the orthographic projection of the fourth area A4 on the substrate 10 is a square is shown in

[0180] As can be seen from the drawings, similar to the second area A2, the distance L4 between the center C5 of the fourth area A4 and the center C1 of the array substrate 100 in the first direction X is greater than the distance L1 between the center C2 of the first area A1 and the center C1 of the array substrate 100 in the first direction X, and on this basis, the conductor structure 21 in the fourth area A4 is adjusted, so that the area of the orthographic projection of the substrate 10 of the conductor structure 21 located in the fourth area A4 is greater than the area of the orthographic projection of the substrate 10 of the conductor structure 21 located in the first area A1, thereby improving the bonding yield and quality.

[0181] It should be noted that the size relationship of the corresponding orthographic projection areas of the conductor structure 21 at the second area A2 and the fourth area A4 can be determined with reference to the distances of the center C3 of the second area A2 and the center C5 of the fourth area A4 relative to the center C1 of the array substrate 100 in the first direction X, and the present application does not limit this.

[0182] In some embodiments, referring to Figure 32 , the array substrate 100 has a fifth area A5, the area of the orthographic projection of the substrate of the fifth area A5 is equal to the area of the orthographic projection of the substrate of the first area A1, and the distance between the center C1 of the array substrate 100 and the fifth area A5 in the second direction Y is greater than the distance between the center C1 of the array substrate 100 and the first area A1, and the first direction X intersects the second direction Y. Wherein, the area of the orthographic projection of the substrate of the conductor structure located in the fifth area A5 is greater than the area of the orthographic projection of the substrate of the conductor structure located in the first area A1.

[0183] The first direction X and the second direction Y are two directions parallel to the plane on which the substrate 10 lies and intersect with each other, and optionally, the first direction X is perpendicular to the second direction Y. Further, taking the projection of the array substrate 100 in the thickness direction Z as a square for example, the first direction X and the second direction Y can be two directions parallel to two adjacent sides of the square, respectively.

[0184] The fifth area A5 is an area at a different position from the first area A1, and the first area A1 and the fifth area A5 have the same area in the orthographic projection of the substrate 10. The fifth area A5 can have various shapes, for example, the orthographic projection of the fifth area A5 on the substrate 10 can be a regular or irregular shape such as a circle or a square, and the like. Figure 32 FIG. 6 shows a case where the orthographic projection of the fifth area A5 on the substrate 10 is a square.

[0185] In the second direction Y, the distance between the center C1 of the array substrate 100 and the fifth area A5 is greater than the distance between the center C1 of the array substrate 100 and the first area A1. That is, the distance L6 between the center C6 of the fifth area A5 and the center C1 of the array substrate 100 in the second direction Y is greater than the distance L5 between the center C2 of the first area A1 and the center C1 of the array substrate 100 in the second direction Y. The center C6 of the fifth area A5 can coincide with the center C1 of the array substrate 100 in the second direction Y, in which case the distance between the center C6 of the fifth area A5 and the center C1 of the array substrate 100 in the second direction Y is the distance of the line connecting the two. Alternatively, the center C6 of the fifth area A5 and the center C1 of the array substrate 100 can not overlap in the second direction Y, in which case the distance between the center C6 of the fifth area A5 and the center C1 of the array substrate 100 in the second direction Y is less than the distance of the line connecting the two, and the same applies to the distance between the center C2 of the first area A1 and the center C1 of the array substrate 100 in the second direction Y.

[0186] In combination with the foregoing, for the surface light spot bonding method, compared with the central region, the edge regions around the central region can all have the problem of poor bonding due to a lower bonding temperature. In view of this, the embodiments of the present application not only increase the orthographic projection area of the conductor structure at the second area A2, but also increase the orthographic projection area of the conductor structure at the fifth area A5, so that the conductor size compensation can be obtained at different positions around the center C1 of the array substrate 100, thereby improving the bonding yield and quality at different positions around the center C1 of the array substrate 100.

[0187] It should be noted that, for the surface light spot bonding mode, the bonding temperature corresponding to different regions depends on the distance of the region from the center C1 of the array substrate 100 in the first direction X and the second direction Y, that is, the corresponding bonding temperature in a certain region depends on the distance of the region from the center C1 of the array substrate 100 in the first direction X and the distance of the region from the center C1 of the array substrate 100 in the second direction Y. For example, if the distance of the fifth region A5 from the center C1 of the array substrate 100 in the second direction Y is greater than the distance of the second region A2 from the center C1 of the array substrate 100 in the first direction X, the conductor structure in the fifth region A5 has a larger area of the conductor structure in the substrate than the conductor structure in the second region A2.

[0188] In some embodiments, the conductor structure 21 comprises a metal material.

[0189] In the embodiments of the present application, the metal material can absorb more light and heat from the outside relative to the light-transmitting material, so that by arranging the conductor structure 21 to comprise a metal material, more external heat can be absorbed by the conductor structure 21 during the bonding process, thereby increasing the actual temperature of the array substrate 100. Further, by adjusting the different sizes of the positive projection of the conductor structure 21 in different regions, the actual temperature of the array substrate 100 in different regions can be adjusted, thereby improving the bonding yield and quality.

[0190] In the second aspect, referring to Figure 7 and Figure 33 the embodiments of the present application provide a display panel 200, which comprises the array substrate 100 in any of the foregoing embodiments and a plurality of light emitting elements 40, part of the light emitting elements 40 being bonded to the first region A1 of the array substrate 100, and part of the light emitting elements 40 being bonded to the second region A2 of the array substrate 100.

[0191] The light emitting element 40 has various forms as long as it needs to be bonded to the array substrate 100. Optionally, the light emitting element 40 includes but is not limited to a mirco LED and a mini LED.

[0192] It should be noted that the first area A1 and the second area A2 are areas on the array substrate 100 for bonding and fixing the light emitting element 40. The display panel 200 can have various forms. For example, the display panel 200 is provided with the light emitting element 40 at each area position, that is, the display panel 200 does not have a frame area not used for light emitting display, and on this basis, the first area A1 and the second area A2 can be correspondingly arranged at any position of the array substrate 100, as long as the distance between the center of the first area A1 and the center of the array substrate 100 in the first direction X is less than the distance between the center of the second area A2 and the center of the array substrate 100 in the first direction X.

[0193] In other cases, the display panel 200 includes a display area and a frame area located on the side of the display area, and the light emitting element 40 is only arranged at the display area, and there is no light emitting element 40 in the frame area. On this basis, the first area A1 and the second area A2 need to be correspondingly located in the display area of the display panel 200, rather than in the frame area.

[0194] In addition, the display panel 200 provided by the embodiment of the present application has the beneficial effects of the array substrate 100 in any of the preceding embodiments. For details, please refer to the description of the beneficial effects of the array substrate 100. The embodiment of the present application will not be described again.

[0195] In some embodiments, referring to Figure 34 The display panel 200 has a sixth area A6 and a seventh area A7 located on at least one side of the sixth area A6, part of the light emitting element 40 is arranged in the sixth area A6, and part of the light emitting element 40 is arranged in the seventh area A7. The array substrate 100 includes a pixel circuit (not shown in the figure), and the pixel circuit is located in the sixth area A6 and not in the seventh area A7 in the orthographic projection of the substrate. The orthographic projection of the first area A1 in the substrate is located in the orthographic projection of the sixth area A6 in the substrate, and the orthographic projection of the second area A2 in the substrate overlaps with the orthographic projection of the seventh area A7 in the substrate 10.

[0196] The display panel 200 has at least a sixth area A6 and a seventh area A7. Exemplarily, the sixth area A6 can include a central area of the display panel 200, and the seventh area A7 can include an edge area of the display panel 200. The seventh area A7 is located on at least one side of the sixth area A6, that is, the seventh area A7 can be located on one side of the sixth area A6 in a single direction, or the seventh area A7 can be annularly arranged on the outer periphery of the sixth area A6.

[0197] The pixel circuit is a circuit structure for controlling the light emitting element 40. The pixel circuit is located in the sixth area A6 and outside the seventh area A7 in the orthographic projection of the substrate 10, that is, the pixel circuit is arranged in the sixth area A6 and not arranged in the seventh area A7. As for the light emitting element 40, part of the light emitting element 40 is arranged in the sixth area A6, and part of the light emitting element 40 is arranged in the seventh area A7, that is, the light emitting element 40 is arranged at each position of the display panel 200, so that the display panel 200 can realize light emitting display at each position. The light emitting element 40 in the seventh area A7 and the light emitting element 40 in the sixth area A6 are both driven and controlled by the pixel circuit in the sixth area A6.

[0198] In the embodiment of the present application, since the light emitting element 40 is distributed in the sixth area A6 and the seventh area A7, in the bonding process, the light emitting element 40 in the sixth area A6 needs to be bonded, and the light emitting element 40 in the seventh area A7 also needs to be bonded. Compared with the sixth area A6, the seventh area A7 is farther away from the center of the array substrate 100, so the corresponding bonding temperature at the seventh area A7 is usually lower than the corresponding bonding temperature at the sixth area A6.

[0199] Therefore, in the embodiment of the present application, the conductor structure in the second area A2 overlapping the seventh area A7 is adjusted, so that the conductor structure 21 in the seventh area A7 can have a larger orthographic projection area, thereby reducing the actual temperature difference between the sixth area A6 and the seventh area A7, and improving the corresponding bonding yield and quality at the seventh area A7.

[0200] In a third aspect, referring to Figure 35 The display device 300 provided in the embodiment of the present application includes the display panel 200 in any of the foregoing embodiments.

[0201] It should be noted that the display device 300 can include only one display panel 200, or can include multiple display panels 200, which is not limited in the embodiment of the present application. The display device 300 provided in the embodiment of the present application has the beneficial effects of the display panel 200 in any of the foregoing embodiments. For details, please refer to the description of the beneficial effects of the display panel 200 and the array substrate 100. The embodiment of the present application will not be repeated here.

[0202] In some embodiments, referring to Figure 36 The display device 300 includes a plurality of display panels 200 arranged in a splicing manner.

[0203] In the embodiments of the present application, the display device 300 can include a plurality of display panels 200, wherein the plurality of display panels 200 can each be connected and fixed between the array substrate 100 and the light emitting element 40 by means of laser bonding. Further, for a single display panel 200 in the display device 300, the corresponding orthographic projection area of the conductor structure 21 at different regions thereof can be adjusted, so as to improve the bonding yield of the display panel 200, and improve the yield and use reliability of the display device 300.

[0204] In a fourth aspect, referring to Figure 37 The embodiments of the present application provide a display panel manufacturing method, comprising:

[0205] S100: providing an array substrate and a light emitting element.

[0206] In step S100, the array substrate is the array substrate in any of the preceding embodiments. Specifically, referring to Figures 1 to 7 The array substrate includes a substrate and a plurality of conductor layers 20 stacked on one side of the substrate, and the plurality of conductor layers 20 are provided with conductor structures 21. The array substrate 100 has a first region A1 and a second region A2, the orthographic projection area of the first region A1 on the substrate 10 is equal to the orthographic projection area of the second region A2 on the substrate 10, and the distance between the center C1 of the array substrate 100 and the second region A2 along the first direction X is greater than the distance between the center C1 of the array substrate 100 and the first region A1, and the first direction X is parallel to the plane on which the substrate 10 is located. The orthographic projection area of the conductor structure 21 located in the second region A2 on the substrate 10 is greater than the orthographic projection area of the conductor structure 21 in the first region A1 on the substrate 10.

[0207] S110: disposing the light emitting element on one side of the array substrate, and irradiating the light emitting element and the array substrate by moving a laser source.

[0208] In step S110, the moving laser source can be a line spot laser, and the moving laser source moves along a third direction M and bonds and fixes the light emitting element 40 and the array substrate 100, the first direction X and the third direction M intersect, and both are parallel to the plane on which the substrate 10 is located. In the bonding process, the bonding temperature of the edge of the line spot is often higher than that of the center of the line spot, and the center of the line spot often coincides or approaches the center C1 of the array substrate 100 in the third direction M. Therefore, when the line spot moves and irradiates the first region A1, and moves and irradiates the second region A2, the bonding temperature at the second region A2 is often lower than that at the first region A1.

[0209] Therefore, in the embodiments of the present application, the structure layout of the conductor structure 21 in the first area A1 and the second area A2 is adjusted, so that the conductor structure 21 in the second area A2 has a larger area of the orthographic projection on the substrate 10 than the conductor structure 21 in the first area A1. In this way, the second area A2 of the array substrate 100 has a stronger heat absorption capacity than the first area A1. Thus, the actual temperature difference between the first area A1 and the second area A2 of the array substrate 100 is reduced, so that the actual temperatures of the first area A1 and the second area A2 can be the same or similar, and the bonding yield and quality are improved.

[0210] In a fifth aspect, referring to Figure 38 The present application provides a preparation method of a display panel, comprising:

[0211] S120: providing an array substrate and a light emitting element.

[0212] In step S120, the array substrate is the array substrate in any of the foregoing embodiments. Specifically, referring to Figures 3 to 7 The array substrate comprises a substrate 10 and a plurality of conductor layers 20 stacked on one side of the substrate 10, and the plurality of conductor layers 20 are provided with a conductor structure 21. The array substrate has a first area A1 and a second area A2, the area of the orthographic projection of the first area A1 on the substrate 10 is equal to the area of the orthographic projection of the second area A2 on the substrate 10, and the distance between the center of the array substrate and the second area A2 along a first direction X is greater than the distance between the center of the array substrate and the first area A1, the first direction X is parallel to the plane on which the substrate 10 is located. The area of the orthographic projection of the conductor structure 21 in the second area A2 on the substrate 10 is greater than the area of the orthographic projection of the conductor structure 21 in the first area A1 on the substrate 10.

[0213] S130: disposing the light emitting element on one side of the array substrate, and irradiating the light emitting element and the array substrate with a fixed laser source.

[0214] In step S130, the fixed laser source can be a surface spot laser, and the fixed laser source is focused on the center of the array substrate, and the light emitting element 40 and the array substrate are bonded and fixed. In the bonding process, the bonding temperature at the edge of the surface spot is often higher than the bonding temperature at the center of the line spot, and the surface spot laser is focused on the center of the array substrate, which results in that the farther away from the center of the array substrate, the lower the corresponding bonding temperature, that is, the bonding temperature at the second area A2 is often lower than the bonding temperature at the first area A1.

[0215] Therefore, in this embodiment, the structural layout of the conductor structure 21 in the first region A1 and the second region A2 has been adjusted so that the projected area of ​​the conductor structure 21 in the second region A2 on the substrate 10 is larger than that of the conductor structure 21 in the first region A1. This results in the second region A2 of the array substrate having a stronger heat absorption capacity than the first region A1. Consequently, the actual temperature difference between the first region A1 and the second region A2 of the array substrate is reduced, allowing the actual temperatures of the first region A1 and the second region A2 to be the same or similar, thereby improving bonding yield and quality.

[0216] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0217] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. An array substrate, characterized by, The substrate and a plurality of conductor layers stacked on one side of the substrate, wherein the plurality of conductor layers are provided with conductor structures; The array substrate has a first area and a second area, a projection area of the first area on the substrate is equal to a projection area of the second area on the substrate, and a distance between the center of the array substrate and the second area is greater than a distance between the center of the array substrate and the first area along a first direction parallel to a plane on which the substrate is located; The conductor structures in the second area have a projection area on the substrate greater than a projection area of the conductor structures in the first area on the substrate.

2. The array substrate of claim 1, wherein, The plurality of conductor layers include a first conductor layer, the first conductor layer includes a first conductive part in the first area and a second conductive part in the second area, and the second conductive part has a projection area on the substrate greater than a projection area of the first conductive part on the substrate.

3. The array substrate of claim 2, wherein, The array substrate includes an active layer, and the first conductor layer is located on a side of the active layer away from the substrate.

4. The array substrate of claim 3, wherein, The plurality of conductor layers further include a second conductor layer between the first conductor layer and the active layer.

5. The array substrate of claim 4, wherein, The first conductive part and the second conductive part both transmit a power signal.

6. The array substrate of claim 2, wherein, The first conductor layer has a planar structure.

7. The array substrate of claim 6, wherein, The first conductor layer is provided with a hollow part, and the hollow part is at least partially located in the first area.

8. The array substrate of claim 7, wherein, The number of the hollow parts in the first area is greater than the number of the hollow parts in the second area; and / or The projection area of the hollow parts in the first area on the substrate is greater than the projection area of the hollow parts in the second area on the substrate.

9. The array substrate of claim 6, wherein, The first conductor layer includes a first power supply structure for providing a first power voltage.

10. The array substrate of claim 9, wherein, The first conductor layer further includes a first pad insulated from the first power supply structure.

11. The array substrate of claim 2, wherein, The array substrate further includes an active layer, and the first conductor layer is located on a side of the active layer facing the substrate.

12. The array substrate of claim 11, wherein, The first conductive part and the second conductive part both transmit a power signal.

13. The array substrate of claim 2, wherein, The first conductive part includes a first part, the second conductive part includes a second part and a third part, the first part and the second part transmit the same type of signal, and the third part is insulated from the first part and the second part.

14. The array substrate of claim 13, wherein, The third part has an extension direction parallel to the extension direction of the second part.

15. The array substrate of claim 13, wherein, The third part transmits a constant voltage signal, and the projection of the third part on the substrate overlaps at least part of the projection of other conductors in the conductor structure on the substrate.

16. The array substrate of claim 2, wherein, The first conductive part includes a first part, the second conductive part includes a second part, the first part and the second part transmit the same type of signal, and the length of the second part is greater than the length of the first part. And / or The width of at least part of the structure in the second part is greater than the width of the first part.

17. The array substrate of claim 16, wherein, The second portion comprises first sub-sections and second sub-sections arranged alternately, and the extending direction of the first sub-sections intersects with the extending direction of the second sub-sections; and / or, The second portion comprises a main section structure and a branch section structure extending from the middle of the main section structure, and the extending direction of the main section structure intersects with the extending direction of the branch section structure.

18. The array substrate of claim 1, wherein, The plurality of conductor layers comprises a third conductor layer, and the third conductor layer comprises a hollow structure covering the first area.

19. The array substrate of claim 1, wherein, The array substrate comprises a fourth conductor layer and a fifth conductor layer stacked and insulated, the fourth conductor layer comprises a third conductive part in the second area, the fifth conductor layer comprises a fourth conductive part in the second area, the fourth conductor layer and the fifth conductor layer correspond to a second projection area Y2 at the second area, the third conductive part has a projection area Z1 in orthographic projection on the substrate, and the fourth conductive part has a projection area Z2 in orthographic projection on the substrate; When the third conductive part and the fourth conductive part are arranged in overlapping orthographic projection on the substrate and have a first overlapping area J1 in orthographic projection on the substrate, Y2=Z1+Z2-J1; or, When the third conductive part in orthographic projection on the substrate does not overlap with the fourth conductive part in orthographic projection on the substrate, Y2=Z1+Z2.

20. The array substrate of claim 19, wherein, The orthographic projection area of the part of the fourth conductor layer in the second area on the substrate is greater than the orthographic projection area of the part of the fourth conductor layer in the first area on the substrate; and / or, The orthographic projection area of the part of the fifth conductor layer in the second area on the substrate is greater than the orthographic projection area of the part of the fifth conductor layer in the first area on the substrate; and / or, The overlapping area of the orthographic projection of the part of the fourth conductor layer and the part of the fifth conductor layer in the first area on the substrate is greater than the overlapping area of the orthographic projection of the part of the fourth conductor layer and the part of the fifth conductor layer in the second area on the substrate.

21. The array substrate of claim 1, wherein, The array substrate further has a third area, and the orthographic projection area of the third area on the substrate is equal to the orthographic projection area of the second area on the substrate, and the third area is located on the side of the second area away from the center of the array substrate in the first direction; The orthographic projection area of the conductor structure in the third area on the substrate is greater than the orthographic projection area of the conductor structure in the second area on the substrate.

22. The array substrate of claim 1, wherein, The array substrate further has a fourth area, and the fourth area is located on the two sides of the first area and the center of the array substrate in the first direction with the second area, and the orthographic projection area of the fourth area on the substrate is equal to the orthographic projection area of the first area on the substrate; The orthographic projection area of the conductor structure in the fourth area on the substrate is greater than the orthographic projection area of the conductor structure in the first area on the substrate.

23. The array substrate of claim 1, wherein, The array substrate further has a fifth area, a distance between the array substrate center and the fifth area along a second direction is greater than a distance between the array substrate center and the first area, the first direction intersects the second direction; A projection area of the conductor structure in the fifth area on the substrate is greater than a projection area of the conductor structure in the first area on the substrate.

24. The array substrate of claim 1, wherein, The conductor structure comprises a metal material.

25. A display panel comprising: The display panel has a sixth area and a seventh area on at least one side of the sixth area, part of the light emitting elements are arranged in the sixth area, and part of the light emitting elements are arranged in the seventh area; 26. The display panel of claim 25, wherein, The array substrate comprises a pixel circuit, a projection of the pixel circuit on the substrate is located in the sixth area and outside the seventh area; A projection of the first area on the substrate is located in a projection of the sixth area on the substrate, and a projection of the second area on the substrate overlaps with a projection of the seventh area on the substrate. The display panel comprises the array substrate and the light emitting elements.

27. A display device comprising: The display device comprises a plurality of display panels arranged in a splicing manner.

28. The display device of claim 27, wherein, Providing the array substrate and the light emitting element as claimed in any one of claims 1 to 24; 29. A method for manufacturing a display panel, characterized in that, The light emitting element is arranged on one side of the array substrate, and a moving laser source is used to irradiate the light emitting element and the array substrate to bond and fix the light emitting element and the array substrate, the moving laser source moves along a third direction, the first direction intersects the third direction and is parallel to a plane on which the substrate is located. Providing the array substrate and the light emitting element as claimed in any one of claims 1 to 24; The light emitting element is arranged on one side of the array substrate, and a fixed laser source is used to irradiate the light emitting element and the array substrate to bond and fix the light emitting element and the array substrate, and the fixed laser source is focused on the center of the array substrate.

30. A method for manufacturing a display panel, characterized in that, ​ ​ ​

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