Fpga implementation method, system and medium based on hierarchical and product code algorithm

Abstract

The application provides an FPGA implementation method, system and medium based on layered and accumulated decoding algorithm, and the method comprises the following steps: obtaining a channel message, preprocessing a check matrix of a QC-LDPC code to obtain preprocessing information; updating node LLR information after initializing and processing the channel message, and storing the node LLR information; performing decoding decision after obtaining the posteriori LLR information of the last layer and updating; ending decoding after determining that a preset condition is met, and storing a decoding result obtained by decoding; the application realizes check matrix preprocessing and fast cyclic shift operation, accelerates decoding speed, improves throughput of a decoder, integrates storage of initial variable node LLR information and posteriori LLR information in data storage, saves storage of variable node LLR information in a layer, and reduces resource consumption of the decoder.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of wireless communication and digital signal processing, and relates to a decoder, in particular to an FPGA implementation method, system and medium based on a layered and sum-product decoding algorithm. BACKGROUND

[0002] The invention of channel coding technology provides reliable data transmission for communication systems. Compared with other channel coding methods, Low-Density Parity-Check (LDPC) codes have the advantages of strong error correction, flexible structure, and low decoding complexity. Quasi-Cyclic LDPC (QC-LDPC) is a class of LDPC codes with quasi-cyclic structure characteristics. The check matrix is an array composed of circulant permutation matrices (CPM) or zero matrices. The CPM is a matrix obtained by cyclically right shifting each row of a unit matrix. The element value in the check matrix represents the shift amount of the circulant permutation matrix, which facilitates the hardware structure of the decoder and has better decoding performance and speed. Field Programmable Gate Array (FPGA) has flexible programmability and high-speed parallel logic processing capability, and is easy to implement decoders with different code lengths, code rates, signal-to-noise ratios and other variable parameters, which can achieve higher reliability and stability in practical applications.

[0003] The decoding algorithm of LDPC codes can be divided into soft decision decoding algorithm and hard decision decoding algorithm. Soft decision decoding algorithm is widely studied due to its stronger decoding performance. LDPC soft decision decoding algorithms mainly include Belief Propagation (BP) decoding algorithm, Log likelihood Ratio (LLR) belief propagation decoding algorithm, and Minimum Sum (MS), Normalized Minimum Sum (NMS) and Offset Minimum Sum (OMS) decoding algorithms improved on the basis of BP algorithm. Among them, the log likelihood ratio belief propagation algorithm simplifies the nonlinear multiplication operation of the BP algorithm to linear addition operation, which greatly reduces the complexity of the decoding algorithm in hardware implementation while ensuring the decoding performance. The layered decoding algorithm divides several rows of the check matrix into a layer, and uses inter-layer serial and intra-layer parallel operation to speed up the convergence speed of iterative decoding. QC-LDPC codes can regard a row of the base matrix as a layer, so the layered LLR BP decoding algorithm for QC-LDPC codes, also known as layered sum-product algorithm (LSPA), can reduce hardware resources and improve the convergence speed of decoding iteration.

[0004] Because the sum-product decoding algorithm involves logarithm operation and trigonometric function operation, it is more complex to implement on FPGA. At present, the FPGA design of LDPC decoder mostly uses the min-sum decoding algorithm, which simplifies the implementation complexity of the decoding algorithm at the cost of certain decoding accuracy. However, in actual application, under certain low signal-to-noise ratio communication conditions, such as continuous variable quantum key distribution system, the decoding performance of the min-sum decoding algorithm is not as good as that of the sum-product decoding algorithm. At present, the FPGA implementation of LDPC decoder focuses on the improvement of decoder performance and the reduction of hardware resource consumption, and it is necessary to design the FPGA implementation of QC-LDPC code decoder based on layered sum-product decoding algorithm.

[0005] The FPGA implementation of the existing QC-LDPC decoder mostly uses layered min-sum decoding algorithm or improvement of the min-sum decoding algorithm. These decoding algorithms are simplifications of the sum-product decoding algorithm, and their decoding performance will be lost, and their performance is poor under low signal-to-noise ratio conditions. The hardware structure of the decoder needs to store a large amount of data information such as parity check matrix, all node information, to-be-decoded information matrix, normalization coefficient, and posteriori LLR information. The decoding performance and hardware resource consumption of the decoder need to be improved. SUMMARY

[0006] The purpose of the present application is to provide a FPGA implementation method, system and medium based on layered sum-product decoding algorithm, which is used to solve the problems of poor decoder performance and slow decoding speed under low signal-to-noise ratio conditions in the prior art.

[0007] In a first aspect, the present application provides a FPGA implementation method based on layered sum-product decoding algorithm, which comprises the following steps: obtaining channel message, preprocessing the check matrix of QC-LDPC code to obtain preprocessing information; after initialization processing of the channel message, updating node LLR information and storing according to the preprocessing information; after calculating the posteriori LLR information of the last layer and updating, performing decoding decision; determining that the preset condition is satisfied, and ending decoding, and storing the decoding result obtained by decoding.

[0008] In an implementation form of the first aspect, the preprocessing of the check matrix of the QC-LDPC code to obtain the preprocessing information comprises: obtaining a check matrix in the QC-LDPC code; filtering a zero matrix in the check matrix, and compressing the filtered check matrix to obtain an offset matrix and an address matrix; wherein there is no information transmission and no message update between a check node and a variable node in the zero matrix in a decoding process, the offset matrix is used to save a cyclic shift amount corresponding to each row of the check matrix, the address matrix is composed of check matrix array numbers corresponding to each cyclic permutation matrix, the number of rows of the offset matrix and the number of rows of the address matrix are consistent with the number of rows of the check matrix, the number of columns of the offset matrix and the number of columns of the address matrix are consistent with a maximum row weight in the check matrix, and the row weight is a number of non-negative values in each row of the check matrix.

[0009] In an implementation form of the first aspect, after the initialization processing of the channel message, the updating of the node LLR information and the storage according to the preprocessing information comprises: performing initialization processing on the channel message to obtain first LLR information; updating second LLR information of each node in each layer in each iteration according to the first LLR information, the second LLR information comprising check node LLR information, a posteriori LLR information and variable node LLR information; storing the check node LLR information and the a posteriori LLR information in the second LLR information in a memory according to the preprocessing information, and storing the variable node LLR information in a register according to an order of reading check node information.

[0010] In an implementation form of the first aspect, the initialization processing of the channel message to obtain first LLR information comprises: calculating initial LLR information of each variable node and check node in the channel information before the start of iteration by using a first formula.

[0011] wherein the first formula satisfies the following conditions:

[0012]

[0013] wherein L (0) (Q j ) is channel initial LLR information of the channel transmitted to the jth variable node, L (0) (r ij ) is variable node initial LLR information of the ith check node transmitted to the jth variable node, Q j represents a posteriori probability information of the received channel information y j corresponding to 0 or 1, r ij represents extrinsic information of the ith check node transmitted to the jth variable node, and σ 2a variance of a Gaussian noise of a channel.

[0014] In an implementation form of the first aspect, the updating the second LLR information of each node in each layer according to the first LLR information comprises: layering the check matrix by row, decoding by using a decoding strategy of intra-layer parallel and inter-layer serial to obtain respectively the check node LLR information and the variable node LLR information transmitted between each layer of variable nodes and check nodes; and calculating the posteriori LLR information according to the check node LLR information and the variable node LLR information of each layer.

[0015] In an implementation form of the first aspect, the calculation processes of the check node LLR information, the variable node LLR information and the posteriori LLR information satisfy the following second formula:

[0016]

[0017] wherein, l is the current iteration number, k is the current layer number, j' represents a set of variable nodes connected to the i-th check node except the j-th variable node, q ji represents extrinsic information of the j-th variable node transmitted to the i-th check node, V(i) represents a set of variable nodes connected to the i-th check node, L (l,k) (q ji ) represents variable node LLR information of the j-th variable node transmitted to the i-th check node after the current layer iteration update, L (l,k-1) (Q j ) is the posteriori LLR information of the j-th variable node of the previous layer, L (l-1,k) (r ij ) is check node LLR information of the i-th check node transmitted to the j-th variable node in the previous iteration, L (l,k) (r ij ) is check node LLR information of the i-th check node transmitted to the j-th variable node after the current layer iteration update, L (l,k) (Q j ) is the posteriori LLR information of the j-th variable node after the k-th layer update, V(i)\j represents a set of variable nodes in V(i) except the j-th variable node, sgn is a sign function, x represents a variable of a function.

[0018] In an implementation form of the first aspect, the check node LLR information is stored in a check node LLR information storage RAM, the posteriori LLR information is stored in a posteriori LLR information storage RAM, and the variable node LLR information is registered by a fast circular shifter in the order of reading the check node information.

[0019] In an implementation form of the first aspect, the decoding decision after the calculation of the a posteriori LLR information of the last layer and the update comprises: determining that the update of the a posteriori LLR information of each layer is completed after the calculation of the a posteriori LLR information of the last layer; and obtaining a decoded codeword sequence after the decision of the a posteriori LLR information of the current layer.

[0020] In an implementation form of the first aspect, the determination of the end of decoding after the satisfaction of the preset condition and the storage of a decoded result obtained by decoding comprises: determining whether a maximum iteration number is reached or a decoded codeword sequence satisfies a check equation; determining the end of decoding after the determination of the satisfaction of any one of the above conditions, and storing the decoded codeword sequence in a decoded result storage; or otherwise, continuing a new round of information iteration and update.

[0021] In a second aspect, the application further provides an FPGA implementation system based on the layered and product decoding algorithm, comprising a control unit, an address generation unit, an a posteriori LLR information storage RAM, a check node LLR information storage RAM, a node information processing unit, a check decision unit, a decomposition check matrix unit, an initial LLR information calculation unit and a decoded result storage, the initial LLR information calculation unit is electrically connected with the a posteriori LLR information storage RAM, used for calculating first LLR information after the reception of channel information and storing the first LLR information in the a posteriori LLR information storage RAM, the node information processing unit is electrically connected with the a posteriori LLR information storage RAM and the check node LLR information RAM respectively, used for calculating second LLR information according to the first LLR information and storing the second LLR information respectively, the decomposition check matrix unit is electrically connected with the node information processing unit, used for storing an offset matrix and an address matrix obtained after the decomposition of a check matrix, the check decision unit is electrically connected with the a posteriori LLR information storage RAM, used for decision after the iteration and update, and storing a decoded codeword sequence in the decoded result storage after the end of iteration.

[0022] In an implementation form of the second aspect, the node information processing unit comprises a variable node information processing module, a check node information processing module, an adder, a first fast cyclic shifter and a second fast cyclic shifter, the variable node information processing module is configured to calculate variable node LLR information, the check node information processing module is configured to calculate check node LLR information, the input and output terminals of the first fast cyclic shifter are electrically connected with the variable node processing module and the check node processing module respectively, and the variable node LLR information transmitted from the variable node to the check node is cyclically shifted according to the order of reading the check node LLR information, the input and output terminals of the second fast cyclic shifter are electrically connected with the check node information processing module and the check node LLR information storage RAM respectively, and the check node LLR information is reversely cyclically shifted and stored in the check node LLR information storage RAM according to the variable node reading order, and the adder is electrically connected with the variable node information processing module and the check node information processing module respectively to calculate posteriori LLR information according to the variable node LLR information and the check node LLR information.

[0023] In an implementation form of the second aspect, the fast cyclic shifter comprises a shift controller, a left shift module, a right shift module and a selection module, the shift controller generates a shift control signal and a shift number after receiving the variable node LLR information, the shift controller is electrically connected with the left shift module and the right shift module respectively to perform left shift and right shift on the variable node LLR information to obtain left shift result and right shift result, and the selection module is electrically connected with the left shift module and the right shift module to select the left shift result or the right shift result as the shift result according to the shift control signal.

[0024] In a third aspect, the application further provides a computer readable storage medium having a computer program stored thereon, the program being executed to implement the FPGA implementation method based on layered and product code algorithm.

[0025] As described above, the FPGA implementation method, system and medium based on layered and product code algorithm have the following beneficial effects:

[0026] Compared with the traditional decoder, the pre-processing of the check matrix, the fast cyclic shift operation are realized, the decoding speed is accelerated, and the throughput of the decoder is improved. Meanwhile, the storage of the initial variable node LLR information and the posteriori LLR information is integrated in the data storage aspect, the storage of the intra-layer variable node LLR information is saved, and the resource consumption of the decoder is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1A flow chart of the FPGA implementation method based on layered and product-sum decoding algorithm is shown in the embodiments of the present application.

[0028] Figure 2 A schematic diagram of the execution process of the FPGA implementation method based on layered and product-sum decoding algorithm is shown in the embodiments of the present application.

[0029] Figure 3 A schematic diagram of the process of the check matrix preprocessing in the FPGA implementation method based on layered and product-sum decoding algorithm is shown in the embodiments of the present application.

[0030] Figure 4 A structure block diagram of the FPGA implementation system based on layered and product-sum decoding algorithm is shown in the embodiments of the present application.

[0031] Figure 5 A structure block diagram of the fast cyclic shifter in the FPGA implementation system based on layered and product-sum decoding algorithm is shown in the embodiments of the present application. DETAILED DESCRIPTION

[0032] Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description. The present application can also be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details in the specification based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0033] It should be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of the present application, and only show the components related to the present application, not the number, shape and size of the components in actual implementation. The type, number and proportion of each component in actual implementation can be arbitrarily changed, and the layout type of the components can be more complex.

[0034] Reference Figures 1 to 5 The embodiments of the present application provide a FPGA implementation method, system and medium based on layered and product-sum decoding algorithm. Compared with the traditional decoder, the present application realizes check matrix preprocessing and fast cyclic shift operation, speeds up the decoding speed, and improves the throughput of the decoder. Meanwhile, the storage of the initial variable node LLR information and the posteriori LLR information is integrated in the data storage, the storage of the intra-layer variable node LLR information is saved, and the resource consumption of the decoder is reduced.

[0035] FPGA, English full name: Field Programmable Gate Array, Chinese translation: field programmable gate array.

[0036] LLR, English full name: Log-Likelihood Ratio, Chinese translation: Log-Likelihood Ratio, that is, the ratio of the likelihood information (LR, Likelihood Ratio) is logarithmic; in this embodiment, the LLR information refers to the probability information in the logarithmic domain.

[0037] The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application.

[0038] As shown in Figure 1 and Figure 2 In an embodiment, the present application provides an FPGA implementation method based on layered and product code algorithm, which comprises the following steps:

[0039] S1, obtaining channel information, preprocessing the check matrix of QC-LDPC code to obtain preprocessing information.

[0040] QC-LDPC, English full name: Quasi-Cyslic Low-Density Parity-Check Codes, Chinese translation: quasi-cyclic low-density parity-check code.

[0041] In an embodiment, the preprocessing of the check matrix of QC-LDPC code to obtain preprocessing information comprises:

[0042] Obtaining the check matrix in QC-LDPC code;

[0043] Filtering the zero matrix in the check matrix, and compressing the filtered check matrix to obtain an offset matrix and an address matrix;

[0044] Wherein, the check nodes and variable nodes in the zero matrix have no information transmission and no message update in the decoding process, the offset matrix is used to save the cyclic shift amount corresponding to each row of the check matrix, and the address matrix is composed of the check matrix array number corresponding to each cyclic permutation matrix, the number of rows of the offset matrix and the number of rows of the address matrix are consistent with the number of rows of the check matrix, the number of columns of the offset matrix and the number of columns of the address matrix are consistent with the maximum row weight in the check matrix, and the row weight is the number of non-negative values in each row of the check matrix.

[0045] In this embodiment, before decoding the channel information, the check matrix is preprocessed to remove the zero matrix in the check matrix. Since there is no information transmission between the check nodes and variable nodes in the zero matrix in the decoding process, no message update is performed, which is beneficial to improve the speed of subsequent decoding.

[0046] Further, since the cyclic shifters need to use the offset of each non-zero CPM of the check matrix multiple times in the subsequent decoding process, and the node LLR information storage address needs to be generated according to the address of the CPM in the check matrix, the workload of repeatedly generating the address and reading the offset multiple times after reading the check matrix can be reduced by preprocessing the check matrix to obtain the address matrix and the offset matrix, which is beneficial to improve the work efficiency.

[0047] As shown in Figure 3 FIG. 1, taking a 12x24 check matrix as an example, first, the zero matrix in the check matrix is removed, and then the check matrix after removing the zero matrix is compressed to obtain the offset matrix and the address matrix, the elements in the address matrix correspond to the column number of the elements in the offset matrix in the check matrix.

[0048] S2, after the initialization processing of the channel message, updating the node LLR information and storing according to the preprocessing information.

[0049] In an embodiment, after the initialization processing of the channel message, updating the node LLR information and storing according to the preprocessing information, includes:

[0050] S21, the channel message is initialized to obtain first LLR information.

[0051] In an embodiment, the initialization processing of the channel message to obtain first LLR information includes:

[0052] The initial LLR information of each variable node and check node in the channel information before the iteration starts is calculated by the first formula;

[0053] Wherein, the first formula satisfies the following conditions:

[0054]

[0055] Wherein, L (0) (Q j ) is the channel initial LLR information (i.e. the probability information in the logarithmic domain) of the channel transmitted to the jth variable node, L (0) (r ij ) is the variable node initial LLR information of the ith check node transmitted to the jth variable node, Q j represents the received channel information y j , the corresponding posterior probability information of the transmitted code word is 0 or 1, r ij represents the extrinsic information of the ith check node transmitted to the jth variable node, σ 2 represents the variance of the channel Gaussian noise.

[0056] S22, updating second LLR information of each layer node in each iteration according to the first LLR information, the second LLR information comprising check node LLR information, a posteriori LLR information and variable node LLR information.

[0057] In an embodiment, the updating second LLR information of each layer node in each iteration according to the first LLR information comprises:

[0058] The check matrix is layered by row, and a decoding strategy of intra-layer parallel and inter-layer serial is adopted to decode to obtain check node LLR information and variable node LLR information transmitted between each layer variable node and check node respectively;

[0059] The a posteriori LLR information is calculated according to the check node LLR information and variable node LLR information of each layer.

[0060] In this embodiment, after the first LLR information is calculated, the variable node LLR information transmitted from the variable node to the check node is updated by a variable node information processing module, the check node LLR information transmitted from the check node to the variable node is updated by a check node information processing module, and the a posteriori LLR information is calculated according to the variable node LLR information and the check node LLR information.

[0061] Specifically, the check matrix is layered by row using a layered and product decoding algorithm, can be divided into M layers and each layer contains Z check nodes, a decoding strategy of intra-layer parallel and inter-layer serial is adopted, and variable node LLR information, check node LLR information and a posteriori LLR information are calculated respectively according to corresponding calculation formulas.

[0062] The calculation of the second formula process meets the following requirements:

[0063]

[0064] Wherein, l is the current iteration number, k is the current layer number, j' represents a set of variable nodes connected to the ith check node except the jth variable node, q ji represents extrinsic information transmitted from the jth variable node to the ith check node, V(i) represents a set of variable nodes connected to the ith check node, L (l,k) (q ji ) represents variable node LLR information of the jth variable node transmitted to the ith check node after the current layer iteration is updated, L (l,k-1) (Q j ) is a posteriori LLR information of the jth variable node of the previous layer, L (l-1,k) (r ij ) is check node LLR information transmitted from the ith check node to the jth variable node in the last iteration.(l,k) (r ij ) is the check node LLR information of the i-th check node transmitted to the j-th variable node after the current layer iteration, stored in the check node LLR information storage RAM, L (l,k) (Q j ) is the posteriori LLR information of the j-th variable node after the k-th layer update, stored in the posteriori LLR information storage RAM. V(i)\j represents the variable node set excluding the j-th variable node in V(i), sgn is the sign function, x represents the variable of a function.

[0065] RAM, the full name of which is Random Access Memory, which is translated into Chinese as Random Access Memory.

[0066] S23, according to the address matrix, storing the check node LLR information and the posteriori LLR information in the second LLR information in the memory, and storing the variable node LLR information in the order of check node reading information.

[0067] Since the position of 1 in each CPM represents that the variable node and the corresponding check node have information transmission, after the variable node LLR information L (l,k) (q ji ) transmitted from the variable node to the check node in the CPM is calculated, it needs to be stored in the order of check node reading information, so as to ensure the correctness of the information transmission between nodes.

[0068] In an embodiment, the check node LLR information is stored in the check node LLR information storage RAM, the posteriori LLR information is stored in the posteriori LLR information storage RAM, and the variable node LLR information is stored in the order of check node reading information by the fast circular shifter.

[0069] Since only the check node LLR information and the posteriori LLR information in the layer need to be stored, and the variable node LLR information transmitted from the variable node to the check node does not need to be transmitted between layers, it does not need to be stored by a separate memory, thereby reducing the time of information storage and reading in the decoder.

[0070] Specifically, taking a 6*6 matrix as an example, if the offset is 4, then each row of data in the matrix is cyclically right-shifted by 4 bits. The cyclic shift step of the fast cyclic shifter is that after generating the shift control signal and the left and right shift numbers, each row of data of the unit matrix is left-shifted or right-shifted by the left and right shift numbers, and 0 is used for padding, and then the left-shifted and right-shifted parts are selected to obtain the cyclically shifted matrix. The cyclic shifter can quickly complete the cyclic shift of a matrix of any order according to any offset, simultaneously left-shifts and right-shifts the matrix in one clock cycle and then selects, which can greatly save the time required for sequentially cyclically shifting the matrix data, and the flexibility ensures the parallel processing of multiple matrix cyclic shift operations and reduces the complexity of matrix shifting caused by different offsets.

[0071] In an embodiment, the present application adopts a partial parallel architecture, the size of the CPM is Z*Z, and the parallel degree is Z, each Z check node in a layer is updated at the same time, and the LLR information update of all nodes in a layer is completed once. The LLR information storage module of the present application includes a posteriori LLR information storage RAM and a check node LLR information storage RAM, wherein each storage RAM includes Z block RAMs, the width of each block RAM is consistent with the LLR information data width, and the depth is N. The storage rule is that each block RAM stores the column corresponding to the CPM in the check matrix with the same RAM label, specifically, the i-th RAM stores the i-th column of N block columns, that is, the first positions of RAM1-RAMZ store the posteriori LLR information of the first-Z variable nodes of the first block column of the check matrix, the second positions of RAM1-RAMZ store the posteriori information of the first-Z variable nodes of the second block column of the check matrix, and so on.

[0072] S3, after calculating the posteriori LLR information of the last layer and updating, decoding decision is performed.

[0073] In an embodiment, after calculating the posteriori LLR information of the last layer and updating, decoding decision is performed, including:

[0074] After calculating the posteriori LLR information of the last layer, it is determined that the posteriori LLR information of each layer is updated;

[0075] After the posteriori LLR information of the current layer is determined, a decoded code word sequence is obtained.

[0076] After calculating the posteriori LLR information of the last layer, decoding decision is performed, and when the posteriori LLR information of all layers is updated once, the current iteration is ended, the current posteriori LLR information needs to be determined, and if L (l,k) (Q j )<0, the decoded code word c j =1, otherwise cj = 0, obtaining a decoding code word sequence

[0077] S4, determining that the decoding ends after the preset condition is met, and storing the decoding result obtained by decoding.

[0078] In an embodiment, the determining that the decoding ends after the preset condition is met, and storing the decoding result obtained by decoding, comprises:

[0079] determining whether a maximum iteration number is reached or the decoding code word sequence satisfies the check equation;

[0080] determining that the decoding ends after any one of the above conditions is met, and storing the decoding code word sequence to a decoding result storage;

[0081] Otherwise, a new round of information iteration update is continued.

[0082] Specifically, the decoding result needs to be checked at the end of each iteration. Specifically, it is determined whether an iteration stop condition is met during the iteration process, and the iteration number reaches a maximum l max or the decoding sequence satisfies all the check equations, that is, c x H T = 0. If one of the conditions is met, the decoding ends, and the decoding result is stored to the decoding result storage; if the end condition is not met, a new round of information update needs to be performed in the next iteration, and the current layer jth variable node posteriori LLR information L (l,k) (Q j ) is taken as the posteriori LLR information L (l-1,k) (Q j ) of the jth variable node of the previous layer.

[0083] Compared with the conventional decoder, the application realizes the check matrix preprocessing and the fast cyclic shift operation, speeds up the decoding, and improves the throughput of the decoder. Meanwhile, the storage of the initial variable node LLR information and the posteriori LLR information is integrated in the data storage, the storage of the intra-layer variable node LLR information is omitted, and the resource consumption of the decoder is reduced.

[0084] The protection scope of the FPGA implementation method based on the layered and product decoding algorithm according to the embodiments of the application is not limited to the execution order of the steps listed in the embodiments, and any scheme realized by adding, replacing or replacing the steps of the prior art according to the principle of the application is included in the protection scope of the application.

[0085] The application further discloses a computer readable storage medium, which stores a computer program, and the program is executed to realize the FPGA implementation method based on the layered and product decoding algorithm.

[0086] Those skilled in the art can understand that all or part of the steps in the method for implementing the above-mentioned embodiments can be instructed by a program to complete the processor, and the program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid state disk, magnetic tape, floppy disk, optical disc, and any combination thereof. The storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, digital video disc (DVD)), or a semiconductor medium (for example, solid state disk (SSD)), etc.

[0087] The embodiment of the present application also provides an FPGA implementation system based on the layered and product code algorithm, which can implement the FPGA implementation method based on the layered and product code algorithm. However, the implementation device of the FPGA implementation method based on the layered and product code algorithm includes but is not limited to the structure of the FPGA implementation system based on the layered and product code algorithm listed in the embodiment, and any modification and replacement of the existing technology according to the principle of the present application is included in the protection scope of the present application.

[0088] As Figure 4As shown, in an embodiment, the application also discloses an FPGA implementation system based on layered and sum-product decoding algorithm, which comprises a control unit 1, an address generation unit 2, a posteriori LLR information storage RAM 3, a check node LLR information storage RAM 4, a node information processing unit 5, a check decision unit 6, a check matrix decomposition unit 7, an initial LLR information calculation unit 8 and a decoding result storage 9. The initial LLR information calculation unit 8 is electrically connected with the posteriori LLR information storage RAM 3, used for calculating first LLR information after receiving channel information and storing into the posteriori LLR information storage RAM 3. The node information processing unit 5 is electrically connected with the posteriori LLR information storage RAM 3 and the check node LLR information RAM 4 respectively, used for calculating second LLR information according to the first LLR information and storing respectively. The check matrix decomposition unit 7 is electrically connected with the node information processing unit 5, used for storing offset matrix and address matrix obtained after decomposition of check matrix. The check decision unit 6 is electrically connected with the posteriori LLR information storage RAM 3, used for decision after iterative update and storing decoding code word sequence in the decoding result storage 9 after iteration ends.

[0089] Specifically, after receiving input channel information, the control unit 1 gives decoding start signal and then decomposes check matrix through the check matrix decomposition unit 7 to obtain offset matrix and address matrix and store in corresponding ROM (English full name: Read-Only Memory, Chinese translation: Read-Only Memory) respectively, so that the decomposition of check matrix saves repeated reading and processing time of check matrix when generating LLR information access address, and shortens the waiting time of shift amount before node LLR information cyclic shift operation. Then the address generation unit 2 directly generates LLR information access address according to address matrix stored in the decomposition check matrix ROM, to read out node LLR information from corresponding address of check node information storage RAM and posteriori LLR information storage RAM. Then the node information processing unit 5 updates check node LLR information, variable node LLR information and posteriori LLR information of each layer in channel information, and after updating the last layer, the check decision unit 6 performs decoding decision to obtain decoding code word sequence, and ends decoding after determining that decoding stop condition is satisfied, stores the final decoding code word sequence in the decoding result storage 9, and completes the whole decoding process. Compared with the traditional decoder, the scheme of the application not only realizes check matrix preprocessing and fast cyclic shift operation, but also speeds up the decoding speed and improves the throughput of the decoder. At the same time, the storage of initial variable node LLR information and posteriori LLR information is integrated in the aspect of data storage, the storage of intra-layer variable node LLR information is saved, and the resource consumption of the decoder is reduced.

[0090] The decomposition check matrix unit 7 further comprises an address matrix storage ROM 71 and an offset matrix storage ROM 72 for storing the address matrix and the offset matrix of the check matrix after preprocessing, respectively.

[0091] In an embodiment, the node information processing unit 5 comprises a variable node information processing module 51 for calculating variable node LLR information, a check node information processing module 52 for calculating check node LLR information, an adder 54, a first fast cyclic shifter 53 and a second fast cyclic shifter 55. The input and output terminals of the first fast cyclic shifter 53 are electrically connected to the variable node processing module 51 and the check node processing module 52, respectively, for cyclically shifting the variable node LLR information transmitted from the variable node to the check node according to the order of reading the check node LLR information. The input and output terminals of the second fast cyclic shifter 55 are electrically connected to the check node information processing module 52 and the check node LLR information storage RAM 4, respectively, for reversely cyclically shifting the check node LLR information according to the order of reading the variable node and storing the check node LLR information into the check node LLR information storage RAM 4. The adder 54 is electrically connected to the variable node information processing module 51 and the check node information processing module 52 for calculating posteriori LLR information according to the variable node LLR information and the check node LLR information.

[0092] The first fast cyclic shifter 53 and the second fast cyclic shifter 55 can quickly complete the cyclic shifting of any order square matrix according to any offset. The matrix is simultaneously left shifted and right shifted in one clock cycle and then selected, which can greatly save the time required for sequentially cyclically shifting the matrix data. The flexibility ensures the parallel processing of multiple matrix cyclic shift operations and reduces the complexity of matrix shifting due to different offsets.

[0093] In the embodiment, the variable node LLR information transmitted from the variable node to the check node is first cyclically shifted according to the order of reading the check node LLR information for the check node to calculate the check node LLR information transmitted from the check node to the variable node. The LLR information needs to be reversely cyclically shifted according to the order of reading the variable node and stored into the check node LLR information storage RAM 4, which ensures that the variable node LLR information and the check node LLR information read from the RAM in the second iteration calculation of the LLR information correspond to each other (corresponding to the fact that the positions of 1 in the check matrix CPM correspond to the LLR information transmission between the corresponding variable node and check node, and the positions of 0 in the check matrix correspond to no LLR information transmission between the two nodes)

[0094] As Figure 5As shown, in an embodiment, the fast cyclic shifter 53 comprises a shift controller 531, a left shift module 532, a right shift module 533 and a selection module 534, the shift controller 531 generates a shift control signal and a shift number after receiving the variable node LLR information, the shift controller 531 is electrically connected with the left shift module 532 and the right shift module 533 respectively, to perform left shift and right shift on the variable node LLR information respectively to obtain left shift result and right shift result, the selection module 534 is electrically connected with the left shift module 532 and the right shift module 533, for selecting the left shift result or the right shift result as a shift result according to the shift control signal.

[0095] In several embodiments provided by the present application, it should be understood that the disclosed system, device or method can be implemented in other manners. For example, the embodiments of the device described above are merely schematic, and the division of modules / units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of modules or units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different modules / units can be indirect couplings or communication connections through some interfaces, devices or modules / units, and can be electrical, mechanical or in other forms.

[0096] The modules / units described as separated components can or can not be physically separated, and the components displayed as modules / units can or can not be physical modules, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the modules / units can be selected according to actual needs to achieve the purposes of the embodiments of the present application. For example, the functional modules / units in the embodiments of the present application can be integrated in one processing module, or can be physically separated, or two or more modules / units can be integrated in one module / unit.

[0097] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0098] The descriptions of the corresponding flow or structure of each of the above figures are each focused, and the parts not described in detail in a certain flow or structure can be referred to the related description of other flow or structure.

[0099] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present application should be covered by the claims of the present application.

Claims

1. An FPGA implementation method based on a hierarchical sum-product decoding algorithm, characterized in that, The method includes the following steps: Obtain channel messages and preprocess the parity check matrix of the QC-LDPC code to obtain preprocessed information; The preprocessing of the QC-LDPC code parity-check matrix to obtain preprocessed information includes: Obtain the parity check matrix from the QC-LDPC code; The zero matrix in the parity check matrix is ​​filtered out, and the filtered parity check matrix is ​​compressed to obtain the offset matrix and the address matrix; In this process, there is no information transmission or message update between the check nodes and variable nodes in the zero matrix during the decoding process. The offset matrix is ​​used to store the cyclic shift amount corresponding to each row of the check matrix. The address matrix is ​​composed of the column number of the check matrix corresponding to each cyclic permutation matrix. The number of rows in the offset matrix and the address matrix are the same as the number of rows in the check matrix. The number of columns in the offset matrix and the address matrix are the same as the maximum row weight in the check matrix. The row weight is the number of non-negative values ​​in each row of the check matrix. After initializing the channel messages, the node LLR information is updated and stored according to the preprocessed information, including: The channel message is initialized to obtain the first LLR information; The second LLR information of each layer node in each iteration is updated based on the first LLR information. The second LLR information includes the LLR information of the verification node, the posterior LLR information, and the LLR information of the variable node. The verification node LLR information and the a posteriori LLR information in the second LLR information are stored in the memory according to the address matrix, and the variable node LLR information is stored in the order in which the verification node reads the information. Update the second LLR information of each layer node in each iteration based on the first LLR information, including: The verification matrix is ​​layered by row, and a decoding strategy of intra-layer parallelism and inter-layer serialism is used for decoding to obtain the verification node LLR information and variable node LLR information transmitted between the variable node and the verification node in each layer. The posterior LLR information is calculated based on the LLR information of the verification node and the LLR information of the variable node in each layer; The calculation process of the verification node LLR information, the variable node LLR information, and the posterior LLR information satisfies the following second formula: ； in, It is the current iteration number. It is the current floor number. Let represent the set of variable nodes connected to the i-th check node, excluding the j-th variable node. This represents the external information passed from the j-th variable node to the i-th check node. This represents the set of variable nodes connected to the i-th check node. Indicates the number of iterations after the current layer is updated. The variable node is passed to the first... LLR information for each verification node's variable node. It is the next level Posterior LLR information for each variable node, It is the last iteration number The verification node sends to the first LLR information for each variable node's check node. It is the th iteration after the current layer is updated. The verification node transmits to the first... LLR information for each variable node's check node. For the first After the layer update, the first Posterior LLR information for each variable node, express Except for the first The set of variable nodes other than the 1 variable node, It is a symbolic function. , Variables representing functions; Decoding and decision-making are performed after calculating and updating the a posteriori LLR information of the last layer; Once the preset conditions are met, the decoding ends, and the decoded result is stored.

2. The FPGA implementation method based on the hierarchical sum-product decoding algorithm according to claim 1, characterized in that, The initialization process of the channel message to obtain the first LLR information includes: The initial LLR information of each variable node and check node in the channel message before the iteration begins is calculated using the first formula. The first formula satisfies the following condition: ； in, The initial LLR information of the channel is transmitted to the j-th variable node. The initial LLR information of the check node is passed from the i-th check node to the j-th variable node. Indicates the received channel message The posterior probability information corresponding to the transmitted codeword being 0 or 1. This represents the external information passed from the i-th check node to the j-th variable node. This represents the variance of the Gaussian noise in the channel.

3. The FPGA implementation method based on the hierarchical sum-product decoding algorithm according to claim 1, characterized in that, The verification node LLR information is stored in the verification node LLR information storage RAM, the a posteriori LLR information is stored in the a posteriori LLR information storage RAM, and the variable node LLR information is registered in the order in which the verification node information is read by a fast cyclic shifter.

4. The FPGA implementation method based on the hierarchical sum-product decoding algorithm according to claim 1, characterized in that, The decoding decision after calculating and updating the posterior LLR information of the last layer includes: After calculating the posterior LLR information of the last layer, it is determined that the posterior LLR information of each layer has been updated. The decoded codeword sequence is obtained by making a decision on the posterior LLR information of the current layer.

5. The FPGA implementation method based on the hierarchical sum-product decoding algorithm according to claim 4, characterized in that, The decoding process ends after the preset conditions are met, and the decoded result is stored, including: Determine whether the maximum number of iterations has been reached or whether the decoded codeword sequence satisfies the check equation; After determining that any of the above conditions are met, the decoding is considered complete, and the decoded codeword sequence is stored in the decoding result memory. Otherwise, continue with a new round of information iteration and updates.

6. An FPGA implementation system based on a hierarchical sum-product decoding algorithm, characterized in that, The system includes a control unit, an address generation unit, a posterior LLR information storage RAM, a check node LLR information storage RAM, a node information processing unit, a check decision unit, a check matrix decomposition unit, an initial LLR information calculation unit, and a decoding result memory. The initial LLR information calculation unit is electrically connected to the posterior LLR information storage RAM and is used to calculate first LLR information and store it in the posterior LLR information storage RAM after receiving a channel message. The node information processing unit is electrically connected to both the posterior LLR information storage RAM and the check node LLR information RAM and is used to calculate second LLR information based on the first LLR information and store it respectively. The check matrix decomposition unit is electrically connected to the node information processing unit and is used to store the offset matrix and address matrix obtained after decomposing the check matrix. The check decision unit is electrically connected to the posterior LLR information storage RAM and is used to make a decision after iterative update and store the decoded codeword sequence in the decoding result memory after the iteration ends. The node information processing unit includes a variable node information processing module, a verification node information processing module, an adder, a first fast cyclic shifter, and a second fast cyclic shifter. The variable node information processing module is used to calculate the variable node LLR information, and the verification node information processing module is used to calculate the verification node LLR information. The input and output terminals of the first fast cyclic shifter are electrically connected to the variable node processing module and the verification node processing module, respectively, and are used to cyclically shift the variable node LLR information transmitted from the variable node to the verification node according to the order in which the verification node reads the LLR information. The input and output terminals of the second fast cyclic shifter are electrically connected to the verification node information processing module and the verification node LLR information storage RAM, respectively, and are used to perform reverse cyclic shifting of the verification node LLR information according to the variable node reading order and store it in the verification node LLR information storage RAM. The adder is electrically connected to the variable node information processing module and the verification node information processing module to calculate the posterior LLR information based on the variable node LLR information and the verification node LLR information. Both the first fast cyclic shifter and the second fast cyclic shifter include a shift controller, a left shift module, a right shift module, and a selection module. After receiving the variable node LLR information, the shift controller generates a shift control signal and a shift number. The shift controller is electrically connected to the left shift module and the right shift module respectively to perform left and right shifts on the variable node LLR information to obtain left shift results and right shift results. The selection module is electrically connected to the left shift module and the right shift module and is used to select the left shift result or the right shift result as the shift result according to the shift control signal.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed, it implements the FPGA implementation method based on the hierarchical and product decoding algorithm as described in any one of claims 1 to 5.

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