Method, device, equipment, medium and program product for optimizing redundant logic of non-AND graph

Abstract

The present invention relates to the technical field of electronic circuit design, and discloses a method, device, equipment, medium and program product for optimizing redundant logic of a non-AND graph, the method comprising: determining a critical path in a first non-AND graph corresponding to a circuit to be optimized; splitting a target node on the critical path, and based on the split target node, converting the first non-AND graph into a second non-AND graph, wherein the target node is a multi-output node and the signal output by the target node is not an output signal of the first non-AND graph; performing redundant optimization based on the second non-AND graph, and obtaining a target non-AND graph corresponding to the optimized circuit to be optimized. The present invention can effectively expand the optimization range, so that the non-AND graph redundant logic optimization method can be effectively applied to large-scale non-AND graph optimization.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuit design, and in particular to a method, device, equipment, medium and program product for optimizing redundant logic of a NAND graph. Background Art

[0002] The And Inverter Graph (AIG) optimization method based on redundant logic optimization has a wide range of application scenarios in the field of circuit design and optimization. For example, in digital circuit design, the And Inverter Graph optimization method can be used to design and optimize digital circuits such as integrated circuits and processors. The And Inverter Graph is a form of expression of Boolean functions, which is often used in the field of logic optimization. It can express complex Boolean functions in a more concise and easier to optimize form. The use of this graphical structure can help designers achieve higher performance and smaller area in the design process of logic circuits.

[0003] Classic NAND graph optimization methods often start from the structure of the NAND graph and try to replace the subgraphs in the NAND graph based on the pre-generated NAND graph library, so as to achieve the optimization effect of reducing the number of nodes and logic levels of the NAND graph. However, due to its high time complexity, the existing NAND graph redundant logic optimization methods may become infeasible or take too long to run for large-scale NAND graphs (the scale is measured by the number of input signals and the number of nodes. The more input signals, the larger the scale; the more nodes, the larger the scale). Therefore, in practical applications, they can often only be effectively used on small-scale NAND graphs. Summary of the invention

[0004] In view of this, the present invention provides a method, device, equipment, medium and program product for optimizing redundant logic of NAND graph to solve the problem in the prior art that it is difficult to be effectively used on large-scale NAND graph.

[0005] In a first aspect, the present invention provides a method for optimizing redundant logic of a NAND graph, the method comprising:

[0006] Determine a critical path in the first NAND graph corresponding to the circuit to be optimized;

[0007] Splitting the target node on the critical path, and based on the split target node, converting the first NAND graph into a second NAND graph, wherein the target node is a multi-output node and the signal output by the target node is not the output signal of the first NAND graph;

[0008] Redundancy optimization is performed based on the second NAND graph to obtain a target NAND graph corresponding to the optimized circuit to be optimized.

[0009] A redundant logic optimization method for a NAND graph provided in this embodiment splits the nodes of the critical path before optimization, thereby expanding the optimization scope, so that the redundant logic optimization method for the NAND graph can be effectively applied to large-scale NAND graph optimization.

[0010] In an optional implementation manner, determining a critical path in a first NAND graph corresponding to the circuit to be optimized includes:

[0011] Calculate the actual level and the required level corresponding to each node in the first non-graph;

[0012] Based on the actual number of levels and the required number of levels, calculate the node margin corresponding to each node one by one;

[0013] The path with all node slack equal to zero is identified as the critical path.

[0014] In this embodiment, by calculating the difference between the actual level and the required level of each node in the first NAND graph, the importance of each node in the logic can be accurately evaluated, which helps to improve the accuracy of determining the critical path, thereby improving the logic optimization efficiency of the NAND graph.

[0015] In an optional implementation, the target nodes on the critical path are split, and based on the split target nodes, the first NAND graph is converted into a second NAND graph, including:

[0016] Copy the target node and use the copied target node as the copy node;

[0017] Convert other nodes connected to the output terminal of the target node in the first NAND graph to be connected to the copy node, wherein the other nodes are nodes other than the nodes connected to the output terminal of the target node on the critical path;

[0018] Determine whether the target node is also a multi-output node;

[0019] When the target node is still a multi-output node, continue to copy the target node, and continue to convert the nodes connected to the output end of the target node to be connected to the copy node, so that there is only a single output node on the critical path;

[0020] The converted first NOT-AND graph is used as the second NOT-AND graph.

[0021] In this embodiment, by splitting the target nodes on the critical path, and converting the first NAND graph into a second NAND graph based on the split copy nodes, and then performing redundancy optimization based on the second NAND graph, the complex logic paths can be effectively reduced, thereby improving the optimization efficiency. At the same time, the optimization scope can be effectively expanded, so that the NAND graph redundant logic optimization method can be effectively applied to large-scale NAND graph optimization.

[0022] In an optional implementation, performing redundancy optimization based on the second NAND graph to obtain an optimized target NAND graph corresponding to the circuit to be optimized includes:

[0023] Step S1, inputting the first NAND graph and the second NAND graph into a pre-built XOR model simultaneously;

[0024] Step S2, determining an object edge in the second AND-NOT graph, wherein the object edge is any edge in the second AND-NOT graph;

[0025] Step S3, setting the input of the object edge to a first preset value, and performing random simulation;

[0026] Step S4, determining whether the random simulation result is a second preset value;

[0027] Step S5, when the random simulation result is a second preset value, determining the object edge as a non-redundant edge; when the random simulation result is not the second preset value, determining the object edge as a suspected redundant edge;

[0028] Step S6, performing a redundancy check based on the suspected redundant edges;

[0029] Step S7, repeating the above steps S2 to S6 until all object edges in the second AND-NOT graph are traversed;

[0030] Step S8, merging nodes of the second NAND graph after the redundancy check to obtain a target NAND graph corresponding to the circuit to be optimized.

[0031] In this embodiment, the input is a first AND-NON graph to be optimized, and the output is an optimized target AND-NON graph. Based on the input first AND-NON graph, the critical path of the first AND-NON graph is first found, and then the multiple output nodes on the critical path are split to obtain a second AND-NON graph containing split nodes. Next, a random simulation is performed based on the second AND-NON graph containing the split nodes, and all determined non-redundant edges are excluded, and the remaining ones are possible redundant edges. Finally, a redundancy check is performed on all possible redundant edges, and corresponding optimization is performed on the determined redundant edges, and after all optimizations are completed, the remaining split nodes are merged again to obtain the optimized target AND-NON graph. This can effectively expand the optimization scope, so that the AND-NON graph redundant logic optimization method can be effectively applied to large-scale AND-NON graph optimization.

[0032] In an optional implementation, performing a redundancy check based on suspected redundant edges includes:

[0033] Create a simulation window corresponding to each suspected redundant edge;

[0034] Based on the simulation window, build a simulation XOR device;

[0035] Perform random simulation on the corresponding simulation window based on the simulation XOR;

[0036] When the simulation result is a third preset value, determining the suspected redundant edge as a non-redundant edge;

[0037] When the simulation result is not the third preset value, solving the Boolean satisfiability problem of the simulation XOR device;

[0038] When the solution result is satisfiable, the suspected redundant edge is determined to be a non-redundant edge;

[0039] Based on the non-redundant edges, the redundant edges in the second AND-NOT graph are determined and removed.

[0040] In this embodiment, by simulating the XOR random simulation and combining it with the redundancy check method of the SAT solver, non-redundant edges can be accurately identified, thereby improving the accuracy of optimization, reducing the misjudgment rate, and ensuring the reliability of the design.

[0041] In an optional implementation, creating a simulation window corresponding to each suspected redundant edge includes:

[0042] Determine the output and input levels;

[0043] Determine the input nodes of suspected redundant edges;

[0044] Based on the input node, the output direction series are traversed in the output direction to determine the output node of the window;

[0045] Based on the output node, the input direction series are traversed in the input direction to determine the input node of the window.

[0046] In this embodiment, the balance between optimization effect and optimization duration can be achieved by controlling the size of the window. Generally, the larger the optimization window, the better the optimization effect and the longer the optimization duration. In this embodiment, the operation duration and optimization effect can be balanced by adjusting the size of the window.

[0047] In a second aspect, the present invention provides a device for optimizing redundant logic of a non-AND graph, the device comprising:

[0048] A determination module, used to determine a critical path in a first NAND graph corresponding to the circuit to be optimized;

[0049] A splitting module is used to split the target node on the critical path, and based on the split target node, convert the first NAND graph into a second NAND graph, wherein the target node is a multi-output node and the signal output by the target node is not the output signal of the first NAND graph;

[0050] The redundancy optimization module is used to perform redundancy optimization based on the second NAND graph to obtain a target NAND graph corresponding to the optimized circuit to be optimized.

[0051] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the NAND graph redundant logic optimization method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0052] In a fourth aspect, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the NAND graph redundant logic optimization method of the first aspect or any corresponding embodiment thereof.

[0053] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the NAND graph redundant logic optimization method of the first aspect or any corresponding embodiment thereof.

[0054] It should be noted that, since the NAND graph redundant logic optimization device, computer equipment and computer-readable storage medium provided by the present invention correspond to the NAND graph redundant logic optimization method described above, therefore, for the beneficial effects of the NAND graph redundant logic optimization device, computer equipment and computer-readable storage medium, please refer to the description of the corresponding beneficial effects of the NAND graph redundant logic optimization method described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 is a flow chart of a method for optimizing redundant logic of a NAND graph according to an embodiment of the present invention;

[0057] Figure 2 is a schematic diagram of a NAND graph according to an embodiment of the present invention;

[0058] Figure 3 is a schematic diagram of calculating the actual number of stages and the required number of stages according to an embodiment of the present invention;

[0059] Figure 4 is a schematic diagram of target node splitting according to an embodiment of the present invention;

[0060] Figure 5 is a schematic diagram of an XOR model according to an embodiment of the present invention;

[0061] Figure 6 is a schematic diagram of a redundancy optimization process according to an embodiment of the present invention;

[0062] Figure 7 is a schematic diagram of a redundancy check process according to an embodiment of the present invention;

[0063] Figure 8 is a schematic diagram of determining the maximum no-fan-out cone according to an embodiment of the present invention;

[0064] Fig. 9 is a schematic diagram of window construction according to an embodiment of the present invention;

[0065] Fig.10 is a structural block diagram of a device for optimizing redundant logic of a NAND graph according to an embodiment of the present invention;

[0066] Fig.11 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0068] According to an embodiment of the present invention, an embodiment of a method for optimizing redundant logic of a non-graph is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0069] In this embodiment, a method for optimizing redundant logic of a non-AND graph is provided, which can be executed by a server, a terminal, a mobile terminal, etc. Figure 1 is a flowchart of a method for optimizing redundant logic of a NAND graph according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0070] Step S101, determining a critical path in a first NAND graph corresponding to a circuit to be optimized;

[0071] It should be noted that the AIG described in the present invention is an And Inverter Graph, which is a graph that can be used to describe a Boolean function, namely, the AND-NON graph in this embodiment. Figure 2 The figure shows a schematic diagram of a NAND graph, which consists of input signals, output signals, nodes and edges. Each node is an AND gate, and each edge can be added with a NOT logic. Figure 2 As shown, a, b, c, d are input signals, and o is the output signal. Nodes 1, 2, and 3 are all AND gates (AND logic gates). The lines between signals and nodes and between nodes are edges. The solid black dots on the edges represent the inversion of the signals on the edges (non-logical). For example, the signal between node 1 and node 3 is an inverted edge. For example: assuming that the output signal of node 1 is 0, the input signal to node 3 becomes 1 after passing through the inverted edge.

[0072] In this embodiment, it is necessary to first determine the first NAND graph that needs to be optimized, and then determine the critical path in the first NAND graph. All nodes on the critical path must satisfy the margin of zero.

[0073] Step S102, split the target node on the critical path, and based on the split target node, convert the first NAND graph into a second NAND graph, wherein the target node is a multi-output node and the signal output by the target node is not the output signal of the first NAND graph.

[0074] In this embodiment, the target node may be split by duplicating the target node and then transferring multiple nodes connected to the target node to the duplicate nodes respectively, which can effectively expand the optimization scope.

[0075] Step S103 , performing redundancy optimization based on the second NAND graph to obtain a target NAND graph corresponding to the optimized circuit to be optimized.

[0076] Redundancy optimization is to remove unnecessary nodes or edges in the second NAND graph. The number of nodes and the number of logic levels in the optimized target NAND graph will be significantly less than or equal to the number of nodes and the number of logic levels in the first NAND graph to be optimized, and can be effectively used on large-scale NAND graphs. In this embodiment, the NAND graph is optimized entirely from the perspective of redundant logic, so classic optimization methods, such as optimization methods based on subgraph replacement, can be used to achieve better optimization effects.

[0077] In the embodiment, a redundant logic optimization method for a non-AND graph is provided, which splits the nodes of the critical path before optimization, expands the optimization range, and enables the redundant logic optimization method for the non-AND graph to be effectively applied to large-scale non-AND graph optimization. By comparing the non-AND graphs before and after optimization, there may be a reduction in node outputs on the critical path.

[0078] In this embodiment, by splitting the multi-output nodes of the critical path before optimization, the optimization scope is expanded to a greater extent, and at the same time, it is ensured that the expanded optimization scope acts on the critical path, thereby greatly increasing the possibility of optimizing the number of logic levels (the optimization of the number of logic levels often brings greater benefits than the optimization of the number of nodes). By splitting the multi-output nodes on the critical path, complex logical dependencies can be better handled, and unnecessary logical paths can be effectively reduced, thereby improving operating efficiency and speed.

[0079] In some optional implementations, the above step S101, i.e., determining a critical path in the first NAND graph corresponding to the circuit to be optimized, includes:

[0080] Calculate the actual level and the required level corresponding to each node in the first non-graph;

[0081] Based on the actual number of levels and the required number of levels, calculate the node margin corresponding to each node one by one;

[0082] The path with all node slack equal to zero is identified as the critical path.

[0083] Specifically, the margin can be calculated by subtracting the actual level from the required level. The actual level of a node in the non-AND graph is the maximum level of all its input nodes plus 1. The actual level of a node whose input is only connected to the input signal of the non-AND graph is 0. The required level of a node in the non-AND graph is the minimum required level of all its output nodes minus 1. The required level of a node whose output is only connected to the output signal of the non-AND graph is the maximum actual level of the non-AND graph.

[0084] Reference Figure 3As shown in the figure, it is a specific example of calculating the actual level and the required level. Among them, the non-AND graph has 6 input signals: a, b, c, d, e, f, and two output signals: o1 and o2. First, the actual level of each node in the non-AND graph is calculated according to the topological order. All inputs of node 1 are connected to the input signal, so the actual level of node 1 is 0; similarly, the actual level of node 2 is 0. The actual level of node 3 is the maximum level of all its input nodes plus 1, that is, 1; similarly, the actual level of node 4 is also 1. The actual level of node 5 is equal to the maximum level of all its input nodes plus 1, that is, 2. After calculating the actual level, the required level of each node can be calculated according to the reverse topological order. First, the outputs of node 4 and node 5 are only connected to the output signal of the non-AND graph. Therefore, the required level of node 4 and node 5 is the maximum actual level, that is, 2; then the required level of node 2 and node 3 is the required level of node 5 minus 1, that is, 1. The required level of node 1 is the minimum of the required levels of nodes 3 and 4 minus 1, that is, the required level of node 3 minus 1, which is 0. After all the calculations of the actual levels and the required levels are completed, the node with a result of 0 is the node with a margin of 0, that is, the node on the critical path. Figure 3 The nodes on the critical path are node 1, node 3, and node 5.

[0085] In this embodiment, by calculating the difference between the actual level and the required level of each node in the first NAND graph, the importance of each node in the logic can be accurately evaluated, which helps to improve the accuracy of determining the critical path, thereby improving the logic optimization efficiency of the NAND graph.

[0086] In some optional implementations, the above step S102, i.e., splitting the target nodes on the critical path, and converting the first NAND graph into a second NAND graph based on the split target nodes, includes:

[0087] Step S1021, copy the target node, and use the copied target node as the copy node;

[0088] Step S1022, converting other nodes in the first AND-NOT graph connected to the output terminal of the target node to be connected to the copy node, wherein the other nodes are nodes other than the nodes on the critical path connected to the output terminal of the target node;

[0089] Step S1023, determining whether the target node is still a multi-output node;

[0090] Step S1024: if the target node is still a multi-output node, continue to copy the target node, and continue to convert the node connected to the output end of the target node to be connected to the copy node, so that there is only a single output node on the critical path;

[0091] Step S1025, using the converted first NAND graph as the second NAND graph.

[0092] After determining the critical path, it is necessary to split the multi-output nodes on the critical path, that is, the nodes that output signals to multiple nodes and do not output output signals. The splitting method can be to copy the multi-output nodes and transfer all the multiple output edges of the multi-output nodes except the edges connected to the critical path nodes to the copy nodes. If there are still multiple outputs after the transfer, the node is copied according to the number of outputs. Each time it is copied, one output is transferred to the copy node until all nodes on the critical path meet the following conditions: If the output is only connected to the node, then it must be connected to only one node.

[0093] Reference Figure 4 The figure shows a specific example of target node splitting, where the first NAND graph on the far left has four input signals a, b, c, d and two output signals o1 and o2. There are two critical paths, {node 1, node 2, node 5} and {node 1, node 3, node 5}. The output signal of target node 1 on the critical path is output to multiple nodes {node 2, node 3, node 4}, so target node 1 needs to be split. Target node 1 can be copied to obtain copy node 6, and all nodes in the output edge of target node 1 except those connected to the critical path nodes can be transferred to copy node 6 to obtain Figure 4 The AIG shown in the middle part. After the transfer, the target node 1 still has two output edges left, and the node needs to be replicated again. Each replication moves one output edge connecting the key path node to the replication node until there are no multiple output nodes on the key path in the AIG. That is, the target node 1 is replicated to obtain the replication node 7, and the edge connecting the target node 1 and node 2 is assigned to the replication node 7, and the Figure 4 The resulting graph shown on the far right is the second NOT graph.

[0094] In this embodiment, by splitting the target nodes on the critical path, and converting the first NAND graph into a second NAND graph based on the split copy nodes, and then performing redundancy optimization based on the second NAND graph, the complex logic paths can be effectively reduced, thereby improving the optimization efficiency. At the same time, the optimization scope can be effectively expanded, so that the NAND graph redundant logic optimization method can be effectively applied to large-scale NAND graph optimization.

[0095] In some optional implementations, performing redundancy optimization based on the second NAND graph to obtain an optimized target NAND graph corresponding to the circuit to be optimized includes:

[0096] Step S1, inputting the first NAND graph and the second NAND graph into a pre-built XOR model simultaneously;

[0097] Step S2, determining an object edge in the second AND-NOT graph, wherein the object edge is any edge in the second AND-NOT graph;

[0098] Step S3, setting the input of the object edge to a first preset value, and performing random simulation;

[0099] Step S4, determining whether the random simulation result is a second preset value;

[0100] Step S5, when the random simulation result is a second preset value, determining the object edge as a non-redundant edge; when the random simulation result is not the second preset value, determining the object edge as a suspected redundant edge;

[0101] Step S6, performing a redundancy check based on the suspected redundant edges, determining whether the suspected redundant edges are non-redundant edges, and removing the redundant edges;

[0102] Step S7, repeating the above steps S2 to S6 until all object edges in the second AND-NOT graph are traversed;

[0103] Step S8, merging nodes of the second NAND graph after the redundancy check to obtain a target NAND graph corresponding to the circuit to be optimized.

[0104] After the target node is split, we can start to perform random simulation on each edge in the obtained NAND graph to filter out all non-redundant edges. A XOR model is required for random simulation. The XOR model can be found in Figure 5 As shown, an XOR model consists of an original NAND graph, a copy NAND graph, a series of XOR gates and an OR gate. The difference between the original NAND graph and the copy NAND graph is that the copy NAND graph changes the input of the object edge to a constant value (0 or 1), which is the first preset value in this embodiment. Each group of corresponding outputs between the original NAND graph and the copy NAND graph is connected to an XOR gate. If the two output values ​​are different, the output of the XOR gate is 1. The outputs of all XOR gates are connected to an OR gate, which means that when any group of corresponding output signal values ​​are different, the output signal o of the OR gate is 1, which is the second preset value in this embodiment.

[0105] The random simulation process starts with randomly assigning values ​​to each input signal based on the XOR device, and observing whether the value of o is 1. Once the value of o is 1, it can be determined that the edge is not a redundant edge, and the next edge will be traversed. After excluding all non-redundant edges, all the remaining edges are possible redundant edges, that is, suspected redundant edges. Then, all suspected redundant edges are traversed for redundancy checks, and the confirmed redundant edges are optimized and node merged accordingly.

[0106] Specifically, after all optimizations are completed, the nodes that were split before the optimization started and have not been optimized are merged. Figure 4 Node 6 is optimized, but nodes 1 and 7 are not optimized, then node 7 can be merged into node 1 again. In addition, an important significance of node splitting in this embodiment is to expand the optimization scope, especially the optimization on the critical path. As mentioned above, when the input of an edge can be replaced by a constant value 1, the node connected to the output of the edge can be deleted. At this time, if the deleted node is a node on the critical path, the logical level of the critical path will be reduced by 1. Here, we still use Figure 4 For example, assuming that the input signal a can be equivalent to a constant value 1 for the output from node 1 to node 2 and node 3, but cannot be equivalent to a constant value 1 for the output from node 1 to node 4 (in simple terms, construct an XOR device, the XOR gate values ​​corresponding to the outputs of node 2 and node 3 are both 0, and only the XOR gate value corresponding to the output of node 4 is 1, resulting in the XOR result being 1), resulting in the edge connecting the input signal a and node 1 not being equivalent to a constant value. However, if node 1 is split, then node 1 and node 7 can be optimized, thereby reducing the number of logical levels of the entire AIG.

[0107] Reference Figure 6 As shown, all the suspected redundant edges in the second AND-NOT graph are traversed one by one, and each suspected redundant edge traversed is checked for redundancy. If it is found to be indeed redundant, it is optimized until all the suspected redundant edges are traversed. Finally, the nodes are merged, and the node merging at this time mainly merges the nodes on the previously split critical path.

[0108] In this embodiment, the input is a first AND-NON graph to be optimized, and the output is an optimized target AND-NON graph. Based on the input first AND-NON graph, the critical path of the first AND-NON graph is first found, and then the multiple output nodes on the critical path are split to obtain a second AND-NON graph containing split nodes. Next, a random simulation is performed based on the second AND-NON graph containing the split nodes, and all determined non-redundant edges are excluded, and the remaining ones are possible redundant edges. Finally, a redundancy check is performed on all possible redundant edges, and corresponding optimization is performed on the determined redundant edges, and after all optimizations are completed, the remaining split nodes are merged again to obtain the optimized target AND-NON graph. This can effectively expand the optimization scope, so that the AND-NON graph redundant logic optimization method can be effectively applied to large-scale AND-NON graph optimization.

[0109] In some optional implementations, performing a redundancy check based on suspected redundant edges includes:

[0110] Create a simulation window corresponding to each suspected redundant edge;

[0111] Based on the simulation window, build a simulation XOR device;

[0112] Perform random simulation on the corresponding simulation window based on the simulation XOR;

[0113] When the simulation result is a third preset value, determining the suspected redundant edge as a non-redundant edge;

[0114] When the simulation result is not the third preset value, solving the Boolean satisfiability problem of the simulation XOR device;

[0115] When the solution result is satisfiable, the suspected redundant edge is determined to be a non-redundant edge;

[0116] Based on the non-redundant edges, the redundant edges in the second AND-NOT graph are determined and removed.

[0117] The specific process of the redundancy check described in this embodiment can be referred to Figure 7 As shown, a simulation window is constructed based on each suspected redundant edge, and then a simulation XOR is constructed based on the constructed simulation window, and random simulation is performed on the simulation XOR. If there is a simulation result of 1, that is, the third preset value, it proves that the edge must not be redundant, otherwise the simulation XOR is solved by SAT, which is the solution of the Boolean satisfiability problem, used to determine whether the Boolean formula has a solution, that is, whether there is a set of variable assignments that make the formula valid. If the solution result is satisfiable, it proves that there is a set of input signals that make the output value of the XOR 1, which means that the edge must not be equivalent to a constant signal, which means that it must not be redundant.

[0118] The SAT solution described in this embodiment uses an open source SAT solving tool. Its input is an expression of a product of sums, for example: (a+b)(b+c). If the SAT solution result is not satisfied, it means that there is no set of input signals that make the result of the XOR device 1, which means that the input of the edge can be equivalent to a constant, which means logical redundancy. On the contrary, if the SAT solution result is satisfied, it means that there is a set of input signals that make the result of the XOR device 1, that is, the input of the edge cannot be equivalent to a constant, and then the logic of the edge is not redundant. In addition, another open source tool can be used in this embodiment to convert AIG into an expression of a product of sums as the input of the SAT solver.

[0119] When an edge is determined to be logically redundant, the corresponding optimization will be performed immediately. During the optimization, the edge will be deleted first. After that, if the input of an edge is equivalent to the constant value 0, the output of the node to which the edge outputs must also be the constant value 0 (all nodes in AIG are two-input AND gates. Once one input is 0, its output must be 0). Therefore, the node and its corresponding MFFC (maximum fan-out cone) can be deleted, and the value of 0 will continue to be passed to the output direction. If the input of an edge is equivalent to the constant value 1, the output of the node to which the edge outputs must be the same as the other input signal. Therefore, the node can be directly deleted and the other input of the node can be directly connected to the output.

[0120] The MFFC described in this embodiment can refer to Figure 8 A MFFC consists of a root node and all its transitive fan-in nodes without external fan-out (a transitive fan-in node is a node that has a path with the root node). Figure 8 For example, all of its transitive fan-in nodes are node 6, node 9, and node 0. However, node 9 has an external fan-out to node 5 (external fan-out means that the fan-out node is not the transitive fan-in of the root node), so node 9 is not counted in the MFFC with node 3 as the root node. The MFFC with node 3 as the root node is: {node 3, node 6, node 0}. Similarly, if the MFFC with node 2 as the root node is: {node 2, node 4, node 5, node 8, node 7}.

[0121] The advantage of using MFFC is that if the root node of MFFC can be optimized and removed from AIG, then all nodes in MFFC can be removed from AIG. Figure 8 For example, we can assume Figure 8 Node 3 in the diagram can be removed without affecting the function of the entire AIG. After removing node 3, the output of node 6 will be left floating, which will not affect the function of AIG and can be removed. Similarly, after removing node 6, the output of node 0 will not affect the function of AIG and can be removed from the entire AIG. At this point, all MFFCs with node 3 as the root node are removed from AIG.

[0122] In this embodiment, by simulating the XOR random simulation and combining it with the redundancy check method of the SAT solver, non-redundant edges can be accurately identified, thereby improving the accuracy of optimization, reducing the misjudgment rate, and ensuring the reliability of the design.

[0123] In some optional implementations, creating a simulation window corresponding to each suspected redundant edge includes:

[0124] Determine the output and input levels;

[0125] Determine the input nodes of suspected redundant edges;

[0126] Based on the input node, the output direction series are traversed in the output direction to determine the output node of the window;

[0127] Based on the output node, the input direction series are traversed in the input direction to determine the input node of the window.

[0128] The window construction described in this embodiment includes two constraints, namely the output-direction series and the input-direction series. The specific construction process is: 1. Get the input node of the edge based on the edge; 2. Traverse the output-direction series based on the input node toward its output direction (stop if traversing to the output of AIG), and get the output node of the window; 3. Traverse the input-direction series based on the output node toward its input direction to get the nodes connected to the input node of the window, and the input of these nodes is the input of the window; the construction of the window is completed. It should be noted here that the input-direction series must be greater than the output-direction series, otherwise the window cannot be constructed. The input-direction series and the output-direction series can be set manually. In general, the larger the series setting, that is, the larger the window, the better the optimization effect, but the longer the running time.

[0129] Reference Fig. 9 As shown below, a simple example of window construction is shown. Assume Fig. 9 The thick solid line in is the edge that needs to be verified to be redundant. Then we can first find its input node, which is node 5. Next, we can build a window with an output level of 1 and an input level of 2. Then we can first traverse from node 5 to the output direction to get the output node of the window {node 2, node 3}, and then traverse upward from node 2 and node 3 by 2 levels to get the nodes connected to the input of the window {node 1, node 9, node 8, node 7}. The input of the window is {I0, I1, I2, I3}. So far, we have obtained a window whose input signal is {I0, I1, I2, I3}, and the output signal is the output of node 2 and node 3. The nodes in the entire window are Fig. 9 All nodes except node 0 in .

[0130] In this embodiment, the balance between optimization effect and optimization duration can be achieved by controlling the size of the window. Generally, the larger the optimization window, the better the optimization effect and the longer the optimization duration. In this embodiment, the operation duration and optimization effect can be balanced by adjusting the size of the window.

[0131] The present embodiment provides an AIG optimization method based on redundant logic optimization that can be used for large-scale AIG. First, a global random simulation is used to find certain non-redundant edges, and the remaining ones are possible redundant edges. After that, the possible redundant edges are further checked to determine the redundancy of the edges, and the redundant edges are optimized accordingly. In the present embodiment, all possible redundant edges are only traversed once, and each check of the possible redundant edges is completed based on the generated local window. Assuming that the time consumption of one check is t and the number of edges is n, the time complexity of the present embodiment is only O(nt). In addition, the present embodiment expands the optimization range by special processing of the critical path. In practice, in addition to reducing the number of AIG nodes, the present embodiment can also effectively reduce the number of logical levels of the AIG.

[0132] In this embodiment, a non-graph redundant logic optimization device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0133] This embodiment provides a device for optimizing redundant logic of a non-and graph, such as Fig.10 As shown, including:

[0134] A determination module 201 is used to determine a critical path in a first NAND graph corresponding to the circuit to be optimized;

[0135] A splitting module 202 is used to split the target node on the critical path, and based on the split target node, convert the first NAND graph into a second NAND graph, wherein the target node is a multi-output node and the signal output by the target node is not an output signal of the first NAND graph;

[0136] The redundancy optimization module 203 is used to perform redundancy optimization based on the second NAND graph to obtain a target NAND graph corresponding to the optimized circuit.

[0137] In some optional implementations, the determining module 201 includes:

[0138] The calculation unit is used to calculate the actual level and the required level corresponding to each node in the first AND-NOT graph; based on the actual level and the required level, calculate the node margin corresponding to each node; and determine the path with all node margins being zero as the critical path.

[0139] In some optional implementations, the splitting module 202 includes:

[0140] A split conversion unit is used to copy a target node and use the copied target node as the copy node; convert other nodes connected to the output end of the target node in the first NAND graph to be connected to the copy node, wherein the other nodes are nodes other than those connected to the output end of the target node on the critical path; determine whether the target node is also a multi-output node; if the target node is still a multi-output node, continue to copy the target node, and continue to convert nodes connected to the output end of the target node to be connected to the copy node, so that only a single output node exists on the critical path; and use the converted first NAND graph as the second NAND graph.

[0141] In some optional implementations, the redundancy optimization module 203 includes:

[0142] A redundant optimization unit is used to input a first NAND graph and a second NAND graph into a pre-built XOR model at the same time; determine an object edge in the second NAND graph, wherein the object edge is any edge in the second NAND graph; set the input of the object edge to a first preset value, and perform random simulation; determine whether the random simulation result is a second preset value; when the random simulation result is the second preset value, determine that the object edge is a non-redundant edge; when the random simulation result is not the second preset value, determine that the object edge is a suspected redundant edge; perform redundancy check based on the suspected redundant edge; until all object edges in the second NAND graph are traversed; merge nodes of the second NAND graph after the redundancy check to obtain a target NAND graph corresponding to the circuit to be optimized.

[0143] The redundancy check subunit is used to create a simulation window corresponding to each suspected redundant edge; based on the simulation window, a simulation XOR is constructed; based on the simulation XOR, a corresponding simulation window is randomly simulated; when the simulation result is a third preset value, the suspected redundant edge is determined to be a non-redundant edge; when the simulation result is not the third preset value, a Boolean satisfiability problem is solved for the simulation XOR; when the solution result is satisfiable, the suspected redundant edge is determined to be a non-redundant edge; based on the non-redundant edge, the redundant edges in the second NAND graph are determined, and the redundant edges are eliminated.

[0144] The window creation subunit is used to determine the output-direction series and the input-direction series; determine the input node of the suspected redundant edge; traverse the output-direction series in the output direction based on the input node to determine the output node of the window; traverse the input-direction series in the input direction based on the output node to determine the input node of the window.

[0145] The NAND graph redundant logic optimization device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0146] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0147] The embodiment of the present invention also provides a computer device having the above Fig.10 The NAND diagram shown is a redundant logic optimization device.

[0148] See also Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.11 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.11 A processor 10 is taken as an example.

[0149] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0150] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0151] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0152] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0153] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0154] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0155] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0156] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for optimizing redundant logic of NAND graphs. It is characterized in that The method comprises: Determine the critical path in the first NAND graph corresponding to the circuit to be optimized; wherein the method comprises: calculating the actual level and the required level corresponding to each node in the first NAND graph; calculating the node margin corresponding to each node based on the actual level and the required level; determining the path where all the node margins are zero as the critical path; The target node on the critical path is split, and based on the split target node, the first NAND graph is converted into a second NAND graph, wherein the target node is a multi-output node and the signal output by the target node is not the output signal of the first NAND graph; wherein, it includes: copying the target node, and using the copied target node as the copy node; converting other nodes connected to the output end of the target node in the first NAND graph to be connected to the copy node, wherein the other nodes are nodes other than those connected to the output end of the target node on the critical path; determining whether the target node is also a multi-output node; if the target node is still a multi-output node, continue to copy the target node, and continue to convert nodes connected to the output end of the target node to be connected to the copy node, so that there is only a single output node on the critical path; using the converted first NAND graph as the second NAND graph; Redundancy optimization is performed based on the second NAND graph to obtain an optimized target NAND graph corresponding to the circuit to be optimized; wherein: Step S1, inputting the first NAND graph and the second NAND graph into a pre-built XOR model at the same time; Step S2, determining an object edge in the second AND-NOT graph, wherein the object edge is any edge in the second AND-NOT graph; Step S3, setting the input of the object edge to a first preset value, and performing random simulation; Step S4, determining whether the random simulation result is a second preset value; Step S5, when the random simulation result is a second preset value, determining that the object edge is a non-redundant edge; when the random simulation result is not the second preset value, determining that the object edge is a suspected redundant edge; Step S6, performing a redundancy check based on the suspected redundant edge; Step S7, repeating the above steps S2 to S6 until all the object edges in the second AND-NOT graph are traversed; Step S8, merging nodes of the second AND-NOT graph after the redundancy check to obtain a target AND-NOT graph corresponding to the circuit to be optimized.

2. The method according to claim 1, It is characterized in that The performing redundancy check based on the suspected redundant edge includes: Creating a simulation window corresponding to each of the suspected redundant edges; Based on the simulation window, construct a simulation XOR device; Performing random simulation on the corresponding simulation window based on the simulation XOR device; When the simulation result is a third preset value, determining the suspected redundant edge to be the non-redundant edge; When the simulation result is not the third preset value, solving a Boolean satisfiability problem for the simulation XOR; When the solution result is satisfactory, determining the suspected redundant edge as the non-redundant edge; Based on the non-redundant edges, redundant edges in the second AND-NORMAL graph are determined, and the redundant edges are removed.

3. The method according to claim 2, It is characterized in that The step of creating a simulation window corresponding to each of the suspected redundant edges comprises: Determine the output and input levels; Determining the input node of the suspected redundant edge; Based on the input node traversing the output direction series in the output direction, determining the output node of the window; Based on traversing the input-direction series from the output node to the input direction, an input node of the window is determined.

4. A device for optimizing redundant logic of a non-and graph, It is characterized in that The device comprises: A determination module is used to determine a critical path in a first NAND graph corresponding to the circuit to be optimized; wherein the determination module includes: a calculation unit, used to calculate the actual level and the required level corresponding to each node in the first NAND graph; based on the actual level and the required level, calculate the node margin corresponding to each node; determine the path where all the node margins are zero as the critical path; A splitting module, used for splitting the target node on the critical path, and based on the split target node, converting the first NAND graph into a second NAND graph, wherein the target node is a multi-output node and the signal output by the target node is not the output signal of the first NAND graph; wherein the splitting module includes: a splitting conversion unit, used for copying the target node, and using the copied target node as the copy node; converting other nodes connected to the output end of the target node in the first NAND graph to be connected to the copy node, wherein the other nodes are nodes other than those connected to the output end of the target node on the critical path; judging whether the target node is also a multi-output node; if the target node is still a multi-output node, continuing to copy the target node, and continuing to convert nodes connected to the output end of the target node to be connected to the copy node, so that there is only a single output node on the critical path; using the converted first NAND graph as the second NAND graph; A redundant optimization module, used for performing redundant optimization based on the second AND-NOT graph to obtain a target AND-NOT graph corresponding to the optimized circuit to be optimized; wherein the redundant optimization module includes: a redundant optimization unit, used for simultaneously inputting the first AND-NOT graph and the second AND-NOT graph into a pre-built XOR model; determining an object edge in the second AND-NOT graph, wherein the object edge is any edge in the second AND-NOT graph; setting the input of the object edge to a first preset value and performing random simulation; judging whether the random simulation result is a second preset value; determining that the object edge is a non-redundant edge when the random simulation result is the second preset value; determining that the object edge is a suspected redundant edge when the random simulation result is not the second preset value; performing a redundancy check based on the suspected redundant edges; until all the object edges in the second AND-NOT graph are traversed; merging nodes of the second AND-NOT graph after the redundancy check to obtain a target AND-NOT graph corresponding to the circuit to be optimized.

5. A computer device, It is characterized in that include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the NAND graph redundant logic optimization method described in any one of claims 1-3 by executing the computer instructions.

6. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the NAND graph redundant logic optimization method according to any one of claims 1 to 3.

7. A computer program product, It is characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the NAND graph redundant logic optimization method according to any one of claims 1 to 3.

Images