A hardware fault protection circuit suitable for electric drive systems of new energy vehicles

Abstract

The present invention discloses a hardware fault protection circuit applicable to an electric drive system of a new energy vehicle, comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, wherein the collector of the transistor T1 is connected to a power supply terminal VCC through the resistor R1 and the emitter of the transistor T1 is grounded, and the base of the transistor T1 is electrically connected to the collector of the transistor T2 through the resistor R4. The present invention discloses a hardware fault protection circuit applicable to an electric drive system of a new energy vehicle, and the required components are only 4 transistors and 6 resistors. The cost of the circuit and the layout space of the circuit board are further reduced. The fault latching function is realized by a self-locking circuit constructed by transistors; the fault clearing and fault shielding functions are realized by adding an IO control input at an appropriate position of the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of hardware fault protection, and in particular relates to a hardware fault protection circuit suitable for an electric drive system of a new energy vehicle. Background Art

[0002] New energy electric drive systems are core safety components of new energy vehicles and have high functional safety requirements. General electric drive inverter products need to meet the functional safety level requirements of ASIL-D. Therefore, when high voltage overvoltage, high voltage overcurrent or other driver chip failures occur in the drive circuit part, the electric drive inverter system needs to perform effective and safe fault protection actions to ensure that the product will not suffer serious hardware failures and protect the safety of new energy vehicles.

[0003] Electric drive inverter product fault protection usually includes two levels: hardware and software. Among them, the hardware fault protection action can complete the protection action in the shortest time after the product fails, which is the key to protecting product safety.

[0004] Therefore, the functional design requirements of the hardware fault protection circuit are relatively strict, including at least:

[0005] 1) When a fault occurs, the circuit can latch the fault, that is, after the fault disappears, the fault flag is still valid;

[0006] 2) After the fault disappears, the main control chip (MCU) can clear the fault flag through IO;

[0007] 3) When a fault exists, the MCU cannot clear the fault;

[0008] 4) When a fault exists, the MCU can mask the fault through IO and clear the fault flag.

[0009] The commonly used hardware fault protection circuit solutions are:

[0010] 1) Use complex programmable logic devices (CPLD) to write protection programs internally;

[0011] 2) Use logic chips such as NAND gates, AND gates, latches, etc. to build protection circuits.

[0012] CPLD can realize more complex protection functions, but its cost is high, and special tools are needed to develop CPLD software. In the circuit board test offline link, the CPLD program needs to be installed. Because CPLD requires external resources such as crystal oscillator and power supply, it will take up layout space when designing the circuit board.

[0013] The cost of the protection circuit built with logic chips is lower than that of CPLD, and there is no need to develop a separate program, so this solution is gradually replacing the CPLD solution. However, this solution still requires the use of multiple logic chips, so it still takes up a lot of circuit board layout space and the cost remains at a high level. As the volume requirements and cost reduction requirements of the electric drive system of the whole vehicle become more and more stringent, the number of components and component costs of the hardware fault protection circuit need to be further reduced. Summary of the invention

[0014] The main purpose of the present invention is to provide a hardware fault protection circuit suitable for the electric drive system of new energy vehicles. According to the functional requirements of the hardware fault protection circuit, a new type of extremely simplified circuit scheme is designed. The required devices are only 4 transistors and 6 resistors. The cost of the circuit and the layout space of the circuit board can be further reduced. The fault latching function is realized by a self-locking circuit built by transistors; by adding IO control input at the appropriate position of the circuit, the fault clearing and fault shielding functions are realized.

[0015] To achieve the above objectives, the present invention provides a hardware fault protection circuit suitable for an electric drive system of a new energy vehicle, comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, wherein:

[0016] The collector of the transistor T1 is connected to the power supply terminal VCC through the resistor R1 and the emitter of the transistor T1 is grounded, and the base of the transistor T1 is electrically connected to the collector of the transistor T2 through the resistor R4;

[0017] The base of the transistor T2 is connected to the FLT signal as an external fault signal through the resistor R3, the emitter of the transistor T2 is connected to the power supply terminal VCC through the resistor R2, and the collector of the transistor T2 is grounded through the resistor R5;

[0018] The base of the transistor T3 is connected to the DIS signal as a fault shielding signal output by the MCU, the collector of the transistor T3 is electrically connected to the collector of the transistor T2 through the resistor R6 and is connected to the OE signal as an enable signal output by the protection circuit to the level conversion chip;

[0019] The base of the transistor T4 is connected to the CLR signal serving as a fault clearing signal output by the MCU, and the collector of the transistor T4 is electrically connected to the base of the transistor T1 .

[0020] As a further preferred technical solution of the above technical solution, the hardware fault protection circuit is used for fault latching, fault clearing, failure to clear the fault when the fault exists, and fault shielding, wherein:

[0021] For fault latching, the fault latching is realized by transistor T1 and transistor T2. When an external fault occurs, the FLT signal becomes low level, and transistor T2 is turned on, making the OE signal become high level. Therefore, after the external fault disappears, the FLT signal returns to high level. Since transistor T1 is turned on, transistor T2 is also kept on, so the OE signal maintains high level, and finally the fault latching is realized;

[0022] For fault clearing, when the external fault disappears, the FLT signal returns to a high level, and the MCU outputs a high-level CLR signal, thereby pulling the base of transistor T1 down to GND, turning off transistor T1, and then pulling the base of transistor T2 up to VCC, turning off transistor T2, and the OE signal becomes a low level, finally achieving fault clearing;

[0023] If the fault cannot be cleared when it exists, when the FLT signal is at a low level (the fault always exists), the MCU outputs a high-level CLR signal to try to clear the fault. At this time, transistor T4 is turned on, and the base of transistor T1 is pulled down to GND, and transistor T1 is turned off. Since the FLT signal is at a low level, the base voltage of transistor T2 is lower than the emitter voltage, so transistor T2 is still in the on state, and the OE signal maintains a high level, and finally the fault cannot be cleared;

[0024] For fault shielding, when a FLT signal fault occurs, the collector of transistor T2 is high, the MCU outputs a high-level DIS signal, transistor T3 is turned on, and the OE signal is pulled down to GND, ultimately achieving fault shielding.

[0025] As a further preferred technical solution of the above technical solution, the MCU is connected to the level conversion chip through a drive control signal, the MCU is connected to the hardware fault protection circuit through a CLR signal and a DIS signal, and the level conversion chip is connected to the hardware fault protection circuit through an OE signal.

[0026] As a further preferred technical solution of the above technical solution, the emitter of the transistor T3 is grounded.

[0027] As a further preferred technical solution of the above technical solution, the emitter of the transistor T4 is grounded. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is an electrical connection diagram of a hardware fault protection circuit suitable for an electric drive system of a new energy vehicle of the present invention.

[0029] Figure 2 It is a schematic diagram of a hardware fault protection circuit suitable for an electric drive system of a new energy vehicle of the present invention.

[0030] Figure 3 It is a working state flow chart of a hardware fault protection circuit suitable for an electric drive system of a new energy vehicle of the present invention. DETAILED DESCRIPTION

[0031] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0032] In the preferred embodiments of the present invention, those skilled in the art should note that the MCU and the like involved in the present invention may be regarded as prior art.

[0033] Preferred embodiments.

[0034] like Figure 1-3 As shown, the present invention discloses a hardware fault protection circuit suitable for an electric drive system of a new energy vehicle, including a transistor T1, a transistor T2, a transistor T3, a transistor T4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, wherein:

[0035] The collector of the transistor T1 is connected to the power supply terminal VCC through the resistor R1 and the emitter of the transistor T1 is grounded, and the base of the transistor T1 is electrically connected to the collector of the transistor T2 through the resistor R4;

[0036] The base of the transistor T2 is connected to the FLT signal as an external fault signal through the resistor R3, the emitter of the transistor T2 is connected to the power supply terminal VCC through the resistor R2, and the collector of the transistor T2 is grounded through the resistor R5;

[0037] The base of the transistor T3 is connected to the DIS signal as a fault shielding signal output by the MCU, the collector of the transistor T3 is electrically connected to the collector of the transistor T2 through the resistor R6 and is connected to the OE signal as an enable signal output by the protection circuit to the level conversion chip;

[0038] The base of the transistor T4 is connected to the CLR signal serving as a fault clearing signal output by the MCU, and the collector of the transistor T4 is electrically connected to the base of the transistor T1 .

[0039] Specifically, the hardware fault protection circuit is used for fault latching, fault clearing, failure to clear the fault when the fault exists, and fault shielding, wherein:

[0040] For fault latching, the fault latching is realized by transistor T1 and transistor T2. When an external fault occurs, the FLT signal becomes low level, and transistor T2 is turned on, making the OE signal become high level. Therefore, after the external fault disappears, the FLT signal returns to high level. Since transistor T1 is turned on, transistor T2 is also kept on, so the OE signal maintains high level, and finally the fault latching is realized;

[0041] For fault clearing, when the external fault disappears, the FLT signal returns to a high level, and the MCU outputs a high-level CLR signal, thereby pulling the base of transistor T1 down to GND, turning off transistor T1, and then pulling the base of transistor T2 up to VCC, turning off transistor T2, and the OE signal becomes a low level, finally achieving fault clearing;

[0042] If the fault cannot be cleared when it exists, when the FLT signal is at a low level (the fault always exists), the MCU outputs a high-level CLR signal to try to clear the fault. At this time, transistor T4 is turned on, and the base of transistor T1 is pulled down to GND, and transistor T1 is turned off. Since the FLT signal is at a low level, the base voltage of transistor T2 is lower than the emitter voltage, so transistor T2 is still in the on state, and the OE signal maintains a high level, and finally the fault cannot be cleared;

[0043] For fault shielding, when a FLT signal fault occurs, the collector of transistor T2 is high, the MCU outputs a high-level DIS signal, transistor T3 is turned on, and the OE signal is pulled down to GND, ultimately achieving fault shielding.

[0044] More specifically, the MCU is connected to the level conversion chip through a driving control signal, the MCU is connected to the hardware fault protection circuit through a CLR signal and a DIS signal, and the level conversion chip is connected to the hardware fault protection circuit through an OE signal.

[0045] Furthermore, the emitter of the transistor T3 is grounded.

[0046] Furthermore, the emitter of the transistor T4 is grounded.

[0047] For the present invention:

[0048] The hardware fault protection circuit described in the present invention is located in the electric drive controller system as follows: Figure 1 The working principle of the system is described as follows:

[0049] In normal working state, MCU outputs driving control signal, which is transmitted to high voltage driving circuit through level conversion chip. The characteristic of level conversion chip is: when OE signal is low level, signal is transmitted normally; when OE signal is high level, signal transmission is disconnected.

[0050] The hardware fault protection circuit described in the present invention has a structure as follows: Figure 2 As shown in the figure. The FLT signal is an external fault signal, and a low level indicates overvoltage, overcurrent or driver chip fault; the CLR signal is a fault clearing signal output by the MCU; the OE signal is an enable signal output by the protection circuit to the level conversion chip; and the DIS signal is a fault shielding signal output by the MCU.

[0051] The truth table of the circuit of the present invention is shown in Table 1:

[0052] Table 1 Latch logic truth table

[0053]

[0054] Description: H = high level; L = low level; X = any level

[0055] The circuit working state flow of the present invention Figure 3 As shown:

[0056] It can be seen from the truth table and the state flow chart that the circuit scheme described in the present invention can meet the functional requirements of the hardware fault protection circuit: 1) When a fault occurs (FLT=L), the CLR signal is low to latch the fault; 2) After the fault disappears, the CLR signal is set high to clear the fault; 3) When a fault exists, the CLR signal cannot clear the fault; 4) When a fault exists, the DIS signal is set high to shield the fault.

[0057] It is worth mentioning that the technical features such as MCU involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0058] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A hardware fault protection circuit suitable for an electric drive system of a new energy vehicle, characterized in that: It includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, wherein: The collector of the transistor T1 is connected to the power supply terminal VCC through the resistor R1 and the emitter of the transistor T1 is grounded, and the base of the transistor T1 is electrically connected to the collector of the transistor T2 through the resistor R4; The base of the transistor T2 is connected to the FLT signal as an external fault signal through the resistor R3, the emitter of the transistor T2 is connected to the power supply terminal VCC through the resistor R2, and the collector of the transistor T2 is grounded through the resistor R5; The base of the transistor T3 is connected to the DIS signal as a fault shielding signal output by the MCU, the collector of the transistor T3 is electrically connected to the collector of the transistor T2 through the resistor R6 and is connected to the OE signal as an enable signal output by the protection circuit to the level conversion chip; The base of the transistor T4 is connected to the CLR signal serving as a fault clearing signal output by the MCU, and the collector of the transistor T4 is electrically connected to the base of the transistor T1 .

2. A hardware fault protection circuit suitable for an electric drive system of a new energy vehicle according to claim 1, characterized in that: Hardware fault protection circuits are used for fault latching, fault clearing, failure to clear faults when faults exist, and fault shielding, where: For fault latching, the fault latching is realized by transistor T1 and transistor T2. When an external fault occurs, the FLT signal becomes low level, and transistor T2 is turned on, making the OE signal become high level. Therefore, after the external fault disappears, the FLT signal returns to high level. Since transistor T1 is turned on, transistor T2 is also kept on, so the OE signal maintains high level, and finally the fault latching is realized; For fault clearing, when the external fault disappears, the FLT signal returns to a high level, and the MCU outputs a high-level CLR signal, thereby pulling the base of transistor T1 down to GND, turning off transistor T1, and then pulling the base of transistor T2 up to VCC, turning off transistor T2, and the OE signal becomes a low level, finally achieving fault clearing; If the fault cannot be cleared when it exists, when the FLT signal is at a low level, the MCU outputs a high-level CLR signal to try to clear the fault. At this time, transistor T4 is turned on, and the base of transistor T1 is pulled down to GND, and transistor T1 is turned off. Since the FLT signal is at a low level, the base voltage of transistor T2 is lower than the emitter voltage, so transistor T2 is still in the on state, and the OE signal maintains a high level, and finally the fault cannot be cleared; For fault shielding, when a FLT signal fault occurs, the collector of transistor T2 is high, the MCU outputs a high-level DIS signal, transistor T3 is turned on, and the OE signal is pulled down to GND, ultimately achieving fault shielding.

3. A hardware fault protection circuit suitable for an electric drive system of a new energy vehicle according to claim 2, characterized in that: The MCU is connected to the level conversion chip through a driving control signal, the MCU is connected to the hardware fault protection circuit through a CLR signal and a DIS signal, and the level conversion chip is connected to the hardware fault protection circuit through an OE signal.

4. A hardware fault protection circuit suitable for an electric drive system of a new energy vehicle according to claim 3, characterized in that: The emitter of the transistor T3 is grounded.

5. A hardware fault protection circuit suitable for an electric drive system of a new energy vehicle according to claim 4, characterized in that: The emitter of the transistor T4 is grounded.

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