FPGA interconnection resource testing method, device, equipment and storage medium

Abstract

The present invention relates to the field of data testing technology, and in particular to a method, device, equipment and storage medium for testing interconnection resources of an FPGA, wherein the method comprises: obtaining interconnection resources to be tested, and constructing an interconnection resource model to be tested based on the interconnection resources to be tested; obtaining a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested; generating a routing configuration path for the routable path; generating a bitstream file based on the routing configuration path; and obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file. The present invention can reduce the number of interconnection resource test configurations and improve the efficiency of FPGA interconnection resource testing.

Description

Technical Field

[0001] The present invention relates to the field of data testing technology, and in particular to a method, device, equipment and storage medium for testing FPGA interconnection resources. Background Art

[0002] As a programmable hardware platform, Field Programmable Gate Array (FPGA) is versatile, flexible, reconfigurable and parallel computing, and is widely used in many important fields such as national defense, medical treatment, computing acceleration and communication signal processing. Its unique feature is that it can reconfigure hardware logic circuits through programming, so that it can adapt to different application scenarios and realize specific digital logic functions.

[0003] The integrity of the interconnection line is the basis for the testability of the internal resources of the entire FPGA device. Any fault in the interconnection line may cause the configuration of the circuit design to fail. The test of interconnection resources in related technologies mainly generates test configurations for the chip structure of the FPGA, which is not universal, requires many configurations for testing, and has low test efficiency. In addition, it is also limited by the hardware structure, the selection of I / O ports, etc., making it difficult to achieve comprehensive testing of the internal interconnection resources of the FPGA.

[0004] In view of this, there is a need for an FPGA interconnection resource testing method that reduces the number of interconnection resource test configurations and improves test efficiency. Summary of the invention

[0005] In view of this, the present invention provides a method for testing FPGA interconnection resources to reduce the number of interconnection resource test configurations and improve the efficiency of FPGA interconnection resource testing.

[0006] In a first aspect, the present invention provides a method for testing FPGA interconnection resources, the method comprising: obtaining interconnection resources to be tested, and constructing an interconnection resource model to be tested based on the interconnection resources to be tested; obtaining a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested; generating a routing configuration path for the routable path; generating a bitstream file based on the routing configuration path; and obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file.

[0007] In the disclosed embodiment, by extracting the interconnection resources to be tested in the FPGA to be tested and constructing the interconnection resource model to be tested, the test method can be applied to different FPGA structures, thereby improving the versatility of the method. By selecting a suitable routing configuration path corresponding to a routable path to generate a bitstream file, the test of the interconnection resources is completed. The test efficiency of the FPGA interconnection resources can be improved.

[0008] In an optional implementation, obtaining interconnection resources to be tested and constructing an interconnection resource model to be tested based on the interconnection resources to be tested includes: obtaining test requirements of the FPGA to be tested, and determining a range of interconnection resources to be tested based on the test requirements; extracting interconnection resources to be tested, wherein the interconnection resources to be tested are within the range of interconnection resources to be tested; and constructing an interconnection resource model to be tested according to the types and connection relationships of the interconnection resources to be tested.

[0009] In the disclosed embodiment, by determining the scope of interconnection resources to be tested and the interconnection resources to be tested according to the test requirements, a model of interconnection resources to be tested is constructed. According to different test requirements, the interconnection resources to be tested can be extracted in a targeted manner, thereby improving the targetedness and test efficiency of the test.

[0010] In an optional embodiment, the interconnection resource model to be tested includes vertices and a first directed edge, wherein the vertices represent a set of interconnection metal wires of the same type in the interconnection resource to be tested, the set of interconnection metal wires of the same type includes at least one interconnection metal wire, and the first directed edge corresponds to the connection relationship between the sets of interconnection metal wires of the same type.

[0011] In the disclosed embodiment, the connection relationship of the interconnection metal wire set in the interconnection resource to be tested can be intuitively represented through the vertex and the first directed edge, which can improve the readability of the model and facilitate subsequent testers to better understand the model.

[0012] In an optional embodiment, for a routable path, generating a routing configuration path includes: for the routable path, generating a directed graph matching the routable path, the directed graph including nodes and a second directed edge, wherein the nodes represent interconnected metal wires, and the second directed edge represents interconnected switches between the interconnected metal wires; constructing SMT constraints, and generating a routing configuration path corresponding to the routable path based on the SMT constraints.

[0013] In the disclosed embodiment, a routing configuration path corresponding to a routable path is obtained by constructing SMT constraints, and a routing configuration path that satisfies all SMT constraints can be automatically found, thereby improving the efficiency of interconnection resource testing and automating the testing process.

[0014] In an optional implementation, the SMT constraints include at least one of signal transmission constraints, mutual exclusion constraints, interconnection switch coverage constraints, constant constraints, and configuration frequency constraints.

[0015] In the disclosed embodiment, by using at least one of signal transmission constraint, mutual exclusion constraint, interconnection switch coverage constraint, constant constraint, and configuration number constraint as SMT constraint, the test efficiency can be improved, the reliability of the test result can be guaranteed, and the time required for interconnection resource testing can be reduced.

[0016] In an optional implementation manner, the configuration times of the routing configuration path is the minimum configuration times that can cover the first interconnection switch, wherein the first interconnection switch represents the interconnection switch covered by the routable path corresponding to the routing configuration path.

[0017] In the disclosed embodiment, by establishing SMT constraints and solving the minimum number of configurations required to satisfy the constraints, the number of configurations required for interconnected resource testing can be reduced, thereby reducing the time required for testing and improving the efficiency of interconnected resource testing.

[0018] In an optional implementation, obtaining the interconnection resource test results of the FPGA to be tested based on the bitstream file includes: loading the bitstream file to the FPGA to be tested and collecting response data; and obtaining the interconnection resource test results of the FPGA to be tested based on the response data.

[0019] In the disclosed embodiment, by loading the bitstream file onto the FPGA to be tested and obtaining the test result of the interconnected resources through the response of the FPGA, a real-time hardware test environment can be provided to achieve rapid testing of the interconnected resources.

[0020] In a second aspect, the present invention provides an FPGA interconnection resource testing device, the device comprising: a construction module, used to obtain the interconnection resources to be tested, and to construct an interconnection resource model to be tested based on the interconnection resources to be tested; an acquisition module, used to obtain a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested; a routing configuration path generation module, used to generate a routing configuration path for the routable path; a bitstream file generation module, used to generate a bitstream file based on the routing configuration path; and a test module, used to obtain the interconnection resource test result of the FPGA to be tested based on the bitstream file.

[0021] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the FPGA interconnection resource testing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0022] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the FPGA interconnection resource testing method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 It is a flowchart of a method for testing FPGA interconnection resources according to an embodiment of the present invention;

[0025] Figure 2 is a flow chart of another FPGA interconnection resource testing method according to an embodiment of the present invention;

[0026] Figure 3 is a flow chart of another FPGA interconnection resource testing method according to an embodiment of the present invention;

[0027] Figure 4 is a flow chart of another FPGA interconnection resource testing method according to an embodiment of the present invention;

[0028] Figure 5 is a structural block diagram of an FPGA interconnection resource testing device according to an embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0031] The main components of a Field Programmable Gate Array (FPGA) are configurable logic blocks, programmable interconnect networks, and programmable input / output blocks. The configurable logic blocks are used to implement user-defined logic functions, and are generally placed in a two-dimensional grid and connected through a programmable interconnect network. The programmable input / output blocks provide all input / output connections for the FPGA, and are generally placed at the boundaries of the two-dimensional grid and connected to the programmable interconnect network. The interconnection resources of the programmable interconnect network include interconnection metal wires and interconnection switches.

[0032] The integrity of the interconnection is the basis for the testability of the entire FPGA's internal resources. Any fault in the interconnection may cause the circuit design configuration to fail. In order to reduce or even eliminate the interconnection faults inside the FPGA device and improve programming reliability, it is necessary to design bit stream information with a small number of configurations and a high interconnection coverage rate to complete testing and fault diagnosis.

[0033] In the related art, there are two main methods for testing interconnected resources. One is to generate test configurations for the structure of FPGA chips. This method is inefficient, has poor versatility, and cannot be applied to the current complex FPGA design structure. The other method is to test interconnected resources through routing coverage algorithms such as depth-first search or graph theory methods such as graph coloring. However, this method is not only limited by the hardware structure, but also requires a large number of configurations in the process of achieving interconnected resource coverage. It is difficult to achieve comprehensive testing of interconnected resources within the FPGA, and even if comprehensive testing is achieved, the required testing time will be greatly increased.

[0034] Therefore, there is a need for an FPGA interconnection resource testing method that can reduce the number of interconnection resource test configurations and improve the efficiency and versatility of interconnection resource testing.

[0035] According to an embodiment of the present invention, an embodiment of a method for testing FPGA interconnection resources is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0036] In this embodiment, a method for testing FPGA interconnection resources is provided. Figure 1 : is a flow chart of a method for testing FPGA interconnection resources according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0037] Step S101: acquiring interconnection resources to be tested, and constructing an interconnection resource model to be tested based on the interconnection resources to be tested.

[0038] In practical applications, the chip documentation of the FPGA to be tested is used to understand the basic information of the FPGA to be tested and to find the interconnection resources that need to be tested. Then, the design tool is used to export the detailed information of the interconnection resources to be tested. Based on the extracted information, an abstract model is created to represent these interconnection resources. The abstract model can be a mathematical model, a graphical model, or a software-based simulation model.

[0039] The type and content of the interconnection resource to be tested are not limited, and can be global wiring resources, long-line resources, short-line resources and / or distributed wiring resources. The selection of the interconnection resource model to be tested is not limited, as long as it can represent the content and connection relationship of the interconnection resource.

[0040] Step S102: obtaining a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested.

[0041] The method of obtaining the routable paths is not limited, and the interconnection resource model to be tested can be split into multiple routable paths through the search algorithm. In order to ensure the effectiveness of the interconnection resource test, the routable paths need to cover all interconnection switches to test all connection relationships within the interconnection resource to be tested.

[0042] In the case where the interconnection resource model to be tested includes fewer interconnection metal wires, the routable path includes the connection relationship between several interconnection metal wires in the interconnection resource model to be tested. The input, output, and nodes experienced by the routable path are all interconnection metal wires, and the directionality of the routable path is determined by the connection relationship between different interconnection metal wires. In a practical application, the interconnection resource model to be tested includes interconnection metal wire 1, interconnection metal wire 2, and interconnection metal wire 3. There are two-to-two connection relationships among interconnection metal wire 1, interconnection metal wire 2, and interconnection metal wire 3. In the case where there are no special restrictions on the input and output of the routable path, the three interconnection metal wires can all be used as the input or output of the routable path. For example, the routable path can be interconnection metal wire 1->interconnection metal wire 1->interconnection metal wire 2->interconnection metal wire 3, interconnection metal wire 2->interconnection metal wire 3->interconnection metal wire 1->interconnection metal wire 1, and other routable paths.

[0043] In the case where the interconnection resource model to be tested includes a large number of interconnection metal wires, the interconnection metal wires of the same type can be regarded as a set. Then, the routable path includes the connection relationship between the interconnection metal wire sets of the same type in the interconnection resource model to be tested and these interconnection metal wire sets of the same type. The input, output, and experienced nodes of the routable path are all interconnection metal wire sets, and the directionality of the routable path is determined by the connection relationship between different interconnection metal wire sets. In a practical application, the interconnection resource model to be tested includes interconnection metal wire set 1, interconnection metal wire set 2, and interconnection metal wire set 3. There are two-to-two connection relationships in interconnection metal wire set 1, interconnection metal wire set 2, and interconnection metal wire set 3. In the case where there are no special restrictions on the input and output of the routable path, the three interconnection metal wire sets can all be used as the input or output of the routable path. For example, the routable path can be interconnection metal wire set 1->interconnection metal wire set 1->interconnection metal wire set 2->interconnection metal wire set 3, interconnection metal wire set 2->interconnection metal wire set 3->interconnection metal wire set 1->interconnection metal wire set 1, and other routable paths.

[0044] Step S103: Generate a routing configuration path for the routable path.

[0045] Among them, the generation method of routing configuration path is not restricted. It can be automatically generated by setting constraints and using tools, or it can be generated for specific routing attributes according to actual needs. The routing configuration path can be extended to the entire FPGA chip and used to detect all interconnected resources in the FPGA.

[0046] In the case where the input, output, and nodes traversed by the routable path are all single interconnected metal wires, the routable path can be directly used as a routing configuration path.

[0047] When the input, output, and traversed nodes of the routable path are all sets of interconnected metal wires of the same type, it is necessary to further obtain the connection relationship between the interconnected metal wires to determine their interconnection switch directions, and then obtain a routing configuration path that can cover the interconnection switches. The input, output, and traversed nodes of the routing configuration path are all interconnected metal wires, and the direction of the routing configuration path is determined according to the connection relationship between the interconnected metal wires.

[0048] In a practical application, a routable path that can cover all interconnection switches in the interconnection resource model to be tested is obtained: interconnection metal wire set 1->interconnection metal wire set 1->interconnection metal wire set 2, interconnection metal wire set 1 has two interconnection metal wires: interconnection metal wire a and interconnection metal wire b; interconnection metal wire 2 has two interconnection metal wires: interconnection metal wire c and interconnection metal wire d. Interconnection metal wire a is connected to interconnection metal wire c and interconnection metal wire d respectively, and interconnection metal wire b is connected to interconnection metal wire a. Then, the routing configuration path corresponding to the routable path can be interconnection metal wire a->interconnection metal wire b->interconnection metal wire c, interconnection metal wire a->interconnection metal wire b->interconnection metal wire d, interconnection metal wire b->interconnection metal wire a->interconnection metal wire c, and interconnection metal wire b->interconnection metal wire a->interconnection metal wire d. The configuration is performed four times to achieve a comprehensive test of the interconnection resource to be tested.

[0049] Step S104: Generate a bitstream file based on the routing configuration path.

[0050] The bitstream file is the internal configuration state file of the FPGA, which contains the settings of the wiring, logic resources, and input / output interfaces. There is no restriction on how to generate the bitstream file. After the bitstream file is generated, the integrity and correctness of the bitstream file can also be verified to avoid errors in subsequent tests.

[0051] Step S105, obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file.

[0052] Among them, the way to obtain the interconnection resource test results is not restricted. The bitstream file can be directly loaded into the FPGA to be tested to obtain the interconnection resource test results. The type of interconnection resource test results is not restricted. The response of the FPGA to be tested can be directly output, or it can be a result obtained based on the response analysis. If there is a problem with the interconnection resource, the problem interconnection resource can be located, and the location of the problem interconnection resource can be output for subsequent processing.

[0053] The FPGA interconnection resource testing method provided in this embodiment extracts the interconnection resources to be tested in the FPGA to be tested and constructs the interconnection resource model to be tested, so that the testing method can be applied to different FPGA structures and improve the versatility of the method. By selecting a suitable routing configuration path corresponding to the routable path to generate a bit stream file, the interconnection resource test is completed. The test efficiency of the FPGA interconnection resource can be improved.

[0054] In this embodiment, a method for testing FPGA interconnection resources is provided. Figure 2 : is a flow chart of a method for testing FPGA interconnection resources according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0055] Step S201: Acquire interconnection resources to be tested, and construct an interconnection resource model to be tested based on the interconnection resources to be tested.

[0056] Specifically, the above step S201 includes:

[0057] Step S2011, obtaining the test requirements of the FPGA to be tested, and determining the scope of the interconnection resources to be tested based on the test requirements.

[0058] Among them, test requirements may include functional requirements, performance requirements, etc. Analyze and determine the test requirements, and clarify which interconnected resources need to be tested.

[0059] In practical applications, a detailed resource mapping table can be determined based on the hierarchical structure and logical division of the FPGA design to be tested. This resource mapping table should include the interconnection structure of the FPGA to be tested. Then, combined with the test requirements, the scope of the interconnection resources to be tested can be determined from this resource mapping table.

[0060] Step S2012: extracting interconnection resources to be tested, wherein the interconnection resources to be tested are within the range of interconnection resources to be tested.

[0061] Among them, the interconnection resources to be tested and detailed information of the interconnection resources to be tested, including connection relationships, ports, timing constraints, etc., can be extracted through FPGA design tools.

[0062] Step S2013: construct a model of the interconnected resources to be tested according to the types and connection relationships of the interconnected resources to be tested.

[0063] The form and construction method of the interconnection resource model to be tested are not limited. For example, based on the form of a mathematical model, digital numbers are used to represent interconnection metal wires, and arrows represent the connection relationship between the interconnection metal wires.

[0064] When there are a large number of interconnect metal wires and the connection relationship is complex, the interconnect metal wires to be tested can be divided into multiple parts according to the length or type of the interconnect metal wires in the interconnect resource to be tested, and the interconnect resource model to be tested can be constructed according to the division results.

[0065] In some optional embodiments, the interconnection resource model to be tested includes vertices and a first directed edge, wherein the vertices represent a set of interconnection metal wires of the same type in the interconnection resource to be tested, the set of interconnection metal wires of the same type includes at least one interconnection metal wire, and the first directed edge corresponds to the connection relationship between the sets of interconnection metal wires of the same type.

[0066] Among them, the division of types is not restricted, and a vertex can represent a group of interconnected metal wires with the same width, length or similar signal transmission tasks. The first directed edge can be used to represent the connection mode and dependency relationship between vertices. In a practical application, two vertices represent interconnected metal wire set 1 and interconnected metal wire set 2 respectively, and interconnected metal wire set 1 is connected to interconnected metal wire set 2. Then, a first directed edge can be used to represent the connection relationship between interconnected metal wire set 1 and interconnected metal wire set 2, reflecting the directionality of the signal flow.

[0067] The types and connection relationships of the interconnected resources to be tested can be intuitively represented through the vertices and the first directed edges, which can improve the readability of the model and help subsequent testers better understand how signals are transmitted through different interconnected resources.

[0068] In a practical application, interconnection resources are divided into multiple levels according to the types of interconnection metal wires. Each level represents a group of interconnection metal wires of the same type, and the interconnection metal wires in each level are connected. Then the vertices in the interconnection resource model to be tested can represent different levels, and the first directed edge can represent the connection relationship between the levels.

[0069] Step S202: obtaining a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested.

[0070] For details, please see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0071] Step S203: Generate a routing configuration path for the routable path.

[0072] For details, please see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0073] Step S204: Generate a bitstream file based on the routing configuration path.

[0074] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0075] Step S205: obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file.

[0076] For details, please see Figure 1 Step S105 of the illustrated embodiment will not be described in detail here.

[0077] The FPGA interconnection resource testing method provided in this embodiment determines the scope of interconnection resources to be tested and the interconnection resources to be tested according to the test requirements, and constructs an interconnection resource model to be tested. According to different test requirements, the interconnection resources to be tested can be extracted in a targeted manner, thereby improving the targetedness and test efficiency of the test and systematizing the test process.

[0078] In this embodiment, a method for testing FPGA interconnection resources is provided. Figure 3 : is a flow chart of a method for testing FPGA interconnection resources according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0079] Step S301: Acquire the interconnection resources to be tested, and construct an interconnection resource model to be tested based on the interconnection resources to be tested.

[0080] For details, please see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0081] Step S302: obtaining a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested.

[0082] For details, please see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0083] Step S303: Generate a routing configuration path for the routable path.

[0084] Specifically, the above step S303 includes:

[0085] Step S3031, for a routable path, generating a directed graph matching the routable path, the directed graph comprising a node and a second directed edge, wherein the node represents an interconnection metal wire, and the second directed edge represents an interconnection switch between the interconnection metal wires.

[0086] The node represents a specific interconnection metal line, and the second directed edge represents the interconnection switch between the interconnection metal lines. The interconnection switch can be a transmission gate, a multiplexer, etc. Each second directed edge can not only indicate the possibility of a signal flowing from one node to another, but also includes the routing decision implemented by a specific interconnection switch.

[0087] There is no restriction on the way to generate directed graphs. You can first determine the nodes and directed edges, and then determine which nodes need to establish directed edges based on the given routable paths. After generating the directed graph, you can check the directed graph according to actual needs to ensure that the directed graph can correctly represent the routable paths.

[0088] Step S3032, constructing SMT constraints, and generating routing configuration paths corresponding to routable paths based on the SMT constraints.

[0089] In practical applications, each interconnect metal line and each interconnect switch can be defined as a logical variable. Then, the SMT language is used to express the relationship between these logical variables, which can include the availability of interconnect resources, resource conflict avoidance, etc., to determine feasible configurations. Then, some constraints on configuration performance, such as timing constraints, are added. The SMT problem is solved to obtain a feasible routing configuration path that meets the designed performance indicators.

[0090] Among them, there is no restriction on the way to solve the SMT problem. The SMT solver can be used to solve the constructed constraint set to find a configuration scheme that satisfies the SMT constraints. Then, according to the obtained configuration scheme, specific configuration data is generated, including the selection of the internal wiring path of the FPGA to be tested.

[0091] In some optional implementations, the SMT constraints include at least one of signal transmission constraints, mutual exclusion constraints, interconnect switch coverage constraints, constant constraints, and configuration frequency constraints.

[0092] The signal transmission constraint indicates that when one of the fan-in interconnection switches of a node in the directed graph is switched on in the configuration, the fan-out interconnection switch also has at least one switched on in the configuration. When one of the fan-out interconnection switches of a node in the directed graph is switched on in the configuration, the fan-in interconnection switch also has at least one switched on in the configuration.

[0093] By constructing signal transmission constraints, the signal transmission can be guaranteed.

[0094] The mutual exclusion constraint means that for a multi-way selector, at most one way is selected in each configuration.

[0095] By constructing mutual exclusion constraints, potential conflicts caused by multiple signals competing for the output path can be avoided, and the clarity of the output signal can be ensured.

[0096] The interconnect switch coverage constraint indicates that each interconnect switch needs to be covered at least once in the generated routing configuration path.

[0097] By constructing interconnect switch coverage constraints, it can be ensured that all interconnect resources are checked, thus improving the reliability of the test.

[0098] The constant constraint means that when there is no second directed edge connecting two nodes in a directed graph, the logical variable corresponding to the corresponding second directed edge is configured as a zero constant in the generated routing configuration path. If a node must be included in the generated routing configuration path, the node is configured as a non-zero constant.

[0099] By building constant constraints, you can simplify the routing configuration path.

[0100] The configuration number constraint means that the number of configurations needs to be minimized in the SMT solution. By constructing the configuration number constraint, the minimum number of configurations can be obtained.

[0101] By using at least one of signal transmission constraints, mutual exclusion constraints, interconnection switch coverage constraints, constant constraints, and configuration number constraints as SMT constraints, the reliability of test results can be guaranteed and the time required for interconnection resource testing can be reduced.

[0102] In some optional implementations, the number of configurations of the routing configuration path is the minimum number of configurations required to cover the first interconnection switch, wherein the first interconnection switch represents an interconnection switch covered by a routable path corresponding to the routing configuration path.

[0103] The number of configurations of the routing configuration path corresponds to the number of configurations required for the interconnection resource test. In a practical application, a routable path is generated based on the interconnection resource model to be tested, and a directed graph corresponding to the routable path is generated based on the routable path. The routing configuration path is obtained by constructing SMT constraints. The number of configurations required for the interconnection resource test is the minimum number of configurations of the routing configuration paths corresponding to all routable paths.

[0104] In a practical application, several routable paths are generated. Based on each routable path, a directed graph corresponding to the routable path is generated. The routing configuration path is obtained by constructing SMT constraints. The number of configurations required for the interconnection resource test is the sum of the minimum number of configurations of the routing configuration paths corresponding to all routable paths.

[0105] By establishing SMT constraints and solving the minimum number of configurations required to meet the constraints, the number of configurations required for interconnection resource testing can be reduced, thereby reducing the time required for testing and improving the efficiency of interconnection resource testing.

[0106] Step S304: Generate a bitstream file based on the routing configuration path.

[0107] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0108] Step S305: obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file.

[0109] For details, please see Figure 1 Step S105 of the illustrated embodiment will not be described in detail here.

[0110] The FPGA interconnection resource testing method provided in this embodiment generates a routing configuration path corresponding to a routable path by constructing SMT constraints, and can automatically find a routing configuration path that satisfies all SMT constraints, has strong applicability, can improve the efficiency of interconnection resource testing, and automate the testing process.

[0111] In this embodiment, a method for testing FPGA interconnection resources is provided. Figure 4 : is a flow chart of a method for testing FPGA interconnection resources according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0112] Step S401: Acquire the interconnection resources to be tested, and construct an interconnection resource model to be tested based on the interconnection resources to be tested.

[0113] For details, please see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0114] Step S402: obtaining a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested.

[0115] For details, please see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0116] Step S403: Generate a routing configuration path for the routable path.

[0117] For details, please see Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0118] Step S404: Generate a bitstream file based on the routing configuration path.

[0119] For details, please see Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0120] Step S405: obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file.

[0121] Specifically, the above step S405 includes:

[0122] Step S4051, loading the bitstream file into the FPGA to be tested, and collecting response data.

[0123] In actual applications, after receiving the bitstream data of the bitstream file, the FPGA to be tested will automatically start the configuration process. After the configuration is completed, the development tool will display a message of configuration success or failure. After the configuration is successful, according to the test requirements, select a suitable test instrument to connect the input and output interfaces of the FPGA to be tested. The operation of the internal logic of the FPGA to be tested is triggered by software or hardware signals. The response data of the FPGA to be tested is monitored and recorded by the test instrument. The response data includes the output signal of the FPGA to be tested, the timing information, etc.

[0124] Step S4052: Based on the response data, obtain the interconnection resource test result of the FPGA to be tested.

[0125] There is no restriction on the way to obtain the test results. According to the test requirements, the response data can be compared with the expected results, and the comparison results can be used to determine whether the interconnected resource to be tested has a fault. After obtaining the test results, the test results can also be recorded for subsequent processing.

[0126] The FPGA interconnection resource testing method provided in this embodiment loads a bitstream file onto the FPGA to be tested and obtains the test result of the interconnection resource through the response of the FPGA. It can provide a real-time hardware testing environment and realize rapid testing of the interconnection resources.

[0127] In this embodiment, a FPGA interconnection resource testing device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0128] This embodiment provides a FPGA interconnection resource testing device, such as Figure 5 As shown, the device comprises:

[0129] The construction module 501 is used to obtain the interconnection resources to be tested and construct the interconnection resource model to be tested based on the interconnection resources to be tested.

[0130] The acquisition module 502 is used to acquire a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested.

[0131] The routing configuration path generation module 503 is used to generate a routing configuration path for a routable path.

[0132] The bitstream file generating module 504 is used to generate a bitstream file based on the routing configuration path.

[0133] The testing module 505 is used to obtain the interconnection resource test result of the FPGA to be tested based on the bit stream file.

[0134] In some optional implementations, the building block 501 includes:

[0135] The scope determination unit is used to obtain the test requirements of the FPGA to be tested, and determine the scope of the interconnection resources to be tested based on the test requirements.

[0136] The resource acquisition unit is used to extract the interconnection resources to be tested, wherein the interconnection resources to be tested are within the scope of the interconnection resources to be tested.

[0137] The model building unit is used to build a model of the interconnected resources to be tested according to the types and connection relationships of the interconnected resources to be tested.

[0138] In some optional implementations, the routing configuration path generation module 503 includes:

[0139] A graph generation unit, configured to generate a directed graph based on the routable paths, wherein the directed graph includes nodes and second directed edges, wherein the nodes represent interconnected metal wires, and the second directed edges represent interconnected switches;

[0140] The path acquisition unit is used to construct SMT constraints and generate a routing configuration path corresponding to the routable path based on the SMT constraints.

[0141] In some optional implementations, the testing module 505 includes:

[0142] The response acquisition unit is used to load the bit stream file into the FPGA to be tested and collect response data.

[0143] The output unit is used to obtain the interconnection resource test result of the FPGA to be tested based on the response data.

[0144] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0145] The FPGA interconnect resource testing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0146] The embodiment of the present invention also provides a computer device having the above Figure 5 FPGA interconnect resource test setup shown.

[0147] See also Figure 6, Figure 6 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0148] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0149] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0150] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0151] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0152] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 6 The example of connecting through bus is taken in the following.

[0153] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0154] The computer device also includes a communication interface, which is used for the computer device to communicate with other devices or a communication network.

[0155] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0156] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0157] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for testing FPGA interconnection resources, characterized in that: The method comprises: Acquire the interconnection resources to be tested, and construct an interconnection resource model to be tested based on the interconnection resources to be tested; Acquire a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested; For the routable path, generating a routing configuration path; Based on the routing configuration path, generating a bitstream file; Based on the bitstream file, obtain the interconnection resource test results of the FPGA to be tested The generating of a routing configuration path for the routable path includes: For a routable path, generating a directed graph matching the routable path, the directed graph comprising a node and a second directed edge, wherein the node represents an interconnection metal wire, and the second directed edge represents an interconnection switch between the interconnection metal wires; Construct SMT constraints, and generate a routing configuration path corresponding to the routable path based on the SMT constraints; the SMT constraints include signal transmission constraints, mutual exclusion constraints, interconnection switch coverage constraints, constant constraints, and configuration number constraints; the signal transmission constraint indicates that when the fan-in interconnection switch of a node in a directed graph has one path enabled in the configuration, the fan-out interconnection switch also has at least one path enabled in the configuration; the mutual exclusion constraint indicates that for a multiplexer, at most one path is selected in each configuration; the interconnection switch coverage constraint indicates that each interconnection switch is covered at least once in the generated routing configuration path; the constant constraint indicates that when there is no second directed edge connecting two nodes in a directed graph, in the generated routing configuration path, the logical variable corresponding to the corresponding second directed edge is configured as a zero constant; the configuration number constraint indicates that in the SMT solution, the configuration number needs to be minimized.

2. The method according to claim 1, characterized in that The step of acquiring the interconnection resources to be tested and constructing the interconnection resource model to be tested based on the interconnection resources to be tested includes: Obtaining the test requirements of the FPGA to be tested, and determining the scope of the interconnection resources to be tested based on the test requirements; Extracting an interconnection resource to be tested, wherein the interconnection resource to be tested is within the range of the interconnection resource to be tested; The interconnection resource model to be tested is constructed according to the type and connection relationship of the interconnection resource to be tested.

3. The method according to claim 1 or 2, characterized in that: The interconnection resource model to be tested includes a vertex and a first directed edge, wherein the vertex represents a set of interconnection metal wires of the same type in the interconnection resource to be tested, the set of interconnection metal wires of the same type includes at least one interconnection metal wire, and the first directed edge corresponds to a connection relationship between the sets of interconnection metal wires of the same type.

4. The method according to claim 1, characterized in that The configuration times of the routing configuration path is the minimum configuration times that can cover the first interconnection switch, wherein the first interconnection switch represents the interconnection switch covered by the routable path corresponding to the routing configuration path.

5. The method according to claim 1, characterized in that: The obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file includes: Load the bitstream file into the FPGA to be tested and collect response data; Based on the response data, an interconnection resource test result of the FPGA to be tested is obtained.

6. A FPGA interconnection resource testing device, characterized in that: The device comprises: A construction module, used for acquiring the interconnection resources to be tested, and constructing an interconnection resource model to be tested based on the interconnection resources to be tested; An acquisition module, configured to acquire a routable path, wherein the routable path covers the interconnection switches of the interconnection resource model to be tested; A routing configuration path generation module, used for generating a routing configuration path for the routable path; A bitstream file generating module, used for generating a bitstream file based on the routing configuration path; A test module, used for obtaining the interconnection resource test result of the FPGA to be tested based on the bitstream file; Among them, the routing configuration path generation module includes: A graph generation unit, configured to generate a directed graph based on the routable path, wherein the directed graph includes a node and a second directed edge, wherein the node represents an interconnected metal wire, and the second directed edge represents an interconnected switch; A path acquisition unit, used to construct SMT constraints and generate a routing configuration path corresponding to a routable path based on the SMT constraints; Among them, the SMT constraints include signal transmission constraints, mutual exclusion constraints, interconnection switch coverage constraints, constant constraints, and configuration number constraints; the signal transmission constraint means that when one fan-in interconnection switch of a node in a directed graph is enabled in the configuration, at least one fan-out interconnection switch is enabled in the configuration; the mutual exclusion constraint means that for a multiplexer, at most one path is selected in each configuration; the interconnection switch coverage constraint means that each interconnection switch is covered at least once in the generated routing configuration path; the constant constraint means that when there is no second directed edge connecting two nodes in a directed graph, in the generated routing configuration path, the logical variable corresponding to the corresponding second directed edge is configured as a zero constant; the configuration number constraint means that in the SMT solution, the configuration number needs to be minimized.

7. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the FPGA interconnection resource testing method according to any one of claims 1 to 5 by executing the computer instructions.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute an FPGA interconnection resource testing method according to any one of claims 1 to 5.

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