Gate drive circuit and control method

Abstract

The embodiment of the application relates to a kind of gate drive circuit and control method, circuit includes: pull-up control module, pull-up level transmission module, pull-up module, pull-down maintenance module, pull-down reset module, frame after reset module and target capacitor, pull-up control module is connected to the first node with pull-up level transmission module, pull-down maintenance module and frame after reset module;The other end of target capacitor is connected to the input end of next stage shift level transmission unit;By changing the connection relationship of target capacitor, connect next stage shift level transmission unit with target capacitor, then improve the pull-up ability of pull-up module, improve the energizing capacity of pull-up module, reduce the delay time of the scan signal output by drive circuit, reach the purpose of improving the thrust of drive circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display panel driving technology, and more particularly to a gate driving circuit and a control method. Background Art

[0002] The display panel is one of the important components of a display device. The display panel includes pixel units arranged in rows and columns. When the display panel is operating, the gate drive signal controls the opening and closing of the thin film transistors (TFTs) in the pixel units, thereby completing the row scanning of the display panel and realizing the function of the display panel to display images. The gate drive signal is generated by the row drive circuit. Common row drive circuits include gate on array (GOA) drive circuits and chip on film (COF) drive circuits. Due to the advantages of narrow bezels and low cost, gate drive circuits are widely used in display devices.

[0003] By comparing the waveforms at different positions of the existing gate drive circuit during normal operation and the data waveforms under a heavy-load screen, it can be seen that under a heavy-load screen, the actual effective charging time of the gate drive circuit of the display area pixel is very limited. If the scanning signal delay output by the gate drive circuit is large, in order to ensure normal display of the screen, the anti-mischarge time between the scanning line and the signal line will be extended accordingly, further shortening the actual charging time. This leads to the problem of low pixel charging rate, which has a great impact on the application of high-refresh products. Summary of the Invention

[0004] In view of this, in order to solve the technical problem of low pixel charging rate caused by prolonged mis-charging time between scan lines and signal lines in the above-mentioned display area pixels, the embodiments of the present application provide a gate drive circuit and control method.

[0005] In a first aspect, an embodiment of the present application provides a gate drive circuit for driving a display panel. The drive circuit includes a pull-up control module, a pull-up stage transmission module, a pull-up module, a pull-down maintenance module, a pull-down reset module, a post-frame reset module, and a target capacitor, including:

[0006] The pull-up control module is connected to the first node together with the pull-up transmission module, the pull-down maintaining module, and the post-frame reset module. The pull-up control module outputs different control signals to the pull-up transmission module, the pull-down maintaining module, and the post-frame reset module to control the pull-up transmission module, the pull-down maintaining module, and the post-frame reset module to be in corresponding working states.

[0007] The pull-up stage transmission module is connected to the pull-up module, one end of the target capacitor, the pull-down reset module and the pull-down maintenance module, and controls whether the pull-up module is in a signal output state through the pull-up stage transmission module, controls the pull-down maintenance module to be in a signal maintenance state according to a clock signal, controls the pull-down reset module to start a reset process, and controls the charge / discharge state of the target capacitor through the output signal of the pull-up stage transmission module;

[0008] The pull-up module is connected to the input end of the current shift level transmission unit, and is used to output a corresponding shift output signal to the current shift level transmission unit;

[0009] The other end of the target capacitor is connected to the output end of the next-stage shift and transmission unit, and is used to change the point voltage at the first node position according to the change of the output signal of the next-stage shift and transmission unit.

[0010] In one possible implementation, the pull-up control module includes a first transistor, the pull-up stage transmission module includes a second transistor, the pull-up module includes a third transistor, the pull-down reset module includes a fourth transistor, and the target capacitor is a bootstrap capacitor;

[0011] The control terminal of the first transistor is connected to the input signal terminal and the first input terminal of the pull-down maintenance module, the first terminal of the first transistor is connected to the high-potential signal output terminal, and the second terminal of the first transistor is connected to the first node along with the first input terminal of the post-frame reset module, the second input terminal of the pull-down maintenance module, the control terminal of the second transistor, the third input terminal of the pull-down maintenance module, the control terminal of the third transistor, the second terminal of the fourth transistor, and one terminal of the bootstrap capacitor;

[0012] The first end of the second transistor is connected to the first end of the third transistor and the clock signal input end, and the second end of the second transistor is connected to the fourth input end of the pull-down maintenance module, the second input end of the post-frame reset module, and the reset signal;

[0013] The second end of the third transistor is connected to the first output end of the pull-down maintenance module and the output end of the current shift stage transmission unit;

[0014] The other end of the bootstrap capacitor is connected to the output end of the next stage shift stage transmission unit;

[0015] The first end of the fourth transistor, the second output end of the pull-down maintaining module and the output end of the post-frame reset module are connected to the low-level signal output end, and the control end of the fourth transistor is connected to the reset signal output end.

[0016] In one possible implementation, the pull-down maintaining module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0017] The control end of the fifth transistor is connected to the input end of the pull-up control module, the first end of the fifth transistor is connected to the first output end of the post-frame reset module, the second end of the sixth transistor, the second end of the seventh transistor, the control end of the eighth transistor, the control end of the ninth transistor, and the control end of the tenth transistor, and the second end of the fifth transistor is connected to the low-level signal output end, the second end of the seventh transistor, the second end of the eighth transistor, the second end of the ninth transistor, the second end of the tenth transistor, the output end of the pull-down reset module, and the second output end of the post-frame reset module;

[0018] The control terminal of the sixth transistor and the first terminal of the sixth transistor are connected to the high level signal output terminal;

[0019] The control terminal of the seventh transistor and the output terminal of the pull-up control module are connected to the first node;

[0020] A first end of the eighth transistor is connected to the second input end of the post-frame reset module and the output end of the pull-up stage transmission module;

[0021] The first end of the ninth transistor, the third input end of the post-frame reset module, and the output end of the pull-up module are connected to the output end of the current shift stage transmission unit;

[0022] The first end of the tenth transistor is connected to the first node, the output end of the pull-up control module, the input end of the pull-up stage transmission module, the input end of the pull-up module, one end of the target capacitor and the input end of the pull-down reset module.

[0023] In a possible implementation, the post-frame reset module includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;

[0024] The control end of the eleventh transistor, the control end of the twelfth transistor, the control end of the thirteenth transistor, and the control end of the fourteenth transistor are connected to the clock signal output end; the first end of the eleventh transistor is connected as the first input end of the post-frame reset module, the output end of the pull-up control module, the second input end of the pull-down maintaining module, and the input end of the pull-up stage transmission module to the first node; the second end of the eleventh transistor, the second end of the twelfth transistor, the second end of the thirteenth transistor, and the second end of the fourteenth transistor are connected to the low-level signal output end;

[0025] The first end of the twelfth transistor is connected to the output end of the pull-up stage transmission module as the second input end of the post-frame reset module;

[0026] The first end of the thirteenth transistor is connected as the third input end of the post-frame reset module, the input end of the pull-down maintenance module and the output end of the pull-up module to the output end of the current shift stage transmission unit;

[0027] The first end of the fourteenth transistor is connected to the input end of the pull-down maintaining module as the output end of the post-frame reset module.

[0028] In a second aspect, an embodiment of the present application provides a method for controlling a gate drive circuit, including:

[0029] When the pull-up control module receives a high-level input signal, the first output voltage of the current shift stage transmission unit is determined according to the initial voltage of the first node;

[0030] When the pull-up control module receives a low-level input signal, the pull-up control module performs pull-up control on the input signal of the pull-up module according to the second voltage of the first node to obtain a target output voltage of the current shift stage unit, where the second voltage is greater than the initial voltage;

[0031] The charging time of the current shift stage transfer unit is controlled based on the first output voltage and the target output voltage.

[0032] In one possible implementation, when the pull-up control module receives a high-level input signal, determining the first output voltage of the current shift stage unit according to the initial voltage of the first node includes:

[0033] When the first transistor receives a high-level input signal within a first cycle period, obtaining an initial high-level voltage of the first node corresponding to the first cycle period;

[0034] The first output voltage of the current shift stage transfer unit connected to the third transistor is determined according to the initial voltage, the divided voltage of the second transistor and the third transistor.

[0035] In one possible implementation, when the pull-up control module receives a low-level input signal, performing pull-up control on the input signal of the pull-up module according to the second voltage of the first node to obtain a target output voltage of the current shift stage unit includes:

[0036] When the first transistor receives a low-level input signal within the second cycle period, it obtains a high-level signal output by the next-stage shift and transfer unit;

[0037] acquiring a second voltage of the first node according to the high-level signal and a low-level input signal received by the first transistor within a third cycle period;

[0038] The input signal of the third transistor is pulled up based on the second voltage to obtain the target output voltage of the current shift stage transfer unit.

[0039] In a possible implementation, controlling the charging duration of the current shift stage transfer unit based on the first output voltage and the target output voltage includes:

[0040] comparing the first output voltage with the target output voltage to obtain a corresponding comparison result;

[0041] generating a charging strategy for the current shift level transfer unit according to the comparison result;

[0042] The charging time of the current shift and transfer unit is controlled according to the charging strategy.

[0043] In a possible implementation, generating a charging strategy for the current shift and transfer unit according to the comparison result includes:

[0044] When the first output voltage is less than the target output voltage, obtaining a first comparison result;

[0045] generating an accelerated charging strategy for the current shift and transfer unit according to the first comparison result;

[0046] or,

[0047] When the first output voltage is greater than or equal to the target output voltage, obtaining a second comparison result;

[0048] A deceleration charging strategy for the current shift and transfer unit is generated according to the second comparison result.

[0049] In a possible implementation, controlling the charging duration of the current shift and transfer unit according to the charging strategy includes:

[0050] When the charging strategy is an accelerated charging strategy, the maintenance time of the current shift stage transmission unit is reduced based on the target output voltage, and a control operation is performed on the previous shift stage transmission unit to shorten the charging time;

[0051] or,

[0052] When the charging strategy is a deceleration charging strategy, the maintenance time of the current shift stage transmission unit is increased based on the target output voltage, and a control operation of delaying the charging time of the previous shift stage transmission unit is performed.

[0053] The gate drive circuit provided by the embodiment of the present application is provided with a pull-up control module, a pull-up stage transmission module, a pull-up module, a pull-down maintenance module, a pull-down reset module, a post-frame reset module and a target capacitor. The pull-up control module is connected to the pull-up stage transmission module, the pull-down maintenance module and the post-frame reset module to a first node, and different control signals are output to the pull-up stage transmission module, the pull-down maintenance module and the post-frame reset module through the pull-up control module to control the pull-up stage transmission module, the pull-down maintenance module and the post-frame reset module to be in corresponding working states; the pull-up stage transmission module is connected to the pull-up module, one end of the target capacitor, the pull-down reset module and the pull-down maintenance module, and the pull-up module is controlled by the pull-up stage transmission module to be in a signal output state, and the pull-down module is controlled to be in a signal output state. The pull-up maintenance module is in a signal maintenance state according to the clock signal, controls the pull-down reset module to start the reset process, and controls the charge / discharge state of the target capacitor through the output signal of the pull-up stage transmission module; the pull-up module is connected to the input end of the current shift stage transmission unit, and is used to output the corresponding shift output signal to the current shift stage transmission unit; the other end of the target capacitor is connected to the output end of the next-stage shift stage transmission unit, and is used to change the point voltage of the first node position through the change of the output signal of the next-stage shift stage transmission unit; by changing the connection relationship of the target capacitor, the target capacitor is used to connect the next-stage shift stage transmission unit, thereby improving the pull-up ability of the pull-up module, thereby improving the power-on ability of the pull-up module, reducing the maintenance time of the scanning signal output by the driving circuit, and achieving the purpose of improving the driving ability of the driving circuit. By this solution, it is possible to reduce the anti-mischarge time between the scanning line and the signal line of the gate driving circuit, achieve the technical effect of improving the pixel charging rate, and enhance the taste of high-refresh products. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0055] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0057] Figure 1A structural schematic diagram of a gate drive circuit in the prior art;

[0058] Figure 2 An output signal waveform diagram of a gate drive circuit in the prior art;

[0059] Figure 3 A structural schematic diagram of a gate drive circuit provided in the present application;

[0060] Figure 4 A signal timing waveform diagram of a gate drive circuit provided in the present application;

[0061] Figure 5 A signal timing waveform comparison diagram of a gate drive circuit provided in the present application and a signal timing waveform in the prior art;

[0062] Figure 6 A flowchart of a control method of a gate drive circuit provided in the present application;

[0063] Figure 7 A flowchart of another control method of a gate drive circuit provided in the present application. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0065] The terms “include” and “have” in the embodiments of the present application are used to represent an open-ended inclusion, and refer to the presence of additional elements / components, etc. in addition to the listed elements / components, etc.; the terms “first” and “second” and the like are used only as labels, and are not intended to limit the number of objects. In addition, different elements and regions in the drawings are only schematically shown, and thus the present application is not limited to the sizes or distances shown in the drawings.

[0066] Figure 1 A structural schematic diagram of a gate drive circuit in the prior art; Figure 2 An output signal waveform diagram of a gate drive circuit in the prior art. According to Figure 1 and Figure 2 According to the provided diagrams, the gate drive circuit in the prior art includes a pull-up control module 10, a pull-up stage transmission module 20, a pull-up module 30, a pull-down maintenance module 40, a frame post-reset module 50, a pull-down reset module 60 and a bootstrap capacitor C1. According toFigure 1 As can be seen from the provided diagram, the bootstrap capacitor and the output end of the pull-up module are connected to the current shift stage transmission unit, and the charging time during the gate drive process is controlled by the charging and discharging time of the bootstrap capacitor. Figure 2 The provided diagram shows that during the gate drive process, the charging duration of the current shift stage is controlled by the connected bootstrap capacitor. Under heavy load, the gate drive pre-charge function fails, and the effective charging time is limited. This prolongs the charging hold time, making the drive process more susceptible to startup problems caused by the excessive hold time.

[0067] In order to solve the above problems, the present application proposes a gate drive circuit, which changes the connection relationship of the bootstrap capacitor in the gate drive circuit, changes the charging time of the bootstrap capacitor, shortens the maintenance time of the scanning signal output by the drive circuit, and thus achieves the purpose of improving the charging rate.

[0068] To facilitate understanding of the embodiments of the present application, further explanation will be given below with reference to specific embodiments in conjunction with the accompanying drawings. The embodiments do not constitute a limitation on the embodiments of the present application.

[0069] Figure 3 This is a schematic diagram of the structure of a gate drive circuit provided in this application. Figure 3 The structure of the gate drive circuit specifically includes:

[0070] Pull-up control module 11 , pull-up stage transmission module 12 , pull-up module 13 , pull-down maintaining module 14 , pull-down reset module 15 , post-frame reset module 16 and target capacitor C.

[0071] The pull-up control module 11 is connected to the first node PU, and the pull-up transmission module 12, the pull-down maintenance module 14 and the post-frame reset module 16. The pull-up control module 11 outputs different control signals to the pull-up transmission module 12, the pull-down maintenance module 14 and the post-frame reset module 16 to control the pull-up transmission module 12, the pull-down maintenance module 14 and the post-frame reset module 16 to be in the corresponding working state.

[0072] The pull-up transmission module 12 is connected to the pull-up module 13, one end of the target capacitor C, the pull-down reset module 15 and the pull-down maintenance module 14. The pull-up transmission module 12 controls whether the pull-up module 13 is in the signal output state, controls the pull-down maintenance module 14 to be in the signal maintenance state according to the clock signal, controls the pull-down reset module 15 to start the reset processing, and controls the charge / discharge state of the target capacitor C through the output signal of the pull-up transmission module 12.

[0073] The pull-up module 13 is connected to the input end of the current shift stage transmission unit Gn, and is used to output a corresponding shift output signal to the current shift stage transmission unit Gn.

[0074] The other end of the target capacitor C is connected to the output end of the next-stage shift and transmission unit Gn, and is used to change the point voltage at the first node PU according to the change of the output signal of the next-stage shift and transmission unit Gn.

[0075] according to Figure 3 The diagram provided shows that at the initial stage of gate drive, a high-level signal is input to the pull-up control module to control the internal conduction of the pull-up control module, so that the voltage of the first node PU is high. At this time, the target capacitor is charged through the pull-up stage transmission module; in the next stage, the high-level signal is stopped from being input to the pull-up control module, and a low-level signal is output instead, so that the internal is shut down. Due to the charging of the target capacitor, the voltage at the first node PU is still high; in the next stage, under the pull-up action of the pull-up stage transmission module, the voltage at the first node PU is pulled up. Since the other end of the target capacitor is connected to the next shift stage transmission unit, when the next shift stage transmission unit outputs a high level due to the discharge of the target capacitor, the voltage of the target capacitor is higher than the output voltage of the current shift stage transmission unit, thereby improving the discharge capacity and accelerating the discharge, so that the potential of the next-level shift stage transmission unit changes, thereby achieving the purpose of increasing the potential of the first node PU corresponding to the current shift stage transmission unit, thereby achieving the purpose of increasing the discharge rate. Figure 1 Compared with the existing technology provided in, the connection relationship of the target capacitor is changed, so that the current shift stage transfer unit can reduce the maintenance time of the scanning signal during the charging process, increase the charging speed, and achieve the effect of improving the charging rate.

[0076] The gate drive circuit provided by the embodiment of the present application is provided with a pull-up control module, a pull-up stage transmission module, a pull-up module, a pull-down maintenance module, a pull-down reset module, a post-frame reset module and a target capacitor. The pull-up control module is connected to the pull-up stage transmission module, the pull-down maintenance module and the post-frame reset module to the first node, and different control signals are output to the pull-up stage transmission module, the pull-down maintenance module and the post-frame reset module through the pull-up control module to control the pull-up stage transmission module, the pull-down maintenance module and the post-frame reset module to be in corresponding working states; the pull-up stage transmission module is connected to the pull-up module, one end of the target capacitor, the pull-down reset module and the pull-down maintenance module, and the pull-up module is controlled to be in a signal output state through the pull-up stage transmission module, and the pull-down maintenance module is controlled according to the clock signal. In the signal maintenance state, the pull-down reset module is controlled to start the reset process, and the charge / discharge state of the target capacitor is controlled by the output signal of the pull-up stage transmission module; the pull-up module is connected to the input end of the current shift stage transmission unit, and is used to output the corresponding shift output signal to the current shift stage transmission unit; the other end of the target capacitor is connected to the input end of the next-stage shift stage transmission unit, and is used to change the point voltage of the first node position through the change of the output signal of the next-stage shift stage transmission unit; by changing the connection relationship of the target capacitor, the target capacitor is used to connect the next-stage shift stage transmission unit, thereby improving the pull-up ability of the pull-up module, thereby improving the power-on ability of the pull-up module, reducing the maintenance time of the scanning signal output by the driving circuit, and achieving the purpose of improving the driving ability of the driving circuit. By this solution, it is possible to reduce the anti-mischarge time between the scanning line and the signal line of the gate driving circuit, thereby improving the pixel charging rate and enhancing the taste of high-refresh products.

[0077] according to Figure 3 The structure of the gate drive circuit specifically includes:

[0078] Pull-up control module 11 , pull-up stage transmission module 12 , pull-up module 13 , pull-down maintaining module 14 , pull-down reset module 15 , post-frame reset module 16 and target capacitor C.

[0079] according to Figure 3 According to the diagram provided, the pull-up control module in the gate drive circuit includes a first transistor M1, the pull-up stage transmission module includes a second transistor M2, the pull-up module includes a third transistor M3, the pull-down reset module includes a fourth transistor M4, and the target capacitor is the bootstrap capacitor C0.

[0080] The control end of the first transistor M1 is connected to the input signal end input and the first input end of the pull-down maintenance module 14, the first end of the first transistor M1 is connected to the high potential signal vgh output end, and the second end of the first transistor M1 is connected to the first input end of the post-frame reset module 16, the second input end of the pull-down maintenance module 14, the control end of the second transistor M2, the third input end of the pull-down maintenance module 14, the control end of the third transistor M3, the second end of the fourth transistor M4 and one end of the bootstrap capacitor C0 are connected to the first node PU.

[0081] The first end of the second transistor M2 is connected to the first end of the third transistor M3 and the clock signal ckn input end, and the second end of the second transistor M2 is connected to the fourth input end of the pull-down maintenance module 14, the second input end of the post-frame reset module 16 and the reset signal Tn.

[0082] The second end of the third transistor M3 is connected to the first output end of the pull-down maintaining module 14 and the output end of the current shift stage transmission unit Gn.

[0083] The other end of the bootstrap capacitor C0 is connected to the output end of the next-stage shift stage transfer unit Gn+1.

[0084] The first end of the fourth transistor M4 is connected to the low level signal VSS output end, the second output end of the pull-down maintaining module 14 and the output end of the post-frame reset module 16 , and the control end of the fourth transistor M4 is connected to the reset signal reset output end.

[0085] The transistors referred to herein are field-effect transistors, such as MOS transistors, IGBTs, or bipolar insulated gate field-effect transistors, and other transistors or triodes that function as switches, all of which fall within the scope of protection of this application. The control terminal of the transistor referred to herein is the gate of the MOS transistor, the first terminal of the transistor is the drain of the MOS transistor, and the second terminal of the transistor is the source of the MOS transistor.

[0086] according to Figure 3In the diagram provided, the first transistor turns on when it receives a high-level signal. Simultaneously, the high-level signal causes the pull-down holding module to be internally conductive, maintaining electrical signal stability. Simultaneously, after the first transistor turns on, the voltage at the first node PU rises to a high level, charging the bootstrap capacitor C0. The second and third transistors, under the action of the high level, are in a conductive state, transmitting the level signal and transmitting the signal to the current shift level unit Gn, achieving the purpose of level transmission display. When the first transistor stops receiving the high-level signal and switches to receiving a low-level signal, the first transistor turns off. With a certain charge stored in the bootstrap capacitor C0, the third transistor remains in a conductive state and continues to output the level transmission signal. Moreover, at this time, the connection between the bootstrap capacitor and the next-stage shift stage transmission unit causes the next-stage shift stage transmission unit to enter the pre-charging stage in advance, thereby shortening the maintenance time of the scanning signal of the current shift stage transmission unit, and under the action of the pull-up module pulling up the voltage of the bootstrap capacitor, the terminal voltage of the bootstrap capacitor is increased, which increases the gate voltage of the third transistor, thereby improving the conductivity of the third transistor, accelerating the charging process, reducing the anti-mischarge time between the scanning line and the signal line, and thus improving the charging rate.

[0087] according to Figure 3 According to the provided diagram, the pull-down maintaining module in the gate driving circuit includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10.

[0088] The control end of the fifth transistor M5 is connected to the input end of the pull-up control module 11, the first end of the fifth transistor M5 is connected to the first output end of the post-frame reset module 16, the second end of the sixth transistor M6, the second end of the seventh transistor M7, the control end of the eighth transistor M8, the control end of the ninth transistor M9 and the control end of the tenth transistor M10, and the second end of the fifth transistor M5 is connected to the second end of the seventh transistor M7, the second end of the eighth transistor M8, the second end of the ninth transistor M9, the second end of the tenth transistor M10, the output end of the pull-down reset module 15 and the second output end of the post-frame reset module 16 are connected to the low-level signal VSS output end.

[0089] The control terminal of the sixth transistor M6 and the first terminal of the sixth transistor M6 are connected to the high level signal vgh output terminal.

[0090] The control terminal of the seventh transistor M7 and the output terminal of the pull-up control module 11 are connected to the first node PU.

[0091] A first end of the eighth transistor M8 is connected to the second input end of the post-frame reset module 16 and the output end of the pull-up transmission module 12 .

[0092] The first end of the ninth transistor M9 is connected to the output end of the current shift stage transfer unit Gn, the third input end of the post-frame reset module 16 , and the output end of the pull-up module 13 .

[0093] The first end of the tenth transistor M10 is connected to the first node PU, the output end of the pull-up control module 11 , the input end of the pull-up stage transmission module 12 , the input end of the pull-up module 13 , one end of the target capacitor C0 , and the input end of the pull-down reset module 15 .

[0094] The gates of the eighth transistor, the ninth transistor, and the tenth transistor are set to be connected to the second node PD.

[0095] according to Figure 3 The diagram provided shows that when the pull-up control module receives a high-level signal, the voltage at the first node PU increases, initiating the charging process of the bootstrap capacitor C0. This is the lighting period of the current shift-stage transmission unit and the pre-charging period of the next-stage shift-stage transmission unit, thereby shortening the hold time. Simultaneously, under the action of the high-level signal, the fifth transistor is controlled to conduct, lowering the voltage at the second node PD where the gates of the eighth, ninth, and tenth transistors are located. During this stage, the pull-down hold control is not activated, and the circuit is in the charging process. When the pull-up control module receives a low-level signal, the fifth transistor is turned off, causing the voltage at the second node PD where the gates of the eighth, ninth, and tenth transistors are located to increase, thereby achieving the purpose of pull-down hold, maintaining the current state, and enabling stage transmission.

[0096] according to Figure 3 According to the provided diagram, the post-frame reset module in the gate driving circuit includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14.

[0097] The control end of the eleventh transistor M11, the control end of the twelfth transistor M12, the control end of the thirteenth transistor M13 and the control end of the fourteenth transistor M14 are connected to the clock signal ckn output end, the first end of the eleventh transistor M11 serves as the first input end of the post-frame reset module 16 and is connected to the first node PU together with the output end of the pull-up control module 11, the second input end of the pull-down maintenance module 14 and the input end of the pull-up stage transmission module 12, the second end of the eleventh transistor M11, the second end of the twelfth transistor M12, the second end of the thirteenth transistor M13 and the second end of the fourteenth transistor M14 are connected to the low-level signal VSS output end.

[0098] The first end of the twelfth transistor M12 is connected to the output end of the pull-up transmission module 12 as the second input end of the post-frame reset module 16 .

[0099] The first end of the thirteenth transistor M13 is connected as the third input end of the post-frame reset module 16 , the input end of the pull-down maintaining module 14 , and the output end of the pull-up module 13 to the output end of the current shift stage transfer unit Gn.

[0100] The first end of the fourteenth transistor M14 , serving as the output end of the post-frame reset module 16 , is connected to the input end of the pull-down maintaining module 14 .

[0101] according to Figure 3 According to the diagram provided, a high-level signal is received by the pull-up control module, so that the voltage of the first node PU is pulled up, and then the charging state is entered. After the charging is completed, after the pull-up control module receives a low-level signal, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 are controlled to be turned on through the clock signal. At this time, the voltage on the bootstrap capacitor is discharged, thereby realizing reset control.

[0102] In one possible example scenario, Figure 4 This is a signal timing waveform diagram of a gate drive circuit provided by this application. Figure 3 and Figure 4 As shown in the figure, the STV signal is a high-level signal before each frame and serves as the input signal for the first four gate drive units; the CLR signal is a high-level signal after each frame and serves as the reset signal for the last six gate drive units. It also clears the charge of PU, Tn, and Gn in each gate drive unit after each frame. Set the input signal to T1 and the reset signal to T11. Figure 4 The specific waveform states of the waveform diagrams of the important nodes in the gate drive are as follows:

[0103] The time before the t1 phase and after the t3 phase are both the holding time in one frame, and both are low-level signals.

[0104] Phase t1: The input signal T1 of the pull-up control module 11 is high, turning on the first transistor M1 and the fifth transistor M5. The first transistor M1 charges the bootstrap capacitor C0, causing the potential of the PU node to reach a high level of VGH, and the voltage difference across the bootstrap capacitor C0 to be VGH-VSS. The fifth transistor M5 turns on, turning off the pull-down maintenance module 14, rendering it inoperative. This means that the PD node is pulled low via the fifth transistor M5 and the seventh transistor M7 (PU is high). At this time, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are turned off. Since the voltage at point PU reaches a high level, the second transistor M2 and the third transistor M3 turn on, outputting the connected CK5 signal (i.e., T5 and the current shift stage transmission unit G5, which is a low signal at this time).

[0105] Phase t2: The input signal T1 becomes a low-level signal, turning off the first transistor M1 and the fifth transistor M5. Due to the energy storage function of the bootstrap capacitor C0, the PU node is still at a high level VGH. The seventh transistor M7, the second transistor M2, and the third transistor M3 are turned on. When CK5 becomes a high-level signal, T5 and G5 output by the current shift stage transfer unit G5 begin to output a high level.

[0106] Phase t3: The next-stage shift stage transfer unit G6 starts to output a high-level signal (from VSS to VGH). Since the voltage difference across the bootstrap capacitor C0 remains unchanged, the voltage of the PU node is raised to a higher voltage level. During this period, CK5 must become a low-level signal. That is, when T5 / G5 starts to output a low-level signal, the voltage of the PU node is the voltage level raised by the bootstrap capacitor C0 coupling. That is, the gate voltage of the third transistor M3 is larger, and the output capacity is increased, thereby reducing the falling edge Tf time of Gn and shortening the holding time, thereby shortening the anti-mischarge time and improving the charging rate.

[0107] Phase t4: T6 starts to output a low-level signal, the voltage of the PU node is pulled down to the original VGH level, and the second transistor M2 and the third transistor M3 still output the low-level signal of CK5.

[0108] Subsequently, in the maintenance phase: the reset signal T11 becomes a high level, the fourth transistor M4 is turned on, the bootstrap capacitor C0 is discharged, and the bootstrap capacitor C0 is pulled to the low level VSS. At the same time, the seventh transistor M7, the second transistor M2 and the third transistor M3 are controlled to be turned off, and the point voltage of the second node PD is pulled up to a high level by the sixth transistor M6. The maintenance module starts to work, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are turned on, and the point voltage of T5, the current shift stage unit G5 and the first node PU are maintained at the low level VSS, completing the charging and driving process of the current shift stage unit.

[0109] In one possible example scenario, Figure 5 This is a comparison diagram of the signal timing waveform of a gate drive circuit provided by this application and the signal timing waveform of the prior art. Figure 5The provided diagram shows that, compared with the prior art, the gate voltage of the third transistor M3 in the pull-up module is equal to the difference between the voltage at the first node PU and the output voltage of the current shift stage transmission unit Gn. In the initial period when the current shift stage transmission unit Gn outputs a high level, due to the self-boosting capacitor connected to the next shift stage transmission unit Gn+1, according to the stage transmission structure, each shift stage transmission unit enters the pre-charge period in advance, thereby shortening the error-proof charging time of the scan signal, and thereby changing the sudden decrease of the gate voltage of the third transistor M3 in the second time period in the present application. After entering the charging period, stable charging is achieved, but due to the fact that the previous shift stage transmission unit enters the reset period in advance, the voltage at the PU node is still in the charging period, which increases the gate voltage of the third transistor M3 under the action of transistor voltage drop, thereby enhancing the conductivity of the third transistor, accelerating the charging process, and at the same time, due to the fact that the next shift stage transmission unit is pre-charged in advance, the holding time between the scan line and the signal of the current shift stage transmission unit is shortened, thereby achieving the purpose of improving the charging rate.

[0110] Figure 6 A flowchart of a control method of a gate drive circuit is provided for the present application. It is applied to a gate drive circuit. According to Figure 6 The provided diagram shows that the steps of the control method of the gate drive circuit specifically include:

[0111] S601, when the pull-up control module receives a high-level input signal, determining the first output voltage of the current shift stage transmission unit according to the initial voltage of the first node.

[0112] The present application is applied to the control process of a gate drive circuit. It is used to drive a gate display screen. By controlling the size of the input signal, the voltage of the first node connected to the output end of the pull-up control module is controlled, and the charge and discharge state of the self-boosting capacitor is determined according to the voltage at the first node. Since the self-boosting capacitor is connected to the output end of the next shift stage transmission unit, compared with the prior art, the next shift stage transmission unit will be brought into the pre-charge period in advance, thereby increasing the voltage at the first node in the current shift stage transmission unit and improving the charging capacity of the pull-up module, and shortening the maintenance time of the scan signal. At the same time, when the pull-up control module stops transmitting the high-level signal, due to the pull-up effect of the pull-up module, the voltage across the self-boosting capacitor is increased, thereby increasing the voltage at the input end of the pull-up module and increasing the charging capacity of the pull-up module for the current shift stage transmission unit, thereby achieving the technical effect of improving the charging rate.

[0113] The high-level input signal mentioned here is input by an external control signal. The current shift stage transmission unit mentioned here can be understood as a driving unit connected to the output end of the current shift unit. The first output voltage mentioned here can be understood as the output voltage of the shift stage transmission unit.

[0114] Further, after the pull-up control module is started by the external input signal, the pull-up control module is turned on, the pull-down maintenance module is kept in the off state, the voltage of the first node is set as the initial voltage, and under the action of the initial voltage being higher than the turn-on voltage, the pull-up stage transmission module and the pull-up module are turned on, the first output voltage of high level is output to the current shift stage transmission unit, and the bootstrap capacitor enters the charging state.

[0115] S602, when the pull-up control module receives a low-level input signal, the input signal of the pull-up module is controlled according to the second voltage of the first node, the target output voltage of the current shift stage transmission unit is obtained, and the second voltage is higher than the initial voltage.

[0116] Here, the pull-up control can be understood as lifting the input voltage value by the pull-up module to achieve the purpose of pull-up signal.

[0117] Further, when the external input signal is a low-level signal, the pull-up shift stage transmission module is controlled to be turned off, the pull-down maintenance module is started to maintain control, and the charging is ensured to continue. At the same time, the second voltage is accumulated at the first node, and the second voltage is higher than the initial voltage, so as not to affect the voltage of the bootstrap capacitor, but to improve the voltage difference between the bootstrap voltage, so as to improve the input signal of the pull-up module, and output the target output voltage to the current shift stage transmission unit through the pull-up module.

[0118] S603, the charging time of the current shift stage transmission unit is controlled based on the first output voltage and the target output voltage.

[0119] Further, by comparing the first output voltage and the target output voltage, it can be obtained that when the bootstrap capacitor charges the next shift stage transmission unit, the voltage of the output end of the current shift stage transmission unit is increased, thereby improving the voltage output capability and shortening the error prevention charging time between the scan line and the signal line, so as to improve the charging rate.

[0120] Figure 7 Another flowchart of the control method of the gate drive circuit provided in the application is provided. Figure 7 Based on the above embodiment, according to Figure 7 According to the provided diagram, the steps of the control method of the gate drive circuit specifically include:

[0121] S701, when the first transistor receives a high-level input signal in a first period, the initial voltage of the first node corresponding to the high level of the first period is obtained.

[0122] The charging period of the gate drive circuit mentioned here includes four periods. The switching state and the charging state of each transistor are different in each period.

[0123] Furthermore, when the gate drive circuit is started, a high-level voltage is received through the gate of the first transistor, so that the first transistor is turned on, and the fifth transistor is controlled to be turned on at the same time. After the fifth transistor is turned on, the gate voltages of the eighth transistor, the ninth transistor and the tenth transistor are reduced, thereby closing the maintenance control, so that the voltage of the first node is high, and the high-level voltage at this time is used as the initial voltage.

[0124] S702 : Determine a first output voltage of a current shift stage transfer unit connected to the third transistor according to the initial voltage, the divided voltage of the second transistor and the third transistor.

[0125] Furthermore, when the voltage at the first node is initially high, the second and third transistors are controlled to be turned on, thereby entering a bootstrap capacitor charging period and a pre-charging period for the next shift stage transmission unit. By turning on the third transistor, the current shift stage transmission unit outputs the first output voltage.

[0126] S703 : When the first transistor receives a low-level input signal within the second cycle period, it obtains a high-level signal output by the next-stage shift and transfer unit.

[0127] S704 : Obtain a second voltage of the first node according to the high-level signal and the low-level input signal received by the first transistor within the third cycle period.

[0128] S705 , performing pull-up control on the input signal of the third transistor based on the second voltage to obtain a target output voltage of the current shift stage transfer unit.

[0129] The second voltage is greater than the initial voltage.

[0130] Furthermore, when the first transistor receives a low-level signal, the fifth transistor is turned off, while the eighth, ninth, and tenth transistors are turned on. The gate drive circuit enters a maintenance phase, maintaining the output of the current shift stage transmission unit. The output signal at this time is the target output voltage. Under the pull-up action of the pull-up module, the voltage across the bootstrap capacitor is pulled up, and the voltage of the first node is the second voltage. Because the second voltage is higher than the initial voltage, the gate voltage of the third transistor is increased, thereby improving the conductivity of the third transistor and obtaining the target output voltage of the current shift stage transmission unit.

[0131] S706 : Compare the first output voltage with the target output voltage to obtain a corresponding comparison result.

[0132] S707: Generate a charging strategy for the current shift-stage transmission unit according to the comparison result.

[0133] Further, since the initial voltage is lower than the second voltage, it is further inferred that the size relationship between the target output voltage and the first output voltage in the voltage output by the third transistor, and the charging capability of the current shift stage transmission unit is determined by the size relationship between the first output voltage and the target output voltage.

[0134] The specific implementation steps of determining the charging strategy include:

[0135] Step 1: When the first output voltage is less than the target output voltage, a first comparison result is obtained.

[0136] Step 2: An accelerated charging strategy of the current shift stage transmission unit is generated according to the first comparison result.

[0137] Step 3: When the first output voltage is greater than or equal to the target output voltage, a second comparison result is obtained.

[0138] Step 4: A decelerated charging strategy of the current shift stage transmission unit is generated according to the second comparison result.

[0139] According to the steps of determining the charging strategy, it can be known that in the bootstrap capacitor charging and maintaining phase, if the voltage across the bootstrap capacitor is pulled high, the gate voltage of the third transistor will be increased, and the corresponding conduction capability will be increased, the charging period of the next period will be accelerated, and the error prevention charging period between the scan line and the Sine line in the display area will be shortened. When the voltage across the bootstrap capacitor decreases, the charging time will be extended, which will result in an increase in the maintaining time and a decrease in the charging rate.

[0140] S708, control the charging time of the current shift stage transmission unit according to the charging strategy.

[0141] The specific implementation steps of controlling the charging time of the current shift stage transmission unit include:

[0142] Step 1: When the charging strategy is the accelerated charging strategy, the maintaining time of the current shift stage transmission unit is reduced based on the target output voltage, and the control operation of shortening the charging time of the previous shift stage transmission unit is performed.

[0143] Step 2: When the charging strategy is the decelerated charging strategy, the maintaining time of the current shift stage transmission unit is increased based on the target output voltage, and the control operation of delaying the charging time of the previous shift stage transmission unit is performed.

[0144] According to different charging strategies, different control of the charging time length of the current shift stage transmission unit is realized. On the basis of the deceleration charging strategy, the maintenance time length of the current shift stage transmission unit is increased, and the whole charging process is prolonged, so that the charging rate of the driving circuit is reduced. On the basis of the acceleration charging strategy, and under the pre-charging effect of the next stage shift stage transmission unit, the maintenance time length of the scan signal of the current shift stage transmission unit is shortened, and the purpose of shortening the whole charging time length is achieved, and the technical effect of improving the charging rate is realized.

[0145] The control method of the gate drive circuit provided by the embodiments of the present application improves the connection mode of the bootstrap capacitor and the next stage shift stage transmission unit, advances the pre-charging period of the next stage shift stage transmission unit, simultaneously increases the voltage across the bootstrap capacitor, increases the gate voltage of the third transistor, improves the conduction ability of the third transistor, speeds up the charging process, shortens the error-proof charging time between the scan line and the signal line, simultaneously reduces the discharge falling edge time, and achieves the technical effect of improving the charging rate.

[0146] The above specific embodiments further specifically describe the purposes, technical solutions and beneficial effects of the present application, and it should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A gate drive circuit for driving a display panel, comprising a pull-up control module, a pull-up stage transmission module, a pull-up module, a pull-down maintenance module, a pull-down reset module, a post-frame reset module, and a target capacitor, wherein: include: The pull-up control module is connected to the first node together with the pull-up transmission module, the pull-down maintaining module, and the post-frame reset module. The pull-up control module outputs different control signals to the pull-up transmission module, the pull-down maintaining module, and the post-frame reset module to control the pull-up transmission module, the pull-down maintaining module, and the post-frame reset module to be in corresponding working states. The pull-up stage transmission module is connected to the pull-up module, one end of the target capacitor, the pull-down reset module and the pull-down maintenance module, and controls whether the pull-up module is in a signal output state through the pull-up stage transmission module, controls the pull-down maintenance module to be in a signal maintenance state according to a clock signal, controls the pull-down reset module to start a reset process, and controls the charge / discharge state of the target capacitor through the output signal of the pull-up stage transmission module; The pull-up module is connected to the input end of the current shift level transmission unit, and is used to output a corresponding shift output signal to the current shift level transmission unit; The other end of the target capacitor is connected to the output end of the next-stage shift and transmission unit, and is used to change the point voltage at the first node position according to the change of the output signal of the next-stage shift and transmission unit.

2. The circuit according to claim 1, wherein: The pull-up control module includes a first transistor, the pull-up stage transmission module includes a second transistor, the pull-up module includes a third transistor, the pull-down reset module includes a fourth transistor, and the target capacitor is a bootstrap capacitor; The control terminal of the first transistor is connected to the input signal terminal and the first input terminal of the pull-down maintenance module, the first terminal of the first transistor is connected to the high-potential signal output terminal, and the second terminal of the first transistor is connected to the first node along with the first input terminal of the post-frame reset module, the second input terminal of the pull-down maintenance module, the control terminal of the second transistor, the third input terminal of the pull-down maintenance module, the control terminal of the third transistor, the second terminal of the fourth transistor, and one terminal of the bootstrap capacitor; The first end of the second transistor is connected to the first end of the third transistor and the clock signal input end, and the second end of the second transistor is connected to the fourth input end of the pull-down maintenance module, the second input end of the post-frame reset module, and the reset signal; The second end of the third transistor is connected to the first output end of the pull-down maintenance module and the output end of the current shift stage transmission unit; The other end of the bootstrap capacitor is connected to the output end of the next stage shift stage transmission unit; The first end of the fourth transistor, the second output end of the pull-down maintaining module and the output end of the post-frame reset module are connected to the low-level signal output end, and the control end of the fourth transistor is connected to the reset signal output end.

3. The circuit according to claim 1, wherein: The pull-down maintaining module includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The control end of the fifth transistor is connected to the input end of the pull-up control module, the first end of the fifth transistor is connected to the first output end of the post-frame reset module, the second end of the sixth transistor, the second end of the seventh transistor, the control end of the eighth transistor, the control end of the ninth transistor, and the control end of the tenth transistor, and the second end of the fifth transistor is connected to the low-level signal output end, the second end of the seventh transistor, the second end of the eighth transistor, the second end of the ninth transistor, the second end of the tenth transistor, the output end of the pull-down reset module, and the second output end of the post-frame reset module; The control terminal of the sixth transistor and the first terminal of the sixth transistor are connected to the high level signal output terminal; The control terminal of the seventh transistor and the output terminal of the pull-up control module are connected to the first node; A first end of the eighth transistor is connected to the second input end of the post-frame reset module and the output end of the pull-up stage transmission module; The first end of the ninth transistor, the third input end of the post-frame reset module, and the output end of the pull-up module are connected to the output end of the current shift stage transmission unit; The first end of the tenth transistor is connected to the first node, the output end of the pull-up control module, the input end of the pull-up stage transmission module, the input end of the pull-up module, one end of the target capacitor and the input end of the pull-down reset module.

4. The circuit according to claim 1, wherein: The post-frame reset module includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor; The control end of the eleventh transistor, the control end of the twelfth transistor, the control end of the thirteenth transistor, and the control end of the fourteenth transistor are connected to the clock signal output end; the first end of the eleventh transistor is connected as the first input end of the post-frame reset module, the output end of the pull-up control module, the second input end of the pull-down maintaining module, and the input end of the pull-up stage transmission module to the first node; the second end of the eleventh transistor, the second end of the twelfth transistor, the second end of the thirteenth transistor, and the second end of the fourteenth transistor are connected to the low-level signal output end; The first end of the twelfth transistor is connected to the output end of the pull-up stage transmission module as the second input end of the post-frame reset module; The first end of the thirteenth transistor is connected as the third input end of the post-frame reset module, the input end of the pull-down maintenance module and the output end of the pull-up module to the output end of the current shift stage transmission unit; The first end of the fourteenth transistor is connected to the input end of the pull-down maintaining module as the output end of the post-frame reset module.

5. A control method for a gate drive circuit, characterized in that: include: When the pull-up control module receives a high-level input signal, the first output voltage of the current shift stage transmission unit is determined according to the initial voltage of the first node; When the pull-up control module receives a low-level input signal, the pull-up control module performs pull-up control on the input signal of the pull-up module according to the second voltage of the first node to obtain a target output voltage of the current shift stage unit, where the second voltage is greater than the initial voltage; controlling a charging time of the current shift stage transfer unit based on the first output voltage and the target output voltage; The method of determining the first output voltage of the current shift stage transmission unit according to the initial voltage of the first node when the pull-up control module receives a high-level input signal includes: When the first transistor receives a high-level input signal within a first cycle period, obtaining an initial high-level voltage of the first node corresponding to the first cycle period; Determine a first output voltage of a current shift stage transfer unit connected to the third transistor according to the initial voltage, the divided voltage of the second transistor and the third transistor; When the pull-up control module receives a low-level input signal, the pull-up control module performs pull-up control on the input signal of the pull-up module according to the second voltage of the first node to obtain the target output voltage of the current shift stage transfer unit, including: When the first transistor receives a low-level input signal within the second cycle period, it obtains a high-level signal output by the next-stage shift and transfer unit; acquiring a second voltage of the first node according to the high-level signal and a low-level input signal received by the first transistor within a third cycle period; The input signal of the third transistor is pulled up based on the second voltage to obtain the target output voltage of the current shift stage transfer unit.

6. The method according to claim 5, characterized in that The controlling the charging time of the current shift stage transfer unit based on the first output voltage and the target output voltage includes: comparing the first output voltage with the target output voltage to obtain a corresponding comparison result; generating a charging strategy for the current shift level transfer unit according to the comparison result; The charging time of the current shift and transfer unit is controlled according to the charging strategy.

7. The method according to claim 6, characterized in that Generating a charging strategy for the current shift and transfer unit according to the comparison result includes: When the first output voltage is less than the target output voltage, obtaining a first comparison result; generating an accelerated charging strategy for the current shift and transfer unit according to the first comparison result; or, When the first output voltage is greater than or equal to the target output voltage, obtaining a second comparison result; A deceleration charging strategy for the current shift and transfer unit is generated according to the second comparison result.

8. The method according to claim 7, characterized in that The controlling the charging duration of the current shift and transfer unit according to the charging strategy includes: When the charging strategy is an accelerated charging strategy, the maintenance time of the current shift stage transmission unit is reduced based on the target output voltage, and a control operation is performed on the previous shift stage transmission unit to shorten the charging time; or, When the charging strategy is a deceleration charging strategy, the maintenance time of the current shift stage transmission unit is increased based on the target output voltage, and a control operation of delaying the charging time of the previous shift stage transmission unit is performed.

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