Comparator and methods for comparing voltages

Abstract

A comparator includes: a differential amplifier having a first port (INN), a second port (INP), and an output port, wherein the output port outputs a comparison result signal obtained by amplifying the result of subtracting the first signal from a second signal; a first capacitor element (C1) connected between the INN and a system input port (PIXEL), wherein the system input port (PIXEL) receives a signal to be converted into the first signal; a second capacitor element (C2) connected between the INN and a select node (SN); and an AZ switch (SW). AZN ), used to switch between a connected state and a disconnected state between the INN and the output port; wherein, in response to the SW AZN From the connected state to the disconnected state, the comparator changes from a first state where the SN receives a first voltage to a second voltage (V) where the SN receives a first voltage. bst The second state of ).

Description

Technical Field

[0001] The embodiments described herein relate to a comparator and a method for comparing voltages. Background Technology

[0002] Because mobile devices such as smartphones and tablets need to operate for extended periods, it is desirable to design them with low power consumption. Low power consumption also helps suppress heat generation, which can lead to performance degradation issues such as noise and dark current.

[0003] Since most mobile devices include one or more image sensors, these sensors (especially analog-to-digital converters, ADCs) should also operate with low power consumption. More specifically, the comparators in the ADC should operate with low power consumption.

[0004] Since power consumption is directly proportional to the supply voltage, one way to reduce power consumption is to lower the supply voltage, thus operating at a lower voltage. However, simply lowering the supply voltage also reduces the acceptable range of input voltage in ADCs, especially in comparators.

[0005] Related technical documents

[0006] Patent document: US Patent No. 9,774,811 Summary of the Invention

[0007] The present invention, as described in this application, provides a comparator that has been improved to extend the acceptable range of input voltage.

[0008] The present invention, as described in this application, provides an analog-to-digital converter including such a comparator.

[0009] The embodiments of the present invention described in this application provide a CMOS image sensor including such an analog-to-digital converter.

[0010] One embodiment of the aspect described herein provides a comparator including:

[0011] A differential amplifier has a first port (INN) for receiving a first signal, a second port (INP) for receiving a second signal, and an output port, wherein the output port outputs a comparison result signal obtained by amplifying the result of subtracting the first signal from the second signal;

[0012] A first capacitor element (C1) is connected between the first port (INN) and the system input port (PIXEL), wherein the system input port (PIXEL) receives the signal to be converted into the first signal;

[0013] The second capacitor element (C2) is connected between the first port (INN) and the select node (SN);

[0014] AZ switch (SW) AZN ), used to switch between a connected state where the first port (INN) and the output port are connected and a disconnected state where the first port (INN) and the output port are disconnected;

[0015] In response to the AZ switch (SW) AZN When switching from the connected state to the disconnected state, the comparator changes from a first state where the selected node (SN) receives a first voltage to a second voltage (V) where the selected node (SN) receives a first voltage. bst The second state of ). Attached Figure Description

[0016] Figure 1 An image sensor according to one embodiment is conceptually illustrated.

[0017] Figure 2 A schematic diagram illustrating the ADC in a CMOS image sensor is shown.

[0018] Figure 3 A schematic diagram illustrating the operating range of a differential amplifier is shown.

[0019] Figure 4 The structure with a capacitor voltage divider is shown.

[0020] Figure 5 The structure for extending the input range is shown.

[0021] Figure 6 A flowchart illustrating operation according to one embodiment is shown;

[0022] Figure 7 Several signal waveforms for illustrating operation are shown according to one embodiment.

[0023] Figure 8 A variation using a symmetrical structure is shown.

[0024] Figure 9 A variation that allows switching the capacitor is shown.

[0025] Figure 10 The architecture of a mobile terminal according to one embodiment is shown. Detailed Implementation

[0026] Embodiments are described below with reference to the accompanying drawings in the context of the following sections. In the drawings, the same reference numerals or symbols are assigned to the same elements. For the sake of simplicity, redundant descriptions will be omitted.

[0027] 1. System Overview

[0028] 2. Basic Structure

[0029] 3. Basic Operations

[0030] 4. Capacitor attenuator

[0031] 5. Input range expansion

[0032] 6. Variation

[0033] 6.1 Symmetrical Structure

[0034] 6.2 Capacitor Switching

[0035] 7. System Architecture

[0036] The various partitions described below are not essential to the embodiments. Descriptions in two or more partitions may be combined, and descriptions in one partition may be applied to descriptions in another partition as appropriate (unless contraindicated).

[0037] 1. System Overview

[0038] Figure 1 An image sensor 10 according to one embodiment is conceptually illustrated. For example, the image sensor 10 may be a CMOS image sensor. However, the image sensor may be any sensor array (e.g., a fingerprint sensor) comprising an array of sensor elements and elements for reading out the output signals of the sensor elements, each sensor element converting a physical quantity into an electrical signal. Figure 1 The diagram shows multiple pixels 11, a row decoding circuit 20, a readout circuit 13, a power supply 14, and a processor 15. Figure 1 The components associated with the following description are shown. However, other components may actually be present.

[0039] Each of the multiple pixels 11 is connected to a scan line G. i and the data line D connected to that pixel j The following are specified: "i" is the index of the scan line, which is an integer greater than or equal to 1 and less than or equal to M, and "j" is the index of the data line, which is an integer greater than or equal to 1 and less than or equal to N (the same applies below).

[0040] Processor 15 controls the line decoding circuit to drive (activate or deactivate) multiple scan lines G1 to G1 connected to pixel 11. M Because one scan line connects to multiple pixels 11 ( Figure 1 (N pixels in the array), so multiple pixels can be specified simultaneously by specifying a single scan line.

[0041] Processor 15 controls readout circuit 13 using multiple data lines D1 to D2 connected to pixel 11. N Read data from multiple pixels 11.

[0042] The readout circuit 13 includes multiple analog-to-digital converters ADC1 to ADC2. N Each analog-to-digital converter is connected to data line D. j Multiple analog-to-digital converters (ADC1 to ADC2) N Parallel operation. Each analog-to-digital converter (ADC) j Relative to M pixels operating in a time-division multiplexing manner; that is, ADC j Repeat the analog-to-digital conversion M times, where the conversion includes reading data as an analog voltage signal from a pixel 11 and outputting the corresponding digital signal.

[0043] Processor 15 controls power supply 14 to multiple pixels 11 and multiple analog-to-digital converters ADC1 to ADC2. N Provide the predetermined voltage.

[0044] N and M can be any suitable positive integer. For example, N and M can be hundreds, thousands, etc.

[0045] 2. Basic Structure

[0046] Figure 2 The analog-to-digital converter (ADC) in a CMOS image sensor is shown. Figure 2 It shows the relationship with pixel 11 and analog-to-digital converter (ADC) j Some representative components related to this. Figure 2 The diagram shows the pixel source follower component 21, the differential amplifier 22 (which may be referred to as "comparator 22"), and the ramp signal generator 23 associated with pixel 11.

[0047] The pixel source follower component 21 includes a photodiode (PD) whose anode is connected to a low power supply V. SS (For example, V) SS It can be GND); the transmission transistor Tr1 is connected between the cathode of the PD and the floating diffusion layer (FD); the reset transistor Tr2 is connected between the floating diffusion layer and the high power supply V. DD Between. Although only one PD is shown, multiple PDs and Tr1 can be connected to the floating diffusion layer.

[0048] Source follower component 21 further includes: an amplifying transistor Tr3 forming a source follower, wherein the gate receiving the input voltage is connected to a floating diffusion layer; and a selection transistor Tr4 controlling Tr3 and the output signal line ( Figure 1 Data line D in j The connections between the units 11 and 4; bias transistor Tr5 provides source follower bias current to the output signal line. Here, Tr1 to Tr4 correspond to unit pixels 11, and multiple unit pixels 11 are connected to one output signal line. Generally, one Tr5 is connected to one output signal line.

[0049] The amount of photoelectrons generated by a photodiode (PD) is typically proportional to the amount of light received (i.e., the product of illumination and exposure time on the PD). Transmission transistor Tr1 regulates the flow of photoelectrons to node FD. The gate of Tr4 is connected to... Figure 1 The scan line G shown i Tr4 connects to Figure 1 Data line D shown j The output port PIXEL of the pixel source follower component 21, located between Tr4 and Tr5, can be referred to as one of the system input ports of the differential amplifier 22. The bias transistor Tr5 is connected to the same data line D. j Multiple pixels are shared among themselves.

[0050] Differential amplifier 22 includes a pair of load transistors Tr6 and Tr7, the sources of which are connected to a high power supply V. DD A pair of input transistors Tr8 and Tr9; a bias transistor Tr10, whose drain is connected to the corresponding source of Tr8 and Tr9, and which provides bias current. The drains of Tr6 and Tr7 are connected to the drains of Tr8 and Tr9, respectively. The source of Tr10 is connected to the low power supply V. SS The drains of Tr6 and Tr8 are connected to the output port of differential amplifier 22. In the example shown, the common power supply V... DD and V SS Used for pixel source follower component 21 and differential amplifier 22. However, in another embodiment, a different power supply can be used.

[0051] The gate of Tr8 is connected to one input port INN of differential amplifier 22. INN is connected through capacitor C. N PIXEL is connected to the output port (or one of the system input ports) of pixel source follower component 21. The gate of Tr9 is connected to the other input port of differential amplifier 22. INP is connected through capacitor C. PConnect to the output port RAMP. RAMP can be referred to as another system input port of differential amplifier 22.

[0052] Auto zero (AZ) switch SW AZN It is located between an input port INN and an output port OUT. SW AZN The switch toggles between a connected state where INN and the output port of the differential amplifier are connected, and a disconnected state where INN and the output port of the differential amplifier are disconnected. Additionally, the AZ switch SW... AZP Located between the drain of another input port INP and Tr7 (the drain of Tr9). SW AZP The system switches between a connected state (where the drains of INP and Tr7, and the drain of Tr9, are connected) and an open state (where the drains of INP and Tr7, and the drain of Tr9, are disconnected). Tr10 is used as a constant current source. For more details on the auto-zeroing technique, please refer to:

[0053] https: / / www.analog.com / jp / technical-articles / to-chop-or-auto-zero-that-is-the-question.html

[0054] Ramp signal generator 23 generates a reference signal used for the comparison operation performed in a single-slope analog-to-digital converter. In other words, ramp signal generator 23 generates a reference signal for comparison with an analog voltage signal. The digital value corresponding to the analog input can be obtained by a counter circuit by measuring the time of crossover between the ramp signal level and the analog signal level. The ramp signal is a signal with a predetermined waveform. For example, the ramp signal can be generated by a digital-to-analog converter (DAC), and the count value of the counter circuit is used as the digital input of the DAC. For example, at least a portion of ramp signal generator 23 can be incorporated into the readout circuit 13, power supply 14, and / or processor 15.

[0055] The polarity combinations of Tr1 to Tr9 are merely an example; other polarities may be used in other embodiments.

[0056] 3. Basic Operations

[0057] Generally speaking, Figure 2 The ADC shown receives the analog voltage signal of the pixel, amplifies the voltage between a pair of input nodes (INN, INP), and outputs a digital signal from the output port OUT as the comparison result.

[0058] The operation will be explained in detail below.

[0059] First, close switch SW (AZ). AZN and SW AZP The voltage at one input port INN is reset to the drain voltage of Tr6, and the voltage at the other input port INP is reset to the gate and drain voltages of Tr7. Thus, the drain voltage of Tr6 and the voltages at both input ports INN and INP are reset to voltages corresponding to the drain voltage of Tr7. At this time, the floating diffusion layer, which serves as the input to the pixel source follower, is pre-charged to a known level (e.g., V) by the switching reset transistor Tr2. DD "Toggling" refers to the OFF-ON-OFF operation, also known as "switching". When Tr1 and Tr2 are off and Tr4 is on, an analog voltage signal indicating the reference level is input to an input port INN, and thus the voltage at input port INN becomes the corresponding voltage.

[0060] Then, turn on the AZ switch SW. AZN and SW AZP The reference level (or baseline) of the pixel is measured first. Since the precharge voltage may include error components such as kTC noise from the diffusion capacitor and feedthrough caused by the switching of the reset transistor Tr2, the baseline level is measured in advance.

[0061] The ramp signal is input to another input port, INP. Generally, the ramp signal changes from high to low over time. The step size of this change is determined by the resolution of the analog-to-digital converter. The reference voltage can be determined by measuring the time it takes for the voltage levels of the analog voltage signal and the ramp signal to become the same.

[0062] Next, the voltage corresponding to the charge stored in the pixel is measured. Specifically, photoelectrons stored in the photodiode (PD) according to the amount of light are transferred to node FD by switching (or toggling) Tr1, and an analog voltage signal with an amplitude corresponding to the amount of light is generated according to a scaling factor, where the scaling factor is the reciprocal of the capacitance of node FD. This is input to an input port INN through pixel source follower component 21, and the voltage at this input port becomes the corresponding voltage. This voltage is generated by adding a reference level to the voltage corresponding to the amount of photoelectrons from the pixel. In the case where the electrons are signal charge, as in this example, the voltage corresponding to the amount of photoelectrons typically drops below the reference voltage.

[0063] A ramp signal is input to another input port, INP. The ramp signal changes from high to low over time. The step size of the change is determined by the resolution of the analog-to-digital converter. The range of the ramp signal (between high and low levels) can be the same as or different from the range used in the reference level measurement. In any case, it must be ensured that the reference level and the input voltage (the voltage at input port INN) are both within the range of the ramp signal. The pixel voltage corresponding to the state of the photodiode (PD) can be determined by measuring the time it takes for the voltage levels of the analog voltage signal and the ramp signal to become the same.

[0064] In this example, the reference level corresponds to the higher limit of the acceptable voltage for the ADC, and it is assumed that the input voltage within the acceptable range is less than or equal to the reference level. However, this is not essential for the embodiments. For example, in cases where the polarity of the signal charge is different (e.g., in the case of storing holes), the voltage amplitude relationship is reversed, but this situation is also included within the scope of this application.

[0065] After measuring the pixel voltage of one pixel, similarly measure the pixel voltage of another pixel connected to the same data line. Repeat this process for all pixels connected to the same data line. Figure 1 The pixel voltage of M pixels in the image.

[0066] When differential amplifier 22 is properly operated as an amplifier, as described above, the corresponding transistors Tr6 to Tr10 operate in their saturation regions. Therefore, in order to achieve such operation, some voltage is applied to the gate, source, and drain of the corresponding transistors.

[0067] Figure 3 A schematic diagram illustrating the operating range of the differential amplifier 22, comprising transistors Tr6 through Tr10, is shown. It is assumed that the corresponding threshold voltages of transistors Tr6 and Tr7 are V. th,p The corresponding pinch-off voltage between the source and drain is V. dsat,p The corresponding threshold voltages of transistors Tr8 and Tr9 are V. th,n The corresponding pinch-off voltage between the source and drain is V. dsat,n The pinch-off voltage between the source and drain of transistor Tr10 is V. dsat,trail .

[0068] As described above, by closing the AZ switch SW AZN Set the two input ports INN and INP (gates of Tr8 and Tr9) to the drain voltage (V). DD –V dsat,p –V thp(Initial state), and then, after the AZ switch is turned on, it changes from the initial state based on the change in the gate voltages of Tr8 and Tr9. The voltage at one input port INN (input voltage V) IN The input voltage must be less than or equal to the initial voltage (reference level). On the other hand, due to the presence of Tr8, Tr9, and Tr10, the input voltage needs to be greater than (V... dsat,tail +V dsat,n +V th,n As mentioned above, in this example, it is assumed that the reference level corresponds to the higher limit of the acceptable voltage for the ADC, and that the input voltage within the acceptable range is less than or equal to the reference level. Therefore, the input voltage V at input port INN is... IN The following inequalities must be satisfied.

[0069] (V DD –V dsat,p –V thp )>V IN >(V dsat,tail +V dsat,n +V th,n ) (Formula 1)

[0070] For example, if V DD =5[V], V thp =V thn =0.5[V] and V dsat,n =V dsat,p =V dsat,tail =0.2[V], then the input voltage V IN The scope is as follows:

[0071] 4.3[V]>V IN >0.9 [V]. Therefore, the ADC can measure input voltages V in the range of approximately 3.4 [V] that satisfy this inequality. IN .

[0072] If V is affected by low-voltage operation DD =1.8[V], then the input voltage V IN The scope is as follows:

[0073] 1.1[V]>V IN >0.9 [V]. Therefore, the ADC can measure input voltages V within a range of approximately 0.2 [V] that satisfy this inequality. IN An ADC that includes a comparator according to an embodiment described below can measure a wider range of voltages.

[0074] 4. Capacitor attenuator

[0075] Figure 4 An example is shown, in which... Figure 2The basic structure shown includes an addition of a capacitor attenuator (capacitive voltage divider). As indicated by the dashed box in the pixel-side (P-SIDE), the first capacitor element (C1) is connected between a system input port PIXEL and the first input port INN. The second capacitor element (C2) is connected between the first input port INN and the select node SN. While not essential, a similar structure to the one on the pixel-side (P-SIDE) can also exist on the ramp signal side (R-SIDE).

[0076] Select node SN and connect it to a system input port PIXEL via a switch, or connect it to a low power supply V, depending on the operating mode. SS (e.g., GND). For example, the select node SN can be connected to the system input port PIXEL to measure a relatively narrow range of voltages when the amount of photoelectrons stored in a pixel may be small due to low-light environments, short exposure times, etc. For convenience, this operating mode can be referred to as high-gain operating mode or small full-scale range mode. When the amount of photoelectrons stored in a pixel is large, the select node SN is connected to a low power supply V. SS This allows for the measurement of voltage over a relatively wide range. For convenience, this operating mode can be referred to as low-gain operating mode or large full-scale range mode. Switching between selected node SNs can be performed based on the camera system's sensitivity settings (e.g., ISO 100, ISO 200, etc.), exposure time settings, etc.

[0077] In the following description, we primarily discuss operation in low-gain mode or large full-scale range mode. Therefore, from the perspective of a system input port PIXEL, the first capacitor C1 and the second capacitor C2 can be considered to be connected in series. If the voltage of a system input port PIXEL is V IN Due to the capacitor divider, the voltage at the first input port INN can be expressed as:

[0078] C1 / (C1+C2)V IN =(1+(C2 / C1)) –1 V IN (Formula 2)

[0079] If C1 = C2, then the voltage at the first input port INN is V. IN / 2, less than the voltage V at the system input port. IN In other words, if the higher voltage limit at the first input port INN is V... max Therefore, the higher voltage limit at a system input port PIXEL can be 2V. max .

[0080] Thus, by adding the second capacitor C2, the acceptable voltage range at a system input port PIXEL can be increased by a factor of (1 + (C2 / C1)). However, it should be noted that if there is noise in the voltage signal, that noise will also increase. This will be described later.

[0081] 5. Input range expansion

[0082] Figure 5 An example is shown where a structure with an expanded input range is added. Figure 4 In the example shown, the selected node SN is always connected to the low power supply V. SS .exist Figure 5 In the example shown, the selected node SN is connected to the boost voltage source BOOST. For example, at least a portion of the boost voltage source BOOST may be located in the readout circuit 13, power supply 14, and / or processor 15. Figure 1 In ), as mentioned above, the AZ switch SW AZN Switches between the connected state of the drains of the first input ports INN and Tr8 and the disconnected state of the drains of the first input ports INN and Tr8.

[0083] Response to AZ switch SW AZN When switching from a connected state to a disconnected state, the boost voltage source BOOST changes from providing a first voltage to the selected node SN to providing a second voltage V to the selected node SN. bst For example, the first voltage could be the low supply voltage V. SS The second voltage V bst It can be a constant voltage, such as 1 [V]. The boost voltage source can be implemented using a buffer circuit.

[0084] The following is for reference Figure 6 and Figure 7 describe Figure 5 The operations within the structure shown. Figure 6 A flowchart illustrating the operation according to an embodiment is shown; Figure 7 Several signal waveforms used to illustrate operation according to embodiments are shown. It should be noted that... Figure 7 The waveforms shown are for illustrative purposes only and are not intended to represent accurate voltage levels.

[0085] For example, refer to the basic structure ( Figure 2 As mentioned above, the analog-to-digital converter (ADC) j Measure the pixel voltage of one pixel, then measure the pixel voltage of another pixel connected to the same data line, and repeat the measurements in the same way. For convenience, for... Figure 7The periods S0 to S4 shown below describe the measurement periods used to measure the pixel voltage of one pixel. S0 to S4 correspond to... Figure 6 The corresponding steps in the process.

[0086] exist Figure 6 In step S0, the AZ switch SW is closed. AZN and SW AZP ( Figure 5 And the voltage at input port INN is reset to be equal to the drain voltage of Tr6. Similarly, the voltage at input port INP is reset to be equal to the drain voltages of Tr7 and Tr9. Figure 7 In the middle, AZ switch SW AZN and SW AZP The states are collectively indicated as "AZ SW" and they operate in phase. At this time, the floating diffusion layer, which serves as the input to the pixel source follower, is pre-charged to a known level (e.g., V) via the switching reset transistor Tr2. DD With Tr1 and Tr2 off and Tr4 on, an analog voltage signal indicating the reference level is input to an input port INN, and thus the voltage at input port INN becomes the corresponding voltage V. r .

[0087] exist Figure 6 In step S1, turn on switch SW (AZ). AZN and SW AZP The reference level (or baseline) of the pixel is measured first. Since the precharge voltage may include error components such as kTC noise from the diffusion capacitor and feedthrough caused by the switching of the reset transistor Tr2, the baseline level is measured in advance.

[0088] At time t=t g At this point, the boost voltage source transitions from a first state of providing a first voltage to the select node (SN) to a second state of providing a second voltage to the select node (SN). In the example shown, the first voltage is the low supply voltage V. SS The second voltage is V bst For example, V bst It can be a constant voltage of 1 [V], but it can also be a high supply voltage such as 2.8 [V] or 1.8 [V]. DD .

[0089] When the voltage at node SN is selected, at time t = t g From the first voltage V SS Transformed into the second voltage V bst At that time, the voltage at input port INN rises by (1 + (C1 / C2)). –1 V bstThis is because, from the perspective of the high-potential selection node SN, the first capacitor element C1 can be considered as the grounded capacitor element of the C1-C2 series circuit. Therefore, the voltage at the input port INN can be written as:

[0090] V r +(1+(C1 / C2)) –1 V bst (Formula 3)

[0091] When discussing formula (Formula 2), select node SN to be connected to the low supply voltage V. SS It should be noted that when viewed from the system input port PIXEL, capacitor elements C1 and C2 are considered as the grounding capacitor element of the C1-C2 series circuit.

[0092] In step S1, a ramp signal is input to another input port INP. The ramp signal is typically held high for a certain time interval (S1) and then gradually decreases to a low level (S2). The ramp signal remains high during time interval S1. The magnitude of the level depends on the object being measured. In this example, the voltage at input port INN increases as shown in (Equation 3), therefore the "high level" in the ramp signal needs to be higher than this increased voltage.

[0093] In step S2, the ramp signal typically transitions from a high level to a low level gradually over time. The step size of this transition is determined by the resolution of the analog-to-digital converter. This can be measured by measuring the time t it takes for the voltage levels of the analog voltage signal and the ramp signal to become the same. r To determine the voltage of the increased reference level (Formula 3).

[0094] In step S3, the voltage corresponding to the charge stored in the pixel is measured. Specifically, photoelectrons stored in the photodiode (PD) according to the amount of light are transferred to node FD by switching (or toggling) Tr1, and an analog voltage signal with an amplitude corresponding to the amount of light is generated according to a scaling factor, where the scaling factor is the reciprocal of the capacitance of node FD. This is input to an input port INN through pixel source follower component 21, and the voltage at this input port becomes the corresponding voltage. This voltage is generated by adding a reference level to the voltage corresponding to the amount of photoelectrons from the pixel. In the case where the electrons are signal charge, as in this example, the voltage corresponding to the amount of photoelectrons typically drops below the reference voltage.

[0095] At the start of time interval S3, the pixel waveform undergoes a large transient change before stabilizing due to capacitive coupling of Tr1, Tr3, and Tr4 accompanied by photoelectron transfer. Figure 7In the diagram, the solid line waveform of "PIXEL" corresponds to the case of minimum photocurrent (MIN), while the dashed line waveform corresponds to the case of maximum photocurrent (MAX). Therefore, a single waveform is actually drawn between the solid and dashed lines.

[0096] In steps S3 and S4, similar to steps S1 and S2, the ramp signal input to another input port INP typically remains high for a certain time interval (S3), and then gradually decreases to a low level over time (S4). The ramp signal remains high during the time interval S3. The magnitude of the level depends on the object being measured. In this example, the "high level" in the ramp signal is set to a similar value as the "high level" set in step S1.

[0097] In step S4, the ramp signal typically transitions from a high level to a low level gradually over time. The step size of this transition is determined by the resolution of the analog-to-digital converter. The range of the ramp signal (between high and low levels) can be the same as or different from the range used in the reference level measurement. In any case, it is essential to ensure that both the reference level and the input voltage (the voltage at input port INN) are within the range of the ramp signal. This can be achieved by measuring the time (t) it takes for the voltage levels of the analog voltage signal and the ramp signal to become the same. A and t B The pixel voltage corresponding to the state of the photodiode (PD) is determined at a certain time between these points.

[0098] For example, the measurement period (the time interval from S0 to S4) used to measure the pixel voltage of a pixel can be approximately 10 μs, the time interval from S0 to S2 can be approximately 5 μs, and the time interval from S3 to S4 can be approximately 5 μs. However, these values ​​are provided only as examples, and other values ​​may be used in another embodiment.

[0099] In this embodiment, the higher limit of the acceptable voltage corresponds to a reference level, and voltages within the acceptable range are less than or equal to the reference level. Therefore, the higher the reference level, the wider the acceptable voltage range. In this embodiment, as described with reference to (Formula 3), the increased reference level is expressed as:

[0100] V r +(1+(C1 / C2)) –1 V bst

[0101] On the other hand, as described in "4. Capacitor Attenuator", by adding a second capacitor element C2, the acceptable voltage range at a system input port PIXEL can be increased by a factor (1 + (C2 / C1)). Applying this to the aforementioned increased reference level, the acceptable voltage range can be written as:

[0102] (1+(C2 / C1))×(V r +(1+(C1 / C2)) –1 V bst )

[0103] = (1 + (C2 / C1)) × V r +(1+(C2 / C1))×(1+(C1 / C2)) –1 V bst

[0104] = (1 + (C2 / C1)) × V r +(C2 / C1)V bst (Formula 4)

[0105] The first term of the previous formula corresponds to the contribution described in "4. Capacitor Attenuator," namely, the contribution generated by adding capacitor C2. The second term corresponds to the contribution based on the second voltage V. bst The contribution from the boost voltage. Thus, the acceptable voltage range can be increased from V. r Significantly expanded.

[0106] In addition, for Figure 5 The dynamic range of the ADC shown can be estimated as the ratio of the acceptable voltage range to the reference noise.

[0107] Dynamic range = (Acceptable voltage range) / (Reference noise)

[0108] For example, Figure 2 The dynamic range in the basic structure shown can be estimated as follows:

[0109] V r / V n (Formula 5)

[0110] Among them, V r Representing the basic structure ( Figure 2 The reference level in ) is V n Indicates reference noise.

[0111] Next, we will consider increasing the dynamic range of the capacitor C2. In this case, the reference level can be increased by a factor of (1 + (C2 / C1)). However, the reference noise also increases by the same factor (1 + (C2 / C1)). Therefore, the dynamic range is expressed as:

[0112] (1+(C2 / C1))V r / [(1+(C2 / C1))V n ] = V r / V n (Formula 6)

[0113] This yields the same formula as (Formula 5). Only in the basic structure ( Figure 2 Adding a grounding capacitor C2 to the circuit makes it difficult to expand the dynamic range.

[0114] In this regard, according to the embodiment that adds a boost voltage source, the reference level can be increased as shown in (Equation 4), therefore the dynamic range can be written as:

[0115] [(1+(C2 / C1))×V r +(C2 / C1)V bst ] / [(1+(C2 / C1))V n ] = V r / V n +(C2 / C1)(1+(C2 / C1)) –1 (V bst / V n ) (Formula 7)

[0116] The first term in the previous formula corresponds to the dynamic range in the basic structure. The second term corresponds to the improved effect according to the embodiment. According to the embodiment, the dynamic range can be effectively extended.

[0117] Since the first capacitor element C1 plays a major role in receiving voltage from the pixel ( Figure 4 and Figure 5 Therefore, in terms of signal-to-noise ratio (SNR), a larger capacitor value C1 is preferred. On the other hand, according to the formulas (Formula 4) representing the acceptable voltage range and (Formula 7) representing the dynamic range, a larger capacitor value C2 is preferred in terms of increasing the acceptable voltage level and / or dynamic range. In practical applications, C1 and C2 can be appropriately determined while taking these trade-offs into account. Therefore, the capacitance ratio between the first capacitor element C1 and the second capacitor element C2 can be fixed or varied depending on the circumstances.

[0118] Regarding the acceptable voltage range, in the basic ADC structure ( Figure 2 In the above, as described in "3. Basic Operation", the input voltage V at the input port INN is... IN The following inequalities must be satisfied:

[0119] 1.1[V]>V IN >0.9 [V]. Acceptable voltage range (V)r The value is 0.2[V]. Where, we assume V... DD =1.8[V], V thp =V thn =0.5[V], V dsat,n =V dsat,p =V dsat,tail =0.2[V].

[0120] According to (Formula 4) in the embodiment, the acceptable voltage range is:

[0121] (1+(C2 / C1))×V r +(C2 / C1)V bst

[0122] =2×V r +V bst

[0123] =1.4[V], where, assuming C1 = C2, V bst = 1 [V]. Unlike the basic structure, it can measure voltages over a wide range exceeding 1 [V].

[0124] Assume the input reference noise is V n =100[μV], then the dynamic range in the basic structure can be calculated as:

[0125] 20log 10 (V r / V n )

[0126] =20log 10 (0.2[V] / 100[μV])

[0127] =66dB

[0128] In this respect, the improvement contribution generated by the embodiments can be calculated according to the second term in (Formula 7):

[0129] 20log 10 [{(1+(C2 / C1))V r +(C2 / C1)V bst} / (1+(C2 / C1))V n )]=20log 10 [V r / V n +(1 / 2)(V bst / V n )]

[0130] =20log 10 [0.2[V] / 100[uV]+(1 / 2)(1[V] / 100[μV])]

[0131] ~77dB

[0132] Where, assume C1 = C2, V bst =1[V]. In this case, the dynamic range increases to 77dB. This means that when the dynamic range is converted to Effective Number of Bits (ENOB), the dynamic range expands by approximately 12 bits.

[0133] ENOB = (SINAD – 1.76) / 6.02

[0134] = (77–1.76) / 6.02~12

[0135] SINAD is the power ratio indicating signal quality, measured in dB, and is 77 in this example.

[0136] 6. Variation

[0137] Variations of the embodiments will now be described exemplarily.

[0138] 6.1 Symmetrical Structure

[0139] Figure 8 A variation using a symmetrical structure is shown. For example... Figure 8 As shown, the pixel side (P-SIDE or PIX-SIDE) and the ramp signal side (R-SIDE, Ref-SIDE) share a common boost voltage source. While not essential for R-SIDE, the P-SIDE and R-SIDE boost voltage sources can exist independently on either side. When... Figure 8 When using a shared boost voltage source as shown, the advantage is that the noise caused by the boost voltage source can be eliminated.

[0140] 6.2 Capacitor Switching

[0141] As described above, the capacitance ratio between the first capacitor element C1 and the second capacitor element C2 can vary depending on the circumstances. For example, in addition to the first capacitor element C1 connected between the system input node PIXEL and the differential amplifier input node INN, multiple capacitor elements can also be connected to the input node INN.

[0142] Figure 9A variation with switchable capacitors is shown. First capacitor C1 is connected between input node INN and first select node SN1; second capacitor C2 is connected between input node INN and second select node SN2; third capacitor C3 is connected between input node INN and third select node SN3; and fourth capacitor C4 is connected between input node INN and fourth select node SN4. Second select nodes SN2 through SN4 are respectively connected to the boost voltage source BOOST via switches. To eliminate noise components caused by the boost voltage source BOOST, a similar structure can be set on the ramp signal side (R-SIDE), such as... Figure 9 As shown. For example, Figure 9 The illustrated embodiment allows for the selection of the capacitor to be used based on brightness.

[0143] exist Figure 5 , Figure 8 and Figure 9 In the illustrated embodiment, additionally or alternatively, for example from the perspective of post-manufacturing adjustments, the second voltage V provided by the boost voltage source BOOST to the select node SN bst It can switch between two or more voltages. For example, the second voltage V bst It can transition not only between the two states of 0V and 1.0V, but also between four states: 0V, 0.8V, 1.0V, and 1.2V. In other words, the second voltage V... bst The waveform can be represented as an L-value signal (L is an integer greater than or equal to 2).

[0144] According to an embodiment, the acceptable voltage range and dynamic range can be expanded by switching the selection node SN to the boost voltage source side. This is preferred for comparators, analog-to-digital converters including comparators, and CMOS image sensors including both comparators and analog-to-digital converters. This is because CMOS image sensors need to adjust their full-scale range according to the scene's illumination level and / or exposure time.

[0145] This embodiment can provide a low-power comparator with a large input range, an analog-to-digital converter including such a comparator, and a CMOS image sensor including the comparator and the analog-to-digital converter.

[0146] This embodiment can provide a low-power comparator with extended dynamic range, an analog-to-digital converter including such a comparator, and a CMOS image sensor including the analog-to-digital converter.

[0147] This embodiment can be used not only in single-slope parallel ADCs in CMOS image sensors, but also in the input stage of various ADCs.

[0148] 7. System Architecture

[0149] The embodiments described herein can be applied to various devices, including mobile devices and fixed devices. References Figure 10 The following describes an exemplary mobile terminal according to an embodiment. The mobile terminal may be a device that provides image acquisition capabilities and / or data connectivity to a user, a handheld device with wireless connectivity, or other processing devices connected to a wireless modem (e.g., digital cameras, SLR cameras, smartphones, etc.). Alternatively, the mobile terminal may be other smart devices with image acquisition and display capabilities (e.g., wearable devices, tablets, personal digital assistants (PDAs), drones, aerial photography drones).

[0150] Figure 10 This is a schematic diagram of an optional hardware structure for terminal 100, which is an exemplary mobile terminal. See also... Figure 10 The terminal 100 may include components such as a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, an imaging device 101, an audio circuit 160, a speaker 161, a microphone 162, a headphone jack 163, a processor 170, an external interface 180, and a power supply 190.

[0151] The radio frequency (RF) unit 110 can be used to send and receive information or signals during a call. Typically, the RF unit includes, but is not limited to, antennas, amplifiers, transceivers, couplers, low-noise amplifiers (LNAs), duplexers, etc. Furthermore, the RF unit 110 can communicate wirelessly with network devices and other devices. Wireless communication can use any communication standard or protocol.

[0152] The memory 120 can be used to store instructions and data. The memory 120 mainly includes an instruction storage area and a data storage area. The instruction storage area can store software such as the operating system, applications, and instructions. The data storage area can store images acquired by the imaging device 10, audio data input or output by the audio circuit 150, images displayed by the display unit 140, data for operations executed by the processor 170, and various other transient or permanent data.

[0153] The input unit 130 can be used to receive input numeric or character information from the mobile terminal 100. Specifically, the input unit 130 may include a touch screen 131 and other input devices 132. The touch screen 131 can collect touch operations performed by the user on or near the touch screen and drive the corresponding connection device according to a preset program. The touch screen 131 can detect the user's touch action on the touch screen, convert the touch action into a touch signal, send the touch signal to the processor 170, and receive and execute commands sent by the processor 170. Other input devices 132 may include, but are not limited to, one or more of the following: physical keyboard, function keys (e.g., volume control keys, power button), trackball, mouse, joystick, etc.

[0154] The display unit 140 can be used to display user-inputted information, information provided to the user, various menus of the terminal 100, etc. In an embodiment, the display unit 140 is used to display images acquired by the imaging device 101, wherein the images may include preview images in certain shooting modes, captured images, or images processed by a specific algorithm after shooting, etc.

[0155] Imaging device 101 is used to acquire still or moving images and can be activated by application commands to perform shooting or video recording functions. Imaging device 101 may include components such as an imaging lens, a filter, and an image sensor. Specifically, according to an embodiment, imaging device 101 is an image sensor such as a CMOS image sensor. The image sensor may include a reference... Figure 2 The analog-to-digital converter is shown. Light emitted or reflected by the object to be photographed enters the imaging lens, passes through a filter, and is focused onto the image sensor. The imaging lens is mainly used to focus the light emitted or reflected by the object to be photographed into the field of view for imaging. The filter is mainly used to filter out extra light waves (e.g., light waves other than visible light, such as infrared light). The image sensor is mainly used to perform photoelectric conversion on the received light signal, converting the light signal and light intensity changes into an electrical signal, and inputting the electrical signal to the processor 170 for further processing.

[0156] Audio circuitry 160, speaker 161, microphone 162, and headphone jack 163 provide an audio interface between the user and mobile terminal 100. Audio circuitry 160 sends an electrical signal converted from received audio data to speaker 161, which then converts the electrical signal into a sound signal for output. Conversely, microphone 162 collects sound signals and converts them back into electrical signals. Audio circuitry may also include headphone jack 163, which provides a connection interface between the audio circuitry and headphones.

[0157] The processor 170 is the control center of the mobile terminal 100, connected to various components of the mobile terminal 100 through various interfaces and signal lines. The processor 170 executes various functions of the mobile terminal 100, executes instructions stored in the memory 120, and retrieves data stored in the memory 120, thereby processing the data. In some embodiments, the processor and memory can be implemented on a single chip. In some embodiments, the processor and memory can be implemented on separate chips.

[0158] The mobile terminal 100 also includes an external interface 180. The external interface 180 can be a standard micro USB interface or a multi-pin connector. The external interface can be used to connect the terminal 100 to other devices for communication, or to connect to a charger to charge the terminal 100.

[0159] The mobile terminal 100 also includes a power supply 190 (e.g., a battery) that supplies power to each component. Preferably, the power supply can be logically connected to the processor 170, thereby enabling functions such as charging, discharging, and power consumption management through a power management system.

[0160] Those skilled in the art will understand that Figure 10 This is merely one example of a mobile terminal and does not constitute any limitation on the embodiment. A mobile terminal may include more or fewer components than illustrated, or combine certain components, or have different components.

[0161] Figure 1 , Figure 10 The partial division of components is merely for logical function purposes, prioritizing ease of explanation. It is understood that some or all of the divided components can be integrated into a single physical entity or physically separated during actual implementation. For example, each of the aforementioned components can be a separate processing element or integrated onto a chip in the mobile terminal. Alternatively, the processing element can be stored as program code in the controller's storage element and can be invoked and executed as needed. Furthermore, processing elements can be integrated together or implemented independently. The processing element can be an integrated circuit chip with signal processing capabilities. During implementation, the steps in the above method or the aforementioned components can be implemented through hardware integrated logic circuits in the processing element or through software instructions.

[0162] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, storage media, or computer programs. Therefore, the present invention can take the form of a purely hardware embodiment or a combination of hardware and software embodiments.

[0163] The methods, apparatus, storage media, and computer programs relating to embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams. It should be understood that computer program instructions may be used to implement each process and / or each block in the flowchart illustrations and / or block diagrams. These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or any other programmable data processing apparatus to cause the executed instructions to produce the functionality described in the reference embodiments.

[0164] These computer program instructions can be stored in a suitable storage medium or transmitted over a transmission medium. These computer program instructions can be loaded onto a computer or other programmable data processing device to cause the computer to perform a series of operations, thereby producing the functions described in the reference embodiments.

[0165] While embodiments of the invention have been described, those skilled in the art can make changes and modifications to these embodiments. Therefore, the following claims should be interpreted as including the embodiments within the scope of the invention and all their changes and modifications.

[0166] Reference Symbol List

[0167] 10 Image Sensors

[0168] 11 pixels

[0169] 12-line decoding circuit

[0170] 13 Readout Circuit

[0171] 14 Power Supply

[0172] 15 processors

Claims

1. A comparator, characterized in that, include: A differential amplifier has a first port (INN) for receiving a first signal, a second port (INP) for receiving a second signal, and an output port, wherein the output port outputs a comparison result signal obtained by amplifying the result of subtracting the first signal from the second signal; A first capacitor element (C1) is connected between the first port (INN) and the system input port (PIXEL), wherein the system input port (PIXEL) receives the signal to be converted into the first signal; The second capacitor element (C2) is connected between the first port (INN) and the select node (SN); AZ switch (SW) AZN ), used to switch between a connected state where the first port (INN) and the output port are connected and a disconnected state where the first port (INN) and the output port are disconnected; In response to the AZ switch (SW) AZN When switching from the connected state to the disconnected state, the comparator changes from a first state where the selected node (SN) receives a first voltage to a second voltage (V) where the selected node (SN) receives a first voltage. bst The second state of ).

2. The comparator according to claim 1, characterized in that, The capacitance ratio between the first capacitor element (C1) and the second capacitor element (C2) is adjustable.

3. The comparator according to claim 1, characterized in that, It also includes a third capacitor element (C3) connected between the first port (INN) and the select node (SN).

4. The comparator according to claim 1, characterized in that, Also includes: Third capacitor element (C) 1P A signal is connected between the second port (INP) and another system input port (RAMP), wherein the other system input port (RAMP) receives the signal to be converted into the second signal; Another automatic zeroing switch (SW) AZP This is used to switch between a connected state where the second port (INP) and the predetermined node are connected and a disconnected state where the second port (INP) and the predetermined node are disconnected.

5. An analog-to-digital converter, characterized in that, include: The comparator according to claim 1; Boost voltage source, at AZ switch (SW) AZN When the circuit is in the connected state, a first voltage is supplied to the selected node (SN), and the AZ switch (SW) is in the connected state. AZN When the device is in the disconnected state, a second voltage (V) is supplied to the selected node (SN). bst ); The signal to be converted into a first signal is an analog voltage signal from a pixel; the second signal is a reference signal to be compared with the analog voltage signal; the analog-to-digital converter generates a digital signal corresponding to the analog voltage signal through the comparison result signal.

6. The analog-to-digital converter according to claim 5, characterized in that, During the time interval in which the analog voltage signal indicates the reference level of the pixel, the comparator adjusts the voltage according to the second voltage (V). bst ) Boost the voltage in the first port (INN); During the time interval in which the analog voltage signal indicates a voltage corresponding to the charge stored in the pixel, the comparator outputs an output signal from its output port, wherein the output signal indicates the comparison result between the reference signal and the analog voltage signal, the analog voltage signal being based on the second voltage (V). bst )Boost pressure.

7. An image sensor, characterized in that, include: Multiple pixels; A processor for controlling access to the plurality of pixels; The analog-to-digital converter according to claim 5 is connected to the processor.

8. An analog-to-digital converter, characterized in that, include: A differential amplifier has a first port (INN) for receiving a first signal, a second port (INP) for receiving a second signal, and an output port, wherein the output port outputs a comparison result signal obtained by amplifying the result of subtracting the first signal from the second signal; First PIX-side capacitor element (C) 1N A signal is connected between the first port (INN) and the first system input port (PIXEL), wherein the first system input port (PIXEL) receives the signal to be converted into the first signal; Second PIX-side capacitor element (C) 2N ), connected to the first port (INN) and the PIX-side selection node (SN) N )between; PIX-side AZ switch (SW) AZN ), used to switch between a connected state where the first port (INN) and the output port are connected and a disconnected state where the first port (INN) and the output port are disconnected; First REF side capacitor element (C) 1P A reference signal is connected between the second port (INP) and the second system input port (RAMP), wherein the second system input port (RAMP) receives a reference signal to be compared with the first signal; The second REF side capacitor element (C) 2P ), connected to the second port (INP) and the REF-side selection node (SN) P )between; REF side AZ switch (SW) AZP ), used to switch between a connected state where the second port (INP) and the predetermined node are connected and a disconnected state where the second port (INP) and the predetermined node are disconnected; Boost voltage source, on the PIX side AZ switch (SW) AZN ) and the REF-side AZ switch (SW) AZP When the connection is established, select a node (SN) on the PIX side. N ) and the REF-side selection node (SN) P The first voltage is provided, and the AZ switch (SW) on the PIX side... AZN ) and the REF-side AZ switch (SW) AZP When the device is in the disconnected state, select a node (SN) on the PIX side. N ) and the REF-side selection node (SN) P Provides a second voltage (V) bst ); Wherein, the signal to be converted into the first signal is an analog voltage signal from a pixel; the second signal is a reference signal to be compared with the analog voltage signal; and the analog-to-digital converter generates a digital signal corresponding to the analog voltage signal through the comparison result signal.

9. A method for comparing voltages in a device, characterized in that, The device includes: A differential amplifier has a first port (INN) for receiving a first signal, a second port (INP) for receiving a second signal, and an output port for outputting an output signal. A first capacitor element (C1) is connected between the first port (INN) and the system input port (PIXEL), wherein the system input port (PIXEL) receives the signal to be converted into the first signal; The second capacitor element (C2) is connected between the first port (INN) and the select node (SN); AZ switch (SW) AZN ), used to switch between a connected state where the first port (INN) and the output port are connected and a disconnected state where the first port (INN) and the output port are disconnected; Wherein, the signal to be converted into the first signal is an analog voltage signal from a pixel; the second signal is a reference signal to be compared with the analog voltage signal; the output signal is a digital signal corresponding to the analog voltage signal; the method includes: In response to the AZ switch (SW) AZN The process switches from the connected state to the disconnected state, and from the first state where the selected node (SN) receives a first voltage to the second voltage (V) where the selected node (SN) receives a first voltage. bst The second state; During the time interval in which the analog voltage signal indicates the reference level of the pixel, according to the second voltage (V bst ) Boost the voltage in the first port (INN); During the time interval indicated by the analog voltage signal corresponding to the voltage stored in the pixel, a comparison result signal is output from the output port, wherein the comparison result signal is obtained by amplifying the result of subtracting the reference signal from the analog voltage signal, the analog voltage signal being based on the second voltage (V). bst )Boost pressure.

Images