Chip, electronic device

Abstract

The application provides a chip and an electronic device, the chip comprises a Die, a substrate structure and a Ball from top to bottom, the substrate structure comprises a top layer substrate, a middle layer substrate and a bottom layer substrate which are stacked with each other, the top layer substrate is connected with the Die, and the bottom layer substrate is connected with the Ball; a communication signal of the chip is fanned out from the middle layer substrate and connected to the bottom layer substrate through a via hole downwardly. By adopting the scheme, the wiring space can be increased without increasing the substrate area and the number of layers, the wiring space of a single layer substrate is improved, the number of layers of the substrate is reduced, and the substrate cost and the chip cost are significantly saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a chip and an electronic device. BACKGROUND

[0002] In the related art, a chip is an important industrial foundation. With the increasing scale, the chip integrates more and more functions, which leads to more and more signals to be led out of the chip, while the size of the chip is required to be smaller and smaller, which puts forward higher requirements on the packaging design of the chip. The substrate of the chip is to connect all the signals on the Die to the Ball layer at the bottom of the packaging through the punching of the copper layer of the substrate. The diversification and rate improvement of the chip signal type also have higher requirements on the substrate wiring. In the limited substrate space, the best reliability and performance can generally be achieved only by increasing the number of substrate layers to meet the performance requirements of high-speed signals. However, the increase of the number of substrate layers certainly increases the cost of the chip. Without good substrate design planning, it is common to increase the packaging cost of the chip by 20% to 30%.

[0003] In the implementation of the substrate, the most difficult area of wiring is the Bump out line. This area is connected to the Bump Pad substrate L1 layer of the Die. The number of Bump Pads is usually in the order of thousands, which leads to the fact that the L1 layer cannot fan out all the signals, and at least two wiring layers need to be planned, and the number of substrate layers also needs to be increased to provide signal reference ground and isolation degree to ensure signal quality and high performance.

[0004] In view of the above problems existing in the related art, no effective solution has been found so far. SUMMARY

[0005] The embodiments of the present application provide a chip and an electronic device.

[0006] According to one embodiment of the present application, a chip is provided, which comprises, from top to bottom, a Die, a substrate structure, and a Ball. The substrate structure comprises a top layer substrate, an intermediate layer substrate, and a bottom layer substrate which are stacked with each other. The top layer substrate is connected to the Die, and the bottom layer substrate is connected to the Ball. The communication signal of the chip is fanned out from the intermediate layer substrate and connected to the bottom layer substrate through a via.

[0007] Optionally, the communication signal is a non-power signal of the chip.

[0008] Optionally, the intermediate layer substrate comprises a first intermediate substrate and a second intermediate substrate which are stacked with each other. The first intermediate substrate is stacked between the top layer substrate and the second intermediate substrate. The communication signal of the chip is fanned out from the first intermediate substrate.

[0009] Optionally, the top substrate is a complete ground layer of the chip, and the second intermediate substrate is a complete power layer of the chip; or the top substrate is a complete power layer of the chip, and the second intermediate substrate is a complete ground layer of the chip.

[0010] Optionally, the top substrate is provided with a plurality of pads, each pad of the top substrate is connected with the die through a corresponding bump, and the pad guides interface signals of the die to the top substrate through the bump, wherein the communication signals include the interface signals.

[0011] Optionally, the die includes a vertical projection area, and the vertical projection area is provided with a bump arrangement matrix connected with a plurality of bumps.

[0012] Optionally, any three adjacent bumps in the plurality of bumps form an equilateral triangle.

[0013] Optionally, a distance between any two adjacent bumps in the plurality of bumps is a fixed value.

[0014] Optionally, the plurality of bumps include a plurality of signal bumps and a plurality of ground bumps, which correspond to interface signals and common ground signals respectively, an odd row of the bump arrangement matrix is allocated with a maximum of M / 2 signal bumps, and an even row of the bump arrangement matrix is allocated with a maximum of (M / 2)-1 signal bumps, wherein M is a maximum column number of the bump arrangement matrix.

[0015] According to another embodiment of the present application, an electronic device is provided, which includes the chip according to any one of the above embodiments.

[0016] According to the present application, the chip includes the die, the substrate structure and the ball from top to bottom, the substrate structure includes the top substrate, the intermediate substrate and the bottom substrate which are stacked with each other, the top substrate is connected with the die, the bottom substrate is connected with the ball, the communication signals of the chip are fanned out from the intermediate substrate, and connected to the bottom substrate through the via hole, the intermediate substrate below the top substrate is designed as a fan-out substrate, and the size of the via hole is smaller than that of the bump pad on the top substrate, so that the wiring space is increased without increasing the substrate area and the number of layers, the wiring space of the single-layer substrate is improved, the number of substrate layers is reduced, and the substrate cost and the chip cost are significantly saved. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the principles of the present application. In the drawings:

[0018] Figure 1 is a structural schematic diagram of a chip according to an embodiment of the present application;

[0019] Figure 2 is a schematic diagram of a layer stack of a chip structure in an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of a Bump arrangement matrix in an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a first intermediate substrate fan-out signal in an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a reference layer in an embodiment of the present application;

[0023] Figure 6 is a complete fan-out diagram of a fan-out layer in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the personnel in the art better understand the present application scheme, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0025] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, not necessarily to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, product or device including a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0026] In the present embodiment, a chip is provided, Figure 1 is a structural schematic diagram of a chip according to an embodiment of the present application, such as Figure 1As shown, the chip comprises, from top to bottom, a Die 10, a substrate structure 12, and a Ball 14, the substrate structure 12 comprises a top layer substrate 121, an intermediate layer substrate 122, and a bottom layer substrate 123 which are stacked with each other, the top layer substrate 121 is connected with the Die 10, and the bottom layer substrate 123 is connected with the Ball 14.

[0027] The communication signal of the chip is fanned out from the intermediate layer substrate 122 and connected to the bottom layer substrate 123 through a via.

[0028] Optionally, when the intermediate layer substrate is multi-layer, one single layer substrate in the intermediate layer substrate 122 is selected as a wiring layer, and the communication signal is fanned out from the wiring layer and connected to the bottom layer substrate through a via.

[0029] By adopting the scheme of the embodiment, the chip comprises, from top to bottom, a Die, a substrate structure, and a Ball, the substrate structure comprises a top layer substrate, an intermediate layer substrate, and a bottom layer substrate which are stacked with each other, the top layer substrate is connected with the Die, the bottom layer substrate is connected with the Ball, the communication signal of the chip is fanned out from the intermediate layer substrate and connected to the bottom layer substrate through a via, the intermediate layer substrate below the top layer substrate is designed as a fan-out substrate, and the size of the via is smaller than that of the Bump Pad on the top layer substrate, so that the wiring space is increased without increasing the substrate area and the number of layers, the wiring space of the single layer substrate is improved, the number of layers of the substrate is reduced, and the substrate cost and the chip cost are significantly saved.

[0030] In one embodiment of the embodiment, the communication signal is a non-power signal of the chip, including an interface signal and a common ground signal of the Die.

[0031] In one embodiment, the intermediate layer substrate comprises a first intermediate substrate and a second intermediate substrate which are stacked with each other, the first intermediate substrate is stacked between the top layer substrate and the second intermediate substrate, and the communication signal of the chip is fanned out from the first intermediate substrate.

[0032] Optionally, in addition to the first intermediate substrate and the second intermediate substrate, the intermediate layer substrate can further comprise a third intermediate substrate, a fourth intermediate substrate, etc., such as six substrates L1-L6 which are stacked with each other, the L1 layer is the top layer substrate, the L6 layer is the bottom layer substrate, and L2-L5 are intermediate layer substrates, L2 can be selected as the first intermediate substrate layer (fan-out layer), and the communication signal of the chip is fanned out from the first intermediate substrate.

[0033] Figure 2is a schematic diagram of the layer stack of the chip structure in the embodiment of the present application, taking the FCBGA chip as an example, the Flip Chip BGA package (FCBGA) chip stack structure contains 6 layers of substrates, the uppermost is the Die of the chip, located at the uppermost of the package, and the bumps below are all substrates, composed of 6 layers of conductive copper layers, intermediate non-conductive dielectric layers, and package solder balls Ball, all interface signals need to be connected from the Bump to the L1 layer of the substrate, and then need to be exchanged through the via VIA to be connected with the Ball of the L6 layer, to realize the signal connection of the chip from the Die through the substrate to the Ball.

[0034] In the chip design structure of the embodiment, the non-power signals (communication signals) of the substrate are changed from the vertical projection area of the Die to the L2 layer for fan-out wiring, all non-power signals of the substrate are punched from the L1 layer Bump PAD to the L2 layer fan-out Die area, and then punched through the via to the L6 layer to be connected with the corresponding signal Ball of the L6 layer. The other copper layers are planned as power and ground. According to the production process of the chip, the size of the via is smaller than the size of the Bump Pad on the L1, and part of the power and ground is connected on the L1 layer, without the need to punch to the L2 layer, so the wiring space of the L2 layer will be larger than that of the L1 layer, so that all signals can be fanned out from the L2 layer without the need to design multiple substrates as fan-out layers.

[0035] In one example, the top layer substrate is a complete ground layer of the chip, and the second intermediate substrate is a complete power layer of the chip. In another example, the top layer substrate is a complete power layer of the chip, and the second intermediate substrate is a complete ground layer of the chip.

[0036] Part of the power and ground is connected on the L1 layer, without the need to punch to the L2 layer, so the wiring space of the L2 layer will be larger than that of the L1 layer, which further ensures that all signals can be fanned out from the L2 layer.

[0037] The first layer of the intermediate layer substrate is designed as a fan-out layer (the first intermediate substrate), and the second layer of the intermediate layer substrate is designed as a reference layer (the second intermediate substrate), for example, the L1 and L3 layers adjacent to the L2 can be planned as a complete ground layer or a complete power layer, and the specific allocation of the ground layer and the power layer is set according to the specific design, but no matter how the allocation is made, the complete ground layer and the complete power layer will provide a complete reference plane for the signal, which can ensure the continuity of the signal impedance and is better for signal integrity.

[0038] In the embodiment, a plurality of Pads are arranged on the top layer substrate, each Pad of the top layer substrate is connected with the Die through a corresponding Bump, the Pad guides the interface signals of the Die to the top layer substrate through the Bump, and the communication signals include the interface signals.

[0039] In one example based on the embodiment, the Die includes a vertical projection area, and a bump arrangement matrix is arranged on the vertical projection area, and the bump arrangement matrix is connected with a plurality of bumps.

[0040] Optionally, any three adjacent bumps in the plurality of bumps form an equilateral triangle.

[0041] Optionally, the distance between any two adjacent bumps in the plurality of bumps is a fixed value.

[0042] Figure 3 is a schematic diagram of the bump arrangement matrix in the embodiment, which illustrates two modes of equilateral triangle arrangement and square arrangement, and takes the left area of the vertical projection area as an example. The bump arrangement diagram of the Die area satisfies that all signals are routed from the left side, and can also well satisfy the density of the bumps and the technical constraints of substrate production. In the bump x / y, x and y are row / column coordinates, Bump 11 and Bump 31 are the outermost circle, Bump 21 is the second circle, Bump 12 and Bump 32 are the third circle, and so on, which extends to the center area of the Die. In the equilateral triangle arrangement, the distance between any three adjacent bumps is an equilateral triangle layout, and the distance between any two adjacent bumps can be determined according to the technical constraints of the substrate production manufacturer and the total number of signals to be fanned out. The greater the total number of signals, the smaller the fixed value of the distance between adjacent bumps, which is negatively correlated.

[0043] The equilateral triangle arrangement is more compact than other arrangement modes under the production requirements of the minimum distance of the bumps. Taking the square arrangement mode as an example for space occupation comparison: the same number of bumps are arranged in the same vertical projection area, assuming that the minimum distance of the bumps is a, the distance between Bump 1 / 1 and Bump 3-1 of the equilateral triangle arrangement of the bumps in the embodiment is 1.73a; the distance between Bump 1 / 1 and Bump 3 / 1 of the normal square arrangement of the bumps is 2a; therefore, the equilateral triangle arrangement of the bumps in the embodiment is more compact and saves more space.

[0044] In one example of the embodiment, the plurality of bumps include a plurality of signal bumps and a plurality of ground bumps corresponding to interface signals and common ground signals (VSS), respectively, and an odd row of the bump arrangement matrix is allocated with at most M / 2 signal bumps, and an even row of the bump arrangement matrix is allocated with at most (M / 2)-1 signal bumps, and M is the maximum number of columns of the bump arrangement matrix. The remaining bumps in the even row can be allocated with ground bumps.

[0045] In another example, the even rows of the bump arrangement matrix allocate at most M / 2 signal bumps, and the odd rows allocate at most (M / 2)-1 signal bumps.

[0046] Optionally, M=6, and the arrangement of the bump signal types is also required to be specific by rows and columns. Table 1 below lists examples of signal bump arrangements. The combination of Signal (interface signal) and VSS (common ground signal) ensures the possibility of left fan-out space and multi-wire fan-out of the substrate signal. Bump1 / 1 of the first row allocates signals, and Bump1 / 2 to Bump1 / M allocate at most 2 signals, and the signal of the second row can allocate at most 2 signals. In order to ensure the possibility of fan-out space and multi-wire fan-out, the arrangement of the signal bump and the ground bump is required as follows. Table 1 shows the arrangement rules of the signal bump and the ground bump:

[0047] Table 1

[0048] Bump coordinates Column 1 Column 2 Column 3 Column 4 Column 5 Column 6 Row 1 Signal Signal Signal Row 2 VSS Signal Signal Row 3 Signal Signal Signal Row 4 VSS Signal Signal

[0049] Figure 4 FIG. 1 is a schematic diagram of the first intermediate substrate fan-out signal in the embodiment of the present application. All non-power and GND signals (VSS) are directly punched from the L1 layer (top substrate) bump to the L2 layer (first intermediate substrate), and the entire signal DIE area is fan-out outwardly in the L2 layer.

[0050] Figure 5 FIG. 2 is a schematic diagram of the reference layer in the embodiment of the present application. The reference layer corresponds to the L1 layer (top substrate) and the L3 layer (second intermediate substrate), and most of the area is a ground layer, which provides a complete reference plane for the L2 layer signal, ensuring impedance consistency and signal integrity.

[0051] Figure 6 FIG. 3 is a complete wire-out diagram of the fan-out layer in the embodiment of the present application. The complete wire-out diagram of the Die second layer L2 includes the left side, the right side, the TOP (upper) side, and the BOT (lower) side, and each direction wire-out is accordingly deduced, thereby ensuring that all signals are fan-out in the L2 layer, and the signals are completely fan-out in the four edges of the L2 layer of the substrate.

[0052] The scheme of the embodiment also provides an electronic device, which includes the chip described in the above embodiment.

[0053] Optionally, the electronic device can be a mobile phone, a computer, a server, a refrigerator, a television, a washing machine, an air conditioner, or other devices that need to be built-in with a chip.

[0054] The scheme of the embodiment is adopted to arrange the bumps in an equilateral triangle mode, which is more compact under the production requirement of meeting the minimum spacing of the bumps, can meet the fan-out of all non-power signal lines of the substrate, and ingeniously provides convenience for the fan-out of the chip substrate signal lines; the scheme of the single-layer fan-out of all signals reduces the substrate layer requirement, significantly saves the substrate cost and chip cost; the wire-out mode of the substrate signal and ground provides a better reference plane and shielding layer for the signal, can better ensure the consistency of the signal impedance, reduce signal interference or crosstalk, improve the integrity of the substrate and chip signal, and ensure the chip performance and mass production.

[0055] In the above-described embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0056] In the several embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. Of course, the embodiment described above is only illustrative, and the division of units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, unit or module, and can be electrical or other forms.

[0057] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0058] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0059] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0060] The above is only the preferred embodiment of the present application, and it should be pointed out that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should be considered as the protection scope of the present application.

Claims

1. A chip, characterized by The chip, from top to bottom, includes a Die, a substrate structure, and a Ball. The substrate structure includes a top substrate, an intermediate substrate, and a bottom substrate stacked on top of each other. The top substrate is connected to the Die, and the bottom substrate is connected to the Ball. The communication signal of the chip is fanned out from the intermediate layer substrate and connected to the bottom substrate through vias; The intermediate layer substrate includes a first intermediate substrate and a second intermediate substrate stacked on top of each other. The first intermediate substrate is stacked between the top substrate and the second intermediate substrate, and the communication signal of the chip is fanned out from the first intermediate substrate. Wherein, the size of the via is smaller than the size of the bump pad on the top substrate; The Die includes a vertical projection area, on which a bump arrangement matrix is ​​arranged. The bump arrangement matrix connects multiple bumps, which include several signal bumps and several ground bumps, corresponding to interface signals and common ground signals, respectively. The odd-numbered rows of the bump arrangement matrix are allocated with a maximum of M / 2 signal bumps, and the even-numbered rows are allocated with a maximum of (M / 2)-1 signal bumps, where M is the maximum number of columns in the bump arrangement matrix. Any three adjacent bumps in the multiple bumps form an equilateral triangle.

2. The chip according to claim 1, characterized in that, The top substrate is the complete ground layer of the chip, and the second intermediate substrate is the complete power layer of the chip; or, the top substrate is the complete power layer of the chip, and the second intermediate substrate is the complete ground layer of the chip.

3. The chip of claim 1, wherein The top substrate has multiple pads, and each pad on the top substrate is connected to the die via a corresponding bump. The pads export the interface signals of the die to the top substrate via the bumps, and the communication signals include the interface signals.

4. An electronic device, comprising: Includes the chip as described in any one of claims 1 to 3.

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