An ultra-low latency communication device and a method for its cascading

Abstract

This application provides an ultra-low latency communication device and a method for cascading the same. The method includes: allocating a first enhanced signal port located in a Media Access Control (MAC) unit to a unidirectional forwarding port group of a hardware switching unit; wherein the unidirectional forwarding port group includes a first port as a source port and one or more second ports as destination ports; establishing a first inter-chip link from the first port to the first enhanced signal port and looping back through the first enhanced signal port to the second port; and setting pre-emphasis transmission parameters for each second port.

Description

Technical Field

[0001] This application relates to communication technology, specifically to an ultra-low latency communication device and a method for cascading it. Background Technology

[0002] The financial securities industry's demand for high-frequency trading is growing stronger, leading to an explosive increase in demand for ultra-low latency trading systems composed of ultra-low latency switches. It is against this backdrop that ultra-low latency switches, with their advantages of extremely low latency and minimal functionality, have emerged. Ultra-low latency switches have only one layer of forwarding functionality, enabling ultra-low latency forwarding.

[0003] During the networking process, the data ports between ultra-low latency switches are directly connected by cables according to business needs to reduce the forwarding latency of physical links between switches. However, when data packets are forwarded through physical links, there will be problems such as signal attenuation and reduced anti-interference. When ultra-low latency switches send data packets from financial servers to other financial servers or financial clients, the data packets cannot be correctly parsed due to signal attenuation, resulting in data loss and affecting transaction stability. Summary of the Invention

[0004] The purpose of this application is to provide an ultra-low latency communication device and a method for cascading the device, thereby enhancing the signal of forwarded data packets between cascaded ultra-low latency communication devices.

[0005] To achieve the above objectives, this application provides a method for cascading ultra-low latency communication devices. The method includes: allocating a first enhanced signal port located in a Media Access Control (MAC) unit to a unidirectional forwarding port group of a hardware switching unit; wherein the unidirectional forwarding port group includes a first port as a source port and one or more second ports as destination ports; establishing a first inter-chip link from the first port to the first enhanced signal port and looping back through the first enhanced signal port to the second port; and setting pre-emphasis transmission parameters for each second port.

[0006] To achieve the above objectives, this application also provides an ultra-low latency communication device, which includes a processor, a memory, a hardware switching unit, and a media access control (MAC) unit. The hardware switching unit has multiple ports for network communication. The processor executes processor-executable instructions in the memory to perform the following operations: allocating a first enhanced signal port located in the MAC hardware unit to the unidirectional forwarding port group of the hardware switching unit; wherein the unidirectional forwarding port group includes a first port as a source port and one or more second ports as destination ports; establishing a first inter-chip link from the first port to the first enhanced signal port and looping back through the first enhanced signal port to each second port; and setting pre-emphasis transmission parameters for each second port.

[0007] The beneficial effects of this application are that it uses the MAC chip with other functions on the ultra-low latency communication device to achieve signal enhancement, provides signal enhancement for the forwarded data packets, supports multi-level cascading of multiple ultra-low latency communication devices in the network, and extends the transmission distance of the ultra-low latency communication device. Attached Figure Description

[0008] Figure 1 This application provides a flowchart of a method for cascading ultra-low latency communication devices;

[0009] Figure 2 This is a schematic diagram illustrating how an ultra-low latency communication device, provided in an embodiment of this application, enhances the signal of a forwarded data packet.

[0010] Figure 3 A schematic diagram illustrating the signal enhancement of a forwarded data packet by an ultra-low latency communication device provided in another embodiment of this application;

[0011] Figure 4 A schematic diagram illustrating the signal enhancement of a forwarded data packet by an ultra-low latency communication device provided in another embodiment of this application;

[0012] Figure 5 This is a schematic diagram of an ultra-low latency communication device for enhancing the signal of forwarded data packets, provided in an embodiment of this application. Detailed Implementation

[0013] The following detailed description will be provided with reference to several examples illustrated in the accompanying figures. In this detailed description, numerous specific details are used to provide a comprehensive understanding of the present application. Known methods, steps, components, and circuits are not described in detail in the examples to avoid obscuring their meaning.

[0014] In the terminology used, the term "including" means including but not limited to; the term "containing" means including but not limited to; the terms "above," "within," and "below" include the number itself; the terms "greater than" and "less than" mean not including the number itself. The term "based on" means based on at least a portion of them.

[0015] Figure 1 This application provides a flowchart of a method for cascading ultra-low latency communication devices; this embodiment includes,

[0016] Step 102: Assign an enhanced signal port located in the Media Access Control (MAC) unit to the unidirectional forwarding port group of the hardware switching unit; wherein, the unidirectional forwarding port group includes one source port and one or more destination ports;

[0017] Step 102: Establish an inter-chip link from the source port to the enhanced signal port and back to the destination port via the internal loop of the enhanced signal port;

[0018] Step 103: Set the pre-emphasis transmission parameters for each destination port.

[0019] The beneficial effect of this application is that it uses the MAC chip with other functions on the ultra-low latency communication device to achieve signal enhancement, provides signal enhancement for the forwarded data packets, and supports multi-level cascading of multiple ultra-low latency communication devices in the network and extends the transmission distance.

[0020] Figure 2 This is a schematic diagram illustrating how an ultra-low latency communication device, as provided in an embodiment of this application, enhances the signal of a forwarded data packet. Figure 2 In the above, ports P1 and P2 of device 20 are connected to port P21 of device 21 and port P22 of device 22, respectively. Figure 2 Devices 20-22 in the diagram illustrate a basic cascading method between ultra-low latency communication devices, which sends data packets from one device to another.

[0021] According to the network service data forwarding requirements, device 20 sends data packets from device 21 to device 22. Therefore, port P1 of the switching chip 202 of device 20 is the source port and port P2 is the destination port.

[0022] The processor 201 of device 20 assigns a PIPE port C1 located in the media access control MAC chip 203 as an enhancement signal port to ports P1 and P2.

[0023] Processor 201 sets the port index of port P1 recorded in the source port register of port P2 to invalid, and disconnects the intra-chip link from port P1 to port P2.

[0024] Processor 201 sets the invalid value recorded in the source port register of port P2 to the port index of port C1, connects the Tx of port P2 to the Tx of port C1, and establishes an inter-chip link between port C1 and port P2.

[0025] Processor 201 sets port C1 as an internal loopback port; that is, the RX of port C1 is directly connected to the TX. After the data packets received by C1 are enhanced by the PCS (Physical Coding Sublayer) signal, the MAX chip 203 sends them directly through the TX without entering the MAC layer of the MAC chip 203.

[0026] The processor 201 checks that port C1 of the MAC chip 203 is in a normal operating state (up). The processor 201 can check that port C1 is in a normal operating state by calling the API (Application Interface); this application does not limit the implementation method of the processor 201 checking that C1 is in a normal operating state.

[0027] Processor 201 checks that ports P1 and P2 are in normal operating condition. Processor 201 can check whether ports P1 and P2 are signal-locked and can normally receive and transmit signals on the physical link by reading the Loss signal registers of ports P1 and P2 on the switching chip. This application does not limit the implementation method of processor 201 checking that P1 and P2 are in normal operating condition.

[0028] Processor 201 checks that ports C1, P1, and P2 are in normal working condition, thus ensuring the inter-chip link between ports P1, C1, and P2 is working properly, establishing an inter-chip link from port P1 to port C1 and back through the internal loop of port C1 to port P2. Processor 201 then sets the pre-emphasis transmission parameters for port P2.

[0029] In this way, switches 20, 21, and 22 are cascaded.

[0030] When data packet D1 arrives at port P1, the switching chip 202 sends data packet D1 to port C1 via the inter-chip link.

[0031] The MAC chip 203 performs PCS signal enhancement on the data message D1 received at port C1, loops the enhanced signal back through port C1, and sends it to port P2 on the inter-chip circuit.

[0032] The switching chip sends data packet D1 according to the pre-emphasis transmission parameters of port P2.

[0033] Figure 3This is a schematic diagram of an ultra-low latency communication device according to another embodiment of the present application performing signal enhancement on a forwarded data packet; ports P1, P2, and P3 of device 30 are respectively connected to port P31 of device 31, port P32 of device 32, and port 33 of device 33. Figure 3 Devices 30-33 in the diagram illustrate a basic cascading method, which simultaneously sends data packets received from one source port to multiple destination ports.

[0034] According to the network service data forwarding requirements, device 30 sends data packets from device 31 to devices 32 and 33; port P1 of the switching chip 302 of device 30 has been set as the source port, and ports P2 and P3 have been set as the destination ports.

[0035] The processor 301 of device 30 assigns a PIPE port C1 located in the media access control MAC chip 303 as an enhancement signal port to ports P1, P2, and P3.

[0036] Processor 301 sets the port index of port P1 recorded in the source port registers of ports P2 and P3 to invalid, disconnects the intra-chip link from port P1 to port P2, and disconnects the intra-chip link from port P1 to port P3.

[0037] Processor 301 sets the invalid value recorded in the source port register of port P2 to the port index of port C1, and establishes a chip link between port C1 and port P2; it sets the invalid value recorded in the source port register of port P3 to the port index of port C1, and establishes a chip link between port C1 and port P3.

[0038] Processor 301 sets port C1 as an internal loopback port.

[0039] Processor 301 checks that port C1 of MAC chip 303 is in normal working condition, and checks that ports P1, P2, and P3 are in normal working condition. This means that the inter-chip links between ports P1, C1, P2, and P3 are working normally, and an inter-chip link is established from port P1 to port C1 and back to port P2 via the internal loop of port C1, as well as an inter-chip link is established from port P1 to port C1 and back to port P3 via the internal loop of port C1.

[0040] Processor 301 sets the pre-emphasis transmission parameters for ports P2 and P3 respectively.

[0041] In this way, switches 30, 31, 32, and 33 are cascaded.

[0042] When data packet D1 arrives at port P1, the switching chip 302 sends data packet D1 to port C1 via the inter-chip link.

[0043] The MAC chip 303 performs PCS signal enhancement on the data message D1 received at port C1, loops the enhanced signal back through port C1, and sends it to ports P2 and P3 on the inter-chip circuit.

[0044] The switching chip sends data packet D1 according to the pre-emphasis transmission parameters of ports P2 and P3.

[0045] Figure 4 A schematic diagram illustrating the signal enhancement of a forwarded data packet by an ultra-low latency communication device provided in another embodiment of this application;

[0046] Ports P1 and P2 of device 40 are connected to port P41 of device 41 and port P424 of device 42, respectively. Figure 4 Devices 40-42 in the diagram illustrate a basic cascading method, where data packets sent between two devices 41 and 42 are forwarded via device 40.

[0047] Based on the network service data forwarding requirements, ports P1 and P2 of device 40 are each other's source and destination ports; that is, the source port register of port P1 records the index of port P2; and the source port register of port P2 records the index of port P1.

[0048] The processor 401 of device 40 assigns two PIPE ports C1 and C2 located in the media access control MAC chip 403 as enhanced signal ports to ports P1 and P2.

[0049] Processor 401 sets the port indices of the source port registers of ports P1 and P2 to invalid, disconnects the intra-chip link from port P1 to port P2, and disconnects the intra-chip link from port P2 to port P1.

[0050] Processor 401 sets the invalid value recorded in the source port register of port P2 to the port index of port C1, and establishes a link between port C1 and port P2; it sets the invalid value recorded in the source port register in port P1 to the port index of port C2, and establishes a link between port C2 and port P3.

[0051] Processor 401 sets ports C1 and C2 as internal loopback ports.

[0052] Processor 401 checks that ports C1 and C2 of MAC chip 403 are in normal working condition, checks that ports P1 and P2 are in normal working condition, establishes an inter-chip link from port P1 to port C1 and through the internal loop of port C1 back to port P2, and establishes an inter-chip link from port P2 to port C2 and through the internal loop of port C2 back to port P1.

[0053] Processor 401 sets the pre-emphasis transmission parameters for ports P1 and P2 respectively.

[0054] In this way, switches 40, 41, and 42 are cascaded.

[0055] When data packet D3 arrives at port P1, switching chip 402 sends data packet D3 to port C1 via the inter-chip link. MAC chip 403 performs PCS signal enhancement on data packet D3 received at port C1, loops the enhanced data packet D3 back through port C1, and sends it to port P2 on the inter-chip circuit. The switching chip then sends data packet D3 according to the pre-emphasis transmission parameters of port P2.

[0056] When data packet D4 arrives at port P2, switching chip 402 sends data packet D4 to port C2 via the inter-chip link. MAC chip 403 performs PCS signal enhancement on data packet D4 received at port C2, loops the enhanced data packet D4 back through port C2, and sends it to port P1 on the inter-chip circuit. The switching chip then sends data packet D4 according to the pre-emphasis transmission parameters of port P1.

[0057] In an ultra-low latency switch network, ultra-low latency switches can network with each other. Figures 2-4 One or more methods of cascading in the embodiments; based on Figures 2-4 In this embodiment, the cascaded ultra-low latency communication devices do not require CDR circuits at the source and destination ports, thus reducing latency.

[0058] The embodiments described above utilize MAC chips with other functions on the device to achieve signal enhancement and reduce latency. This enables multi-level cascading of ultra-low latency communication devices and extends the transmission distance of ultra-low latency communication devices.

[0059] Figure 5 This is a schematic diagram of an ultra-low latency communication device for signal enhancement of forwarded data packets provided in an embodiment of this application. The device 50 includes a processor 51, a memory 52, a hardware switching unit 53 implemented by a switching chip, and a media access control (MAC) unit 54 implemented by a hardware chip. The hardware switching unit 53 has multiple ports 531 for network communication. The processor 51 executes processor-executable instructions in the memory 52 to perform the following operations: allocate a first enhanced signal port located in the MAC hardware unit to the unidirectional forwarding port group of the hardware switching unit 53; wherein the unidirectional forwarding port group includes a first port as a source port and one or more second ports as destination ports; establish a first inter-chip link from the first port to the first enhanced signal port and looping back through the first enhanced signal port to each second port; and set pre-emphasis transmission parameters for each second port.

[0060] The unidirectional forwarding port group of the hardware switching unit 53 includes a first port and a second port; the processor 51 establishes the first inter-chip link by running processor-executable instructions in the memory 52, including disconnecting the intra-chip link between the first port and the second port; establishing the second inter-chip link between the first enhanced signal port and the second port; setting the first enhanced signal port as an internal loopback port; and checking that the first enhanced signal port, the first port, and the second port are in normal working condition.

[0061] The unidirectional forwarding port group of the hardware switching unit 53 includes a first port and two or more second ports; the processor 51 establishes the first inter-chip link by running processor-executable instructions in the memory 52, including disconnecting the intra-chip link between the first port and each second port; establishing the second inter-chip link between the first enhanced signal port and each second port; setting the first enhanced signal port as an internal loopback port; and checking that the first enhanced signal port, the first port, and each second port are in normal working condition.

[0062] The bidirectional forwarding port group of the hardware switching unit 53 includes a third port and a fourth port that are both source and destination ports. The processor 51, through processor-executable instructions in the running memory 52, also performs the following operations: allocates a pair of second and third enhanced signal ports located in the MAC unit to the bidirectional forwarding port group; establishes a third inter-chip link from the third port to the second enhanced signal port and through the internal loop of the second enhanced signal port back to the fourth port; establishes a fourth inter-chip link from the fourth port to the third enhanced signal port and through the internal loop of the enhanced signal port back to the destination port; and sets the pre-emphasis transmission parameters for the third port and the fourth port respectively.

[0063] The processor 51 establishes the inter-chip link between the third and fourth chips by running processor-executable instructions in the memory 52, including disconnecting the intra-chip link between the third port and the fourth port; establishing the inter-chip link between the second enhanced signal port and the fourth port; establishing the inter-chip link between the third enhanced signal port and the third port; setting the second and third enhanced signal ports as internal loopback ports; and checking that the second enhanced signal port, the third enhanced signal port, the third port, and the fourth port are in normal working condition.

[0064] Hardware switching unit 53 is used to send the first data packet arriving at the first port to the first enhanced signal port via the first chip; MAC unit 54 is used to perform physical coding sublayer signal enhancement on the first data packet received by the first enhanced signal port, and loop back the first data packet to each second port via the first enhanced signal port; hardware switching unit 53 is also used to send the first data packet according to the pre-emphasis transmission parameters of each second port.

[0065] The hardware switching unit 53 is further configured to send the second data packet arriving at the third port to the second enhanced signal port; and to send the third data packet arriving at the fourth port to the third enhanced signal port; the MAC unit 54 is configured to perform physical coding sublayer signal enhancement on the second data packet received at the second enhanced signal port, and loop back the second data packet to the fourth port through the second enhanced signal port; and to perform physical coding sublayer signal enhancement on the third data packet received at the third enhanced signal port, and loop back the third data packet to the third port through the third enhanced signal port; the hardware switching unit 53 is further configured to send the second data packet according to the pre-emphasis transmission parameters of the fourth port; and to send the third data packet according to the pre-emphasis transmission parameters of the third port.

[0066] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for implementing cascading of ultra-low latency communication devices, the method comprising: The method comprises, allocating a first enhanced signal port in a media access control (MAC) unit for a unidirectional forwarding port group of a hardware switching unit; wherein the unidirectional forwarding port group comprises a first port as a source port and one or more second ports as destination ports; establishing a first inter-chip link from the first port to the first enhanced signal port and internally looped back to the second ports through the first enhanced signal port; setting pre-emphasis transmission parameters of each of the second ports.

2. The method of claim 1, wherein, The unidirectional forwarding port group comprises the first port and one second port.

3. The method of claim 1, wherein, The first inter-chip link from the first port to the first enhanced signal port and internally looped back to the second ports through the first enhanced signal port comprises, disconnecting the intra-chip link between the first port and the second port; establishing a second inter-chip link between the first enhanced signal port and the second port; setting the first enhanced signal port as an internal loopback port; checking that the first enhanced signal port, the first port and the second port are in a normal working state.

4. The method of claim 1, wherein, The unidirectional forwarding port group comprises the first port and two or more second ports.

5. The method of claim 1, wherein, The first inter-chip link from the first port to the first enhanced signal port and internally looped back to the second ports through the first enhanced signal port comprises, disconnecting the intra-chip link between the first port and each of the second ports; establishing a second inter-chip link between the first enhanced signal port and each of the second ports; setting the first enhanced signal port as an internal loopback port; checking that the first enhanced signal port, the first port and each of the second ports are in a normal working state.

6. The method of claim 1, wherein, The method further comprises, allocating a pair of second and third enhanced signal ports in the MAC unit for a bidirectional forwarding port group of the hardware switching unit; wherein the bidirectional forwarding port group comprises a third port and a fourth port as the source port and the destination port respectively; establishing a third inter-chip link from the third port to the second enhanced signal port and internally looped back to the fourth port through the second enhanced signal port; and establishing a fourth inter-chip link from the fourth port to the third enhanced signal port and internally looped back to the destination port through the third enhanced signal port; setting pre-emphasis transmission parameters of the third and fourth ports respectively.

7. The method of claim 6, wherein, The third inter-chip link from the third port to the second enhanced signal port and internally looped back to the fourth port through the second enhanced signal port; and the fourth inter-chip link from the fourth port to the third enhanced signal port and internally looped back to the destination port through the third enhanced signal port comprises, disconnecting the intra-chip link between the third port and the fourth port; establishing a third inter-chip link between the second enhanced signal port and the fourth port; establishing a fourth inter-chip link between the third enhanced signal port and the third port; setting the second and third enhanced signal ports as internal loopback ports; checking whether the second enhanced signal port, the third enhanced signal port, the third port and the fourth port are in normal working state.

8. The method according to claim 3 or 5, characterized in that, The method further comprises, a first data packet arriving at the first port is sent to the first enhanced signal port via the first inter-chip link; the first data packet received by the first enhanced signal port is subjected to physical coding sublayer signal enhancement by the MAC unit, and the first data packet looped back by the first enhanced signal port is sent to each of the second ports on the first inter-chip circuit; the first data packet is sent by the hardware switching unit according to pre-emphasis sending parameters of each of the second ports.

9. The method of claim 6, wherein, The method further comprises, a second data packet arriving at the third port is sent to the second enhanced signal port via the second sending; the MAC unit subjects the second data packet received by the second enhanced signal port to physical coding sublayer signal enhancement, and the second data packet looped back by the second enhanced signal port is sent to the fourth port; the hardware switching unit sends the second data packet according to pre-emphasis sending parameters of the fourth port; the hardware switching unit sends a third data packet arriving at the fourth port to the third enhanced signal port; the MAC unit subjects the third data packet received by the third enhanced signal port to the physical coding sublayer signal enhancement, and the third data packet looped back by the third enhanced signal port is sent to the third port; the hardware switching unit sends the third data packet according to pre-emphasis sending parameters of the third port.

10. An ultra-low latency communication device, comprising: The device has a processor, a memory, a hardware switching unit and a media access control (MAC) unit; wherein the hardware switching unit is provided with a plurality of ports for network communication; the processor executes processor-executable instructions in the memory to perform the following operations, a unidirectional forwarding port group of the hardware switching unit is assigned a first enhanced signal port in the MAC hardware unit; wherein the unidirectional forwarding port group comprises a first port as a source port and one or more second ports as destination ports; an inter-chip link is established from the first port to the first enhanced signal port and internally looped back to each of the second ports via the first enhanced signal port; pre-emphasis sending parameters of each of the second ports are set.

11. The apparatus of claim 10, wherein, The unidirectional forwarding port group of the hardware switching unit comprises the first port and one of the second ports; the processor, by executing the instructions, establishes the first inter-chip link, including, disconnecting an intra-chip link between the first port and the second port; establishing a second inter-chip link between the first enhanced signal port and the second port; setting the first enhanced signal port as an internal loopback port; checking whether the first enhanced signal port, the first port and the second port are in normal working state.

12. The apparatus of claim 10, wherein, The unidirectional forwarding port group of the hardware switching unit comprises the first port and two or more of the second ports; The processor, by running the instructions, establishes the first inter-chip link, and the operations include, disconnecting the first port from an intra-chip link of each of the second ports; establishing a second inter-chip link of the first enhanced signal port and each of the second ports; setting the first enhanced signal port as an internal loopback port; and checking the first enhanced signal port, the first port, and each of the second ports as normal working states.

13. The apparatus of claim 10, wherein, The bidirectional forwarding port group of the hardware switching unit includes a third port and a fourth port, which are the source port and the destination port respectively; The processor, by running the instructions, further performs the following operations, allocating a pair of second and third enhanced signal ports of the MAC unit for the bidirectional forwarding port group; establishing a third inter-chip link from the third port to the second enhanced signal port and internally looping back to the fourth port through the second enhanced signal port; establishing a fourth inter-chip link from the fourth port to the third enhanced signal port and internally looping back to the destination port through the third enhanced signal port; setting pre-emphasis transmission parameters of the third port and the fourth port respectively.

14. The apparatus of claim 13, wherein, The processor, by running the instructions, establishes the third and the fourth inter-chip links, and the operations include, further disconnecting the third port from an intra-chip link of the fourth port; establishing a third inter-chip link of the second enhanced signal port and the fourth port; establishing a fourth inter-chip link of the third enhanced signal port and the third port; setting the second and third enhanced signal ports as internal loopback ports; checking the second enhanced signal port, the third enhanced signal port, the third port, and the fourth port as normal working states.

15. The device of claim 11 or 12, wherein, the hardware switching unit is configured to send a first data packet arriving at the first port to the first enhanced signal port via the first inter-chip link; the MAC unit is configured to perform physical coding sublayer signal enhancement on the first data packet received by the first enhanced signal port, and loop back the first data packet via the first enhanced signal port to each of the second ports; the hardware switching unit is further configured to send the first data packet according to pre-emphasis transmission parameters of each of the second ports.

16. The device of claim 14, wherein, the hardware switching unit is further configured to send a second data packet arriving at the third port to the second enhanced signal port, and send a third data packet arriving at the fourth port to the third enhanced signal port; the MAC unit is configured to perform physical coding sublayer signal enhancement on the second data packet received by the second enhanced signal port, and loop back the second data packet via the second enhanced signal port to the fourth port; and perform the physical coding sublayer signal enhancement on the third data packet received by the third enhanced signal port, and loop back the third data packet via the third enhanced signal port to the third port. The hardware switching unit is further configured to send the second data packet according to pre-emphasis sending parameters of the fourth port, and send the third data packet according to pre-emphasis sending parameters of the third port.

Images