Dynamic aging monitor and correction for critical path duty cycle and delay degradation

Abstract

In certain aspects, a duty cycle monitor includes a first oscillator; and a flip-flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty cycle monitor, and the clock input is coupled to the first oscillator. The duty cycle monitor further includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flip-flop. The duty cycle monitor further includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flip-flop.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of non-provisional patent application serial number 17 / 652,092, filed in the United States Patent Office on February 22, 2022, and thereafter published as Patent No. 11,533,045 on December 20, 2022, the entire contents of which are hereby incorporated by reference as if set forth in full hereinbelow and for all applicable purposes. BACKGROUND TECHNICAL FIELD

[0004] Aspects of the present disclosure generally relate to aging, and more specifically to monitoring duty cycle degradation due to aging. BACKGROUND

[0006] A system can include a clock generator (e.g., a phase-locked loop) configured to generate a clock signal for timing operations of one or more circuits (e.g., sequential logic, processors, memories, etc.) in the system. The system can also include a clock path for distributing the clock signal from the clock generator to the one or more circuits. A challenge faced by clock distribution is that asymmetric aging in the clock path can cause duty cycle degradation in the clock signal, which can cause timing problems (e.g., timing violations) to arise in the one or more circuits. SUMMARY

[0007] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0008] A first aspect is directed to a system. The system includes a duty cycle monitor. The duty cycle monitor includes a first oscillator having an output, and a flip-flop having a signal input, a clock input, and an output, where the signal input is coupled to an input of the duty cycle monitor, and the clock input is coupled to the output of the first oscillator. The duty cycle monitor further includes a first counter having a count input, an enable input, and a count output, where the count input of the first counter is coupled to the output of the first oscillator, and the enable input of the first counter is coupled to the output of the flip-flop. The duty cycle monitor further includes a second counter having a count input, an enable input, and a count output, where the count input of the second counter is coupled to the output of the first oscillator, and the enable input of the second counter is coupled to the output of the flip-flop.

[0009] A second aspect is directed to a method of duty cycle monitoring. The method includes receiving a clock signal and a reference signal, inputting the clock signal to a signal input of a flip-flop, inputting the reference signal to a clock input of the flip-flop, counting a number of cycles of the reference signal in which an output of the flip-flop is high to generate a first count value, and counting a number of cycles of the reference signal in which the output of the flip-flop is low to generate a second count value. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 An example of a system including a clock generator, a clock path, and a circuit is shown in accordance with certain aspects of the present disclosure.

[0011] Figure 2A An example of a clock path including a clock buffer is shown in accordance with certain aspects of the present disclosure.

[0012] Figure 2B An example is shown in accordance with certain aspects of the present disclosure in which an input of a clock path is latched low in an idle mode.

[0013] Figure 2C A timing diagram illustrating an example of a duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure.

[0014] Figure 2D An example is shown in accordance with certain aspects of the present disclosure in which an input of a clock path is latched high in an idle mode.

[0015] Figure 2E A timing diagram illustrating another example of a duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure.

[0016] Figure 3 An example of a system with duty cycle correction is shown in accordance with certain aspects of the present disclosure.

[0017] Figure 4A An example of a duty cycle monitor is shown in accordance with certain aspects of the present disclosure.

[0018] Figure 4B Another example of a duty cycle monitor is shown in accordance with certain aspects of the present disclosure.

[0019] Figure 5 is a timing diagram illustrating example operations of a duty cycle monitor in accordance with certain aspects of the present disclosure.

[0020] Figure 6 An example implementation of a sense circuit is shown in accordance with certain aspects of the present disclosure.

[0021] Figure 7 is a flow diagram illustrating a method of duty cycle monitoring in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0022] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0023] Figure 1 An example of a system 110 including a clock generator 115, a clock path 120, and a circuit 130 in accordance with certain aspects is shown. The clock generator 115 is configured to generate a clock signal used to time the operation of the circuit 130. The circuit 130 can include sequential logic, a processor, a memory, etc. The clock generator 115 can be implemented with a phase-locked loop (PLL) or another type of clock generator. The clock path 120 is configured to distribute the clock signal from the clock generator 115 to the circuit 130. As used herein, a “clock signal” can be a periodic signal that oscillates between a high and a low. The clock signal has a duty cycle, which can be expressed as a percentage or fraction of clock cycles (i.e., clock cycles) in which the clock signal is at a high (i.e., 1).

[0024] In some aspects, system 110 includes a clock gating circuit 140 configured to gate a clock signal to save power when circuit 130 is inactive (e.g., in an idle mode), and to pass a clock signal when circuit 130 is active. Clock gating is a known technique for reducing dynamic power consumption when circuit is inactive. Although in Figure 1 In the diagram, a clock gating circuit 140 is shown between clock generator 115 and clock path 120, but it should be understood that system 110 may include two or more clock gating circuits (e.g., at different locations along clock path 120). It should also be understood that clock path 120 may include multiple branches (not shown) forming a clock tree to distribute clock signals to multiple circuits including circuit 130.

[0025] Aging effects such as bias temperature instability (BTI) can degrade the performance of clock path 120 over time. For example, BTI stress in the clock path during idle mode can cause duty cycle shift in the clock path over time, which may lead to timing problems (e.g., timing violations) in circuit 130.

[0026] Now refer to Figures 2A-2E Discuss examples of duty cycle shift caused by aging. Figure 2A An example is shown in which clock path 120 includes series-coupled clock buffers 220-1 to 220-4. Although for simplicity... Figure 2A Four clock buffers 220-1 to 220-4 are shown, but it should be understood that clock path 120 may include a large number of clock buffers. Figure 2A In the example shown, each of the clock buffers 220-1 to 220-4 is implemented using a corresponding complementary inverter, which includes a corresponding transistor (e.g., an n-type field-effect transistor) from transistors 225-1 to 225-4 and a corresponding transistor (e.g., a p-type field-effect transistor) from transistors 230-1 to 230-4. However, it should be understood that each of the clock buffers 220-1 to 220-4 can be implemented using another type of circuit or logic gate.

[0027] When circuit 130 is in active mode, clock path 120 receives clock signal, and the clock signal is propagated to circuit 130 through clock buffers 220-1 to 220-4. When circuit 130 is in idle mode, clock gating circuit 140 can keep the input of clock path 120 in a high or low position for one idle cycle.

[0028] Figure 2BAn example is shown in which the input of the clock path 120 is pulled low (i.e., logic 0) in the idle mode. Figure 2B The logic state at the input and output of each of the clock buffers 220-1 to 220-4 is also shown. In this example, the output of the clock path 120 is low (i.e., logic 0) in the idle mode. In this example, transistors 230-1, 225-2, 230-3, and 225-4 are turned on in the idle mode, and transistors 225-1, 230-2, 225-3, and 230-4 are turned off in the idle mode. Figure 2B In the example shown, transistors 230-1, 225-2, 230-3, and 225-4, which are turned on in the idle mode, are shown in bold. Transistors 230-1, 225-2, 230-3, and 225-4, which are turned on in the idle mode, are stressed in the idle mode, while transistors 225-1, 230-2, 225-3, and 230-4, which are turned off in the idle mode, are not stressed in the idle mode. This results in asymmetric aging, in which the transistors 230-1, 225-2, 230-3, and 225-4, which are stressed in the idle mode, age faster than the transistors 225-1, 230-2, 225-3, and 230-4, which are not stressed in the idle mode.

[0029] In this example, the asymmetric aging shifts the threshold voltage of the transistors 230-1, 225-2, 230-3, and 225-4, which are stressed in the idle mode, resulting in an increase in the fall edge delay at the output of the clock path 120 relative to the rise edge delay at the output of the clock path 120. The increase in the fall edge delay relative to the rise edge delay results in a duty cycle shift in the clock path 120. Figure 2C An example of the duty cycle shift is illustrated in the timing diagram shown. In the example shown, the clock signal 250, which has a 50% duty cycle, is input to the clock path 120 in the active mode. Figure 2C In the example shown, the clock signal 250, which has a 50% duty cycle, is input to the clock path 120 in the active mode. Figure 2C The clock signal 260 at the output of the clock path 120 after propagating through the clock path 120 is also shown. The clock path 120 delays the rise edge of the clock signal 250 by a delay T r , and delays the fall edge of the clock signal 250 by a delay T f . As shown, Figure 2C due to the asymmetric aging, the delay T f of the fall edge is longer than the delay T r of the rise edge. In this example, the longer delay of the fall edge results in an increase in the duty cycle of the clock signal 260 at the output of the clock path 120 (i.e., results in a duty cycle greater than 50%).

[0030] InFigure 2B and Figure 2C In the example illustrated, the input to the clock path 120 is high in idle mode. Asymmetric aging can occur for cases where the input to the clock path 120 is low in idle mode as well. In this regard, Figure 2D An example is shown in which the input to the clock path is high (i.e., logic 1) in idle mode. Figure 2D The logic state at the input and output of each of the clock buffers 220-1 through 220-4 is also shown. In this example, the output of the clock path 120 is high (i.e., logic 1) in idle mode. In this example, transistors 225-1, 230-2, 225-3, and 230-4 are on in idle mode, and transistors 230-1, 225-2, 230-3, and 225-4 are off in idle mode. In Figure 2D In the example shown in FIG. 2B, transistors 225-1, 230-2, 225-3, and 230-4, which are on in idle mode, are shown in bold. Transistors 225-1, 230-2, 225-3, and 230-4, which are on in idle mode, are stressed in idle mode, while transistors 230-1, 225-2, 230-3, and 225-4, which are off in idle mode, are not stressed in idle mode, which results in asymmetric aging in which transistors 225-1, 230-2, 225-3, and 230-4, which are stressed in idle mode, age faster than transistors 230-1, 225-2, 230-3, and 225-4.

[0031] In this example, the asymmetric aging shifts the threshold voltage of transistors 225-1, 230-2, 225-3, and 230-4, which are stressed in idle mode, resulting in an increase in the rise delay at the output of the clock path 120 relative to the fall delay at the output of the clock path 120. The increase in the rise delay relative to the fall delay results in a duty cycle shift in the clock path 120. Figure 2E An example of the duty cycle shift is illustrated in the timing diagram shown. In Figure 2E In the example shown, a clock signal 250 having a 50% duty cycle is input to the clock path 120 in active mode. Figure 2E The clock signal 270 at the output of the clock path 120 after propagating through the clock path 120 is also shown. The clock path 120 delays the rise of the clock signal 250 by a delay T r and delays the fall of the clock signal 250 by a delay T f . As Figure 2E shown, due to the asymmetric aging, the delay T rDelay T longer than falling edge f In this example, the longer delay of the rising edge causes the duty cycle of the clock signal 270 at the output of the clock signal to decrease (i.e., to result in a duty cycle that is less than 50%).

[0032] Accordingly, asymmetric aging in the idle mode can cause a duty cycle shift (i.e., a duty cycle degradation) to occur over time. Whether the duty cycle shift raises or lowers the duty cycle depends on, for example, whether the input of the clock path 120 is parked at a low or high value in the idle mode and / or the number of clock buffers in the clock path 120. The duty cycle shift can cause timing problems to occur in the circuit 130. For examples in which the circuit 130 includes sequential logic, the duty cycle shift can cause setup time and / or hold time violations.

[0033] To address the duty cycle shift (i.e., degradation) due to asymmetric aging, the system can employ duty cycle correction. In this regard, Figure 3 An example of a system 310 with duty cycle correction is shown in accordance with certain aspects. In this example, the system 310 includes the clock generator 115, the clock path 120, the circuit 130, and the clock gating circuit 140 discussed above. For duty cycle correction, the system 310 also includes a duty cycle monitor 320, a control circuit 330, and a duty cycle regulator 340.

[0034] The duty cycle monitor 320 has an input 322 and an output 324. In Figure 3 In the example of FIG. 3, the input 322 of the duty cycle monitor 320 is coupled to the output of the clock path 120. The duty cycle monitor 320 is configured to receive the clock signal at the input 322, measure one or more parameters of the clock signal that are related to the duty cycle of the clock signal, and output a measurement signal at the output 324 that indicates the one or more measured parameters. Examples of the measured parameters are provided below in accordance with certain aspects. The duty cycle monitor 320 can also be referred to as a duty cycle detector, a duty cycle measurement circuit, or another term.

[0035] The duty cycle regulator 340 has a clock input 342, a control input 346, and a clock output 344. The clock input 342 is coupled to the clock generator 115 (e.g., via the clock gating circuit 140 in active mode) and the clock output 344 is coupled to the input of the clock path 120. The duty cycle regulator 340 is configured to receive a clock signal at the clock input 342 and a control signal at the control input 346. The control signal is provided by the control circuit 330, as discussed further below. The duty cycle regulator 340 is configured to adjust the duty cycle of the clock signal based on the control signal and output the duty cycle adjusted clock signal at the output 344. The duty cycle regulator 340 can also be referred to as a clock shaper, a duty cycle shifter, or another term.

[0036] The control circuit 330 has an input 332 and an output 334. The input 332 of the control circuit 330 is coupled to the output 324 of the duty cycle monitor 320 and the output 334 of the control circuit 330 is coupled to the control input 346 of the duty cycle regulator 340. The control circuit 330 is configured to receive a measurement signal from the duty cycle monitor 320 indicative of one or more measured parameters via the input 332. As discussed above, the one or more measured parameters are related to the duty cycle of the clock signal at the output of the clock path 120 and thus provide information to the control circuit 330 about the duty cycle of the clock signal at the output of the clock path 120.

[0037] The control circuit 330 is configured to determine a duty cycle correction for the clock signal based on the one or more measured parameters and generate a control signal based on the determined duty cycle correction. The control circuit 330 outputs the generated control signal to the control input 346 of the duty cycle regulator 340, which adjusts the duty cycle of the clock signal based on the control signal. The control signal causes the duty cycle regulator 340 to adjust (i.e., shift) the duty cycle of the clock signal in a direction that compensates for the duty cycle shift caused by the clock path 120.

[0038] Thus, in this example, the duty cycle monitor 320 monitors the duty cycle of the clock signal at the output of the clock path 120 and the control circuit 330 causes the duty cycle regulator 340 to adjust the duty cycle of the clock signal based on the monitored duty cycle to correct for the duty cycle shift caused by the clock path 120. In certain aspects, the duty cycle correction can be performed each time the system 310 is started up.

[0039] Various circuits have been developed to implement the duty cycle monitor 320. In one method, the duty cycle monitor 320 uses beat frequency detection to calculate the duty cycle shift of the clock signal due to aging (also known as stress) in the clock path 120. In this method, the duty cycle monitor 320 includes generating a clock signal with a frequency of F. ref The reference oscillator is a reference signal with a reference frequency. The duty cycle monitor 320 uses a counter to count the number of cycles of the reference signal in one beat cycle to generate a count value. One beat cycle is equal to 1 / F. 拍 , where F 拍 It is the frequency of the reference signal (i.e., F). ref The duty cycle is the difference between the clock signal frequency and the clock signal frequency. To determine the duty cycle shift of the clock signal due to aging, the duty cycle monitor 320 generates a count value before aging and a count value after aging. Then, the control circuit 330 calculates the duty cycle shift based on the count value before aging, the count value after aging, the clock signal frequency, and the propagation delay of the clock path 120 before aging.

[0040] However, this method has several drawbacks. First, it requires memory (e.g., Efuse memory) to record the count values ​​before aging. Second, it requires knowledge of the clock signal frequency to calculate the duty cycle shift. The clock signal frequency may not be precisely known and / or may vary due to process angles, which negatively impacts the ability of the control circuit 330 to accurately calculate the duty cycle shift of the clock signal.

[0041] Figure 4A An example of a system 410 including an exemplary duty cycle monitor 420 is shown, which overcomes one or more of the disadvantages of the duty cycle monitor 320 discussed above. The duty cycle monitor 420 has an input 422 and an output 424. Figure 4A In the example shown, the duty cycle monitor 420 includes a first oscillator 425, a flip-flop 430 (e.g., a D flip-flop), a first counter 440, a second counter 450, and a readout circuit 460. The first oscillator 425 is configured to generate a frequency F at a reference frequency F. ref The reference signal for oscillation is output at the output terminal 427 of the first oscillator 425. In this respect, the first oscillator 425 can also be referred to as the reference oscillator. The duty cycle monitor 420 is further discussed below in certain aspects.

[0042] In this example, the system 410 also includes the clock path 120, the duty cycle adjuster 340, the control circuit 330, the circuit 130, and the clock generator 115 discussed above. The system 410 also includes a first selection circuit 470, a second selection circuit 480, and a second oscillator 465. The second oscillator 465 is configured to generate a test clock signal having a frequency that is close to a reference frequency F ref , and to output the test clock signal at an output 467 of the second oscillator 465. For example, the frequency of the test clock signal can be within 5% of the reference frequency F ref , i.e., between 0.95 F ref and 1.05 F ref . As discussed further below, bringing the frequency of the test clock signal close to the reference frequency improves the resolution of the duty cycle monitor 420. Each of the first oscillator 425 and the second oscillator 465 can be implemented with a respective ring oscillator or another type of oscillator.

[0043] The first selection circuit 470 has a first input 472 coupled to the clock generator 115, a second input 474 coupled to the output 467 of the second oscillator 465, an output 476 coupled to the input 342 of the duty cycle adjuster 340, and a selection input 478. The first selection circuit 470 is configured to receive a selection signal at the selection input 478, select the first input 472 or the second input 474 based on the selection signal, and couple the selected one of the first input 472 and the second input 474 to the output 476. The selection signal can be from the control circuit 330 or another control circuit. The first selection circuit 470 can be implemented with a multiplexer.

[0044] The second selection circuit 480 has an input 482 coupled to the clock path 120, a first output 484 coupled to the circuit 130, a second output 486 coupled to the input 422 of the duty cycle monitor 420, and a selection input 488. In this example, the clock path 120 is coupled between the output 344 of the duty cycle adjuster 340 and the input 482 of the second selection circuit 480. The second selection circuit 480 is configured to receive a selection signal at the selection input 478, select the first output 484 or the second output 486 based on the selection signal, and couple the input 482 to the selected one of the first output 484 and the second output 486.

[0045] In the example of Figure 4A , the input 332 of the control circuit 330 is coupled to the output 424 of the duty cycle monitor 420. The output 334 of the control circuit 330 is coupled to the control input 346 of the duty cycle adjuster 340, as discussed above with reference to Figure 3The discussion. Although Figure 4A Although not explicitly shown, control circuit 330 may be coupled to selection inputs 478 and 488 of selection circuits 470 and 480 to control selection of selection circuits 470 and 480.

[0046] According to certain aspects, selection circuits 470 and 480 allow system 410 to switch between task mode and test mode. In task mode, control circuit 330 causes first selection circuit 470 to select first input terminal 472 and causes second selection circuit 480 to select first output terminal 484. Thus, first selection circuit 470 couples clock generator 115 to duty cycle regulator 340, and second selection circuit 480 couples clock path 120 to circuit 130. This allows the clock signal generated by clock generator 115 (e.g., PLL) to propagate to circuit 130 via duty cycle regulator 340 and clock path 120. As discussed above, duty cycle regulator 340 can adjust the duty cycle of the clock signal to correct duty cycle shift in clock path 120 due to aging. As further discussed below, in test mode, the duty cycle adjustment used to correct duty cycle shift is determined. Test mode and task mode may also be referred to as first mode and second mode, respectively.

[0047] although Figure 4A Although not explicitly shown, it should be understood that system 410 may include one or more clock gating circuits (e.g., clock gating circuit 140) at one or more locations between clock generator 115 and circuit 130 to gate the clock signal when circuit 130 is inactive. When the circuit is active, the one or more clock gating circuits pass the clock signal from clock generator 115 to circuit 130.

[0048] In the test mode, the control circuit 330 causes the first selection circuit 470 to select the second input 474 and causes the second selection circuit 480 to select the second output 486. Thus, the first selection circuit 470 couples the output 467 of the second oscillator 465 to the duty cycle adjuster 340 and the second selection circuit 480 couples the clock path 120 to the input 422 of the duty cycle monitor 420. This allows the test clock signal generated by the second oscillator 465 to propagate to the input 422 of the duty cycle monitor 420 via the duty cycle adjuster 340 and the clock path 120. As the test clock signal propagates through the clock path 120 to the duty cycle monitor 420, the duty cycle of the test clock signal is shifted by the clock path 120. This allows the control circuit 330 to determine the duty cycle shift caused by the clock path 120 based on the measurement of the test clock signal by the duty cycle monitor 420, as discussed further below. For examples in which the system 410 includes the one or more clock gating circuits (not shown), the one or more clock gating circuits can pass the test clock signal in the test mode.

[0049] The duty cycle monitor 420 will now be discussed in accordance with certain aspects. In Figure 4A In examples in which the trigger 430 is a D flip-flop, the signal input 434 is also referred to as the D input. In examples in which the trigger 430 is a D flip-flop, the signal input 434 is coupled to the input 422 of the duty cycle monitor 420 and thus receives the test clock signal in the test mode. In examples in which the trigger 430 is a D flip-flop, the clock input 432 is coupled to the output 427 of the first oscillator 425 and thus receives the reference signal from the first oscillator 425.

[0050] In certain aspects, the trigger 430 is configured to latch the logic state of the test clock signal at the signal input 434 on each rising edge of the reference signal (for a positive edge triggered implementation of the trigger 430) or on each falling edge of the reference signal (for a negative edge triggered implementation of the trigger 430) and output the latched logic state at the output 436. This results in the trigger 430 outputting a signal at the output 436 having a frequency approximately equal to the difference between the frequency of the reference signal and the frequency of the test clock signal. In certain aspects, the frequency of the test clock signal is close to the frequency of the reference signal (e.g., within 5% of the frequency of the reference signal). As discussed further below, bringing the frequency of the test clock signal close to the frequency of the reference signal increases the resolution of the duty cycle monitor 420. The output signal of the trigger 430 is used to measure the duty cycle of the test clock signal, as discussed further below.

[0051] In Figure 4AIn the example of FIG. 4, the first counter 440 has a count input 442, a count output 446, and an enable input 444. The count input 442 is coupled to the output 427 of the first oscillator 425 and thus receives the reference signal from the first oscillator 425. The enable input 444 is coupled to the output 436 of the flip-flop 430 and thus receives the output signal of the flip-flop 430. The count output 446 is coupled to a first input 462 of the readout circuit 460. In certain aspects, the first counter 440 is configured to count cycles of the reference signal to generate a count value when the output signal at the enable input 444 is at a high (i.e., logic 1) and output the count value at the count output 446. For example, the first counter 440 can increment the count value on each rising edge of the reference clock signal when the enable input 444 is at a high (i.e., logic 1). As discussed further below, the count value from the first counter 440 is used to measure a high phase of the test clock signal, where the high phase is a duration of time in which the test clock signal is at a high during each cycle of the test clock signal.

[0052] In Figure 4A In the example of FIG. 4, the first counter 440 has a count input 442, a count output 446, and an enable input 444. The count input 442 is coupled to the output 427 of the first oscillator 425 and thus receives the reference signal from the first oscillator 425. The enable input 444 is coupled to the output 436 of the flip-flop 430 and thus receives the output signal of the flip-flop 430. The count output 446 is coupled to a first input 462 of the readout circuit 460. In certain aspects, the first counter 440 is configured to count cycles of the reference signal to generate a count value when the output signal at the enable input 444 is at a high (i.e., logic 1) and output the count value at the count output 446. For example, the first counter 440 can increment the count value on each rising edge of the reference clock signal when the enable input 444 is at a high (i.e., logic 1). As discussed further below, the count value from the first counter 440 is used to measure a high phase of the test clock signal, where the high phase is a duration of time in which the test clock signal is at a high during each cycle of the test clock signal. Figure 4B Alternative implementations of the second counter 450 are discussed below with reference to

[0053] Example operations of the duty cycle monitor 420 will now be discussed according to certain aspects with reference to Figure 5 FIG. 5. Figure 5 is a timing diagram showing an example of the test clock signal (labeled “Clk”), the reference signal (labeled “Ref”), and the output signal (labeled “Q”) of the flip-flop 430. In Figure 5In the example, trigger 430 is implemented using a positive-edge triggered trigger. However, it should be understood that this disclosure is not limited to this example, as discussed below.

[0054] exist Figure 5 In the example, the rising edge of the reference signal sweeps across the high-order phase of the test clock signal, where for each cycle of the reference clock signal, the rising edge of the reference signal is shifted by ΔT relative to the test clock signal, where ΔT is the period of the test clock signal (denoted as "Tclk") and the period of the reference signal (denoted as "T"). ref The difference between ") and ". Figure 5 As shown, when the rising edge of the reference signal sweeps through the high-order phase of the test clock signal, the output signal (labeled "Q") of the flip-flop 430 is at the high-order position.

[0055] exist Figure 5 In the example, the first counter 440 counts the number of cycles of the reference clock signal in which the output signal of the flip-flop 430 is in the high position, obtaining a count value M. Therefore, in this example, the rising edge of the reference signal needs M cycles of the reference signal to sweep through the high-order phase of the test clock signal. Since the rising edge of the reference signal shifts by ΔT relative to the test clock signal for each cycle of the reference clock signal, the rising edge of the reference signal is shifted by M·ΔT to sweep through the high-order phase of the test clock signal. Therefore, the high-order phase of the test clock signal is approximately equal to M·ΔT. Thus, the count value M from the first counter 440 provides a measure of the high-order phase of the test clock signal. As discussed above, the high-order phase is the duration during which the test clock signal is in the high position in each cycle of the test clock signal. The resolution of the high-order phase measurement depends on the magnitude of the shift ΔT. The smaller the shift ΔT, the higher the resolution. A small shift ΔT is achieved by making the frequency of the test clock signal close to the frequency of the reference signal.

[0056] exist Figure 5 In the example, the rising edge of the reference signal also sweeps across the low-order phase of the test clock signal, where for each cycle of the reference clock signal, the rising edge of the reference signal is shifted by ΔT relative to the test clock signal. For example... Figure 5 As shown, when the rising edge of the reference signal sweeps through the low-order phase of the test clock signal, the output signal (labeled "Q") of the flip-flop 430 is at the low-order position.

[0057] exist Figure 5In the example of FIG. 4, the second counter 450 counts the number of periods of the reference clock signal in which the output signal of the flip-flop 430 is low, resulting in a count value N. Thus, in this example, it takes N periods of the reference clock signal for the rising edge of the reference clock signal to sweep through the low phase of the test clock signal. Since for each period of the reference clock signal, the rising edge of the reference signal is shifted by AT relative to the test clock signal, the rising edge of the reference signal is shifted by N-AT to sweep through the low phase of the test clock signal. Thus, the low phase of the test clock signal is approximately equal to N-AT. Accordingly, the count value N from the second counter 450 provides a measure of the low phase of the test clock signal. As discussed above, the low phase is the duration of time during which the test clock signal is low during each period of the test clock signal. The resolution of the low phase measurement depends on the size of the shift AT. The smaller the shift AT, the higher the resolution. A small shift AT is achieved by making the frequency of the test clock signal close to the frequency of the reference signal.

[0058] In Figure 5 In the example of FIG. 4, the flip-flop 430 is implemented with a positive edge triggered flip-flop. However, it should be understood that the present disclosure is not limited to this example. In another example, the flip-flop 430 can be implemented with a negative edge triggered flip-flop. In this example, the first counter 440 provides the M count value by counting the number of periods of the reference signal needed for the falling edge of the reference signal to sweep through the high phase of the test clock signal. Additionally, in this example, the second counter 450 provides the N count value by counting the number of periods of the reference signal needed for the falling edge of the reference signal to sweep through the low phase of the test clock signal. Thus, the flip-flop 430 can be positive edge triggered or negative edge triggered.

[0059] The count value M from the first counter 440 and the count value N from the second counter 450 can be used to determine the duty cycle of the test clock signal. The duty cycle of the test clock signal is given by:

[0060]

[0061] where T H is the high phase of the test clock signal, and T L is the low phase of the test clock signal. Substituting M-AT for the high phase and N-AT for the low phase in equation (1) results in:

[0062]

[0063] By canceling AT, this equation can be simplified to:

[0064]

[0065] Accordingly, the count value M from the first counter 440 and the count value N from the second counter 450 allow determination of the duty cycle of the test clock signal. In certain aspects, the duty cycle shift of the test clock signal can be given by:

[0066]

[0067] where DC 目标 is a target duty cycle (e.g., 0.5). In these aspects, the target duty cycle can be a desired duty cycle at the output of the clock path 120.

[0068] In certain aspects, the readout circuit 460 is configured to receive the count value M from the first counter 440 and the count value N from the second counter 450 via inputs 462 and 464, and output the count values M and N to the control circuit 330 via output 424. The control circuit 330 can use the count values M and N to estimate the duty cycle shift caused by the clock path 120 and determine a correction for the duty cycle shift. Since the test clock signal propagates through the clock path 120 to reach the duty cycle monitor 420, the duty cycle of the test clock signal is shifted by the clock path 120 before reaching the duty cycle monitor 420. Accordingly, the duty cycle of the test clock signal (as measured using the count values M and N) allows the control circuit 330 to determine (e.g., based on equation (3) or (4)) an appropriate correction for the duty cycle shift caused by the clock path 120. The control circuit 330 can then generate a control signal based on the determined duty cycle correction and output the control signal to the control input 346 of the duty cycle adjuster 340 to perform the correction. As discussed above, the duty cycle adjuster 340 corrects for the duty cycle shift caused by the clock path 120 by shifting the duty cycle of the clock signal in a direction that compensates for the duty cycle shift caused by the clock path 120. For example, the control circuit 330 can estimate the duty cycle shift caused by the clock path 120 using the count values M and N (e.g., based on equation (4)) and generate a control signal that causes the duty cycle adjuster 340 to apply an opposite duty cycle shift to the clock signal to correct for the duty cycle shift caused by the clock path 120.

[0069] The duty cycle monitor 420 has one or more advantages. For example, the duty cycle monitor 420 does not need to record the count value before burn-in and thus eliminates the need for memory (e.g., Efuse memory) to store the count value before burn-in. Additionally, the duty cycle monitor 420 does not need to know accurately the frequency of the test clock signal or the frequency of the reference signal to calculate the duty cycle of the test clock signal. For example, as shown in equation (3), the duty cycle can be determined from the count value M and the count value N from the counters 440 and 450.

[0070] In certain aspects, the first oscillator 425 and the second oscillator 465 are implemented with similar structures and integrated on the same chip. For example, each of the first oscillator 425 and the second oscillator 465 can be implemented with a ring oscillator, a PLL, etc. Since the first oscillator 425 and the second oscillator 465 have similar structures and are integrated on the same chip in this example, the frequency of the test clock signal and the frequency of the reference signal are affected in a similar manner across process corners. In other words, due to process variations, the frequency of the reference signal varies following the variations of the frequency of the test clock signal. This allows the frequency of the reference signal to remain close to the frequency of the test clock signal across process corners to keep AT small and maintain the high resolution of the duty cycle monitor 420 across process corners.

[0071] Figure 4B Another example implementation for generating the count value N is shown in accordance with certain aspects. In this example, Figure 4A The output 436 includes a first output 436-1 and a second output 436-2, where the first output 436-1 (labeled “Q”) is coupled to the enable input 444 of the first counter 440 and the second output 436-2 (labeled “Qb”) is coupled to the enable input 454 of the second counter 450. The flip-flop 430 outputs the output signal discussed above at the first output 436-1 and outputs an inversion (i.e., a complementary signal) of the output signal at the second output 436-2 (i.e., the outputs 436-1 and 436-2 are complementary). In this example, the enable input 444 of the first counter 440 receives the output signal discussed above, and operates in the same manner as discussed above with reference to Figure 4A .

[0072] The enable input 454 of the second counter 450 receives the inverted output signal. In this example, the second counter 450 is configured to count the cycles of the reference signal when the inverted output signal is at a high to generate the count value N. Since the inverted output signal (labeled “Qb”) is at a high when the output signal (labeled “Q”) is at a low, this is equivalent to counting the cycles of the reference signal when the output signal (labeled “Q”) is at a low to generate the count value N. Thus, the count value N in this example is the same as the count value N in the example of Figure 4A . Figure 5 This is illustrated in

[0073] It should be appreciated that in alternative implementations, Figure 4BThe first counter 440 and the second counter 450 in FIG. 4 can each be enabled when the respective enable inputs 444 and 454 are low instead of high. In this case, the first counter 440 can generate a count value N and the second counter 450 can generate a count value M. Thus, it should be understood that the present disclosure is not limited to the specific implementation of the flip-flop 430 and the counters 440 and 450 for generating the count values N and M.

[0074] Figure 6 An example implementation of the readout circuit 460 is shown in accordance with certain aspects. In this example, the readout circuit 460 includes a first readout latch 610 and a second readout latch 620. Additionally, in this example, the readout circuit 460 has a first output 466-1 coupled to the first output 424-1 of the duty cycle monitor 420 and a second output 466-2 coupled to the second output 424-2 of the duty cycle monitor 420. The outputs 424-2 and 424-2 are coupled to the input 332 of the control circuit 330. As discussed further below, the count value M is output from the first output 424-1 to the control circuit 330 and the count value N is output from the second output 424-2 to the control circuit 330. Each of the readout latches 610 and 620 can be implemented with a D flip-flop or another type of latch.

[0075] The first readout latch 610 has a data input 614, a clock input 612, and an output 616. The data input 614 is coupled to the output 446 of the first counter 440 to receive the count value M. In certain aspects, the count value M is a plurality of bits and the first readout latch 610 is a multi-bit latch (i.e., a latch capable of latching a multi-bit value). The clock input 612 of the first readout latch 610 is coupled to the first output 436-1 of the flip-flop 430 to receive the output signal (labeled “Q”) of the flip-flop 430.

[0076] In operation, the first readout latch 610 is configured to latch the count value M from the output 446 of the first counter 440 on a falling edge 510 of the output signal (labeled “Q”) from the flip-flop 430, as shown in FIG. 5. As shown in FIG. 5, when the output signal transitions from high to low, the falling edge 510 of the output signal occurs. Thus, the latched count value M indicates the number of reference periods counted by the first counter 440 during the time the output signal was high. The first readout latch 610 outputs the latched count value M to the control circuit 330 via the first output 466-1. Figure 5 Figure 5 In operation, the first readout latch 610 is configured to latch the count value M from the output 446 of the first counter 440 on a falling edge 510 of the output signal (labeled “Q”) from the flip-flop 430, as shown in FIG. 5. As shown in FIG. 5, when the output signal transitions from high to low, the falling edge 510 of the output signal occurs. Thus, the latched count value M indicates the number of reference periods counted by the first counter 440 during the time the output signal was high. The first readout latch 610 outputs the latched count value M to the control circuit 330 via the first output 466-1.

[0077] ​The second read latch 620 has a data input 624, a clock input 622, and an output 626. The data input 624 is coupled to the output 456 of the second counter 450 to receive the count value N. In certain aspects, the count value N is a plurality of bits and the second read latch 620 is a multi-bit latch. The clock input 622 of the second read latch 620 is coupled to the second output 436-2 of the flip-flop 430 to receive the inverted output signal (labeled "Qb") of the flip-flop 430.

[0078] In operation, the second read latch 620 is configured to latch the count value N from the output 456 of the second counter 450 on a falling edge 520 of the inverted output signal (labeled "Qb") from the flip-flop 430, as shown by way of example in Figure 5 The second read latch 620 outputs the latched count value N to the control circuit 330 via the second output 466-2.

[0079] In Figure 6 the example, each of the first read latch 610 and the second read latch 620 is a falling edge triggered latch (also referred to as a negative edge triggered latch). However, it should be understood that the present disclosure is not limited to this example.

[0080] Figure 7 A method 700 of duty cycle monitoring according to certain aspects is illustrated.

[0081] At block 710, a clock signal and a reference signal are received. For example, the clock signal can correspond to the test clock signal from the second oscillator 465 and the reference signal can correspond to the reference signal from the first oscillator 425. In certain aspects, the reference signal is an oscillating signal and the frequency of the clock signal is within 5% of the frequency of the reference signal.

[0082] At block 720, the clock signal is input to a signal input of a flip-flop. For example, the clock signal can be input to the signal input 434 of the flip-flop 430. The signal input 434 can also be referred to as a D input.

[0083] At block 730, the reference signal is input to a clock input of the flip-flop. For example, the reference signal can be input to the clock input 432 of the flip-flop 430.

[0084] At block 740, a number of cycles of the reference signal in which an output of the flip-flop is in a high state is counted to generate a first count value. For example, the number of cycles of the reference signal in which the output of the flip-flop is in a high state can be counted by the first counter 440. The first count value can correspond to the count value M. The output of the flip-flop can correspond to the output 436 of the flip-flop 430.

[0085] At block 750, a number of cycles of the reference signal in which the output of the flip-flop is low is counted to generate a second count value. For example, the number of cycles of the reference signal in which the output of the flip-flop is low can be counted by the second counter 450. The second count value can correspond to the count value N.

[0086] In certain aspects, a duty cycle of the clock signal is determined based on the first count value and the second count value. For example, the control circuit 330 can determine the duty cycle based on equation (3).

[0087] In certain aspects, a duty cycle shift of a duty cycle adjuster can be controlled based on the determined duty cycle. For example, the duty cycle adjuster can correspond to the duty cycle adjuster 340, and the duty cycle shift of the duty cycle adjuster can be controlled by the control circuit 330 based on the determined duty cycle.

[0088] In certain aspects, the output of the flip-flop includes a first output and a second output, where the first output and the second output are complementary. For example, the first output can correspond to the first output 436-1 and the second output can correspond to the second output 436-2. In these aspects, counting a number of cycles of the reference signal in which the output of the flip-flop is high can include counting a number of cycles of the reference signal in which the first output of the flip-flop is high or low, and counting a number of cycles of the reference signal in which the output of the flip-flop is low can include counting a number of cycles of the reference signal in which the second output of the flip-flop is high or low.

[0089] It will be appreciated that the outputs disclosed herein can include a single output or multiple parallel outputs. For example, the count outputs 446 and 456 of each of the counters 440 and 450 can include a single serial output or multiple parallel outputs (e.g., to output bits of the respective count values in parallel). Similarly, the inputs disclosed herein can include a single input or multiple parallel inputs.

[0090] The control circuit 330 can be implemented with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. The processor can perform the functions described herein by executing software comprising code for performing the functions described herein. The software can be stored on a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and / or a magnetic disk.

[0091] Particular embodiments are described in the following numbered clauses:

[0092] 1. A system comprising:

[0093] a duty cycle monitor comprising:

[0094] a first oscillator having an output;

[0095] a flip-flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty cycle monitor and the clock input is coupled to the output of the first oscillator;

[0096] a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the output of the first oscillator and the enable input of the first counter is coupled to the output of the flip-flop; and

[0097] a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the output of the first oscillator and the enable input of the second counter is coupled to the output of the flip-flop.

[0098] 2. The system of clause 1, wherein:

[0099] the first counter is enabled when the enable input of the first counter is high; and

[0100] the second counter is enabled when the enable input of the second counter is low.

[0101] 3. The system of clause 1, wherein:

[0102] the output of the flip-flop comprises a first output and a second output, wherein the first output and the second output are complementary;

[0103] the enable input of the first counter is coupled to the first output of the flip-flop; and

[0104] the enable input of the second counter is coupled to the second output of the flip-flop.

[0105] 4. The system of clause 3, wherein:

[0106] the first counter is enabled when the enable input of the first counter is high; and

[0107] The second counter is enabled when the enable input of the second counter is high.

[0108] 5. The system of clause 3, wherein:

[0109] The first counter is enabled when the enable input of the first counter is low; and

[0110] The second counter is enabled when the enable input of the second counter is low.

[0111] 6. The system of any one of clauses 1-5, wherein the duty cycle monitor further comprises a readout circuit coupled to the count output of the first counter and the count output of the second counter.

[0112] 7. The system of clause 6, wherein the readout circuit comprises:

[0113] a first readout latch having a data input, a clock input, and an output, wherein the data input of the first readout latch is coupled to the count output of the first counter, the clock input of the first readout latch is coupled to the output of the flip-flop, and the output of the first readout latch is coupled to a first output of the duty cycle monitor; and

[0114] a second readout latch having a data input, a clock input, and an output, wherein the data input of the second readout latch is coupled to the count output of the second counter, the clock input of the second readout latch is coupled to the output of the flip-flop, and the output of the second readout latch is coupled to a second output of the duty cycle monitor.

[0115] 8. The system of clause 7, wherein:

[0116] the output of the flip-flop comprises a first output and a second output, wherein the first output and the second output are complementary;

[0117] the clock input of the first readout latch is coupled to the first output of the flip-flop; and

[0118] the clock input of the second readout latch is coupled to the second output of the flip-flop.

[0119] 9. The system of any one of clauses 1-8, further comprising:

[0120] a second oscillator having an output;

[0121] a clock path coupled between the output of the second oscillator and the input of the duty cycle monitor.

[0122] 10. The system of clause 9, wherein the clock path comprises a clock buffer coupled in series.

[0123] 11. The system of clause 9 or 10, wherein a frequency of the second oscillator is within 5% of a frequency of the

[0124] first oscillator.

[0125] 12. The system of any of clauses 9-11, further comprising a duty cycle adjuster coupled between the output of the second oscillator and the clock path.

[0126] 13. The system of clause 12, further comprising a control circuit coupled between the duty cycle monitor and the duty cycle adjuster.

[0127] 14. The system of any of clauses 1-8, further comprising:

[0128] a second oscillator having an output;

[0129] a clock generator;

[0130] a first selection circuit having a first input, a second input, and an output, wherein the first input is coupled to the output of the second oscillator and the second input is coupled to the clock generator;

[0131] a second selection circuit having an input, a first output, and a second output, wherein the first output is coupled to the input of the duty cycle monitor and the second output is coupled to at least one of sequential logic, a processor, and a memory; and

[0132] a clock path coupled between the output of the first selection circuit and the input of the second selection circuit.

[0133] 15. The system of clause 14, wherein a frequency of the second oscillator is within 5% of a frequency of the first oscillator.

[0134] 16. The system of clause 14 or 15, further comprising a duty cycle adjuster coupled between the output of the first selection circuit and the clock path.

[0135] 17. The system of clause 16, further comprising a control circuit coupled between the duty cycle monitor and the duty cycle adjuster.

[0136] 18. The system of any of clauses 14-17, wherein:

[0137] in a first mode, the first selection circuit is configured to select the first input and the second selection circuit is configured to select the first output; and

[0138] in a second mode, the first selection circuit is configured to select the second input and the second selection circuit is configured to select the second output.

[0139] 19. A method of duty cycle monitoring, the method comprising:

[0140] receiving a clock signal and a reference signal;

[0141] inputting the clock signal to a signal input of a flip-flop;

[0142] inputting the reference signal to a clock input of the flip-flop;

[0143] counting a number of cycles of the reference signal in which an output of the flip-flop is high to generate a first count value; and

[0144] counting a number of cycles of the reference signal in which the output of the flip-flop is low to generate a second count value.

[0145] 20. The method of clause 19, wherein the reference signal is an oscillating signal and a frequency of the clock signal is within 5% of a frequency of the reference signal.

[0146] 21. The method of clause 19 or 20, further comprising determining a duty cycle of the clock signal based on the first count value and the second count value.

[0147] 22. The method of clause 21, further comprising controlling a duty cycle shift of a duty cycle adjuster based on the determined duty cycle.

[0148] 23. The method of clause 22, wherein:

[0149] receiving the clock signal includes receiving the clock signal from an output of a clock path; and

[0150] the duty cycle adjuster is coupled to an input of the clock path.

[0151] 24. The method of any of clauses 19-23, wherein:

[0152] the output of the flip-flop includes a first output and a second output;

[0153] the first output and the second output are complementary;

[0154] counting the number of the cycles of the reference signal in which the output of the flip-flop is high includes counting the number of the cycles of the reference signal in which the first output of the flip-flop is high or low; and

[0155] counting the number of the cycles of the reference signal in which the output of the flip-flop is low includes counting the number of the cycles of the reference signal in which the second output of the flip-flop is high or low.

[0156] Within the present disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to express either a direct or indirect electrical coupling between two structures.

[0157] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system for duty cycle monitoring, the system comprising: a duty cycle monitor, the duty cycle monitor comprising: a first oscillator having an output; a flip-flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty cycle monitor, and the clock input is coupled to the output of the first oscillator; a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the output of the first oscillator, and the enable input of the first counter is coupled to the output of the flip-flop; a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the output of the first oscillator, and the enable input of the second counter is coupled to the output of the flip-flop; a second oscillator having an output; and a clock path coupled between the output of the second oscillator and the input of the duty cycle monitor.

2. The system of claim 1, wherein: the first counter is enabled when the enable input of the first counter is high; and the second counter is enabled when the enable input of the second counter is low.

3. The system of claim 1, wherein: the output of the flip-flop comprises a first output and a second output, wherein the first output and the second output are complementary; the enable input of the first counter is coupled to the first output of the flip-flop; and the enable input of the second counter is coupled to the second output of the flip-flop.

4. The system of claim 3, wherein: the first counter is enabled when the enable input of the first counter is high; and the second counter is enabled when the enable input of the second counter is high.

5. The system of claim 3, wherein: the first counter is enabled when the enable input of the first counter is low; and the second counter is enabled when the enable input of the second counter is low.

6. The system of claim 1, wherein the duty cycle monitor further comprises a readout circuit coupled to the count output of the first counter and the count output of the second counter.

7. The system of claim 6, wherein the readout circuit comprises: a first read latch having a data input, a clock input, and an output, wherein the data input of the first read latch is coupled to the count output of the first counter, the clock input of the first read latch is coupled to the output of the flip-flop, and the output of the first read latch is coupled to a first output of the duty cycle monitor; and a second read latch having a data input, a clock input, and an output, wherein the data input of the second read latch is coupled to the count output of the second counter, the clock input of the second read latch is coupled to the output of the flip-flop, and the output of the second read latch is coupled to a second output of the duty cycle monitor.

8. The system of claim 7, wherein: the output of the flip-flop comprises a first output and a second output, wherein the first output and the second output are complementary; the clock input of the first read latch is coupled to the first output of the flip-flop; and the clock input of the second read latch is coupled to the second output of the flip-flop.

9. The system of claim 1, wherein the clock path comprises clock buffers coupled in series.

10. The system of claim 1, wherein a frequency of the second oscillator is within 5% of a frequency of the first oscillator.

11. The system of claim 1, further comprising a duty cycle adjuster coupled between the output of the second oscillator and the clock path.

12. The system of claim 11, further comprising a control circuit coupled between the duty cycle monitor and the duty cycle adjuster.

13. The system of claim 1, further comprising: a clock generator; a first selection circuit having a first input, a second input, and an output, wherein the first input is coupled to the output of the second oscillator and the second input is coupled to the clock generator; a second selection circuit having an input, a first output, and a second output, wherein the first output is coupled to the input of the duty cycle monitor and the second output is coupled to at least one of sequential logic, a processor, and a memory; and the clock path, further coupled between the output of the first selection circuit and the input of the second selection circuit.

14. The system of claim 13, wherein a frequency of the second oscillator is within 5% of a frequency of the first oscillator.

15. The system of claim 13, further comprising a duty cycle adjuster coupled between the output of the first selection circuit and the clock path.

16. The system of claim 15, further comprising a control circuit coupled between the duty cycle monitor and the duty cycle adjuster.

17. The system of claim 13, wherein: in a first mode, the first selection circuit is configured to select the first input and the second selection circuit is configured to select the first output; and in a second mode, the first selection circuit is configured to select the second input and the second selection circuit is configured to select the second output.

18. A method of duty cycle monitoring, the method comprising: receiving a clock signal and a reference signal; inputting the clock signal to a signal input of a flip-flop; inputting the reference signal to a clock input of the flip-flop; counting a number of cycles of the reference signal in which an output of the flip-flop is high to generate a first count value; and counting a number of cycles of the reference signal in which the output of the flip-flop is low to generate a second count value; wherein receiving the clock signal comprises receiving the clock signal from an output of a clock path, and wherein the clock path is coupled to an output of a second oscillator.

19. The method of claim 18, wherein the reference signal is an oscillating signal and a frequency of the clock signal is within 5% of a frequency of the reference signal.

20. The method of claim 18, further comprising determining a duty cycle of the clock signal based on the first count value and the second count value.

21. The method of claim 20, further comprising controlling a duty cycle shift of a duty cycle adjuster based on the determined duty cycle.

22. The method of claim 21, wherein: the duty cycle adjuster is coupled to an input of the clock path.

23. The method of claim 18, wherein: the output of the flip-flop comprises a first output and a second output; the first output and the second output are complementary; counting the number of cycles of the reference signal in which the output of the flip-flop is high comprises counting the number of cycles of the reference signal in which the first output of the flip-flop is high or low; and counting the number of cycles of the reference signal in which the output of the flip-flop is low comprises counting the number of cycles of the reference signal in which the second output of the flip-flop is high or low. ​ ​

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