Semiconductor device

Abstract

A semiconductor device (1) includes a transistor (10) formed in a first region (A1) of a semiconductor layer (40), a transistor (20) formed in a second region (A2) adjacent to the first region (A1) of the semiconductor layer (40), and a drain pad (151) formed in a third region (A3) that does not overlap the first region (A1) and the second region (A2) in a plan view. The first region (A1) and the second region (A2) are one side and the other side that bisect the semiconductor layer (40) excluding the third region (A3) in area in the plan view. The transistor (10) and the transistor (20) are arranged in a first direction in the plan view. A center of the third region (A3) is located on a straight central line (90) that bisects the semiconductor layer (40) in the first direction and is orthogonal to the first direction in the plan view. The drain pad (151) is surrounded in the third region (A3) in the plan view.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device of a chip size package type. BACKGROUND

[0002] A vertical MOS transistor of a dual structure is used for the purpose of preventing conduction before a lithium ion battery becomes overcharged and overdischarged, and in this vertical MOS transistor of a dual structure, since the current that flows at the time of charge and discharge is relatively large, reducing the on-resistance in the on state is particularly important.

[0003] However, in charge that starts when the lithium ion battery becomes in a state of overdischarge with the passage of time and the like, in consideration of safe use of the battery, it is desirable to flow a relatively small current to slowly start the charge. Therefore, if a path in which a relatively small current flows is attached to the vertical MOS transistor of a dual structure, it is convenient in the battery protection circuit.

[0004] (Prior Art Documents)

[0005] (Patent Documents)

[0006] Patent Document 1 Japanese Patent Application Publication No. 2021-005732 A SUMMARY

[0007] Problems to be Solved by the Invention

[0008] However, in the vertical MOS transistor of a dual structure, if the attached path is added in a limited device area, the conduction of the original charge and discharge current can be hindered.

[0009] Means for Solving the Problems

[0010] To solve the above problems, a semiconductor device according to one embodiment of the present disclosure is a flip chip mounted chip size package type semiconductor device including: a semiconductor substrate; a low concentration impurity layer formed on the semiconductor substrate; a first vertical MOS transistor formed in a first region of a semiconductor layer including the semiconductor substrate and the low concentration impurity layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a plurality of first source pads formed in the first region in the plan view and connected to first source electrodes of the first vertical MOS transistor; a first gate pad formed in the first region in the plan view and connected to a first gate electrode of the first vertical MOS transistor; a plurality of second source pads formed in the second region in the plan view and connected to second source electrodes of the second vertical MOS transistor; a second gate pad formed in the second region in the plan view and connected to a second gate electrode of the second vertical MOS transistor; and a metal layer formed in contact with a back surface of the semiconductor substrate, the semiconductor substrate being a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, the semiconductor layer being rectangular in the plan view, the first vertical MOS transistor and the second vertical MOS transistor being arranged in a first direction in the plan view, the semiconductor layer having a third region that does not overlap the first region and the second region in the plan view, the first region and the second region being one side and the other side that bisect the semiconductor layer excluding the third region in area in the plan view, a center of the third region being located on a center line that bisects the semiconductor layer in the first direction and is a straight line orthogonal to the first direction in the plan view, the semiconductor layer including one drain pad connected to the common drain region in the plan view, the drain pad being arranged in a manner surrounded in the third region in the plan view.

[0011] To solve the above problems, a semiconductor device according to one embodiment of the present disclosure is a flip chip mounted chip size package type semiconductor device including: a semiconductor substrate; a low concentration impurity layer formed on the semiconductor substrate; a first vertical MOS transistor formed in a first region of a semiconductor layer including the semiconductor substrate and the low concentration impurity layer; a second vertical MOS transistor formed in a second region that is a region adjacent to the first region in a plan view of the semiconductor layer; a plurality of first source pads formed in the first region in the plan view and connected to first source electrodes of the first vertical MOS transistor; a first gate pad formed in the first region in the plan view and connected to a first gate electrode of the first vertical MOS transistor; a first drain pad formed in the first region in the plan view and connected to a first drain electrode of the first vertical MOS transistor; a plurality of second source pads formed in the second region in the plan view and connected to second source electrodes of the second vertical MOS transistor; a second gate pad formed in the second region in the plan view and connected to a second gate electrode of the second vertical MOS transistor; a second drain pad formed in the second region in the plan view and connected to a second drain electrode of the second vertical MOS transistor; and a metal layer formed in contact with a back surface of the semiconductor substrate that is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, wherein the semiconductor layer is rectangular in the plan view, the first region and the second region are one side and the other side that bisects the semiconductor layer in area in the plan view, a midpoint of a line segment connecting a center of the first gate pad and a center of the second gate pad is located on a boundary line between the first region and the second region in the plan view, a midpoint of a line segment connecting a center of the first drain pad and a center of the second drain pad is located on the boundary line in the plan view, the plurality of first source pads are arranged such that no part thereof is sandwiched between the first gate pad and the first drain pad, and the plurality of second source pads are arranged such that no part thereof is sandwiched between the second gate pad and the second drain pad.

[0012] To solve the above problems, a semiconductor device according to one embodiment of the present disclosure is a flip chip mounted chip size package type semiconductor device including: a semiconductor substrate; a low concentration impurity layer formed on the semiconductor substrate; a first vertical MOS transistor formed in a first region of a semiconductor layer including the semiconductor substrate and the low concentration impurity layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a plurality of first source pads formed in the first region in the plan view and connected to first source electrodes of the first vertical MOS transistor; a first gate pad formed in the first region in the plan view and connected to a first gate electrode of the first vertical MOS transistor; a first drain pad formed in the first region in the plan view and connected to a first drain electrode of the first vertical MOS transistor; a plurality of second source pads formed in the second region in the plan view and connected to second source electrodes of the second vertical MOS transistor; a second gate pad formed in the second region in the plan view and connected to a second gate electrode of the second vertical MOS transistor; a second drain pad formed in the second region in the plan view and connected to a second drain electrode of the second vertical MOS transistor; and a metal layer formed in contact with a back surface of the semiconductor substrate, which is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, wherein the semiconductor layer is rectangular in the plan view, the first region and the second region are one side and the other side that bisects the semiconductor layer in area in the plan view, a midpoint of a line segment connecting a center of the first drain pad and a center of the second drain pad is located on a boundary line between the first region and the second region in the plan view, the plurality of first source pads are arranged such that at least a portion is sandwiched between the first drain pad and the boundary line in the plan view, and the plurality of second source pads are arranged such that at least a portion is sandwiched between the second drain pad and the boundary line in the plan view.

[0013] Effects of Invention

[0014] With the above configuration, in a bidirectional conduction double structure vertical MOS transistor, a relatively small current path can be added to the same device without interfering with the conduction of a relatively large current path.

[0015] Thus, the present disclosure enables the main path through which a relatively large current flows to be turned on as much as possible without being hindered, and enables the sub path through which a relatively small current flows to be attached to the same device. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a cross-sectional view illustrating one example of a configuration of the semiconductor device according to Embodiment 1.

[0017] Figure 2A is a plan view illustrating one example of a configuration of a pad of the semiconductor device according to Embodiment 1.

[0018] Figure 2B is a cross-sectional view illustrating a main current flowing in the semiconductor device according to Embodiment 1.

[0019] Figure 2C is a plan view illustrating one example of a shape of a body region and an active region of the semiconductor device according to Embodiment 1.

[0020] Figure 2D is a plan view illustrating one example of a gate electrode portion of the semiconductor device according to Embodiment 1 being enlarged.

[0021] Figure 3A is a cross-sectional view illustrating one example of a configuration of the semiconductor device according to Embodiment 1.

[0022] Figure 3B is a cross-sectional view illustrating a sub current flowing in the semiconductor device according to Embodiment 1.

[0023] Figure 4A is a plan view of a substantially unit structure of the first transistor according to Embodiment 1.

[0024] Figure 4B is an oblique view of a substantially unit structure of the first transistor according to Embodiment 1.

[0025] Figure 5A is a circuit diagram illustrating an application example of the semiconductor device according to Embodiment 1 in a charge / discharge circuit.

[0026] Figure 5B is a circuit diagram illustrating an application example of the semiconductor device according to Embodiment 1 in a charge / discharge circuit.

[0027] Figure 6A is a plan view illustrating one example of a configuration of a pad of a comparative example of the semiconductor device according to Embodiment 1.

[0028] Figure 6BFIG. 1 is a circuit diagram showing an application example of the semiconductor device according to Embodiment 1 to a charge / discharge circuit.

[0029] Figure 7A FIG. 2 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0030] Figure 7B FIG. 3 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0031] Figure 7C FIG. 4 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0032] Figure 7D FIG. 5 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0033] Figure 8A FIG. 6 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0034] Figure 8B FIG. 7 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0035] Figure 8C FIG. 8 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0036] Figure 8D FIG. 9 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0037] Figure 9A FIG. 10 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0038] Figure 9B FIG. 11 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0039] Figure 10A FIG. 12 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0040] Figure 10B FIG. 13 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0041] Figure 10C FIG. 14 is a plan view showing one example of the configuration of a pad of the semiconductor device according to Embodiment 1.

[0042] Figure 11 is a cross-sectional view showing a pattern of warping of the semiconductor device according to Embodiment 1.

[0043] Figure 12A is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0044] Figure 12B is a cross-sectional view showing a sub-current flowing in the semiconductor device according to Embodiment 2.

[0045] Figure 12C is a plan view showing one example of an enlarged drain electrode portion and a gate electrode portion of the semiconductor device according to Embodiment 2.

[0046] Figure 13A is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0047] Figure 13B is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0048] Figure 13C is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0049] Figure 14A is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0050] Figure 14B is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0051] Figure 14C is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0052] Figure 14D is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0053] Figure 15A is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0054] Figure 15B is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0055] Figure 16A is a plan view showing one example of a configuration of a pad of the semiconductor device according to Embodiment 2.

[0056] Figure 16B FIG. 2A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 2.

[0057] Figure 16C FIG. 2A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 2.

[0058] Figure 16D FIG. 2A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 2.

[0059] Figure 17A FIG. 3A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 3.

[0060] Figure 17B FIG. 3A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 3.

[0061] Figure 17C FIG. 3A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 3.

[0062] Figure 17D FIG. 3A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 3.

[0063] Figure 18A FIG. 3A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 3.

[0064] Figure 18B FIG. 3A is a plan view showing one example of a configuration of a pad of a semiconductor device according to Embodiment 3. DETAILED DESCRIPTION

[0065] The following embodiments to be described below are each one specific example illustrating the present disclosure. Numerical values, shapes, materials, component configurations, component arrangement positions, connection modes, and the like shown in the following embodiments are one example, and the gist of the present disclosure is not limited to them.

[0066] In the present disclosure, the case where "A is electrically connected to B" includes the case where A and B are directly connected via a wiring, the case where A and B are not directly connected via a wiring, and the case where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0067] (Embodiment 1)

[0068] [1. Configuration of Semiconductor Device]

[0069] The configuration of the semiconductor device according to Embodiment 1 will be described below. The semiconductor device according to Embodiment 1 is a face-down mountable chip size package (CSP) type semiconductor device in which two longitudinal MOS (Metal Oxide Semiconductor) transistors are formed on a semiconductor substrate. The two longitudinal MOS transistors are power transistors, and are so-called trench type MOSFETs (Field Effect Transistor).

[0070] Figure 1 is a cross-sectional view showing one example of the configuration of the semiconductor device 1 according to Embodiment 1. Figure 2A is a plan view showing one example of the arrangement of pads of the semiconductor device 1, the size and / or shape of which is one example except that the shape thereof is rectangular. Also, the size, shape, and arrangement of the pads are one example.

[0071] Figure 1 is a cross-sectional view showing Figure 2A at I―I.

[0072] As shown in Figure 1 and Figure 2A , the semiconductor device 1 has a semiconductor layer 40, a metal layer 41, a first longitudinal MOS transistor 10 (hereinafter also referred to as transistor 10) formed in a first region A1 within the semiconductor layer 40, a second longitudinal MOS transistor 20 (hereinafter also referred to as transistor 20) formed in a second region A2 within the semiconductor layer 40, and a third region A3 which does not overlap with either the first region A1 or the second region A2.

[0073] In the present disclosure, the semiconductor layer formed on the semiconductor substrate 32 is referred to as the semiconductor layer 40 together with the semiconductor substrate 32. The semiconductor layer 40 is configured by laminating the semiconductor substrate 32 and a low-concentration impurity layer 33. The semiconductor substrate 32 is arranged on the back surface side of the semiconductor layer 40, and is composed of silicon containing impurities of the first conductivity type. The low-concentration impurity layer 33 is an impurity layer of the first conductivity type formed in contact with the semiconductor substrate 32 on the surface side of the semiconductor layer 40, and has a lower concentration of impurities of the first conductivity type than the semiconductor substrate 32. The low-concentration impurity layer 33 may, for example, be formed on the semiconductor substrate 32 by epitaxial growth.

[0074] The metal layer 41 is formed in contact with the back side of the semiconductor layer 40 and is composed of silver (Ag) or copper (Cu). Furthermore, the metal layer 41 may contain trace amounts of elements other than metals that have been introduced as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 41 may be formed on the entire back side of the semiconductor layer 40 or on a portion thereof; either method is acceptable.

[0075] like Figure 1 as well as Figure 2A As shown, a first body region 18 of the second conductivity type is formed in the first region A1 of the low-concentration impurity layer 33. The first body region 18 of the second conductivity type contains impurities of the second conductivity type, which is different from the first conductivity type. A first source region 14 of the first conductivity type containing impurities of the first conductivity type is formed in the first body region 18. A plurality of first gate trenches 17 are formed in the first region A1. These first gate trenches 17 extend from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 and extend to a depth that reaches a portion of the low-concentration impurity layer 33. The first gate conductor 15 is formed on the first gate insulating film 16 within the first gate trenches 17.

[0076] The first source electrode 11 includes a portion 12 and a portion 13 . The portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13 . The first gate conductor 15 is a buried gate electrode embedded in the semiconductor layer 40 and is electrically connected to the first gate pad 119 .

[0077] Portion 12 of the first source electrode 11 is a layer that is bonded to solder during reflow in face-down mounting. As a non-limiting example, it can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium. The surface of portion 12 can be plated with gold or the like.

[0078] The portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver, as a non-limiting example.

[0079] A second body region 28 of the second conductivity type containing impurities of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 of the first conductivity type containing impurities of the first conductivity type is formed in the second body region 28. A plurality of second gate trenches 27 are formed in the second region A2. These plurality of second gate trenches 27 extend from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a depth that reaches a portion of the low-concentration impurity layer 33. The second gate conductor 25 is formed on the second gate insulating film 26 within the second gate trenches 27.

[0080] Second source electrode 21 includes portion 22 and portion 23 . Portion 22 is connected to second source region 24 and second body region 28 via portion 23 . Second gate conductor 25 is a buried gate electrode embedded in semiconductor layer 40 and electrically connected to second gate pad 129 .

[0081] Portion 22 of the second source electrode 21 is a layer that is bonded to solder during reflow in face-down mounting. As a non-limiting example, it can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium. The surface of portion 22 can be plated with gold or the like.

[0082] The portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver, as a non-limiting example.

[0083] With the above-described structures of transistors 10 and 20, the semiconductor substrate 32 and the area immediately above the semiconductor substrate 32 in the low-concentration impurity layer 33 function as a common drain region, common to the first drain region of transistor 10 and the second drain region of transistor 20. Furthermore, the metal layer 41 functions as a common drain electrode (hereinafter also referred to as a back-side drain electrode) provided on the back side of the semiconductor layer 40, common to the drain electrodes of transistors 10 and 20.

[0084] like Figure 1 As shown, the first body region 18 is covered by an interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 is provided, which is connected to the first source region 14 via the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered by a passivation layer 35 having an opening, and a portion 12 is provided, which is connected to the portion 13 of the first source electrode 11 via the opening of the passivation layer 35.

[0085] The second body region 28 is covered by an interlayer insulating layer 34 having an opening, and is provided with a portion 23 of the second source electrode 21 connected to the second source region 24 through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered by a passivation layer 35 having an opening, and is provided with a portion 22 connected to the portion 23 of the second source electrode 21 through the opening of the passivation layer 35.

[0086] Therefore, the plurality of first source pads 111 and the plurality of second source pads 121 refer to the areas where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, that is, the so-called terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 refer to the first gate electrode 19 (at Figure 1 、Figure 2A The second gate electrode 29 (not shown in FIG. 1) is partially exposed on the surface of the semiconductor device 1, i.e., a so-called terminal portion. Figure 1 、 Figure 2A The second gate electrode 29 (not shown in FIG. 1) is partially exposed on the surface of the semiconductor device 1, i.e., a so-called terminal portion.

[0087] Figure 3A is a sectional view taken along the line II-II of Figure 2A . As shown in Figure 3A , in the third region A3 of the low-concentration impurity layer 33, a drain lead-out region 58 of the first conductivity type containing an impurity of the first conductivity type having a higher concentration than that of the impurity of the first conductivity type in the low-concentration impurity layer 33 is formed within the low-concentration impurity layer 33. In addition, the drain lead-out region 58 can also be formed within the low-concentration impurity layer 33 to a depth reaching the semiconductor substrate 32.

[0088] The drain electrode (hereinafter also referred to as a surface-side drain electrode) 51 is composed of a portion 52 and a portion 53, and the portion 52 is connected to the drain lead-out region 58 via the portion 53.

[0089] The portion 52 of the drain electrode 51 is a layer which is joined with solder at the time of reflow mounting with the face down, and is composed of a metal material containing one or more of nickel, titanium, tungsten, and palladium, for example, as a non-limiting example. A plating layer of gold or the like can be applied to the surface of the portion 52.

[0090] The portion 53 of the drain electrode 51 is a layer which connects the portion 52 to the drain lead-out region 58. Therefore, the drain electrode 51 has a drain potential common to the transistors 10 and 20. In addition, the portion 53 of the drain electrode 51 can be composed of a metal material containing one or more of aluminum, copper, gold, and silver, for example, as a non-limiting example.

[0091] As shown in Figure 3A , the low-concentration impurity layer 33 is covered with an interlayer insulating layer 34 having an opening, and the portion 53 of the drain electrode 51 connected to the drain lead-out region 58 via the opening of the interlayer insulating layer 34 is provided. The interlayer insulating layer 34 and the portion 53 of the drain electrode 51 are covered with a passivation layer 35 having an opening, and the portion 52 connected to the portion 53 of the drain electrode 51 via the opening of the passivation layer 35 is provided.

[0092] Therefore, the drain pad 151 refers to a region in which the drain electrode 51 is partially exposed on the surface of the semiconductor device 1, i.e., a so-called terminal portion.

[0093] As a standard design example of each configuration in the semiconductor device 1, the thickness of the semiconductor layer 40 is 10 to 90 μm, the thickness of the metal layer 41 is 10 to 90 μm, and the sum of the thicknesses of the interlayer insulating layer 34 and the passivation layer 35 is 3 to 13 μm.

[0094] As Figure 1 and Figure 2A shown, the transistor 10 has a plurality of first source pads 111 and a first gate pad 119 on the surface of the semiconductor layer 40 that are to be bonded to a mounting substrate via a bonding material at face-down mounting. Also, the transistor 20 has a plurality of second source pads 121 and a second gate pad 129 on the surface of the semiconductor layer 40 that are to be bonded to a mounting substrate via a bonding material at face-down mounting. Also, the third region A3 has a drain pad 151 on the surface of the semiconductor layer 40 that is to be bonded to a mounting substrate via a bonding material at face-down mounting.

[0095] As Figure 1 and Figure 2A shown, the semiconductor device 1 and the semiconductor layer 40 are rectangular in plan view. Also in Figure 2A , the semiconductor device 1 and the semiconductor layer 40 are rectangular, the semiconductor device 1 and the semiconductor layer 40 can also be square.

[0096] In plan view, a direction in which the first region A1 and the second region A2 are arranged among directions parallel to the outer periphery of the semiconductor device 1 is referred to as a first direction. In plan view, the arrangement of the first region A1 and the second region A2 in the first direction means that the first region A1 and the second region A2 are arranged most proximally in the first direction.

[0097] Most proximal in the first direction means that, in plan view, a portion of a boundary line 90C between the first region A1 and the second region A2 described later that is orthogonal to the first direction is the longest. For example, in the case where the boundary line 90C is curved in plan view, the boundary line 90C is divided into line segments that constitute the boundary line 90C, and a direction orthogonal to a direction in which the sum of the line segments in the same direction is the longest is the first direction.

[0098] As Figure 2A shown, in plan view of the semiconductor layer 40, the first region A1 and the second region A2 are adjacent to each other, and the area of the semiconductor layer 40 other than the third region A3 is bisected into one side and the other side.

[0099] As Figure 2A shown, in plan view of the semiconductor layer 40, the center line 90 is a line that bisects the semiconductor layer 40 in the first direction. In plan view of the semiconductor layer 40, the center line 90 is a line that is linear in a direction orthogonal to the first direction.

[0100] Also, the center of the third region A3 of the semiconductor layer 40 is located on the center line 90 of the semiconductor layer 40 in plan view of the semiconductor layer 40. Regarding the center, as Figure 2AAs shown, if the shape is a circular shape such as the drain pad 151, the center refers to the center of the circle, if the shape is a rectangular shape such as the third region A3, the center refers to the intersection of the diagonals of the rectangle, and if the shape is an elliptical shape, the center refers to the intersection of the major axis and the minor axis of the ellipse.

[0101] Also in Figure 2A , the virtual boundary line 90C for distinguishing the first region Al, the second region A2, and the third region A3 of the semiconductor layer 40 is indicated by a dotted line. The boundary line 90C on the region where the first region Al and the second region A2 are adjacent can also be regarded as a virtual line along the center of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Also in the case where the interval is of a finite width, it can also be regarded as the interval itself (even in the case where there is the interval, it can be regarded as a line in the appearance under naked eye observation or at a low magnification).

[0102] The boundary line 90C on the region where the first region Al and the third region A3 are adjacent can also be regarded as a virtual line along the center of the interval between the portion 13 of the first source electrode 11 and the portion 53 of the drain electrode 51. Also in the case where the interval is of a finite width, it can also be regarded as the interval itself.

[0103] The boundary line 90C on the region where the second region A2 and the third region A3 are adjacent can also be regarded as a virtual line along the center of the interval between the portion 23 of the second source electrode 21 and the portion 53 of the drain electrode 51. Also in the case where the interval is of a finite width, it can also be regarded as the interval itself.

[0104] In addition, although the boundary line 90C bisects the area of the semiconductor layer 40 other than the third region A3 in the plan view of the semiconductor layer 40, it need not necessarily be a straight line. Also in the plan view of the semiconductor layer 40, the center line 90 and the boundary line 90C can coincide at least in part.

[0105] The drain pad 151 is disposed inside the third region A3 of the semiconductor layer 40 in the plan view of the semiconductor layer 40, and is surrounded by the third region A3. In Figure 2A the example, the center of the drain pad 151 coincides with the center of the third region A3. The drain pad 151 can be located within the third region A3, and there can also be a case where the center of the drain pad 151 does not coincide with the center of the third region A3.

[0106] In the plan view of the semiconductor layer 40, it is desirable that the area of the third region A3 of the semiconductor layer 40 be formed smaller than the areas of the first region Al and the second region A2. This is because the areas of the first region Al and the second region A2 need to be as large as possible in order to reduce the on-resistance of the main path, as will be described later. The third region A3 of the semiconductor device 1 need not be increased in area for the main path, since the sub path of the semiconductor device 1 flows a relatively small current. As a representative example, the shape of the third region A3 in the plan view is desired to be a rectangle circumscribing the shape of the drain pad 151, except for a space, regardless of the shape of the drain pad 151.

[0107] Also, the drain pad 151 can not necessarily be limited to the shape in the example of Figure 2A Also, the drain pad 151 can not necessarily be limited to the shape in the example of Figure 2A the substantially elliptical shape exemplified in the example of

[0108] The number of the plurality of first source pads 111 of the transistor 10 and the number of the plurality of second source pads 121 of the transistor 20 can not necessarily be limited to the five exemplified in the example of Figure 2A The number of the plurality of first source pads 111 of the transistor 10 and the number of the plurality of second source pads 121 of the transistor 20 can not necessarily be limited to the five exemplified in the example of Figure 2A The shape of the plurality of first source pads 111 of the transistor 10 and the shape of the plurality of second source pads 121 of the transistor 20 can not necessarily be limited to the substantially rectangular shape exemplified in the example of Figure 2A The shape of the plurality of first source pads 111 of the transistor 10 and the shape of the plurality of second source pads 121 of the transistor 20 can not necessarily be limited to the substantially rectangular shape exemplified in the example of Figure 2A The arrangement of the plurality of first source pads 111 of the transistor 10 and the arrangement of the plurality of second source pads 121 of the transistor 20 can not necessarily be limited to the arrangement exemplified in the example of

[0109] Also, the number of the first gate pad 119 of the transistor 10 and the number of the second gate pad 129 of the transistor 20 can not necessarily be limited to the one exemplified in the example of Figure 2A The number of the first gate pad 119 of the transistor 10 and the number of the second gate pad 129 of the transistor 20 can not necessarily be limited to the one exemplified in the example of Figure 2A The shape of the first gate pad 119 and the shape of the second gate pad 129 can not necessarily be the substantially circular shape exemplified in the example of Figure 2A The arrangement of the first gate pad 119 and the arrangement of the second gate pad 129 can not necessarily be limited to the arrangement exemplified in the example of

[0110] In addition, in the example of Figure 1 , Figure 2AAlthough not shown, in a plan view of the semiconductor layer 40, a first EQR (Equi potential Ring) electrically connected to the drain region of the transistor 10 can also be provided at the outer periphery of the first region Al. Similarly, in a plan view of the semiconductor layer 40, a second EQR electrically connected to the drain region of the transistor 20 can be provided at the outer periphery of the second region A2. The first EQR and the second EQR can be common in a portion where the transistor 10 and the transistor 20 are adjacent and face each other.

[0111] The first EQR is provided in expectation of a function of preventing a leakage current from flowing between the outside and the first body region 18 with respect to the transistor 10. Also, the second EQR is provided in expectation of a function of preventing a leakage current from flowing between the outside and the second body region 28 with respect to the transistor 20.

[0112] The first EQR and the second EQR can be composed of a metal material including one or more of aluminum, copper, gold, and silver, as a non-limiting example. Also, the first EQR and the second EQR can be electrically connected to the surface-side drain electrode 51, or can be electrically connected to the back-face-side drain electrode 41 via the semiconductor substrate 32 as a common drain region.

[0113] [2. Operation of semiconductor device]

[0114] Figure 4A and Figure 4B are a plan view and an oblique view of a substantially unit structure of the transistor 10 or the transistor 20 repeatedly formed in the X direction and the Y direction of the semiconductor device 1, respectively. In Figure 4A and Figure 4B In the above-described Embodiments, the semiconductor substrate 32, the metal layer 41, and also the passivation layer 35, the first source electrode 11 or the second source electrode 21, and the interlayer insulating layer 34 are not illustrated for convenience of understanding.

[0115] Further, the Y direction is a direction parallel to the upper surface of the semiconductor layer 40 and in which the first gate trench 17 extends. Also, the X direction is a direction parallel to the upper surface of the semiconductor layer 40 and orthogonal to the Y direction. The Z direction is a direction orthogonal to both the X direction and the Y direction, and is a direction in which the height of the semiconductor device 1 is shown.

[0116] Although the above-described definitions are made with respect to the directions, the Y direction and the X direction can be reversed in the following description. That is, the X direction can be a direction parallel to the upper surface of the semiconductor layer 40 and in which the first gate trench 17 extends. The Y direction in this case is a direction parallel to the upper surface of the semiconductor layer 40 and orthogonal to the X direction.

[0117] As Figure 4A and Figure 4BAs shown, the transistor 10 has a first connecting portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connecting portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and contains impurities of the same second conductivity type as the first body region 18. The first source region 14 and the first connecting portion 18a are alternately and periodically repeatedly arranged along the Y direction. The same applies to the transistor 20.

[0118] In the semiconductor device 1, for example, the first conductivity type can be set to N type, and the second conductivity type can be set to P type, and the first source region 14, the second source region 24, the drain lead region 58, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be N type semiconductors, and the first body region 18, the first connecting portion 18a, the second body region 28, and the second connecting portion 28a can be P type semiconductors.

[0119] Also, in the semiconductor device 1, for example, the first conductivity type can be set to P type, and the second conductivity type can be set to N type, and the first source region 14, the second source region 24, the drain lead region 58, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be P type semiconductors, and the first body region 18, the first connecting portion 18a, the second body region 28, and the second connecting portion 28a can be N type semiconductors.

[0120] In the following description, the transistor 10 and the transistor 20 are taken as examples of so-called N channel type transistors in which the first conductivity type is N type and the second conductivity type is P type, and the following description is given. Figure 2B The bidirectional conduction path through which the main current of the semiconductor device 1 shown flows is described.

[0121] In the semiconductor device 1, if a high voltage is applied to the first source electrode 11, a low voltage is applied to the second source electrode 21, and a voltage of the threshold value or more is applied to the second gate electrode 29 (the second gate conductor 25) with the second source electrode 21 as a reference, a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28. In this way, the main current flows through a path of the first source electrode 11 - the first connecting portion 18a - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second body region 28 - the second source region 24 - the second source electrode 21, and the semiconductor device 1 becomes a conduction state. This conduction path is referred to as a main path in the present disclosure. A PN junction exists at the contact surface of the first body region 18 and the low-concentration impurity layer 33 in the main path, and functions as a body diode.

[0122] Also in the semiconductor device 1, if a high voltage is applied to the second source electrode 21, a low voltage is applied to the first source electrode 11, and a voltage exceeding the threshold value is applied to the first gate electrode 19 (the first gate conductor 15) with the first source electrode 11 as a reference, a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18. In this way, the main current flows through a path of the second source electrode 21 - the second connection portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the first body region 18 - the first source region 14 - the first source electrode 11, and the semiconductor device 1 becomes in the on state. This conduction path is also referred to as the main path in the present disclosure. A PN junction exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in the main path, and functions as a body diode.

[0123] Also, in the semiconductor device 1, a voltage exceeding the threshold value can be applied to the first gate electrode 19 to form a conduction channel in the vicinity of the first gate insulating film 16 in the first body region 18, and a voltage exceeding the threshold value can be applied to the second gate electrode 29 to form a conduction channel in the vicinity of the second gate insulating film 26 in the second body region 28. In this way, the main current can flow through a path of the first source electrode 11 - the first source region 14 - the conduction channel formed in the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second body region 28 - the second source region 24 - the second source electrode 21 or a path opposite to this path, and the semiconductor device 1 is turned on. This bidirectional conduction path is also referred to as the main path in the present disclosure.

[0124] Further, the main current and the main path in the present disclosure are named for the sake of convenience in distinguishing from the sub-current and the sub-path to be described later.

[0125] Figure 3B is a sectional view showing a sub-current flowing in the semiconductor device 1. The sub-current is not illustrated in Figure 3B , and is a current controlled to be turned on by an external switching element (for example, a single-structure vertical MOS transistor) connected in series to the drain electrode 51 of the semiconductor device 1, and is a relatively small current compared to the main current. Further, in the present disclosure, a conduction path through which the sub-current flows in the semiconductor device 1 is referred to as the sub-path.

[0126] In the semiconductor device 1, if a high voltage is applied to the first source electrode 11, a low voltage is applied to the drain electrode 51, and the external switching element connected in series with the drain electrode 51 is brought to an on state, a sub-current flows in the path of the first source electrode 11 - the first connecting portion 18a - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the drain lead-out region 58 - the drain electrode 51, and the semiconductor device 1 is brought to an on state. Also, if a high voltage is applied to the first source electrode 11, a low voltage is applied to the drain electrode 51, and the external switching element is brought to an on state, a voltage exceeding the threshold value is applied to the first gate electrode 19 with the first source electrode 11 as a reference, a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18, a sub-current flows in the path of the first source electrode 11 - the first source region 14 - the conduction channel formed in the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the drain lead-out region 58 - the drain electrode 51, and the semiconductor device 1 is brought to an on state.

[0127] Also, if a high voltage is applied to the second source electrode 21, a low voltage is applied to the drain electrode 51, and the external switching element connected in series with the drain electrode 51 is brought to an on state, a sub-current flows in the path of the second source electrode 21 - the second connecting portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the drain lead-out region 58 - the drain electrode 51, and the semiconductor device 1 is brought to an on state. Also, if a high voltage is applied to the second source electrode 21, a low voltage is applied to the drain electrode 51, and the external switching element is brought to an on state, a voltage exceeding the threshold value is applied to the second gate electrode 29 with the second source electrode 21 as a reference, a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28, a sub-current flows in the path of the second source electrode 21 - the second source region 24 - the conduction channel formed in the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the drain lead-out region 58 - the drain electrode 51, and the semiconductor device 1 is brought to an on state.

[0128] The conduction paths through which the sub-current flows are sub-paths. The sub-paths of the semiconductor device 1 are controlled by bringing the external switching element connected in series with the drain electrode 51 into an on state or an off state. In the case where the switching element is in the on state, the sub-paths of the semiconductor device 1 are in the on state. In addition, PN junctions exist at the contact surfaces of the first body region 18 and the low-concentration impurity layer 33 and the contact surfaces of the second body region 28 and the low-concentration impurity layer 33 in the sub-paths, and function as body diodes.

[0129] In the case where the main path is in the on state, since the external switching element connected in series with the drain electrode 51 is necessarily controlled to be in the off state, the sub-paths are in the off state, and only the main path is in the on state.

[0130] Figure 2C is a plan view showing one example of the shapes of the first body region 18 and the second body region 28, the first active region 112, and the second active region 122 among the constituent elements of the semiconductor device 1 in a plan view of the semiconductor layer 40. In Figure 2C , the passivation layer 35, the first source electrode 11, the first gate electrode 19, the second source electrode 21, the second gate electrode 29, the drain electrode 51, and the interlayer insulating layer 34 are regarded as transparent and the illustration thereof is omitted in order to be able to easily show the configuration of the upper surface of the semiconductor layer 40, which cannot actually be seen. Also, the illustration of the first source region 14 and the second source region 24 and the drain lead-out region 58 is omitted.

[0131] To reduce the on-resistance of the main path of the semiconductor device 1, it is necessary to secure as large first and second active regions 112 and 122 as possible. The first active region 112 is the smallest range that encloses all the portions in which a conduction channel is formed when a voltage of a threshold value or more is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The portions in which a conduction channel is formed are the portions in which each of the plurality of first gate trenches 17 is adjacent to the first source region 14. As Figure 2C shown in the plan view of the semiconductor layer 40, the first active region 112 is enclosed in the first body region 18. The second active region 122 is the smallest range that encloses all the portions in which a conduction channel is formed when a voltage of a threshold value or more is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The portions in which a conduction channel is formed are the portions in which each of the plurality of second gate trenches 27 is adjacent to the second source region 24. As Figure 2C shown in the plan view of the semiconductor layer 40, the second active region 122 is enclosed in the second body region 28.

[0132] The larger the area of the first active region 112 and the area of the second active region 122, the larger the main path is expanded, and thus the on-resistance of the main path of the semiconductor device 1 is reduced.

[0133] Figure 2D is a plan view of the first gate pad 119-enlarged portion of Figure 2A . Figure 2D is one example of the shape of the first source electrode 11 portion 13, the first gate electrode 19, and the first gate pad 119 in the plan view of the semiconductor layer 40 among the constituent elements of the semiconductor device 1. In Figure 2D , the passivation layer 35 and the interlayer insulating layer 34 are omitted from the illustration as if they were transparent in order to easily show the configuration of the upper surface of the semiconductor layer 40, which is not actually visible. Also, the illustration of the first source region 14 is omitted.

[0134] Although the illustration is omitted, the second source electrode 21 portion 23, the second gate electrode 29, and the second gate pad 129 are line-symmetrical with the first source electrode 11 portion 13, the first gate electrode 19, and the first gate pad 119 shown in Figure 2D , with the center line 90 as the axis of symmetry.

[0135] The area directly below and in the vicinity of the first gate electrode 19, and the area directly below and in the vicinity of the second gate electrode 29 are areas that do not contribute to the conduction of the main path. The vicinity here refers to the area along the outer periphery of the first gate electrode 19 and the second gate electrode 29, which can be understood in Figure 2D to be the area between the first gate electrode 19 and the first source electrode 11 portion 13, and the area between the second gate electrode 29 and the second source electrode 21 portion 23, which is omitted from the illustration.

[0136] Also, the third area A3, which surrounds the drain pad 151, is also an area that does not contribute to the conduction of the main path.

[0137] That is, the area directly below and in the vicinity of the first gate electrode 19, the area directly below and in the vicinity of the second gate electrode 29, and the third area A3 are areas that, although necessary for the semiconductor device 1 to function, are desirably reduced as much as possible in the limited device area in order to reduce the on-resistance of the main path of the semiconductor device 1.

[0138] [3. Application Example of Semiconductor Device]

[0139] Figure 5Ais a circuit diagram showing an application example when the semiconductor device 1 in the present disclosure is applied to a protection circuit for a lithium-ion battery 5. In this application example, the semiconductor device 1 controls the bidirectional conduction as a main path in accordance with a control signal supplied from a control IC 4 to the first gate electrode 19 and the second gate electrode 29, and controls the discharge operation from the lithium-ion battery 5 to a load 6 or the charge operation from the load 6 to the lithium-ion battery 5. At this time, since the charge current CI or the discharge current C2 flowing in the semiconductor device 1 is a relatively large current, the sub path is not used. In the case where the semiconductor device 1 in the present disclosure is applied to a battery protection circuit, the control of the bidirectional conduction of the charge and the discharge using the main path can also be said to be the main function of the semiconductor device 1. The main path is desired to reduce the on-resistance as much as possible since a relatively large current is to flow therethrough.

[0140] Next, the application of the sub path will be described. Figure 5A The semiconductor device 1 has a sub path using the drain electrode 51 in addition to the main path. In the pre-charge, the charge current C3 flows in the sub path. In the case where the voltage of the lithium-ion battery 5 is in the over-discharge state, it is dangerous to perform the charge operation with a relatively large charge current CI as in the normal charge. The pre-charge refers to the charge operation with a relatively small charge current C3.

[0141] In the pre-charge, the charge operation is performed with a relatively small charge current C3. In the case where the voltage of the lithium-ion battery 5 is in the over-discharge state, it is dangerous to perform the charge operation with a relatively large charge current CI as in the normal charge. The pre-charge refers to the charge operation with a relatively small charge current C3. Figure 5A In the pre-charge, the charge operation is performed with a relatively small charge current C3. In the case where the voltage of the lithium-ion battery 5 is in the over-discharge state, it is dangerous to perform the charge operation with a relatively large charge current CI as in the normal charge. The pre-charge refers to the charge operation with a relatively small charge current C3.

[0142] In the pre-charge, the charge operation is performed with a relatively small charge current C3. In the case where the voltage of the lithium-ion battery 5 is in the over-discharge state, it is dangerous to perform the charge operation with a relatively large charge current CI as in the normal charge. The pre-charge refers to the charge operation with a relatively small charge current C3.

[0143] Figure 5B is a circuit diagram showing an application example of the semiconductor device 1, and Figure 5AAlso, the application example of the protection circuit for the lithium-ion battery 5 applied to the lithium-ion battery pack. In Figure 5B the main function of the semiconductor device 1 in Figure 5A is the same as the description, also controls the charging current Cl and the discharging current C2. However, the utilization method of the sub-path is different. The drain electrode 51 of the semiconductor device 1 is connected with the control IC 4, and is utilized as the monitor terminal of the drain voltage common to the transistor 10 and the transistor 20. In Figure 5B , since the sub-path of the semiconductor device 1 is connected with the control IC 4, and is controlled to be in the non-conducting state by the control IC 4, thus no sub-current flows. The control IC 4 utilizes the sub-path to monitor the voltage of the drain electrode 51 when controlling the charging current Cl and the discharging current C2 of the lithium-ion battery 5, when the voltage of the drain electrode 51 deviates from the normal voltage range of the lithium-ion battery 5, then it is judged to be an abnormal state, and stops the charging and discharging work. Accordingly, it is possible to prevent the over-discharge and over-charge of the lithium-ion battery 5.

[0144] [4. Effects of the semiconductor device 1 according to Embodiment 1]

[0145] The features of the semiconductor device 1 in the present disclosure described above are shown as follows.

[0146] The semiconductor device 1 according to one embodiment of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10 formed in a first region Al of a semiconductor layer 40 when the semiconductor substrate 32 and the low-concentration impurity layer 33 are taken together as the semiconductor layer 40; a second vertical MOS transistor 20 formed in a second region A2 that is a region adjacent to the first region Al in a plan view of the semiconductor layer 40; a plurality of first source pads 111 formed in the first region Al in the plan view and connected to first source electrodes 11 of the first vertical MOS transistor 10; a first gate pad 119 formed in the first region Al in the plan view and connected to a first gate electrode 19 of the first vertical MOS transistor 10; a plurality of second source pads 121 formed in the second region A2 in the plan view and connected to second source electrodes 21 of the second vertical MOS transistor 20; a second gate pad 129 formed in the second region A2 in the plan view and connected to a second gate electrode 29 of the second vertical MOS transistor 20; and a metal layer 41 formed in contact with a back surface of the semiconductor substrate 32, the semiconductor substrate 32 being a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, the semiconductor layer 40 being rectangular in the plan view, the first vertical MOS transistor 10 and the second vertical MOS transistor 20 being arranged in a first direction in the plan view, the semiconductor layer 40 having a third region A3 that does not overlap the first region Al and the second region A2 in the plan view, the first region Al and the second region A2 being one side and the other side that bisect the region of the semiconductor layer 40 other than the third region A3 in area in the plan view, a center of the third region A3 being located on a center line 90 that is a straight line-shaped line bisecting the semiconductor layer 40 in the first direction and orthogonal to the first direction in the plan view, the semiconductor layer 40 including one drain pad 151 connected to the common drain region in the plan view, the drain pad 151 being arranged so as to be surrounded in the third region A3 in the plan view.

[0147] With the above configuration, the drain pad 151 required to constitute the sub path can be the minimum number necessary, that is, by having only one drain pad 151, the area of the third region A3 can be reduced compared to the case where a plurality of drain pads are provided, and thus the increase in the on-resistance on the main path due to the provision of the sub path can be suppressed as much as possible.

[0148] Also, in the plan view of the semiconductor layer 40, since the third region A3 of the semiconductor layer 40 can be disposed on the center line 90 of the semiconductor layer 40, by flexibly applying such a region that does not contribute to the conduction of the main path as a region where the drain pad 151 is disposed, it is possible to suppress an increase in the conduction resistance of the main path compared to a case where the third region A3 is disposed at a position other than the center line 90 in the plan view of the semiconductor layer 40.

[0149] Also, in the plan view of the semiconductor layer 40, since the center of the third region A3 is disposed on the center line 90 of the semiconductor layer 40, even if the third region A3 (the drain pad 151) is provided, it is not easy to hinder the first active region 112 and the second active region 122 from having the same area and shape. Therefore, the electrical characteristics and the heat dissipation of the bidirectional conduction between the transistor 10 and the transistor 20 are less likely to be biased.

[0150] Since the main current of the semiconductor device 1 is bidirectional, it is desirable that, as shown in the above-described configuration, the transistor 10 and the transistor 20 are disposed in a line symmetry with the boundary line 90C as the axis of symmetry, or in a point symmetry with the center of the semiconductor layer 40 as the center of symmetry. In this way, it is not easy for the electrical characteristics and the heat dissipation to be biased due to a difference in the direction of the main current. For example, in a lithium ion battery pack of a smartphone, a tablet, or the like, if a protection circuit configured to employ the semiconductor device 1 is employed, it is not necessary to design any particular difference in the conduction direction in the semiconductor device 1, regardless of charging or discharging.

[0151] With the above-described configuration, the semiconductor device 1 is configured to have a bidirectional main current, and the drain pad 151 is disposed in the third region A3 of the semiconductor layer 40. Thus, the semiconductor device 1 is a semiconductor device 1 in which the drain pad 151 is disposed in the third region A3 of the semiconductor layer 40. Figure 6A With the above-described configuration, the semiconductor device 1 is configured to have a bidirectional main current, and the drain pad 151 is disposed in the third region A3 of the semiconductor layer 40. Thus, the semiconductor device 1 is a semiconductor device 1 in which the drain pad 151 is disposed in the third region A3 of the semiconductor layer 40. Figure 6B A semiconductor device 2 related to a comparative example of Embodiment 1 will be described. For the same configuration elements of the semiconductor device 2 related to the comparative example and the semiconductor device 1, since the description has already been made, the same symbols are given and detailed description is omitted.

[0152] In the semiconductor device 2, the third region A3 of the semiconductor layer 40 in the plan view has a third vertical MOS transistor 30 (hereinafter also referred to as a transistor 30). Therefore, the semiconductor device 2 is a triple structure semiconductor device 2 in which three vertical MOS transistors (the transistor 10, the transistor 20, and the transistor 30) each having a separate control function are equipped in one device.

[0153] The transistor 30 has the same configuration as the transistor 10 or the transistor 20, and the semiconductor device 2 does not have the drain pad 151 and the drain lead-out region 58 that the semiconductor device 1 related to Embodiment 1 has.

[0154] The transistor 30 has a third source pad 131 and a third gate pad 139 located on the surface (third region A3) of the semiconductor layer 40. The drain region of the transistor 30 is common to the drain regions of the transistor 10 and the transistor 20.

[0155] Figure 6B is a circuit diagram showing the semiconductor device 2 related to the comparative example and Figure 5A the same applies to the application example of the circuit of the protection circuit of the lithium ion battery 5. In Figure 6B , the main function of the semiconductor device 2 is the same as the main function of the semiconductor device 1 related to the embodiment 1 ( Figure 5A ). In addition, the sub-path of the semiconductor device 2 related to the comparative example is a path in which the current reaches the third source electrode 31 of the transistor 30 from the first source electrode 11 of the transistor 10 through the inside of the semiconductor device 2. Or a path in which the current reaches the third source electrode 31 of the transistor 30 from the second source electrode 21 of the transistor 20 through the inside of the semiconductor device 2.

[0156] In Figure 6B , the on-off control of the sub-path of the semiconductor device 2 is controlled by the control signal supplied from the control IC 4 to the third gate electrode 39 of the transistor 30. That is, the semiconductor device 2 related to the comparative example has a function of controlling the on-off of the sub-path. Therefore, the external switching element S1 required in the embodiment 1 ( Figure 5A ) is not required here.

[0157] The sub-path in the semiconductor device 1 related to the embodiment 1 compared to the sub-path in the semiconductor device 2 related to the comparative example, since the semiconductor device 1 related to the embodiment 1 does not have the control function in the sub-path, the area of the semiconductor device 1 occupied by this part can be reduced. Or this part can be utilized as the main path, thereby increasing the area of the main path, so that the on-resistance of the main path can be reduced.

[0158] Figure 7A-7D , Figure 8A-8D , Figure 9A , Figure 9B , Figure 10A-10C is a plan view showing a configuration example of the pads satisfying the conditions of the semiconductor device 1 related to the embodiment 1.

[0159] As Figure 7A-7DAs shown, the center of the third region A3 is located on the center line 90 of the semiconductor layer 40 in the plan view of the semiconductor layer 40, and the third region A3 is configured so that the first region A1 and the second region A2 are not sandwiched between the third region A3 and the edge of the outer periphery of the semiconductor layer 40 that is parallel to the first direction and closest to the third region A3, and the drain pad 151 can be configured to be enclosed in the third region A3.

[0160] With the above configuration, drain pad 151 can be positioned as close as possible to the outer periphery of semiconductor layer 40 in a plan view of semiconductor layer 40. This reduces the likelihood of poor bonding to the solder due to warping of semiconductor device 1, compared to a case where drain pad 151 is positioned at the center of semiconductor layer 40.

[0161] The following describes the warping of the semiconductor layer 1. As a means of reducing the on-resistance of the semiconductor device 1, Figure 2B Thinning the semiconductor layer 40 (primarily the semiconductor substrate 32), which is the resistance component of the main current flowing in the vertical direction, is effective. Furthermore, thickening the metal layer 41 also helps reduce on-resistance. That is, thinning the semiconductor layer 40 or thickening the metal layer 41 in the semiconductor device 1 has the effect of reducing on-resistance. However, if the thickness of the semiconductor layer 40 and the metal layer 41 are close, the warping of the semiconductor device 1 at high temperatures will increase due to the difference in physical properties such as the thermal expansion coefficient and Young's modulus between the semiconductor and the metal.

[0162] Warping of the semiconductor device 1 occurs primarily during reflow for face-down mounting, a high-temperature environment of approximately 250°C during heat treatment. In face-down mounting, the metal layer 41 expands more than the semiconductor layer 40 at high temperatures, causing convex warping away from the mounting substrate.

[0163] like Figure 11 As shown in FIG. 1 , when a semiconductor device 1 warps, it is difficult to mount the semiconductor device 1. Solder may be insufficient near the center of the semiconductor device 1, which corresponds to the protrusion, resulting in a poor joint (insufficient solder distribution). Furthermore, in the outer peripheral area of ​​the semiconductor device 1, the force pressing toward the mounting substrate increases due to the warping, sometimes causing solder to overflow from the area where it should be (solder overflow).

[0164] When the semiconductor layer 40 has a rectangular shape, the semiconductor layer 40 is most curved in directions parallel to the long sides due to the influence of the warpage occurring in the semiconductor device 1 , and is slightly curved in directions parallel to the short sides.

[0165] The warpage of the semiconductor device 1 that occurs at the time of high temperature under reflow mounting is warpage in which the central portion of the semiconductor layer 40 is raised in a direction away from the mounting substrate. Although there is a possibility that the solder will not be sufficient and bonding will be poor in the vicinity of the center of the semiconductor device 1 corresponding to the raised portion, by Figure 7A-7D As illustrated in the configuration shown in FIG. 1, since the drain pad 151 is disposed at the outer peripheral portion of the semiconductor layer 40, compared to a case in which the drain pad 151 is disposed at the central portion of the semiconductor layer 40, it is possible to reduce the possibility of solder bonding failure occurring due to warpage of the semiconductor device 1.

[0166] In particular, in the case in which the semiconductor layer 40 is rectangular in shape with the direction orthogonal to the first direction as the long side, as illustrated in FIG. 2, it is possible to effectively prevent solder bonding failure. Figure 7B Figure 7C Figure 7D In the case in which the semiconductor layer 40 is rectangular in shape with the direction orthogonal to the first direction as the long side, as illustrated in FIG. 2, it is possible to effectively prevent solder bonding failure.

[0167] As illustrated in FIG. 3, the third region A3 can be disposed so that its center is on the diagonal line of the semiconductor layer 40 in a plan view of the semiconductor layer 40, and the drain pad 151 is enclosed in the third region A3. Figure 8A-8D With the above-described configuration, compared to the pad arrangement illustrated in FIG. 1, it is possible to suppress solder overflow, which is a type of mounting failure, due to warpage of the semiconductor device 1 that occurs at the time of high temperature under reflow mounting.

[0168] Figure 7A-7D The warpage of the semiconductor device 1 that occurs at the time of high temperature under reflow mounting is warpage in which the central portion of the semiconductor layer 40 is raised in a direction away from the mounting substrate. Although there is a possibility that the solder will not be sufficient and bonding will be poor in the vicinity of the center of the semiconductor device 1 corresponding to the raised portion, by

[0169] The warpage of the semiconductor device 1 that occurs at the time of high temperature under reflow mounting is warpage in which the central portion of the semiconductor layer 40 is raised in a direction away from the mounting substrate. Although there is a possibility that the solder will not be sufficient and bonding will be poor in the vicinity of the center of the semiconductor device 1 corresponding to the raised portion, by

[0170] However, by making the semiconductor device 1 the configuration illustrated in FIG. 4, since the drain pad 151 is disposed at the central portion of the semiconductor layer 40, compared to a case in which the drain pad 151 is disposed at the outer peripheral portion of the semiconductor layer 40, it is possible to suppress solder overflow, which is a type of mounting failure, due to warpage of the semiconductor device 1. Figure 8A-8D In particular, in the case in which the semiconductor layer 40 is rectangular in shape with the direction orthogonal to the first direction as the long side, as illustrated in FIG. 2, it is possible to effectively prevent solder bonding failure.

[0171] Figure 8D In particular, in the case in which the semiconductor layer 40 is rectangular in shape with the direction orthogonal to the first direction as the long side, as illustrated in FIG. 2, it is possible to effectively prevent solder bonding failure.

[0172] ​​​​Further, in addition to the above-described configuration, in a plan view of the semiconductor layer 40, the first gate pad 119, the second gate pad 129, and the drain pad 151 can be circular shapes having the same diameter, and can be pads having the smallest area among the pads provided to the semiconductor layer 40.

[0173] With the above-described configuration, in a plan view of the semiconductor layer 40, an area of a region that does not contribute to the conduction of the main path of the semiconductor device 1 can be minimized. Thus, an increase in the conduction resistance of the main path due to the provision of the sub-path can be suppressed.

[0174] Further, the drain pad 151 is not limited to the circular shape shown in Figure 7A-7D and Figure 8A-8D . It can also be a substantially rectangular shape as shown in Figure 9A and Figure 9B . The substantially rectangular shape is a general term that includes not only a shape in which the ends of a rectangle are rounded, but also a shape in which the ends are semicircular or polygonal.

[0175] In the embodiments shown in Figure 9A , Figure 9B , in a plan view of the semiconductor layer 40, the first gate pad 119 and the second gate pad 129 are circular shapes having the same diameter, and the first gate pad 119, the second gate pad 129, and the drain pad 151 are arranged within the same belt-shaped region.

[0176] With the arrangement shown in Figure 9A , since the first gate pad 119, the second gate pad 129, and the drain pad 151 that hinder the bidirectional flow of the main current along the first direction in the plan view can be arranged within the same width along the first direction, they can be prevented from becoming factors that hinder the flow of the main current. Further, with the arrangement shown in Figure 9B , since the first gate pad 119, the second gate pad 129, and the drain pad 151 can be arranged in a region that does not contribute to the conduction of the main path, they can be prevented from becoming factors that increase the conduction resistance of the main current.

[0177] Further, as shown in Figure 10A-10C , on the basis of the embodiments shown in Figure 7A-7D , in a plan view of the semiconductor layer 40, the semiconductor layer 40 has a rectangular shape, the drain pad 151 has a substantially rectangular shape, and the length direction of the drain pad 151 can be in parallel with the center line 90 of the semiconductor device 1 and the long side direction of the semiconductor layer 40.

[0178] In the plan view of the semiconductor layer 40, since the portion in which the center line 90 coincides with the boundary line 90C is large, by the above-described configuration, it is possible to flexibly use the third region A3 of the semiconductor layer 40, which is originally a region that does not contribute to the conduction of the main path, as a region in which the drain pad 151 is arranged, and thus it is possible to suppress an increase in the conduction resistance of the main path.

[0179] Further, it is possible to suppress mounting failure such as solder overflow due to warping of the semiconductor device 1 that occurs at the high temperature at the time of reflow mounting. In the case where the semiconductor layer 40 is a rectangular shape in which a direction orthogonal to the first direction is a long side, if the drain pad 151 is a substantially rectangular shape having a length direction in a direction parallel to the long side direction of the semiconductor layer 40, the length direction of the drain pad 151 and the direction in which the solder is pressed due to warping of the semiconductor device 1 that occurs at the high temperature at the time of reflow mounting become in parallel. Thus, it is possible to suppress the overflow of the solder, and thus it is possible to reduce the influence of warping of the semiconductor device 1 that occurs at the high temperature at the time of reflow mounting on mounting failure.

[0180] (Embodiment 2)

[0181] The semiconductor device 1A related to Embodiment 2, which is obtained by changing a part of the configuration of the semiconductor device 1 related to Embodiment 1, will be described below. With regard to the semiconductor device 1A related to this Embodiment 2, the same reference signs are given to the same configuration elements as those of the semiconductor device 1, which have already been described, and detailed description is omitted, and the description will be made focusing on the differences from the semiconductor device 1.

[0182] Figure 12A is a plan view showing one example of the arrangement of pads of the semiconductor device 1A related to Embodiment 2. The size and shape of the semiconductor device 1A are one example except that the shape is rectangular. Also, the size, shape, and arrangement of the pads are one example. Figure 12A the cross section at I-I of Figure 2A the cross section at I-I of Figure 1 are equivalent.

[0183] Figure 1 the transistor 10 of the semiconductor device 1 related to Embodiment 1 in Figure 12B the first vertical MOS transistor 10A (hereinafter also referred to as transistor 10A) in the semiconductor device 1A related to Embodiment 2 shown in

[0184] Similarly, Figure 1 the transistor 20 of the semiconductor device 1 related to Embodiment 1 inFigure 12B The second longitudinal MOS transistor 20A (hereinafter also referred to as transistor 20A) in the semiconductor device 1A according to Embodiment 2.

[0185] Figure 2A The first region A1 and the second region A2 of the semiconductor device 1 according to Embodiment 1 correspond to Figure 12A The first region A1A and the second region A2A of the semiconductor device 1A according to Embodiment 2.

[0186] Also, Figure 2A The plurality of first source pads 111 and the first gate pad 119 of the semiconductor device 1 according to Embodiment 1 correspond to Figure 12A The plurality of first source pads 111A and the first gate pad 119A of the semiconductor device 1A according to Embodiment 2.

[0187] Also, Figure 2A The plurality of second source pads 121 and the second gate pad 129 of the semiconductor device 1 according to Embodiment 1 correspond to Figure 12A The plurality of second source pads 121A and the second gate pad 129A of the semiconductor device 1A according to Embodiment 2.

[0188] As Figure 12A and Figure 1 shown, the semiconductor device 1A has a semiconductor layer 40, a metal layer 41, a transistor 10A formed in the first region A1A in the semiconductor layer 40, and a transistor 20A formed in the second region A2A in the semiconductor layer 40. The semiconductor device 1A according to Embodiment 2 does not have a third region A3 as compared with the semiconductor device 1 according to Embodiment 1.

[0189] As Figure 12A and Figure 12B and Figure 1 shown, the first region A1A of the semiconductor device 1A according to Embodiment 2 has a first drain electrode 51A in addition to the constituent elements of the first region A1 of the semiconductor device 1 according to Embodiment 1.

[0190] Also, the second region A2A of the semiconductor device 1A has a second drain electrode 61A in addition to the constituent elements of the second region A2 of the semiconductor device 1 according to Embodiment 1.

[0191] In Figure 12A , the cross section at II-II, that is, the cross section of the first drain electrode 51A is identical to Figure 3A and so on. Also, the cross section of the second drain electrode 61A is identical.

[0192] Figure 3A The portion 52 of the semiconductor device 1 according to the first embodiment corresponds to the portion 52A and the portion 62A in the semiconductor device 1A according to the second embodiment.

[0193] and, Figure 3A The portion 53 of the semiconductor device 1 according to the first embodiment corresponds to the portion 53A and the portion 63A in the semiconductor device 1A according to the second embodiment.

[0194] same, Figure 3A The drain electrode 51 composed of the portion 52 and the portion 53 of the semiconductor device 1 according to the first embodiment corresponds to the first drain electrode 51A composed of the portion 52A and the portion 53A, and the second drain electrode 61A composed of the portion 62A and the portion 63A in the semiconductor device 1A according to the second embodiment.

[0195] and, Figure 3A The drain pull-out region 58 of the semiconductor device 1 according to the first embodiment corresponds to the first drain pull-out region 58A and the second drain pull-out region 68A in the semiconductor device 1A according to the second embodiment.

[0196] A first drain lead-out region 58A of the first conductivity type is formed in the low-concentration impurity layer 33 of the first region A1A. The first drain lead-out region 58A includes first conductivity type impurities at a higher concentration than the first conductivity type impurities in the low-concentration impurity layer 33. Alternatively, the first drain lead-out region 58A may be formed in the low-concentration impurity layer 33 to a depth that reaches the semiconductor substrate 32.

[0197] The first drain electrode 51A is composed of a portion 52A and a portion 53A, and the portion 52A is connected to the first drain lead-out region 58A via the portion 53A.

[0198] Portion 52A of the first drain electrode 51A is a layer that is bonded to solder during reflow in face-down mounting. As a non-limiting example, it can be made of one or more metal materials including nickel, titanium, tungsten, and palladium. The surface of portion 52A can be plated with gold or other materials.

[0199] Portion 53A of the first drain electrode 51A is in contact with portion 52A and the first drain lead-out region 58A. Therefore, the first drain electrode 51A and the common drain region of transistors 10A and 20A are at the same potential. Furthermore, as a non-limiting example, the first drain electrode 51A can be made of one or more metal materials selected from aluminum, copper, gold, and silver.

[0200] like Figure 3A as well as Figure 12BAs shown, the low-concentration impurity layer 33 is covered by an interlayer insulating layer 34 having an opening, and a portion 53A of the first drain electrode 51A is provided, connected to the first drain lead-out region 58A through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 53A of the first drain electrode 51A are covered by a passivation layer 35 having an opening, and a portion 52A is provided, connected to the portion 53A of the first drain electrode 51A through the opening of the passivation layer 35.

[0201] Therefore, the first drain pad 151A refers to a region where the first drain electrode 51A is partially exposed on the surface of the semiconductor device 1A, and is a so-called terminal portion.

[0202] Similarly, a first-conductivity-type second drain lead-out region 68A containing first-conductivity-type impurities at a higher concentration than the first-conductivity-type impurities in the low-concentration impurity layer 33 is formed in the low-concentration impurity layer 33 in the second region A2A. Furthermore, the second drain lead-out region 68A may be formed in the low-concentration impurity layer 33 to a depth reaching the semiconductor substrate 32.

[0203] The second drain electrode 61A is composed of a portion 62A and a portion 63A, and the portion 62A is connected to the second drain lead-out region 68A via the portion 63A.

[0204] Portion 62A of the second drain electrode 61A is a layer that is bonded to solder during reflow in face-down mounting. As a non-limiting example, it can be made of one or more metal materials including nickel, titanium, tungsten, and palladium. The surface of portion 62A can be plated with gold or the like.

[0205] Portion 63A of the second drain electrode 61A is a layer connected to portion 62A and the second drain lead-out region 68A. Therefore, the second drain electrode 61A has the same potential as the common drain region of transistors 10A and 20A. Furthermore, as a non-limiting example, the second drain electrode 61A can be made of one or more metal materials selected from aluminum, copper, gold, and silver.

[0206] like Figure 3A as well as Figure 12B As shown, the low-concentration impurity layer 33 is covered by an interlayer insulating layer 34 having an opening, and a portion 63A of the second drain electrode 61A is provided, connected to the second drain lead-out region 68A through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 63A of the second drain electrode 61A are covered by a passivation layer 35 having an opening, and a portion 62A is provided, connected to the portion 63A of the second drain electrode 61A through the opening of the passivation layer 35.

[0207] Therefore, the second drain pad 161A refers to a region where the second drain electrode 61A is partially exposed on the surface of the semiconductor device 1A, and is a so-called terminal portion.

[0208] As Figure 1 , Figure 3A , Figure 12A indicated, the transistor 10A has a plurality of first source pads 111A, a first gate pad 119A, and a first drain pad 151A on the surface of the semiconductor layer 40 to be bonded to a mounting substrate via a bonding material at face-down mounting. Also, the transistor 20A has a plurality of second source pads 121A, a second gate pad 129A, and a second drain pad 161A on the surface of the semiconductor layer 40 to be bonded to a mounting substrate via a bonding material at face-down mounting.

[0209] As Figure 1 and Figure 12A indicated, in a plan view, the semiconductor device 1A and the semiconductor layer 40 are rectangular in shape. Also in Figure 12A , although the semiconductor device 1A and the semiconductor layer 40 are rectangular in shape, the semiconductor device 1A and the semiconductor layer 40 can be square.

[0210] In a plan view, a direction in which the first region A1A and the second region A2A in the direction parallel to the outer periphery of the semiconductor device 1A are arranged is set as a first direction. In a plan view, the first region A1A and the second region A2A arranged in the first direction means that the first region A1A and the second region A2A are in the most opposite state in the first direction.

[0211] The most opposite in the first direction means that, in a plan view, a portion of the boundary line 90C of the first region A1A and the second region A2A orthogonal to the first direction is the longest. For example, in a plan view, in the case where the boundary line 90C is curved, the boundary line 90C is divided into line segments constituting the boundary line 90C, and a direction orthogonal to the direction in which the sum of the line segments in the same direction becomes the longest becomes the first direction.

[0212] As Figure 12A indicated, in a plan view of the semiconductor layer 40, the first region A1A and the second region A2A are adjacent to each other, and are one of the two equal parts of the semiconductor layer 40 in area.

[0213] As Figure 12A indicated, the center line 90 is a line that bisects the semiconductor layer 40 in the first direction in a plan view of the semiconductor layer 40. Therefore, the center line 90 is a straight line in a plan view of the semiconductor layer 40 in a direction orthogonal to the first direction.

[0214] Furthermore, in a plan view of semiconductor layer 40 , the midpoint of a line segment connecting the center of first gate pad 119A of transistor 10A and the center of second gate pad 129A of transistor 20A is located on boundary line 90C of semiconductor device 1A.

[0215] Furthermore, in a plan view of semiconductor layer 40 , the midpoint of a line segment connecting the center of first drain pad 151A of transistor 10A and the center of second drain pad 161A of transistor 20A is located on boundary line 90C of semiconductor device 1A.

[0216] And as Figure 12A As shown, the first source pad 111A is arranged so that no portion is sandwiched between the first gate pad 119A and the first drain pad 151A. Therefore, the first gate pad 119A and the first drain pad 151A are arranged adjacent to each other.

[0217] Likewise, the second source pad 121A is arranged so that no portion is sandwiched between the second gate pad 129A and the second drain pad 161 A. Therefore, the second gate pad 129A and the second drain pad 161A are arranged adjacent to each other.

[0218] like Figure 12A As shown, in a plan view of semiconductor layer 40, first gate pad 119A and second gate pad 129A of semiconductor device 1A have the same shape and area. Also, first drain pad 151A and second drain pad 161A have the same shape and area.

[0219] In addition, Figure 12A As shown, the first gate pad 119A, the second gate pad 129A, the first drain pad 151A, and the second drain pad 161A may also have the same shape and the same area.

[0220] The main current and the main path of the semiconductor device 1A according to the second embodiment are the same as those of the semiconductor device 1 according to the first embodiment.

[0221] Figure 12B This is a cross-sectional view showing a secondary current flowing through the semiconductor device 1A. The secondary current of the semiconductor device 1A is similar to the secondary current of the semiconductor device 1 according to the first embodiment. This secondary current is controlled by an external switching element connected in series with the first drain electrode 51A and the second drain electrode 61A of the semiconductor device 1A, resulting in a current relatively smaller than the main current. The conduction path of the secondary current in the semiconductor device 1A is described below.

[0222] In the semiconductor device 1A, in a case where a high voltage is applied to the first source electrode 11 and a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, and an external switching element connected in series to the first drain electrode 51A and the second drain electrode 61A is made to be in an on state, a sub-current flows in a path of the first source electrode 11 - the first connecting portion 18a - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the first drain lead-out region 58A - the first drain electrode 51A, and the semiconductor device 1A becomes in an on state. In addition, a sub-current can also flow in a path of the first source electrode 11 - the first connecting portion 18a - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the second drain lead-out region 68A - the second drain electrode 61A at this time.

[0223] Also, in a case where a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, and an external switching element connected in series to the first drain electrode 51A and the second drain electrode 61A is made to be in an on state, a sub-current flows in a path of the second source electrode 21 - the second connecting portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the second drain lead-out region 68A - the second drain electrode 61A, and the semiconductor device 1A becomes in an on state. In addition, a sub-current can also flow in a path of the second source electrode 21 - the second connecting portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the first drain lead-out region 58A - the first drain electrode 51A at this time.

[0224] Also, in a case where a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, and an external switching element connected in series to the first drain electrode 51A and the second drain electrode 61A is made to be in an on state, a sub-current flows in a path of the second source electrode 21 - the second connecting portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the second drain lead-out region 68A - the second drain electrode 61A, and the semiconductor device 1A becomes in an on state. In addition, a sub-current can also flow in a path of the second source electrode 21 - the second connecting portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the first drain lead-out region 58A - the first drain electrode 51A at this time.

[0225] Also, in a case where a high voltage is applied to the second source electrode 21, a low voltage is applied to the first drain electrode 51A and the second drain electrode 61A, an external switching element is made to be in an on state, and a voltage of the threshold value or more is applied to the second gate electrode 29 from the second source electrode 21 as a reference, a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28, and a sub-current flows in a path from the second source electrode 21 - the second source region 24 - the conduction channel formed in the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 41 - the semiconductor substrate 32 - the low-concentration impurity layer 33, a path to the 2nd drain lead-out region 68A - the second drain electrode 61A, or a path to the 1st drain lead-out region 58A - the first drain electrode 51A, and the semiconductor device 1A becomes in an on state.

[0226] These conduction paths through which the sub-current flows are sub-paths of the semiconductor device 1A. The sub-paths of the semiconductor device 1A are controlled by making the external switching element connected in series with the first drain electrode 51A and the second drain electrode 61A to be in an on state or an off state. In a case where the switching element is in an on state, the sub-paths of the semiconductor device 1A become in an on state.

[0227] In a case where the main path is made to be in an on state, the external switching element connected in series with the first drain electrode 51A and the second drain electrode 61A is necessarily controlled to be in an off state, and thus the sub-paths become in an off state, and only the main path becomes in an on state.

[0228] In addition, Figure 12C is a plan view showing the positions of the first drain pad 151A and the first gate pad 119A to which the semiconductor layer 40 is attached. Figure 12A is a plan view showing the positions of the first drain pad 151A and the first gate pad 119A to which the semiconductor layer 40 is attached. Figure 12C is a plan view showing the positions of the first drain pad 151A and the first gate pad 119A to which the semiconductor layer 40 is attached.

[0229] The gate resistance element is electrically connected to the gate electrode, and is provided for a function of preventing a transistor from being destroyed when an excessive voltage is applied to the gate electrode and a protection function. That is, the gate resistance element is an element provided for improving ESD (ElectroStatic Discharge) resistance.

[0230] In addition, in the semiconductor device of the present disclosure, it is not necessary to provide the gate resistance element and the EQR, and the gate resistance element and the EQR can not be provided, and it does not matter.

[0231] In Figure 12C order to be able to easily show the configuration of the upper surface of the semiconductor layer 40, which is not actually visible, the passivation layer 35 and the interlayer insulating layer 34 are regarded as transparent and the illustration is omitted. Also, the illustration of the first source region 14 and the first drain lead-out region 58A is omitted.

[0232] Although the illustration is omitted, the portion 23 of the second source electrode 21, the portion 63A of the second drain electrode 61A, the second drain pad 161A, the second gate electrode 29, the second gate pad 129A, the second EQR, and the second gate resistance element, like the portion 13 of the first source electrode 11, the portion 53A of the first drain electrode 51A, the first drain pad 151A, the first gate electrode 19, the first gate pad 119A, the first EQR, and the first gate resistance element shown in FIG. 1, become a linearly symmetrical shape with the center line 90 as the axis of symmetry. Figure 12C

[0233] The area directly below the first drain electrode 51A and the area near it, and the area directly below the second drain electrode 61A and the area near it are areas that do not contribute to the conduction of the main path. The area near it here refers to the area along the outer periphery of the first drain electrode 51A and the second drain electrode 61A, and can also be said to be the area in the vicinity of the outer periphery of the first drain electrode 51A and the second drain electrode 61A. Figure 12C

[0234] That is, the area directly below the first gate electrode 19 and the area near it, the area directly below the first drain electrode 51A and the area near it, the area directly below the second gate electrode 29 and the area near it, and the area directly below the second drain electrode 61A and the area near it, although being areas necessary for the semiconductor device 1A to function, are areas that are desired to be as small as possible in order to reduce the conduction resistance of the main path of the semiconductor device 1A in the limited device area.

[0235] In addition, as shown in FIG. 2, in the plan view of the semiconductor layer 40, the first gate resistance element can also be arranged between the first gate pad 119A and the first drain pad 151A. Also, the portion 53A of the first drain electrode 51A and the first EQR can be directly connected. Figure 12C

[0236] Although the illustration is omitted, similarly in the plan view of the semiconductor layer 40, the second gate resistance element can also be arranged between the second gate pad 129A and the second drain pad 161A. Also, the portion 63A of the second drain electrode 61A and the second EQR can be directly connected.​​​

[0237] The features of the semiconductor device 1A in the present disclosure described above are as shown below.

[0238] The semiconductor device 1A according to one embodiment of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10A formed in a first region A1A when the semiconductor substrate 32 and the low-concentration impurity layer 33 are taken together as a semiconductor layer 40; a second vertical MOS transistor 20A formed in a second region A2A that is a region adjacent to the first region A1A in a plan view of the semiconductor layer 40; a plurality of first source pads 111A formed in the first region A1A in the plan view and connected to first source electrodes 11 of the first vertical MOS transistor 10A; a first gate pad 119A formed in the first region A1A in the plan view and connected to a first gate electrode 19 of the first vertical MOS transistor 10A; a first drain pad 151A formed in the first region A1A in the plan view and connected to a first drain electrode 51A of the first vertical MOS transistor 10A; a plurality of second source pads 121A formed in the second region A2A in the plan view and connected to second source electrodes 21 of the second vertical MOS transistor 20A; a second gate pad 129A formed in the second region A2A in the plan view and connected to a second gate electrode 29 of the second vertical MOS transistor 20A; a second drain pad 161A formed in the second region A2A in the plan view and connected to a second drain electrode 61A of the second vertical MOS transistor 20A; and a metal layer 41 formed in contact with a back surface of the semiconductor substrate 32, the semiconductor substrate 32 being a common drain region of the first vertical MOS transistor 10A and the second vertical MOS transistor 20A, the semiconductor layer 40 being rectangular in the plan view, the first region A1A and the second region A2A being one side and the other side that bisect the semiconductor layer 40 in area in the plan view, a midpoint of a line segment connecting a center of the first gate pad 119A and a center of the second gate pad 129A being located on a boundary line 90C between the first region A1A and the second region A2A in the plan view, a midpoint of a line segment connecting a center of the first drain pad 151A and a center of the second drain pad 161A being located on the boundary line 90C in the plan view, the first source pads 111A being arranged so that none of them is sandwiched between the first gate pad 119A and the first drain pad 151A, and the second source pads 121A being arranged so that none of them is sandwiched between the second gate pad 129A and the second drain pad 161A.

[0239] Figure 13A-13C 、 Figure 14A-14D 、 Figure 15A 、 Figure 15B 、 Figure 16A-16D It is a plan view showing an example of arrangement of pads that satisfies the conditions of the semiconductor device 1A according to the second embodiment.

[0240] With the above configuration, in a plan view of semiconductor layer 40, first gate pad 119A and first drain pad 151A are positioned adjacent to each other, and second gate pad 129A and second drain pad 161A are positioned adjacent to each other. Although the areas surrounding first gate pad 119A and first drain pad 151A are first active region 112, they are regions where the current density of the main current is relatively low. Therefore, by positioning first gate pad 119A and first drain pad 151A adjacent to each other, the effectively usable area of ​​first active region 112 can be expanded compared to when they are positioned apart. Similarly, by positioning second gate pad 129A and second drain pad 161A adjacent to each other, the effectively usable area of ​​second active region 122 can be expanded compared to when they are positioned apart. Consequently, the increase in on-resistance of the main path caused by the provision of the secondary path can be minimized.

[0241] Furthermore, in a plan view of semiconductor layer 40, first gate pad 119A and second gate pad 129A, as well as first drain pad 151A and second drain pad 161A, can be arranged in line symmetry with boundary line 90C as an axis of symmetry, or in point symmetry with the center of semiconductor layer 40 as a center of symmetry. Because first gate pad 119A, first drain pad 151A, second gate pad 129A, and second drain pad 161A can be arranged in this manner, even with the provision of a secondary path, it is unlikely to prevent first active region 112 and second active region 122 from having the same area and shape. Consequently, there is less bias in the electrical characteristics and heat dissipation of bidirectional conduction between transistors 10A and 20A.

[0242] like Figure 14A-14D As shown, the first drain pad 151A and the first gate pad 119A can be arranged in a direction parallel to the boundary line 90C, and the first drain pad 151A can be configured so that no part of other pads is sandwiched between the first drain pad 151A and the edge of the outer periphery of the semiconductor layer 40 closest to the first drain pad 151A.

[0243] Similarly, the second drain pad 161A and the second gate pad 129A can be arranged in a direction parallel to the boundary line 90C, and the second drain pad 161A can be configured so that no portion of other pads is sandwiched between the second drain pad 161A and the edge of the outer periphery of the semiconductor layer 40 closest to the second drain pad 161A.

[0244] Through the above-mentioned configuration, in the planar view of the semiconductor layer 40, the first drain pad 151A, the first gate pad 119A, the second drain pad 161A, and the second gate pad 129A can be arranged close to the outer periphery of the semiconductor layer 40. Therefore, compared with the case where the first drain pad 151A, the first gate pad 119A, the second drain pad 161A, and the second gate pad 129A are arranged in the center of the semiconductor layer 40, the possibility of poor bonding with the solder due to warping of the semiconductor device 1A can be reduced.

[0245] like Figure 14A As shown, for example, the arrangement of first drain pad 151A and first gate pad 119A, and the arrangement of second drain pad 161A and second gate pad 129A may be reversed. In this case, although first gate pad 119A and second gate pad 129A, as well as first drain pad 151A and second drain pad 161A, are not arranged in line symmetry with boundary line 90C as the axis of symmetry, they can be arranged in point symmetry with the center of semiconductor layer 40 as the center of symmetry.

[0246] In addition, the first drain pad 151A and the second drain pad 161A are not Figure 14A-14D It is limited by the circle shown. It can also be Figure 15A The generally rectangular shape shown.

[0247] like Figure 15A as well as Figure 15B As shown, the first drain pad 151A and the first gate pad 119A can be configured to be arranged in a direction orthogonal to the boundary line 90C, the second drain pad 161A and the second gate pad 129A can be configured to be arranged in a direction orthogonal to the boundary line 90C, and the midpoint of the line segment connecting the center of the first drain pad 151A and the center of the second drain pad 161A can be consistent with the center of the semiconductor layer 40.

[0248] With the above configuration, the first drain pad 151A and the second drain pad 161A can be configured to be linearly symmetrical with the boundary line 90C as an axis of symmetry, and the bias in the electrical characteristics of bidirectional conduction between the transistor 10A and the transistor 20A and the heat dissipation can be reduced. Also, since at least a part of the first direction in which the main current flows can overlap, compared to the case where the first drain pad 151A and the first gate pad 119A are arranged in a direction parallel to the boundary line 90C, the first drain pad 151A and the first gate pad 119A can be reduced as factors that hinder the main current.

[0249] Also, as shown in Figure 16A-16D , the first drain pad 151A can be configured to be a first strip shape that is equally spaced from the plurality of first source pads 111A, the first drain pad 151A and the plurality of first source pads 111A can have the same width in a direction in which the first strip shape is configured, the second drain pad 161A can be configured to be a second strip shape that is equally spaced from the plurality of second source pads 121A, and the second drain pad 161A and the plurality of second source pads 121A can have the same width in a direction in which the second strip shape is configured. Also, the first strip shape and the second strip shape can be the same strip shape.

[0250] In the above configuration, one of the plurality of first source pads 111A can be replaced with the first drain pad 151A, and one of the plurality of second source pads 121A can be replaced with the second drain pad 161A. Therefore, in a case where the usage method is changed from a usage method in which the sub path is not required to a usage method in which the sub path is required, the semiconductor device 1A can be used without making a large change in the configuration of the wiring of the mounting substrate.

[0251] (Embodiment 3)

[0252] The semiconductor device 1B related to Embodiment 3, which is obtained by changing a part of the semiconductor device 1A related to Embodiment 2, will be described below. With respect to the configuration elements of the semiconductor device 1B related to this Embodiment 3 that are the same as those of the semiconductor device 1A, the same symbols are given as the already described configuration elements, and detailed description will be omitted, and the following description will be centered on the differences from the semiconductor device 1A.

[0253] Figure 17A is a plan view showing one example of the configuration of the pads of the semiconductor device 1B related to Embodiment 3, and the sizes and shapes other than the semiconductor device 1B being rectangular are one example. Also, the sizes, shapes, and configuration of the pads are one example. Figure 17A the cross section at I-I of Figure 1 is equivalent. Also, Figure 17A the cross section at II- II ofFigure 3A Likewise, the components of the semiconductor device 1B according to the third embodiment are the same as those of the semiconductor device 1A according to the second embodiment.

[0254] like Figure 17A as well as Figure 1 As shown, the semiconductor device 1B includes a semiconductor layer 40 , a metal layer 41 , a transistor 10A formed in a first region A1A within the semiconductor layer 40 , and a transistor 20A formed in a second region A2A within the semiconductor layer 40 .

[0255] The components of the transistor 10A and the transistor 20A of the semiconductor device 1B according to the third embodiment are the same as the components of the transistor 10A and the transistor 20A described in the semiconductor device 1A according to the second embodiment.

[0256] like Figure 17A As shown, in a plan view of the semiconductor layer 40 , the first region A1A and the second region A2A are adjacent to each other and are one side and the other side that divide the semiconductor layer 40 into two equal parts in terms of area.

[0257] And in Figure 17A In order to distinguish the first area A1A and the second area A2A of the semiconductor layer 40 , a virtual boundary line 90C is indicated by a dotted line.

[0258] like Figure 17A As shown, in a plan view of semiconductor layer 40 , the midpoint of a line segment connecting the center of first drain pad 151A and the center of second drain pad 161A is located on boundary line 90C of semiconductor device 1B.

[0259] In addition, Figure 17A As shown in the example of the semiconductor device 1B shown, the midpoint of the line segment connecting the center of the first gate pad 119A and the center of the second gate pad 129A may be located on the boundary line 90C of the semiconductor device 1B.

[0260] Furthermore, in a plan view of the semiconductor layer 40 , a portion of the plurality of first source pads 111A may be disposed between the first drain pad 151A and the boundary line 90C.

[0261] Likewise, in a plan view of the semiconductor layer 40 , a portion of the plurality of second source pads 121A may be disposed between the second drain pad 161A and the boundary line 90C.

[0262] The main current and the main path of the semiconductor device 1B according to the third embodiment are the same as those of the semiconductor device 1 according to the first embodiment.

[0263] Also, the semiconductor device 1B according to Embodiment 3 has the same sub current and sub path as the semiconductor device 1A according to Embodiment 2.

[0264] The features of the semiconductor device 1B according to the present disclosure described above are as follows.

[0265] The semiconductor device 1B according to one embodiment of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes a semiconductor substrate 32, a low-concentration impurity layer 33 formed on the semiconductor substrate 32, a first vertical MOS transistor 10A formed in a first region A1A of a semiconductor layer 40 including the semiconductor substrate 32 and the low-concentration impurity layer 33, a second vertical MOS transistor 20A formed in a second region A2A adjacent to the first region A1A in a plan view of the semiconductor layer 40, a plurality of first source pads 111A formed in the first region A1A in the plan view and connected to first source electrodes 11 of the first vertical MOS transistor 10A, a first gate pad 119A formed in the first region A1A in the plan view and connected to a first gate electrode 19 of the first vertical MOS transistor 10A, a first drain pad 151A formed in the first region A1A in the plan view and connected to a first drain electrode 51A of the first vertical MOS transistor 10A, a plurality of second source pads 121A formed in the second region A2A in the plan view and connected to second source electrodes 21 of the second vertical MOS transistor 20A, a second gate pad 129A formed in the second region A2A in the plan view and connected to a second gate electrode 29 of the second vertical MOS transistor 20A, a second drain pad 161A formed in the second region A2A in the plan view and connected to a second drain electrode 61A of the second vertical MOS transistor 20A, and a metal layer 41 formed in contact with a back surface of the semiconductor substrate 32, which is a common drain region of the first vertical MOS transistor 10A and the second vertical MOS transistor 20A, wherein the semiconductor layer 40 is rectangular in the plan view, the first region A1A and the second region A2A are one side and the other side that bisect the semiconductor layer 40 in area in the plan view, a midpoint of a line segment connecting a center of the first drain pad 151A and a center of the second drain pad 161A is located on a boundary line 90C between the first region A1A and the second region A2A in the plan view, at least a part of the plurality of first source pads 111A is arranged to be sandwiched between the first drain pad 151A and the boundary line 90C in the plan view, and at least a part of the plurality of second source pads 121A is arranged to be sandwiched between the second drain pad 161A and the boundary line 90C in the plan view.

[0266] Figure 17B-17D 、 Figure 18A and Figure 18B is a plan view showing a configuration example of pads satisfying the condition of the semiconductor device IB related to Embodiment 3.

[0267] With the above configuration, in a plan view of the semiconductor layer 40, at least a part of the plurality of first source pads 111A and at least a part of the plurality of second source pads 121A are configured so as not to sandwich the first drain pad 151A and the second drain pad 161A between the plurality of first source pads 111A and the plurality of second source pads 121A and the boundary line 90C. Accordingly, compared to a case where the first drain pad 151A and the second drain pad 161A are configured in the vicinity of the boundary line 90C where the current density of the main current is the highest, since the flow of the main current is not hindered, it is possible to suppress the increase in the on-resistance on the main path due to the provision of the sub-path as much as possible.

[0268] Especially in Figure 17A 、 Figure 17C , the first source pad 111A and the second source pad 121A are disposed opposite to each other in such a manner that no other pad is sandwiched therebetween in the range along the entire length of the boundary line 90C, and thus it is effective for reducing the on-resistance of the main path.

[0269] As shown in Figure 18A and Figure 18B , in a plan view of the semiconductor layer 40, the first drain pad 151A can be configured at a position closest to a corner portion formed by two edges intersecting among four edges constituting the outer periphery of the semiconductor layer 40, and the second drain pad 161A can be configured at a position closest to another corner portion opposite to the corner portion of the semiconductor layer 40 where the first drain pad 151A is configured, on a diagonal line.

[0270] With the above configuration, since it is possible to configure the first drain pad 151A and the second drain pad 161A at a position closest to the outer peripheral portion of the semiconductor layer 40, compared to a case where the first drain pad 151A and the second drain pad 161A are configured at a central portion of the semiconductor layer 40, it is possible to reduce the possibility of a failure in the joining with solder due to warping of the semiconductor device IB.

[0271] Industrial applicability

[0272] The semiconductor device provided with the vertical MOS transistor related to the present application can be widely utilized as a device that controls the on-state of a current path.

[0273] Explanation of reference numerals

[0274] 1, 1A, 1B, 2 semiconductor device

[0275] 4 control IC

[0276] 5 lithium ion battery

[0277] 6 load

[0278] 10, 10A transistor (first vertical MOS transistor)

[0279] 11 first source electrode

[0280] 12, 13 portion

[0281] 14 first source region

[0282] 15 first gate conductor

[0283] 16 first gate insulating film

[0284] 17 first gate trench

[0285] 18 first body region

[0286] 18a first connection portion

[0287] 19 first gate electrode

[0288] 20, 20A transistor (second vertical MOS transistor)

[0289] 21 second source electrode

[0290] 22, 23 portion

[0291] 24 second source region

[0292] 25 second gate conductor

[0293] 26 second gate insulating film

[0294] 27 second gate trench

[0295] 28 second body region

[0296] 28a second connection portion

[0297] 29 second gate electrode

[0298] 30 transistor (third vertical MOS transistor)

[0299] 31 third source electrode

[0300] 32 semiconductor substrate

[0301] 33 low concentration impurity layer

[0302] 34 interlayer insulating layer

[0303] 35 passivation layer

[0304] 39 third gate electrode

[0305] 40 semiconductor layer

[0306] 41 metal layer

[0307] 51 drain electrode

[0308] 52, 53 portion

[0309] 58 drain lead-out region

[0310] 51A first drain electrode

[0311] 52A, 53A portion

[0312] 58A first drain lead-out region

[0313] 61A second drain electrode

[0314] 62A, 63A portion

[0315] 68A second drain lead-out region

[0316] 90 center line

[0317] 90C boundary line

[0318] 111, 111A, 111a-111f first source pad

[0319] 112 first active region

[0320] 119, 119A first gate pad

[0321] 121, 121A, 121a-121f second source pad

[0322] 122 second active region

[0323] 129, 129A second gate pad

[0324] 131 third source pad

[0325] 139 third gate pad

[0326] 151 drain pad

[0327] 151A first drain pad

[0328] 161A second drain pad

[0329] A1, A1A first region

[0330] A2, A2A second region

[0331] A3 third region

[0332] C1 charging current

[0333] C2 discharging current

[0334] C3 relatively small charging current

[0335] S1 external switching element

Claims

1. A semiconductor device, which is a chip-size package type semiconductor device capable of face-down mounting, comprising: semiconductor substrates; a low-concentration impurity layer formed on the semiconductor substrate; When the semiconductor substrate and the low-concentration impurity layer are used together as a semiconductor layer, A first vertical MOS transistor is formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region, the second region being a region adjacent to the first region in a planar view of the semiconductor layer; a plurality of first source pads formed in the first region in the plan view and connected to the first source electrode of the first vertical MOS transistor; a first gate pad formed in the first region in the plan view and connected to the first gate electrode of the first vertical MOS transistor; a plurality of second source pads formed in the second region in the plan view and connected to the second source electrode of the second vertical MOS transistor; a second gate pad formed in the second region in the plan view and connected to the second gate electrode of the second vertical MOS transistor; and a metal layer formed in contact with the back surface of the semiconductor substrate, The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. In the plan view, the semiconductor layer is rectangular, In the plan view, the first vertical MOS transistor and the second vertical MOS transistor are arranged in a first direction, In the plan view, the semiconductor layer has a third region that does not overlap with the first region and the second region. In the plan view, the first region and the second region are one side and the other side that divide the region of the semiconductor layer excluding the third region into two equal parts in terms of area. In the plan view, the center of the third region is located on a center line, which is a straight line that bisects the semiconductor layer in the first direction and is perpendicular to the first direction. In the plan view, the semiconductor layer includes a drain pad connected to the common drain region. In the plan view, the drain pad is arranged so as to be surrounded by the third region.

2. The semiconductor device according to claim 1, In the plan view, the third region is arranged so that the first region and the second region are not sandwiched between the third region and a side of the outer periphery of the semiconductor layer that is parallel to the first direction and closest to the third region.

3. The semiconductor device according to claim 1, In the plan view, the center of the third region coincides with the center of the semiconductor layer.

4. The semiconductor device according to claim 3, In the plan view, the first gate pad, the second gate pad, and the drain pad are circular with the same diameter and are pads with the smallest areas among the pads included in the semiconductor layer.

5. The semiconductor device according to claim 3, In the plan view, the first gate pad and the second gate pad are circles with the same diameter, and the first gate pad, the second gate pad, and the drain pad are located in the same strip region.

6. The semiconductor device according to claim 3, In the plan view, the drain pad is rectangular, a length direction of the drain pad is parallel to the center line, and a length direction of the drain pad is parallel to a long side direction of the semiconductor layer.

7. A semiconductor device, which is a chip-size package type semiconductor device capable of face-down mounting, comprising: semiconductor substrates; a low-concentration impurity layer formed on the semiconductor substrate; When the semiconductor substrate and the low-concentration impurity layer are used together as a semiconductor layer, A first vertical MOS transistor is formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region, the second region being a region adjacent to the first region in a planar view of the semiconductor layer; a plurality of first source pads formed in the first region in the plan view and connected to the first source electrode of the first vertical MOS transistor; a first gate pad formed in the first region in the plan view and connected to the first gate electrode of the first vertical MOS transistor; a first drain pad formed in the first region in the plan view and connected to the first drain electrode of the first vertical MOS transistor; a plurality of second source pads formed in the second region in the plan view and connected to the second source electrode of the second vertical MOS transistor; a second gate pad formed in the second region in the plan view and connected to the second gate electrode of the second vertical MOS transistor; a second drain pad formed in the second region in the plan view and connected to the second drain electrode of the second vertical MOS transistor; as well as a metal layer formed in contact with the back surface of the semiconductor substrate, The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. In the plan view, the semiconductor layer is rectangular, In the plan view, the first region and the second region are one side and the other side that divide the semiconductor layer into two equal parts in terms of area. In the plan view, a midpoint of a line segment connecting the center of the first gate pad and the center of the second gate pad is located on a boundary line between the first region and the second region. In the plan view, the midpoint of a line segment connecting the center of the first drain pad and the center of the second drain pad is located on the boundary line. The plurality of first source pads are arranged so that no portion thereof is sandwiched between the first gate pad and the first drain pad. The plurality of second source pads are arranged such that no portion is sandwiched between the second gate pad and the second drain pad.

8. The semiconductor device according to claim 7, In the plan view, the first gate pad and the first drain pad are arranged in a direction parallel to the boundary line, and the first drain pad is arranged so that no portion of other pads is sandwiched between the first drain pad and the side closest to the first drain pad among the outer periphery of the semiconductor layer. In the plan view, the second gate pad and the second drain pad are arranged in a direction parallel to the boundary line, and the second drain pad is configured so that no part of other pads is sandwiched between the second drain pad and the edge closest to the second drain pad among the outer periphery of the semiconductor layer.

9. The semiconductor device according to claim 7, In the plan view, the first gate pad and the first drain pad are arranged in a direction orthogonal to the boundary line, In the plan view, the second gate pad and the second drain pad are arranged in a direction orthogonal to the boundary line, In the plan view, a midpoint of a line segment connecting a center of the first drain pad and a center of the second drain pad coincides with a center of the semiconductor layer.

10. The semiconductor device according to claim 7, In the plan view, the first drain pad and the plurality of first source pads are arranged in a first strip shape with equal intervals. In the direction of forming the first strip, the first drain pad and the plurality of first source pads have the same width. In the plan view, the second drain pad and the plurality of second source pads are arranged in a second strip shape with equal intervals. In a direction of forming the second stripe shape, the second drain pad and the plurality of second source pads have the same width.

11. A semiconductor device, which is a chip-size package type semiconductor device capable of face-down mounting, comprising: semiconductor substrates; a low-concentration impurity layer formed on the semiconductor substrate; When the semiconductor substrate and the low-concentration impurity layer are used together as a semiconductor layer, A first vertical MOS transistor is formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region, the second region being a region adjacent to the first region in a planar view of the semiconductor layer; a plurality of first source pads formed in the first region in the plan view and connected to the first source electrode of the first vertical MOS transistor; a first gate pad formed in the first region in the plan view and connected to the first gate electrode of the first vertical MOS transistor; a first drain pad formed in the first region in the plan view and connected to the first drain electrode of the first vertical MOS transistor; a plurality of second source pads formed in the second region in the plan view and connected to the second source electrode of the second vertical MOS transistor; a second gate pad formed in the second region in the plan view and connected to the second gate electrode of the second vertical MOS transistor; a second drain pad formed in the second region in the plan view and connected to the second drain electrode of the second vertical MOS transistor; as well as a metal layer formed in contact with the back surface of the semiconductor substrate, The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. In the plan view, the semiconductor layer is rectangular, In the plan view, the first region and the second region are one side and the other side that divide the semiconductor layer into two equal parts in terms of area. In the plan view, the midpoint of a line segment connecting the center of the first drain pad and the center of the second drain pad is located on a boundary line between the first region and the second region. In the plan view, the plurality of first source pads are arranged so that at least a portion is sandwiched between the first drain pad and the boundary line. In the plan view, the plurality of second source pads are arranged so that at least a portion is sandwiched between the second drain pad and the boundary line.

12. The semiconductor device according to claim 11, In the plan view, the first drain pad is arranged so as to be closest to a corner formed by two intersecting sides among four sides constituting the outer periphery of the semiconductor layer. In the plan view, the second drain pad is arranged closest to another corner that is diagonally opposite to the corner of the semiconductor layer, the corner being the corner to which the first drain pad is arranged closest.

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