Circuits with recessed gate transistors and methods of forming the same

Abstract

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit having recessed gate transistors. The peripheral circuits also include a second peripheral circuit having planar gate transistors.

Description

[0001] This application is a divisional application of International Patent Application No. PCT / CN2021 / 103603, filed on June 30, 2021, which entered the Chinese national phase on September 10, 2021, and which claims priority to U.S. Patent Application No. 63 / 271, 1 10, filed on October 1, 2021, the entire disclosure of which is hereby incorporated by reference herein. TECHNICAL FIELD

[0002] The present disclosure relates to memory devices and methods of manufacturing the same. BACKGROUND

[0003] Planar memory cells have been scaled to smaller and smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become more challenging and expensive. As a result, the storage density of planar memory cells approaches an upper limit.

[0004] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral circuits to facilitate operation of the memory array. SUMMARY

[0005] In one aspect, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit having recessed gate transistors. The peripheral circuits also include a second peripheral circuit having planar gate transistors.

[0006] In another aspect, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonded interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of NAND memory strings. The second semiconductor structure includes a page buffer having recessed gate transistors. The array of NAND memory strings is coupled to the page buffer across the bonded interface.

[0007] In yet another aspect, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first well in the substrate and having a recess, a recessed gate structure protruding into the recess of the first well, and a source and a drain separated by the recessed gate structure. The recessed gate structure includes a first gate dielectric and a first gate electrode on the first gate dielectric. The second transistor includes a second well in the substrate, a planar gate structure on the second well, and a second source and a second drain. The planar gate structure includes a second gate dielectric and a second gate electrode on the second gate dielectric.

[0008] In yet another aspect, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit having a recessed gate transistor. The peripheral circuits also include a second peripheral circuit having a planar gate transistor. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the relevant art to make and use the present disclosure.

[0010] Figure 1A A schematic diagram of a cross-section of an exemplary 3D memory device is shown in accordance with some aspects of the present disclosure.

[0011] Figure 1B A schematic diagram of a cross-section of another exemplary 3D memory device is shown in accordance with some aspects of the present disclosure.

[0012] Figure 2 A schematic circuit diagram of an exemplary memory device including a peripheral circuit having a page buffer is shown in accordance with some aspects of the present disclosure.

[0013] Figure 3 A block diagram of an exemplary memory device including an array of memory cells and a peripheral circuit is shown in accordance with some aspects of the present disclosure.

[0014] Figure 4 A schematic plan view of an exemplary memory device having a plurality of planes and a page buffer is shown in accordance with some aspects of the present disclosure.

[0015] Figure 5 A schematic plan view of an exemplary memory device having an array of memory cells and a peripheral circuit including a page buffer is shown in accordance with some aspects of the present disclosure.

[0016] Figure 6A A plan view and a side view of a cross-section of an exemplary planar gate transistor is shown in accordance with some aspects of the present disclosure.

[0017] Figure 6B A plan view and a side view of a cross-section of an exemplary recessed gate transistor is shown in accordance with some aspects of the present disclosure.

[0018] Figure 7 A side view of a cross-section of an exemplary semiconductor device having a recessed gate transistor and a planar gate transistor is shown in accordance with some aspects of the present disclosure.

[0019] Figure 8A A side view of a cross-section of an exemplary 3D memory device is shown, in accordance with some embodiments.

[0020] Figure 8B A side view of a cross-section of another exemplary 3D memory device is shown, in accordance with some embodiments.

[0021] Figure 8C A side view of a cross-section of yet another exemplary 3D memory device is shown, in accordance with some embodiments.

[0022] Figure 8D A side view of a cross-section of yet another exemplary 3D memory device is shown, in accordance with some embodiments.

[0023] Figure 9A FIG. 9J illustrates a manufacturing process for forming an exemplary semiconductor device having recessed gate transistors and planar gate transistors, in accordance with some aspects of the present disclosure.

[0024] Figure 10 FIG. 9K illustrates a flow diagram of a method for forming an exemplary 3D memory device, in accordance with some aspects of the present disclosure.

[0025] Figure 11 FIG. 9L illustrates a flow diagram of a method for forming an exemplary semiconductor device having recessed gate transistors and planar gate transistors, in accordance with some aspects of the present disclosure.

[0026] Figure 12 FIG. 9M illustrates a block diagram of an exemplary system having a memory device, in accordance with some aspects of the present disclosure.

[0027] Figure 13A FIG. 9N illustrates a diagram of an exemplary memory card having a memory device, in accordance with some aspects of the present disclosure.

[0028] Figure 13B FIG. 9O illustrates a diagram of an exemplary solid state drive (SSD) having a memory device, in accordance with some aspects of the present disclosure.

[0029] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0030] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the present disclosure. Moreover, the present disclosure can also be employed in various other applications. The described features and structural or functional aspects of the present disclosure can be combined in other ways without departing from the scope of the present disclosure.

[0031] In general, terminology can be understood at least in part from an ordinary sense of the corresponding terminology as skilled in the relevant art, and / or as understood by a person without skill in the art who nevertheless can be competent to use particular terminology. For example, and as used herein, the term "or" as used herein, can be understood as a disjunctive word meaning either "and" or "or," depending on the context. Similarly, the words "comprise," "comprises," "comprising," "include," "includes," and "including" as used herein, can be understood as meaning "comprising," and thus do not exclude additional steps or features. Also, as used herein, the indefinite articles "a" and "an" can be understood to mean "one or more" unless the context clearly indicates otherwise.

[0032] It will be readily understood that the terms "on," "above," and "over," when used in the present disclosure, shall not mean "directly on," but shall also include the meanings of "on," "above," and "over," with intervening features or layers, as well as the meanings of "on," "above," and "over," without intervening features or layers (i.e., "directly on").

[0033] In addition, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0034] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer, etc.

[0035] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a scope less than the scope of the underlying or overlying structure. Additionally, a layer can be a region of a continuous structure that is uniform or non-uniform in composition, having a thickness less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes between a top surface and a bottom surface of the continuous structure, or at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, thereabove, and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (within which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0036] As 3D memory devices (e.g., 3D NAND flash memory devices) are developed, more stacked layers (e.g., word lines) require more peripheral circuitry to operate the 3D memory device. In particular, the number and / or size of page buffers must be increased to match the increased number of memory cells. In some cases, in 3D NAND flash memory, the page buffers can dominate the chip area, e.g., more than 50% of the total chip area. Moreover, in some 3D memory devices where the memory cell array and the peripheral circuitry are fabricated on different substrates and bonded together, the continued increase in peripheral circuitry area, especially page buffer area, becomes a bottleneck to reducing the overall chip size.

[0037] One way to reduce the size of the peripheral circuitry is to reduce the transistor area by reducing the gate width and length, however doing so can result in degradation of channel leakage, thereby limiting the percentage of device area reduction. Thus, it has become increasingly challenging to reduce the peripheral circuitry in 3D memory devices without sacrificing too much performance.

[0038] To address the foregoing issues, the present disclosure introduces a solution in which recessed gate transistors are used in place of planar gate transistors in forming some of the peripheral circuitry in a memory device (e.g., a 3D NAND flash memory device). That is, the peripheral circuitry can have a mixed type of transistors (both recessed gate transistors and planar gate transistors), which can balance device size reduction and performance degradation. In some implementations, in accordance with the scope of the present disclosure, the page buffer (a chip-size dominant factor) has recessed gate transistors instead of planar gate transistors, thereby reducing device size while maintaining comparable or even better device leakage performance. The peripheral circuitry other than the page buffer can still use planar gate transistors, which can reduce manufacturing complexity and device structure and performance variations compared to using recessed gate transistors.

[0039] Figure 1A A schematic diagram of a cross-section of an exemplary 3D memory device 100 is shown in accordance with some aspects of the present disclosure. The 3D memory device 100 represents an example of a bonded chip. The components of the 3D memory device 100 (e.g., the memory cell array and the peripheral circuitry) can be formed separately on different substrates and then bonded to form the bonded chip. The 3D memory device 100 can include a first semiconductor structure 102 having an array of memory cells (memory cell array). In some implementations, the memory cell array includes an array of NAND flash memory cells. For ease of description, the memory cell array in the present disclosure can be described using a NAND flash memory cell array as an example. However, it should be understood that the memory cell array is not limited to a NAND flash memory cell array and can include any other appropriate type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name a few examples.

[0040] The first semiconductor structure 102 can be a NAND flash memory device in which the memory cells are provided in the form of an array of 3D NAND memory strings and / or an array of two-dimensional (2D) NAND memory cells. The NAND memory cells can be organized into pages, which in turn are organized into blocks, with each NAND memory cell electrically connected to a separate line called a bit line (BL). All cells in the NAND memory cells that have the same vertical position can be electrically connected by a word line (WL) via a control gate. In some implementations, one plane contains a certain number of blocks electrically connected by the same bit line. The first semiconductor structure 102 can include one or more planes, and the peripheral circuitry needed to perform all read / write / erase operations can be included in the second semiconductor structure 104.

[0041] In some embodiments, the array of NAND memory cells is an array of 2D NAND memory cells, each of which includes a floating-gate transistor. According to some embodiments, the array of 2D NAND memory cells includes multiple 2D NAND memory strings, each of which includes multiple series-connected (similar to NAND gates) memory cells (e.g., 32 to 128 memory cells) and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (in 2D). In some embodiments, the array of NAND memory cells is an array of 3D NAND memory strings, each of which extends vertically through the memory stack above the substrate (in 3D). Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), a 3D NAND memory string typically includes 32 to 256 NAND memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor.

[0042] like Figure 1A As shown, the 3D memory device 100 may further include a second semiconductor structure 104, which includes peripheral circuitry for the memory cell array of the first semiconductor structure 102. The peripheral circuitry (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry to facilitate the operation of the memory cell array. For example, the peripheral circuitry may include one or more of a page buffer, a decoder (e.g., a row decoder or column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of the circuitry (e.g., a transistor, diode, resistor, or capacitor). In some embodiments, the peripheral circuitry in the second semiconductor structure 104 uses metal-oxide-semiconductor (MOS) technology, which may be implemented using advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.) to achieve high speeds. It should be understood that, in some examples, other processing units (also referred to as "logic circuits") besides peripheral circuits, such as memory controllers or processors, may also be formed in the second semiconductor structure 104. It should also be understood that the second semiconductor structure 104 may also include other memory devices compatible with the manufacturing process of the logic circuits (e.g., using MOS technology), such as static random access memory (SRAM) and dynamic random access memory (DRAM).

[0043] As shown in FIG. 1, the 3D memory device 100 includes a first semiconductor structure 102 and a second semiconductor structure 104. The first semiconductor structure 102 includes a memory array 108 and a first peripheral circuit 110. The second semiconductor structure 104 includes a second peripheral circuit 112. The first semiconductor structure 102 and the second semiconductor structure 104 are bonded together at a bonding interface 106. The first semiconductor structure 102 and the second semiconductor structure 104 are vertically integrated, and the memory array 108 and the first peripheral circuit 110 of the first semiconductor structure 102 are electrically connected to the second peripheral circuit 112 of the second semiconductor structure 104 through a plurality of interconnects (e.g., bond contacts) across the bonding interface 106. Figure 1A As shown in FIG. 1, the 3D memory device 100 includes a first semiconductor structure 102 and a second semiconductor structure 104. The first semiconductor structure 102 includes a memory array 108 and a first peripheral circuit 110. The second semiconductor structure 104 includes a second peripheral circuit 112. The first semiconductor structure 102 and the second semiconductor structure 104 are bonded together at a bonding interface 106. The first semiconductor structure 102 and the second semiconductor structure 104 are vertically integrated, and the memory array 108 and the first peripheral circuit 110 of the first semiconductor structure 102 are electrically connected to the second peripheral circuit 112 of the second semiconductor structure 104 through a plurality of interconnects (e.g., bond contacts) across the bonding interface 106.

[0044] It should be appreciated that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited. Figure 1B A schematic diagram of a cross-section of another exemplary 3D memory device 101 is shown in accordance with some embodiments. In the 3D memory device 101, the first semiconductor structure 102 includes a memory array 108 and a first peripheral circuit 110, and the second semiconductor structure 104 includes a second peripheral circuit 112. The first semiconductor structure 102 and the second semiconductor structure 104 are bonded together at a bonding interface 106. The first semiconductor structure 102 and the second semiconductor structure 104 are vertically integrated, and the memory array 108 and the first peripheral circuit 110 of the first semiconductor structure 102 are electrically connected to the second peripheral circuit 112 of the second semiconductor structure 104 through a plurality of interconnects (e.g., bond contacts) across the bonding interface 106. Figure 1A In the 3D memory device 100 of FIG. 1, the second semiconductor structure 104 including the peripheral circuit is located above the first semiconductor structure 102 including the memory array, in contrast to the 3D memory device 101 of FIG. 2 in which the first semiconductor structure 102 including the memory array is located above the second semiconductor structure 104 including the peripheral circuit. Figure 1BIn 3D memory device 101, first semiconductor structure 102, which includes an array of memory cells, is located on top of second semiconductor structure 104, which includes peripheral circuitry. Nonetheless, according to some embodiments, bonding interface 106 is formed in a vertical direction between first semiconductor structure 102 and second semiconductor structure 104 in 3D memory device 101, and first semiconductor structure 102 and second semiconductor structure 104 are directly bonded by bonding (e.g., hybrid bonding). Data transfer between the array of memory cells in first semiconductor structure 102 and the peripheral circuitry in second semiconductor structure 104 can be performed through interconnects (e.g., bonding contacts) that span bonding interface 106.

[0045] Figure 2 A schematic circuit diagram of an exemplary memory device 200 including peripheral circuitry with a page buffer is shown in accordance with some aspects of the present disclosure. Memory device 200 can include an array of memory cells 201 and peripheral circuitry 202 coupled to array of memory cells 201. 3D memory devices 100 and 101 can be examples of memory device 200, where array of memory cells 201 and peripheral circuitry 202 can be included in first semiconductor structure 102 and second semiconductor structure 104, respectively. Array of memory cells 201 can be an array of NAND flash memory cells, where memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string 208 extending vertically on a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 coupled in series and stacked vertically. Each memory cell 206 is capable of holding a continuous analog value, e.g., a voltage or charge, which depends on the number of electrons captured within a region of memory cell 206. Each memory cell 206 can be a "floating gate" type of memory cell that includes a floating gate transistor, or can be a "charge trap" type of memory cell that includes a charge-trapping transistor.

[0046] In some embodiments, each memory cell 206 is a single-level cell (SLC) that has two possible memory states and thus is capable of storing one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some embodiments, each memory cell 206 is a multi-level cell (MLC) that is capable of storing more than one bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as triple-level cell (TLC)), or four bits per cell (also referred to as quad-level cell (QLC)). Each MLC can be programmed to exhibit a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to exhibit one of three possible program levels by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used as an erased state.

[0047] As shown in Figure 2 Each NAND memory string 208 can include a source select gate (SSG) 210 at its source end and a drain select gate (DSG) 212 at its drain end, as shown in FIG. 2. The SSGs 210 and DSGs 212 can be configured to activate selected NAND memory strings 208 (columns of the array) during read and program operations. In some embodiments, the SSGs 210 of the NAND memory strings 208 within the same block 204 are coupled to, for example, ground, by the same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSGs 212 of each NAND memory string 208 are coupled to a respective bit line 216 from which data can be read via an output bus (not shown). In some embodiments, each NAND memory string 208 is configured to be selected or deselected by applying a selected voltage (e.g., above the threshold voltage of the transistor having the DSG 212) or a deselected voltage (e.g., 0 V) to the respective DSG 212 via one or more DSG lines 213 and / or by applying a selected voltage (e.g., above the threshold voltage of the transistor having the SSG 210) or a deselected voltage (e.g., 0 V) to the respective SSG 210 via one or more SSG lines 215.

[0048] As shown in Figure 2As shown in FIG. 1, the NAND memory strings 208 can be organized into a plurality of blocks 204, each of which can have a common source line 214. In some embodiments, each block 204 is the basic unit of data for erase operations, i.e., all memory cells 206 on the same block 204 are erased at the same time. Memory cells 206 of adjacent NAND memory strings 208 can be coupled by a word line 218, which selects which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to the memory cells 206 of one page 220, which is the basic unit of data for program operations. The size of one page 220, measured in bits, can correspond to the number of NAND memory strings 208 in one block 204 that are coupled by the word lines 218. Each word line 218 can include a plurality of control gates (gate electrodes) at each memory cell 206 within the corresponding page 220 and a gate line that couples the control gates.

[0049] The peripheral circuitry 202 can be coupled to the memory cell array 201 by the bit lines 216, the word lines 218, the source lines 214, the SSG lines 215, and the DSG lines 213. As described above, the peripheral circuitry 202 can include any suitable circuitry for facilitating operations of the memory cell array 201 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 206 via the bit lines 216 through the word lines 218, the source lines 214, the SSG lines 215, and the DSG lines 213, thereby facilitating the operations. The peripheral circuitry 202 can include various types of peripheral circuitry formed using MOS technology. For example, Figure 3 Some example peripheral circuitry 202 is shown, including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, registers 314, an interface (I / F) 316, and a data bus 318. It should be understood that other peripheral circuitry 202 can also be included in some examples.

[0050] The page buffer 304 can be configured to read data from and program data to the memory cell array 201 under control of the control logic 312. In one example, the page buffer 304 can store a page of program data (write data) to be programmed into one page 220 of the memory cell array 201. In another example, the page buffer 304 also performs a program verify operation to ensure that the data has been correctly programmed into the memory cells 206 coupled to the selected word line 218. As described in more detail below, the page buffer 304 can be configured to store a page of program data in a plurality of memory cells 206 of the memory cell array 201. Figure 2In some embodiments shown, the page buffer 304 includes a plurality of page buffer circuits 222, each coupled to one NAND memory string 208 via a respective bit line 216. That is, the memory device 200 can include a respective bit line 216 coupled to each NAND memory string 208, and the page buffer 304 can include a respective page buffer circuit 222 coupled to each bit line 216 and NAND memory string 208. Each page buffer circuit 222 can include one or more latches, switches, power sources, nodes (e.g., data nodes and I / O nodes), current mirrors, verify logic, sense circuits, etc. In some embodiments, each page buffer circuit 222 is configured to store sense data corresponding to read data received from the respective bit line 216 and output the stored sense data at a read operation; each page buffer circuit 222 is also configured to store program data and output the stored program data to the respective bit line 216 at a program operation.

[0051] The row decoder / word line driver 308 can be configured to be controlled by the control logic 312 and select a block 204 of the memory cell array 201 and a word line 218 of the selected block 204. The row decoder / word line driver 308 can be further configured to drive the selected word line 218 using a word line voltage generated by the voltage generator 310. The voltage generator 310 can be configured to be controlled by the control logic 312 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) to be provided to the memory cell array 201. The column decoder / bit line driver 306 can be configured to be controlled by the control logic 312 and select one or more NAND memory strings 208 by applying a bit line voltage generated by the voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal to select a group of N bits of data from the page buffer 304 to be output in a read operation.

[0052] The control logic 312 can be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. The register 314 can be coupled to the control logic 312 and include a status register, a command register, and an address register to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 202.

[0053] The interface 316 can be coupled to the control logic 312 and act as a control buffer to buffer control commands received from a host (not shown) and forward them to the control logic 312, and to buffer status information received from the control logic 312 and forward them to the host. The interface 316 can also be coupled to the page buffer 304 and the column decoder / bit line driver 306 via the data bus 318 and act as an I / O interface and data buffer to buffer programming data received from the host (not shown) and forward them to the page buffer 304, and to buffer read data from the page buffer 304 and forward them to the host. In some embodiments, the interface 316 and the data bus 318 are part of the I / O circuitry of the peripheral circuitry 202.

[0054] As shown in Figure 4 In some embodiments, the memory cell array 201 is arranged in a plurality of planes 402, each of which has a plurality of blocks 204 and its own page buffer 304, as shown in Figure 4 Although not shown in, it should be understood that in some examples, each plane 402 can have its own set of page buffer 304, row decoder / word line driver 308, and column decoder / bit line driver 306, so that the control logic 312 can control the operation of the plurality of planes 402 in a synchronized manner or an asynchronous manner in parallel to improve the operating speed of the memory device 200. As discussed above in connection with Figures 2-4 As discussed above in connection with, it should be understood that as the number of memory cells increases due to the increase in the number of planes 402, blocks 204, NAND memory strings 208, and / or pages 220, the number of page buffers 304 and the number of page buffer circuits 222 within each page buffer can also increase. Thus, if the device size of each transistor forming the page buffer circuit 222 does not decrease, the total area of the page buffer 304 will continue to increase.

[0055] Further, in the 3D memory device 100 or 101 in which the peripheral circuitry and the memory cell array are stacked one on top of another in a bonded chip, the size of the 3D memory device 100 or 101 depends on the larger size of the first semiconductor structure 102 or the second semiconductor structure 104. As Figure 5As the area of page buffer 304 continues to increase, as shown in FIG. 1, the size of second semiconductor structure 104, which has the peripheral circuitry, can eventually become larger than the size of first semiconductor structure 102, which has the array of memory cells, and thus dominate the size of 3D memory device 100 or 101. As a result, to compensate for the increase in size of memory device 200, particularly 3D memory device 100 or 101, the device size of each transistor forming page buffer circuit 222 must be reduced without sacrificing performance, e.g., device leakage performance, too much, as described above.

[0056] In accordance with the scope of the present disclosure, in some embodiments, each page buffer 304, which is the dominant factor in chip size, has recessed gate transistors instead of planar gate transistors, thereby reducing device size while maintaining comparable or even better device leakage performance. Peripheral circuitry 202 other than page buffer 304, e.g., row decoders / word line drivers 308, column decoders / bit line drivers 306, voltage generators 310, control logic 312, registers 314, data bus 318, and / or interface 316, can still use planar gate transistors, which can reduce manufacturing complexity and device structure and performance variations compared to using recessed gate transistors. In some embodiments, I / O circuitry, including interface 316 and data bus 318, uses planar gate transistors because planar gate transistors can provide higher operating speed than recessed gate transistors, which is a desirable feature for I / O circuitry that must frequently communicate with external devices. For example, Figure 6A Plan views and cross-sectional side views of exemplary planar gate transistors are shown, and Figure 6B Plan views and cross-sectional side views of exemplary recessed gate transistors are shown, in accordance with some aspects of the present disclosure.

[0057] As Figure 6A As shown in FIG. 1, for planar gate transistors, the effective channel length Leff is the same as the gate length L, while in Figure 6BFor recessed gate transistors, the effective channel length Leff = Lb + 2Ld - 2xj, where Lb represents the gate length at the bottom position of the gate structure protruding into the substrate, Ld represents the depth of the gate structure protruding into the substrate (if the slope is not 90 degrees, then the slope is considered for higher accuracy), and xj represents the junction depth of the source / drain. For planar gate transistors, the reduction in device area can be achieved by reducing the gate length L (and in some cases, the gate width W), which in turn shortens the effective channel length. As a result, the channel leakage can be degraded. In contrast, for recessed gate transistors, the reduction in device area (e.g., by scaling down the gate length L) can not reduce the effective channel length Leff due to the increase in Ld. Moreover, better gate control can be achieved due to the protruding shape of the recessed gate structure. Thus, the device area can be reduced while maintaining comparable or even better device leakage performance. On the other hand, the protruding shape of the recessed gate structure in the recessed gate transistors can introduce higher manufacturing complexity and device variation compared to the planar gate transistors. The structures, functions, and processes of the planar gate transistors and the recessed gate transistors will be described in detail below.

[0058] Figure 7 A side view of a cross-section of an exemplary semiconductor device 700 having recessed gate transistors 702 and planar gate transistors 704 is shown, in accordance with some aspects of the present disclosure. The semiconductor device 700 can include the peripheral circuitry disclosed herein (e.g., the peripheral circuitry 202). In some implementations, the recessed gate transistors 702 are part of the page buffer disclosed herein (e.g., the page buffer 304), and the planar gate transistors 704 are part of another peripheral circuitry 202 disclosed herein other than the page buffer 304 (e.g., the I / O circuitry including the data bus 318 and / or the interface 316). That is, the semiconductor device 700 can include a page buffer having recessed gate transistors 702 and a different peripheral circuitry having planar gate transistors 704. For example, the page buffer can be formed using recessed gate transistors 702 instead of planar gate transistors 704, thereby reducing the size of the page buffer without sacrificing device leakage performance, while some or all of the other peripheral circuitry can be formed using planar gate transistors instead of recessed gate transistors 702 to balance the manufacturing complexity and device variation. It should also be understood that the semiconductor device 700 is not limited to the peripheral circuitry of a memory device, and can include any semiconductor device 700 containing a mix of recessed gate transistors 702 and planar gate transistors 704.

[0059] Each recessed gate transistor 702 or planar gate transistor 704 can be a MOS field effect transistor (MOSFET) located on a substrate 701, which can include silicon (e.g., single-crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. The semiconductor device 700 can include an isolation 703, such as a shallow trench isolation (STI), in the substrate 701 between adjacent recessed gate transistors 702 and planar gate transistors 704 to reduce current leakage. The isolation 703 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric having a dielectric constant or k-value higher than that of silicon nitride (k > 7). In some embodiments, the isolation 703 includes silicon oxide.

[0060] It should be noted that the x-axis and y-axis are added in Figure 7 to further illustrate the spatial relationships of the components in the semiconductor device 700. The substrate 701 includes two lateral surfaces (e.g., top and bottom surfaces) that extend laterally in the x-direction (i.e., lateral or width direction). As used herein, when a substrate (e.g., substrate 701) of a semiconductor device (e.g., semiconductor device 700) is located in the lowest plane of the semiconductor device in the y-direction (vertical or thickness direction), whether a component (e.g., layer or device) of the semiconductor device is located “on,” “above,” or “below” another component (e.g., layer or device) is determined with respect to the substrate in the y-direction. The same concept is employed throughout this disclosure to describe spatial relationships.

[0061] As shown in Figure 7 In some embodiments, the recessed gate transistors 702 and planar gate transistors 704 are formed by complementary MOS (CMOS) technology and include pairs of adjacent P-type (e.g., PMOS) and N-type (NMOS) transistors, as shown in Figure 7Wells 714 and 715 are for illustrative purposes only. Depending on the doping type of substrate 701, N-well 714 or P-well 715 may be omitted or may have different extents and boundaries in substrate 701. Each recessed gate transistor 702 may also include a recessed gate structure 719 extending into the recess of well 714 or 715 in substrate 701. For example, the recessed gate structure 719 of P-type recessed gate transistor 706 may extend into the recess of N-well 714, and the recessed gate structure 719 of N-type recessed gate transistor 707 may extend into the recess of P-well 715. That is, the recessed gate structure 719 may have two parts in a side view: a protruding portion below the top surface of substrate 701 and a flat portion above the top surface of substrate 701. (See above for further details.) Figure 6B The depth and slope of the protruding portion of each recessed gate structure 719 determine Ld, which in turn affects the effective channel length Leff of the corresponding recessed gate transistor 702. In some embodiments, the depth of the protruding portion of the recessed gate structure 719 (i.e., the depth to which the recessed gate structure 719 extends into the substrate 701) is between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range defined by any of these values, or any range defined by any two of these values).

[0062] In some embodiments, the recessed gate structure 719 includes a bent gate dielectric 718 and a recessed gate electrode 716 on the bent gate dielectric 718. For example... Figure 7 As shown, according to some embodiments, a recess is formed in the region of substrate 701 where the recessed gate transistor 702 is formed. Each recess may be surrounded by an N-well 714 or a P-well 715. That is, a portion of substrate 701 forming the wells 714 or 715 can be removed from the top surface to form the recess, as detailed below in connection with the manufacturing process. In some embodiments, the depth of the recess is the same as the depth of the protruding portion of the recessed gate structure 719 and is between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range defined by any of these values, or any range defined by any two of these values).

[0063] A bent gate dielectric 718 can be formed on the sidewalls and bottom surface of each recess. As a result, according to some embodiments, the bent gate dielectric 718 has a bent shape in a side view that follows the shape of the sidewalls and bottom of the recess. The bent gate dielectric 718 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the bent gate dielectric 718 includes silicon oxide, i.e., a bent gate oxide. According to some embodiments, a recessed gate electrode 716 is located above and in contact with the bent gate dielectric 718. Figure 7 As shown, the recessed gate electrode 716 in the side view may also include two portions: a protruding portion below the top surface of the substrate 701 and a flat portion above the top surface of the substrate 701. That is, the recess in the substrate 701 can be filled using a bent gate dielectric 718 and the protruding portion of the recessed gate electrode 716. The recessed gate electrode 716 may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten, copper, aluminum, etc.), metal compounds (e.g., titanium nitride, tantalum nitride, etc.), or silicides. In some embodiments, the recessed gate electrode 716 comprises polysilicon, i.e., a recessed gate polysilicon.

[0064] like Figure 7 As shown, each recessed gate transistor 702 may also include a pair of source and drain electrodes separated by a recessed gate structure 719. For example, a P-type recessed gate transistor 706 may include a P-type source 732 and a P-type drain 732 located in an N-well 714. The P-type source and drain 732 may be separated by the recessed gate structure 719 (i.e., the bent gate dielectric 718 and the recessed gate electrode 716). Similarly, an N-type recessed gate transistor 707 may include an N-type source 733 and an N-type drain 733 located in a P-well 715. The N-type source and drain 733 may be separated by the recessed gate structure 719 (i.e., the bent gate dielectric 718 and the recessed gate electrode 716). The P-type source and drain 732 may be doped with any suitable P-type dopant, such as B or Ga, and the N-type source and drain 733 may be doped with any suitable N-type dopant, such as P or Ar. (See above for further details.) Figure 6B The junction depth (i.e., the depth of drain / source 732 or 733) also affects the effective channel length Leff of the corresponding recessed gate transistor 702. For example... Figure 7 As shown, in some embodiments, the recessed gate structure 719 extends below the source and drain 732 or 733. That is, the lower end of the recessed gate structure 719 may be below the lower ends of the source and drain 732 or 733.

[0065] In some embodiments, each recessed gate transistor 702 further includes a spacer 720 located on the sidewall of the flat portion of the recessed gate electrode 716 (i.e., the portion above the substrate 701). The spacer 720 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the spacer 720 comprises silicon nitride. It should be understood that each recessed gate transistor 702 may include or be coupled to... Figure 7 Additional components not shown, such as additional dielectric layers or contacts (e.g., source and drain contacts).

[0066] Similarly, such as Figure 7 As shown, the P-type flat-gate transistor 708 may include an N-well 722 located in the substrate 701, and the N-type flat-gate transistor 709 may include a P-well 723 located in the substrate 701. The N-well 722 may be doped with any suitable N-type dopant, such as P or Ar, and the P-well 723 may be doped with any suitable P-type dopant, such as B or Ga. It should be understood that... Figure 7 Wells 722 and 723 are for illustrative purposes only. Depending on the doping type of substrate 701, N-well 722 or P-well 723 may be omitted or may have different extents and boundaries in substrate 701. Each flat gate transistor 704 may also include a flat gate structure 727. According to some embodiments, unlike the recessed gate structure 719, the flat gate structure 727 does not extend into substrate 701. In some embodiments, due to the presence of the protruding portion of the recessed gate structure 719, the depth of well 714 or 715 in recessed gate transistor 702 is greater than the depth of well 722 or 723 in flat gate transistor 704.

[0067] In some embodiments, the flat gate structure 727 includes a flat gate dielectric 726 and a flat gate electrode 724 located on the flat gate dielectric 726. According to some embodiments, unlike the recessed gate transistor 702, no recess is formed in the region of the substrate 701 where the flat gate transistor 704 is formed. Therefore, the flat gate dielectric 726 can be formed on the top surface of the substrate 701. As a result, according to some embodiments, the flat gate dielectric 726 has a linear shape in a side view. The flat gate dielectric 726 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the flat gate dielectric 726 includes silicon oxide, i.e., a flat gate oxide. According to some embodiments, the flat gate electrode 724 is located on and in contact with the flat gate dielectric layer 726. Unlike the recessed gate transistor 702, the entire flat gate electrode 724 can be located above the top surface of the substrate 701. The flat gate electrode 724 can include any suitable conductive material, such as polysilicon, metal, metal compound, or silicide. In some embodiments, the flat gate electrode 724 comprises polysilicon, i.e., flat gate polysilicon.

[0068] like Figure 7 As shown, each flat-gate transistor 704 may further include a pair of source and drain electrodes located in well 722 or 723. For example, a P-type flat-gate transistor 708 may include a P-type source 730 and a P-type drain 730 located in an N-well 722, and an N-type flat-gate transistor 709 may include an N-type source 731 and an N-type drain 731 located in a P-well 723. The P-type source and drain 730 may be doped with any suitable P-type dopant, such as B or Ga, and the N-type source and drain 731 may be doped with any suitable N-type dopant, such as P or Ar. In some embodiments, the doping concentration of the source / drain 732 or 733 in the recessed gate transistor 702 is different from the doping concentration of the source / drain 730 or 731 in the flat-gate transistor 704, such that the threshold voltage of the recessed gate transistor 702 is different from the threshold voltage of the flat-gate transistor 704. For example, the doping concentration of the source / drain 732 or 733 in the recessed gate transistor 702 and the doping concentration of the source / drain 730 or 731 in the flat gate transistor 704 can be controlled in such a way that the threshold voltage of the flat gate transistor 704 is greater than the threshold voltage of the recessed gate transistor 702.

[0069] In some embodiments, each planar gate transistor 704 also includes a spacer 728 on the sidewalls of the planar gate electrode 724. The spacer 728 can include any appropriate dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the spacer 728 includes silicon nitride. It will be appreciated that each planar gate transistor 704 can include or be coupled to additional components not shown in FIG. 7, such as additional dielectric layers or contacts (e.g., source and drain contacts). Figure 7

[0070] As described above in connection with Figure 6A and Figure 6B Compared to the planar gate transistors 704, the recessed gate transistors 702 can increase Ld due to the protruding shape of the recessed gate structure, thereby reducing the gate length L in the plan view while maintaining the same effective gate length Leff. As a result, in some embodiments, the dimensions (e.g., gate length L) of the planar gate transistors 704 in the plan view are greater than the dimensions (e.g., gate length L) of the recessed gate transistors 702.

[0071] As described above in connection with Figure 1A and Figure 1B The semiconductor device 700 can be an example of the second semiconductor structure 104 bonded with the first semiconductor structure 102 having an array of memory cells, as described above in connection with Figure 8A A side view of a cross-section of an example 3D memory device 800 is shown, in accordance with some embodiments. As one example of the 3D memory device 101 described above in connection with Figure 1B The 3D memory device 800 is a bonded chip including a first semiconductor structure 802 and a second semiconductor structure 804 stacked on the first semiconductor structure 802. According to some embodiments, the first semiconductor structure 802 and the second semiconductor structure 804 are joined at a bonding interface 806 located therebetween. As shown, Figure 8A The first semiconductor structure 802 can include a substrate 808, which can include silicon (e.g., single-crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate material.

[0072] ​The first semiconductor structure 802 may include a device layer 810 located above a substrate 808. A semiconductor device 700 having a recessed gate transistor 702 and a flat gate transistor 704 may be an example of the device layer 810. In some embodiments, the device layer 810 includes peripheral circuitry, including a page buffer 812 and other peripheral circuitry 814 (e.g., I / O circuitry). In some embodiments, the page buffer 812 includes a plurality of recessed gate transistors 816, and the other peripheral circuitry 814 includes a plurality of flat gate transistors 818, as described above. Figure 7 As detailed above, isolation (e.g., STI) and doped regions (e.g., the source and drain of transistors 816 and 818) can also be formed in the substrate 808. According to some embodiments, transistors 816 and 818 are high-speed by means of advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0073] In some embodiments, the first semiconductor structure 802 further includes an interconnect layer 820 located above the device layer 810 to transmit electrical signals to and from peripheral circuits 812 and 814. The interconnect layer 820 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and vertical interconnect channel (VIA) contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-process (BEOL) interconnects. The interconnect layer 820 may also include one or more inter-layer dielectric (ILD) layers (also referred to as “inter-metal dielectric (IMD) layers”) in which the interconnects and VIA contacts may be formed. That is, the interconnect layer 820 may include interconnects and VIA contacts located in multiple ILD layers. In some embodiments, devices in the device layer 810 are coupled to each other via interconnects in the interconnect layer 820. For example, a page buffer 812 may be coupled to other peripheral circuits 814 via the interconnect layer 820.

[0074] like Figure 8A As shown, the first semiconductor structure 802 may further include a bonding layer 822 located at the bonding interface 806 above the interconnect layer 820 and the device layer 810. The bonding layer 822 may include a plurality of bonding contacts 824 and a dielectric material electrically isolating the bonding contacts 824. The bonding contacts 824 may include a conductive material. The remaining regions of the bonding layer 822 may be formed using a dielectric material. The bonding contacts 824 in the bonding layer 822 and the surrounding dielectric material may be used for hybrid bonding. Similarly, as... Figure 8AAs shown in FIG. 8, the second semiconductor structure 804 can also include a bonding layer 826 on the bonding layer 822 of the first semiconductor structure 802 at the bonding interface 806. The bonding layer 826 can include a plurality of bonding contacts 828 and a dielectric that electrically isolates the bonding contacts 828. The bonding contacts 828 can include a conductive material. The rest of the bonding layer 826 can be formed with a dielectric material. The bonding contacts 828 and the surrounding dielectric in the bonding layer 826 can be used for hybrid bonding. According to some embodiments, the bonding contacts 828 contact the bonding contacts 824 at the bonding interface 806.

[0075] The second semiconductor structure 804 can be bonded to the top of the first semiconductor structure 802 in a face-to-face manner at the bonding interface 806. In some embodiments, the bonding interface 806 is disposed between the bonding layer 822 and the bonding layer 826 as a result of hybrid bonding, also known as "metal / dielectric hybrid bonding," which is a direct bonding technique (e.g., forming a bond between surfaces without an intervening layer such as solder or adhesive) and can achieve both metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface 806 is where the bonding layer 822 and the bonding layer 826 meet and bond. In practice, the bonding interface 806 can be a layer of a certain thickness that includes the top surface of the bonding layer 822 of the first semiconductor structure 802 and the bottom surface of the bonding layer 826 of the second semiconductor structure 804.

[0076] In some embodiments, the second semiconductor structure 804 also includes an interconnect layer 830 on the bonding layer 826 to carry electrical signals. The interconnect layer 830 can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 830 also include local interconnects such as bit line contacts and word line contacts. The interconnect layer 830 can also include one or more ILD layers in which interconnect lines and VIA contacts can be formed.

[0077] In some embodiments, the second semiconductor structure 804 includes a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings 838 on the interconnect layer 830 and the bonding layer 826. According to some embodiments, each NAND memory string 838 vertically passes through a plurality of pairs, each pair including a conductive layer 834 and a dielectric layer 836. The stacked, alternating conductive layers 834 and dielectric layers 836 are also referred to herein as memory stacks 832. According to some embodiments, the alternating conductive layers 834 and dielectric layers 836 in the memory stacks 832 alternate in the vertical direction.

[0078] In some embodiments, each NAND memory string 838 is a "charge-trapping" type NAND memory string that includes a semiconductor channel 842 and a memory film 840. In some embodiments, the semiconductor channel 842 includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, the memory film 840 is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a "charge-trapping / storage layer"), and a blocking layer. Each NAND memory string 838 can have a cylindrical (e.g., pillar) shape. According to some embodiments, the semiconductor channel 842 and the tunneling layer, storage layer, and blocking layer of the memory film 840 are arranged in this order in a direction from a middle of the pillar to an outer surface of the pillar. In some embodiments, the NAND memory string 838 also includes a plurality of control gates (each of which is a portion of a word line). Each conductive layer 834 in the memory stack 832 can function as a control gate for each memory cell of the NAND memory string 838.

[0079] In some embodiments, the second semiconductor structure 804 also includes a semiconductor layer 848 disposed above the memory stack 832 and the NAND memory string 838. The semiconductor layer 848 can be a thinned substrate on which the memory stack 832 and the NAND memory string 838 are formed. In some embodiments, the semiconductor layer 848 includes single crystal silicon. The semiconductor layer 848 can also include isolation and doping regions (e.g., functioning as an array common source (ACS) for the NAND memory string 838, which is not shown). It should be understood that the NAND memory string 838 is not limited to a "charge-trapping" type NAND memory string, and in other examples can be a "floating gate" type NAND memory string. The semiconductor layer 848 can include polysilicon as a source plate for the "floating gate" type NAND memory string.

[0080] As Figure 8AAs shown, the second semiconductor structure 804 can further include a pad-out interconnect layer 850 over the semiconductor layer 848. The pad-out interconnect layer 850 can include interconnects, such as contact pads 852, in one or more ILD layers. The pad-out interconnect layer 850 and the interconnect layer 830 can be formed on opposite sides of the semiconductor layer 848. In some embodiments, the interconnects in the pad-out interconnect layer 850 can carry electrical signals between the 3D memory device 800 and external circuitry, for example, for pad-out purposes. In some embodiments, the second semiconductor structure 804 further includes one or more contacts 854 that extend through the semiconductor layer 848 to electrically connect the pad-out interconnect layer 850 as well as the interconnect layers 830 and 820. As a result, the peripheral circuits 812 and 814 can be coupled to the array of NAND memory strings 838 through the interconnect layers 830 and 820 and the bonding contacts 828 and 824. That is, the array of NAND memory strings 838 can be coupled to the page buffer 812 across the bonding interface 806. Further, the peripheral circuits 812 and 814 and the array of NAND memory strings 838 can be coupled to external circuitry through the contacts 854 and the pad-out interconnect layer 850.

[0081] Figure 8B A cross-sectional view of another exemplary 3D memory device 801 is shown, in accordance with some aspects of the present disclosure. As with the 3D memory device 800 described above in connection with FIG. 8, the 3D memory device 801 is a bonded chip that includes a first semiconductor structure 805 and a second semiconductor structure 803 stacked on the first semiconductor structure 805. Like the 3D memory device 800 described above, the 3D memory device 801 represents an example of a bonded chip in which the first semiconductor structure 805 and the second semiconductor structure 803 are separately formed and bonded in a face-to-face manner at a bonding interface 807. It should be understood that details of similar structures (e.g., materials, fabrication processes, functions, etc.) between the 3D memory devices 800 and 801 can not be repeated below. Figure 1A Figure 8A

[0082] The second semiconductor structure 803 can include a substrate 809 and a memory stack 811 over the substrate 809 that includes alternating conductive layers 813 and dielectric layers 815. In some embodiments, an array of NAND memory strings 817 each extend vertically through the alternating conductive layers 813 and dielectric layers 815 in the memory stack 811 over the substrate 809. Each NAND memory string 817 can include a semiconductor channel 821 and a memory film 819. The NAND memory strings 817 can be “charge-trapping” type NAND memory strings or “floating gate” type NAND memory strings.​​

[0083] In some embodiments, the second semiconductor structure 803 further includes an interconnect layer 827 located over the memory stack 811 and the NAND memory string 817 to transmit electrical signals to and from the NAND memory string 817. The interconnect layer 827 may include multiple interconnects, including interconnect lines and VIA contacts. In some embodiments, the interconnects in the interconnect layer 827 may also include local interconnects such as bit line contacts and word line contacts. In some embodiments, the second semiconductor structure 803 further includes a bonding layer 829 located at a bonding interface 807 over the interconnect layer 827 and the memory stack 811 and the NAND memory string 817. The bonding layer 829 may include multiple bonding contacts 855 and a dielectric surrounding and electrically isolating the bonding contacts 855.

[0084] like Figure 8B As shown, the first semiconductor structure 805 includes another bonding layer 851 located above the bonding layer 829 at a bonding interface 807. The bonding layer 851 may include a plurality of bonding contacts 853 and a dielectric surrounding and electrically isolating the bonding contacts 853. According to some embodiments, the bonding contacts 853 and bonding contacts 855 contact at the bonding interface 807. In some embodiments, the first semiconductor structure 805 also includes an interconnect layer 857 located above the bonding layer 851 to transmit electrical signals. The interconnect layer 857 may include a plurality of interconnects, including interconnect lines and VIA contacts.

[0085] The first semiconductor structure 805 may further include a device layer 831 located above the interconnect layer 857 and the bonding layer 851. A semiconductor device 700 having a recessed gate transistor 702 and a flat gate transistor 704 may be an example of the device layer 831. In some embodiments, the device layer 831 includes peripheral circuitry, including a page buffer 835 and other peripheral circuitry 837 (e.g., I / O circuitry). In some embodiments, the page buffer 835 includes a plurality of recessed gate transistors 839, and the other peripheral circuitry 837 includes a plurality of flat gate transistors 841, as described above. Figure 7 As detailed above. According to some implementations, transistors 839 and 841 are high-speed thanks to advanced logic processes (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0086] In some embodiments, the first semiconductor structure 805 further includes a semiconductor layer 833 disposed above the device layer 831. The semiconductor layer 833 may be located above and in contact with the peripheral circuits 835 and 837. The semiconductor layer 833 may be a thinned substrate on which transistors 839 and 841 are formed. In some embodiments, the semiconductor layer 833 comprises single-crystal silicon. The semiconductor layer 833 may also include isolation and doped regions.

[0087] like Figure 8B As shown, the first semiconductor structure 805 may further include a pad-out interconnect layer 843 located above the semiconductor layer 833. The pad-out interconnect layer 843 may include interconnects located in one or more ILD layers, such as contact pads 845. In some embodiments, the interconnects in the pad-out interconnect layer 843 are capable of transmitting electrical signals between the 3D memory device 801 and external circuitry, for example, to achieve pad-out purposes. In some embodiments, the first semiconductor structure 805 also includes one or more contacts 847 extending through the semiconductor layer 833 to couple the pad-out interconnect layer 843 and interconnect layers 857 and 827. As a result, peripheral circuitry 835 and 837 can also be coupled to an array of NAND memory strings 817 via interconnect layers 857 and 827 and bonding contacts 853 and 855. That is, the array of NAND memory strings 817 can be coupled to the page buffer 835 across the bonding interface 807. In addition, the array of peripheral circuits 835 and 837 and NAND memory string 817 can be electrically connected to external circuits via contact 847 and pads leading out the interconnect layer 843.

[0088] To further reduce the footprint of the peripheral circuitry, the peripheral circuitry of a 3D memory device can be arranged in multiple planes stacked in the vertical direction, which is different from arranging it in the same plane (e.g., as shown in the image). Figure 8A and Figure 8B The examples shown (located on the same substrate) form a contrast. For example, Figure 8C A side view of a cross-section of yet another exemplary 3D memory device 860 according to some embodiments is shown. (As per the above...) Figure 1B An example of the described 3D memory device 101, the 3D memory device 860 is a bonded chip including a first semiconductor structure 862 and a second semiconductor structure 864 stacked on the first semiconductor structure 862. (As described above) Figure 8ASimilar to the 3D memory device 800, the 3D memory device 860 represents an example of a bonded chip in which a first semiconductor structure 862 and a second semiconductor structure 864 are formed separately and bonded face-to-face at a bonding interface 886. It should be understood that details (e.g., materials, manufacturing processes, functions, etc.) of similar structures in both 3D memory devices 800 and 860 may not be repeated below.

[0089] and Figure 8A The first semiconductor structure 802, which includes a single device layer 810, is different. Figure 8C The first semiconductor structure 862 of the 3D memory device 860 may include multiple device layers located in different planes in a vertical direction, such as a first device layer 866 and a second device layer 868 stacked above the first device layer 866. The first device layer 866 and the second device layer 868 may each include a first semiconductor layer 870 and a second semiconductor layer 874. In some embodiments, each semiconductor layer 870 or 874 includes monocrystalline silicon. Figure 8C As shown, in some embodiments, the first device layer 866 includes a plurality of recessed gate transistors 872 formed in the semiconductor layer 870. A recessed gate transistor 702 may be an example of a recessed gate transistor 872 in the first device layer 866. The first device layer 866 may include a page buffer having recessed gate transistors 872 as described in this disclosure. In some embodiments, all transistors in the first device layer 866 are recessed gate transistors 872. That is, according to some embodiments, the first device layer 866 does not include any flat gate transistors.

[0090] like Figure 8C As shown, in some embodiments, the second device layer 868 includes a plurality of flat-gate transistors 876 formed on a semiconductor layer 874. A flat-gate transistor 704 may be an example of a flat-gate transistor 876 in the second device layer 868. The second device layer 868 may include peripheral circuitry, such as I / O circuitry, having the flat-gate transistors 876 as described in this disclosure, in addition to a page buffer. In some embodiments, all transistors in the second device layer 868 are flat-gate transistors 876. That is, according to some embodiments, the second device layer 868 does not include any recessed gate transistors. By separating the flat-gate transistors 876 and recessed gate transistors 872 into different device layers in different planes, the flat-gate transistors 876 and recessed gate transistors 872 can be manufactured using different processes, thereby reducing manufacturing complexity.

[0091] In some embodiments, a through-silicon contact (TSC) 878 is formed through the semiconductor layer 874 between the planar gate transistor 876 and the recessed gate transistor 872, thereby electrically connecting the planar gate transistor 876 and the recessed gate transistor 872 in different device layers.

[0092] As with the second semiconductor structure 804 in Figure 8A Similar to the second semiconductor structure 864 of the 3D memory device 860, the second semiconductor structure 865 also can include an array of NAND memory strings 882 extending vertically through the memory stacks 883. The planar gate transistors 876 and the recessed gate transistors 872 in the first semiconductor structure 863 can be electrically connected by TSCs 878 and the above-described Figure 8A Other interconnects and bonding contacts described in detail are electrically connected to the NAND memory strings 882. It should be understood that the number of device layers in the first semiconductor structure 863 and the relative positions and orientations of the planar gate transistors 876 and the recessed gate transistors 872 in the first semiconductor structure 863 are not limited to the examples shown in Figure 8C and can vary in other examples. In one example, the relative positions of the planar gate transistors 876 and the recessed gate transistors 872 can vary relative to the examples in Figure 8C In another example, the relative orientations of the planar gate transistors 876 and the recessed gate transistors 872 can change from facing the same direction to facing each other or back-to-back. It should also be understood that the relative positions and orientations of the first semiconductor structure 863 and the second semiconductor structure 865 can also vary in other examples.

[0093] In some embodiments, the planar gate transistors 876 and the recessed gate transistors 872 are not only in different device layers in different planes, but also in different semiconductor structures. For example, Figure 8D A cross-sectional side view of yet another example 3D memory device 861 is shown, in accordance with some embodiments. As with the above-described Figure 1B As with the 3D memory device 101 described in one example, the 3D memory device 861 is a bonded chip that includes a first semiconductor structure 863 and a second semiconductor structure 865 stacked above the first semiconductor structure 863. As with the above-described Figure 8A Similar to the 3D memory device 800 in

[0094] and Figure 8C Unlike the 3D memory device 860, where device layers 866 and 868 are all located within the first semiconductor structure 862, in some embodiments, at least the first device layer 869 is located within the second semiconductor structure 865 of the 3D memory device 816. That is, in addition to the array of NAND memory strings 881 extending vertically through the memory stack 883, the second semiconductor structure 865 may also include the first device layer 869, which includes a semiconductor layer 875 (e.g., a monocrystalline silicon layer) and a plurality of flat-gate transistors 877 formed on the semiconductor layer 875. A TSC 879 may be formed through the semiconductor layer 875 to electrically connect the NAND memory strings 881 and the flat-gate transistors 877. The first device layer 869 may include peripheral circuitry, such as I / O circuitry, having the flat-gate transistors 877 as described in this disclosure, in addition to page buffers. In some embodiments, all transistors in the first device layer 869 are flat-gate transistors 877. That is, in some embodiments, the first device layer 869 does not include any recessed gate transistors.

[0095] like Figure 8D As shown, the first semiconductor structure 863 may include a second device layer 867 having a semiconductor layer 871 (e.g., a single-crystal silicon layer). In some embodiments, the second device layer 867 includes a plurality of recessed gate transistors 873 formed in the semiconductor layer 871. A recessed gate transistor 702 may be an example of a recessed gate transistor 873 in the second device layer 867. The second device layer 867 may include a page buffer having recessed gate transistors 873 as described in this disclosure. In some embodiments, all transistors in the second device layer 867 are recessed gate transistors 873. That is, according to some embodiments, the second device layer 867 does not include any flat gate transistors. By distributing the flat gate transistors 877 and the recessed gate transistors 873 into different device layers in different planes and into different semiconductor structures, the flat gate transistors 877 and the recessed gate transistors 873 can be manufactured according to different processes, thereby reducing manufacturing complexity.

[0096] It should be understood that the number of device layers in each semiconductor structure 863 or 865, as well as the relative positions and orientations of the flat gate transistor 877 and the recessed gate transistor 873, are not limited to... Figure 8D The example shown is subject to variation in other examples. In one example, the relative positions of the flat gate transistor 877 and the recessed gate transistor 873 may be relative to... Figure 8DIn another example, the relative orientation of the flat gate transistors 877 and the recessed gate transistors 873 can be changed from face-to-face-to-face to face-to-the-same direction or back-to-back. It should also be understood that in other examples, the relative positions and orientations of the first semiconductor structure 863 and the second semiconductor structure 865 can also be changed.

[0097] Figure 12 A block diagram illustrating an exemplary system 1200 having a memory device in accordance with some aspects of the present disclosure is shown. The system 1200 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a storage device located therein. As Figure 12 As shown in FIG. 12, the system 1200 can include a host 1208 and a memory system 1202 having one or more memory devices 1204 and a memory controller 1206. The host 1208 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on chip (SoC), such as an application processor (AP). The host 1208 can be configured to send data to or receive data from the memory device 1204.

[0098] The memory device 1204 can be any memory device disclosed herein, such as the 3D memory devices 100 and 101, the memory device 200, and the 3D memory devices 800, 801, 860, and 861. In some implementations, each memory device 1204 includes a peripheral circuit having one or more page buffers. In accordance with the scope of the present disclosure, the page buffer (a chip-size driver) has recessed gate transistors instead of flat gate transistors, thereby reducing the device size while maintaining comparable or even better device leakage performance. The peripheral circuit other than the page buffer can still use flat gate transistors, which can reduce manufacturing complexity and device structure and performance variations compared to using recessed gate transistors.

[0099] According to some embodiments, a memory controller 1206 is coupled to the memory device 1204 and the host 1208 and is configured to control the memory device 1204. The memory controller 1206 can manage data stored in the memory device 1204 and communicate with the host 1208. In some embodiments, the memory controller 1206 is designed to work in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1206 is designed to work in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as data storage devices for mobile devices such as smartphones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 1206 can be configured to control operations of the memory device 1204, such as read, erase, and program operations. The memory controller 1206 can also be configured to manage various functions related to data stored in or to be stored in the memory device 1204, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 1206 is further configured to process error-correcting codes (ECC) related to data read from or written to the memory device 1204. Any other suitable functions can also be performed by the memory controller 1206, such as formatting the memory device 1204. The memory controller 1206 can communicate with external devices (e.g., the host 1208) according to a particular communication protocol. For example, the memory controller 1206 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0100] The memory controller 1206 and the one or more memory devices 1204 can be integrated into various types of memory devices, such as included within the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1202 can be implemented and packaged into different types of end electronic products. In as Figure 13AIn one example shown, the memory controller 1206 and a single memory device 1204 can be integrated into a memory card 1302. The memory card 1302 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1302 may also include a connection between the memory card 1302 and a host computer (e.g., Figure 12 The memory card connector 1304 is coupled to the host 1208. In such a... Figure 13B In another example shown, the memory controller 1206 and multiple memory devices 1204 can be integrated into the SSD 1306. The SSD 1306 may also include interfaces for connecting the SSD 1306 to a host computer (e.g., Figure 12 The SSD connector 1308 is coupled to the host 1208 in the memory card 1302. In some embodiments, the storage capacity and / or operating speed of the SSD 1306 is greater than that of the memory card 1302.

[0101] Figure 9A –9J illustrates a fabrication process for forming an exemplary semiconductor device having a recessed gate transistor and a flat gate transistor, according to some aspects of this disclosure. Figure 10 A flowchart of a method 1000 for forming an exemplary 3D memory device according to some aspects of this disclosure is shown.

[0102] Figure 11 A flowchart of a method 1100 for forming an exemplary semiconductor device having a recessed gate transistor and a flat gate transistor, according to some aspects of this disclosure, is shown. Figure 9A –9J、 Figure 10 and Figure 11 Examples of semiconductor devices shown include Figure 7 The semiconductor device 700 shown is to be... Figure 9A –9J、 Figure 10 and Figure 11 Described together. It should be understood that the operations shown in methods 1000 and 1100 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a sequence different from the operations described. Figure 10 and Figure 11 The execution is performed in the order shown.

[0103] refer to Figure 10Method 1000 begins with operation 1002, in which a first semiconductor structure comprising an array of NAND memory strings is formed on a first substrate. For example, as Figure 8B As shown, an array of NAND memory strings 817 is formed on substrate 809. Method 1000 proceeds to operation 1004, as follows. Figure 10 As shown, in this operation, a first bonding layer comprising a plurality of first bonding contacts is formed over an array of NAND memory strings. For example, as Figure 8B As shown, a bonding layer 829 including bonding contacts 855 is formed over the array of NAND memory strings 817. In some embodiments, a planar gate transistor is also formed to form the first semiconductor structure. The planar gate transistor can be formed in a device layer that is stacked one on top of the array of NAND memory strings, i.e., formed on different planes. For example, as Figure 8D As shown, a flat gate transistor 877 is formed in a semiconductor layer 875 located above the array of NAND memory strings 817.

[0104] Method 1000 proceeds to operation 1006, such as... Figure 10 As shown, in this operation, a second semiconductor structure including a recessed gate transistor is formed on a second substrate. The recessed gate transistor may include a recessed gate structure extending into the second substrate. In some embodiments, the second semiconductor structure also includes a planar gate transistor formed on the second substrate. To form both the recessed gate transistor and the planar gate transistor on the same substrate, such as Figure 11 As shown, in operation 1102, a first well is formed in a substrate. This substrate may be a silicon substrate.

[0105] like Figure 9A As shown, multiple isolation units 902 (e.g., STI) are formed in the silicon substrate 900. These isolation units are formed, for example, using wet / dry etching and thin film deposition of silicon oxide. The isolation units 902 divide the silicon substrate 900 into multiple regions, in which multiple transistors can be formed respectively. Figure 9A As shown, an N-well 904 and a P-well 906 are then formed in the silicon substrate 900. In some embodiments, the N-well 904 and P-well 906 are formed in regions used to form planar gate transistors. The N-well 904 and P-well 906 can be patterned using photolithography and aligned between the isolation units 902, followed by ion implantation of the corresponding N-type and P-type dopants.

[0106] like Figure 11 As shown, in operation 1104, a second well is formed in the substrate. In some embodiments, the depth of the second well is greater than the depth of the first well. Figure 9BAs shown, an N-well 910 is formed in a silicon substrate 900. The N-well 910 may be part of a P-type recessed gate transistor and can therefore be formed in the region where the P-type recessed gate transistor is formed. To form the N-well 910, in some embodiments, a mask layer 908 is formed on the silicon substrate 900, and then the mask layer 908 is patterned to expose the region where the N-well 910 will be formed. The mask layer 908 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 908 may be patterned and aligned between the isolation layers 902 using photolithography and wet / dry etching. N-type dopant (such as P or As) ion implantation into the desired region between the isolation layers 902 may be performed using the mask layer 908 to form the N-well 910. In some embodiments, the ion implantation conditions of N-well 904, P-well 906, and N-well 910 are controlled such that the depth of N-well 910 is greater than the depths of N-well 904 and P-well 906.

[0107] like Figure 9C As shown, a P-well 912 is formed in a silicon substrate 900. The P-well 912 may be part of an N-type recessed gate transistor and can therefore be formed within the region where the N-type recessed gate transistor is formed. To form the P-well 912, in some embodiments, a mask layer 909 is formed on the silicon substrate 900, and then the mask layer 909 is patterned to expose the region where the P-well 912 will be formed. The mask layer 909 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 909 can be patterned and aligned between the isolation layers 902 using photolithography and wet / dry etching. P-type dopant (e.g., B or Ga) ion implantation into the desired region between the isolation layers 902 can be performed using the mask layer 909 to form the P-well 912. In some embodiments, the ion implantation conditions of N-well 904, P-well 906, and P-well 912 are controlled such that the depth of P-well 912 is greater than the depths of N-well 904 and P-well 906.

[0108] like Figure 11 As shown, in operation 1106, a recess is formed in a first well in the substrate, such that the recess is surrounded by the first well. In some embodiments, the depth of the recess is between 50 nm and 100 nm. Figure 9DAs shown, recesses 914 are formed in N-well 910 and P-well 912 respectively using, for example, the same etching process. In some embodiments, a mask layer 911 is formed on the silicon substrate 900 and then patterned to expose the regions in N-well 910 and P-well 912 where the recesses 914 will be formed. The mask layer 911 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 911 may be patterned using photolithography and wet / dry etching. Etching of the silicon substrate 900 is then performed using the mask layer 911 to form the recesses 914 in wells 910 and 912. This etching process may include dry etching and / or wet etching. In some embodiments, the etching process is a dry etching process, such as reactive ion etching (RIE). The etching conditions (e.g., etch rate and etch duration) may be controlled to control the depth of the recesses 914. In some embodiments, the depth of the recess 914 is between 50 nm and 100 nm. For example... Figure 9D As shown, the recess 914 is formed only in the wells 910 and 912 of the recessed gate transistor, and not in the wells 904 and 906 of the flat gate transistor.

[0109] like Figure 11 As shown, in operation 1108, a curved gate dielectric is formed on the sidewalls and bottom surface of the recess, and a flat gate dielectric is formed on the substrate. In some embodiments, to form the curved gate dielectric and the flat gate dielectric, a sacrificial dielectric layer is formed on the sidewalls and bottom surface of the recess, the sacrificial dielectric layer is removed, a gate dielectric layer is formed on the sidewalls and bottom surface of the recess, and the gate dielectric layer is patterned.

[0110] like Figure 9J As shown, in each recess 914 (as Figure 9D A bent gate dielectric 931 is formed on the sidewalls and bottom surface of the silicon substrate 900, and a flat gate dielectric 925 is formed on the silicon substrate 900. To form the bent gate dielectric 931 and the flat gate dielectric 925, as shown... Figure 9EAs shown, a gate dielectric layer 916 can be formed on the sidewalls and bottom surfaces of each recess 914 and on the top surface of the silicon substrate 900 (e.g., wells 904 and 906) using the same deposition process. In some embodiments, a dielectric material, such as silicon oxide, is deposited using one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, an in-situ vapor generation (ISSG) process can be used to deposit a silicon oxide layer to form the gate dielectric layer 916. In some embodiments, a sacrificial dielectric layer (not shown) is formed on the sidewalls and bottom surfaces of the recess 914 using, for example, thermal oxidation, to remove defects on the sidewalls and bottom surfaces of the recess 914 caused by the etching process. Subsequently, the sacrificial dielectric layer is removed using, for example, wet etching, before forming the gate dielectric layer 916. Figure 9I and Figure 9J As shown, the gate dielectric layer 916 can be patterned using photolithography and etching processes in successive steps or in the same step to form a flat gate dielectric 925 and a curved gate dielectric 931.

[0111] like Figure 11 As shown, in step 1110, a recessed gate electrode is formed on a curved gate dielectric and a flat gate electrode is formed on a flat gate dielectric. In some embodiments, in order to form the recessed gate electrode and the flat gate electrode, a gate electrode layer is formed on the curved gate dielectric to fill the recess, the gate electrode layer is planarized, and the planarized gate electrode layer is patterned.

[0112] like Figure 9J As shown, a recessed gate electrode 920 is formed on a curved gate dielectric 931, and a flat gate electrode 922 is formed on a flat gate dielectric 925. To form the recessed gate electrode 920 and the flat gate electrode 922, as... Figure 9F As shown, a gate electrode layer 918 is formed on the gate dielectric layer 916. The recess 914 can be filled by the gate electrode layer 918. Figure 9E (As shown in the diagram). In some embodiments, a conductive material, such as polysilicon, is deposited on the gate dielectric layer 916 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Depending on the surface flatness of the gate electrode layer 918 affected by the depth of the recess 914, a planarization process, such as chemical mechanical polishing (CMP), can be performed to planarize the top surface of the gate electrode layer 918. Figure 9G As shown, recessed gate electrode 920 and flat gate electrode 922 are formed by patterning the gate electrode layer 918 using photolithography and etching processes in the same step.

[0113] like Figure 11 As shown, in operation 1112, spacers are formed on the sidewalls of the flat gate electrode above the substrate and on the sidewalls of the recessed gate electrode above the substrate. Figure 9H As shown, spacers 924 are formed on the sidewalls of the planar gate electrode 922 and the sidewalls of the recessed gate electrode 920 on the silicon substrate 900. In some embodiments, to form spacers 924, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, are used to deposit a dielectric material (not shown), such as silicon nitride, on the sidewalls and top surfaces of the recessed gate electrode 920 and the planar gate electrode 922, and on the gate dielectric layer 916. Subsequently, in the same step, the deposited dielectric material is patterned using photolithography and etching processes to remove portions located on the top surfaces of the recessed gate electrode 920, the planar gate electrode 922, and the gate dielectric layer 916, leaving portions located on the sidewalls of the recessed gate electrode 920 and the planar gate electrode 922 to form spacers 924.

[0114] like Figure 11 As shown, in operation 1114, a first source and a first drain, separated by a bent gate dielectric and a recessed gate dielectric, are formed in the first well. Figure 9I As shown, a P-type source 932 and a P-type drain 932, separated by a bent gate dielectric 931 and a recessed gate electrode 920, are formed in the N-well 910. To form the P-type source and drain 932, in some embodiments, a mask layer 930 is formed on a silicon substrate 900, and then the mask layer 930 is patterned to expose the regions where the P-type source and drain 932 will be formed. The mask layer 930 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 930 can be patterned and aligned with the N-well 910 using photolithography and wet / dry etching. Ion implantation of a P-type dopant (e.g., B or Ga) can be performed into the N-well 910 using the mask layer 930 to form the P-type source and drain 932 separated by the bent gate dielectric 931 and the recessed gate electrode 920.

[0115] like Figure 11 As shown, in operation 1116, a second source and a second drain are formed in the second well. As... Figure 9JAs shown, an N-type source 934 and an N-type drain 934, separated by a bent gate dielectric 931 and a recessed gate electrode 920, are formed in a P-well 912. To form the N-type source and drain 934, in some embodiments, a mask layer 933 is formed on a silicon substrate 900, and then patterned to expose the regions where the N-type source and drain 934 will be formed. The mask layer 933 may include a soft mask layer, such as a photoresist layer, and / or may include a hard mask layer, such as a silicon oxide layer. The mask layer 933 can be patterned and aligned with the P-well 912 using photolithography and wet / dry etching. Ion implantation of an N-type dopant (e.g., P or As) can be performed into the P-well 912 using the mask layer 933 to form the N-type source and drain 934 separated by the bent gate dielectric 931 and the recessed gate electrode 920.

[0116] like Figure 9I As shown, next, P-type source and drain 926 and N-type source and drain 928 are formed in the N-well 904 and P-well 906 of the planar gate transistor, respectively, using photolithography and subsequent ion implantation with corresponding P-type and N-type dopants. In some embodiments, the ion implantation conditions of the P-type source and drain 926, N-type source and drain 928, P-type source and drain 932, and N-type source and drain 934 are such that the doping concentration of the P-type source and drain 932 and N-type source and drain 934 of the recessed gate transistor is different from the doping concentration of the P-type source and drain 926 and N-type source and drain 928 of the planar gate transistor.

[0117] In some embodiments, to form a second semiconductor structure including a recessed gate transistor, a recessed gate transistor is formed in a first device layer, and a planar gate transistor is formed in a second device layer. The first and second device layers can be stacked one on top of the other, i.e., formed in different planes. For example, as... Figure 8C As shown, a recessed gate transistor 872 is formed in a semiconductor layer 870 (e.g., a second substrate), and a flat gate transistor 876 is formed on a semiconductor layer 874 above the recessed gate transistor 872.

[0118] refer to Figure 10 Method 1000 proceeds to operation 1008, in which a second bonding layer including a plurality of second bonding contacts is formed over the recessed gate transistor. For example, as... Figure 8B As shown, a bonding layer 851 including bonding contacts 853 is formed over an array of recessed gate transistors 839. Method 1000 proceeds to operation 1010, as follows. Figure 10As shown, in this operation, the first and second semiconductor structures are bonded face-to-face, such that an array of NAND memory strings is coupled to a recessed gate transistor across the bonding interface. This bonding can be a hybrid bonding. In some embodiments, after bonding, the second semiconductor structure sits on top of the first semiconductor structure. In some embodiments, after bonding, the first semiconductor structure sits on top of the second semiconductor structure.

[0119] like Figure 8A As shown, a second semiconductor structure 804 having a NAND memory string 838 is flipped vertically. A downward-facing bonding layer 826 is bonded to an upward-facing bonding layer 822, i.e., face-to-face, thereby forming a bonding interface 806. In some embodiments, a processing technique, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surfaces prior to bonding. After bonding, bonding contacts 828 in bonding layer 826 are aligned and contacted with bonding contacts 824 in bonding layer 822, enabling the NAND memory string 838 to be coupled to device layer 810 (e.g., peripheral circuitry 812 and 814). Similarly, as... Figure 8B As shown, a first semiconductor structure 805 having peripheral circuits 835 and 837 is flipped vertically. A downward-facing bonding layer 851 is bonded to an upward-facing bonding layer 829, i.e., face-to-face, thereby forming a bonding interface 807. After bonding, bonding contacts 853 in bonding layer 851 and bonding contacts 855 in bonding layer 829 are aligned and in contact with each other, allowing the NAND memory string 817 to be coupled to device layer 831 (e.g., peripheral circuits 835 and 837).

[0120] Method 1000 proceeds to operation 1012, such as Figure 10 As shown, in this operation, one of the first and second substrates is thinned, said substrate being situated on top of the other of the first and second substrates. Figure 8A As shown, since the substrate of the second semiconductor structure 804 having NAND memory strings 838 is located on the substrate of the first semiconductor structure 802 having peripheral circuits 812 and 814, the substrate of the second semiconductor structure 804 is thinned using CMP and / or etching processes to form a semiconductor layer 848. Similarly, as Figure 8B As shown, since the substrate of the first semiconductor structure 805 having peripheral circuits 835 and 837 is located on the substrate of the second semiconductor structure 803 having NAND memory string 817, the substrate of the first semiconductor structure 805 is thinned using CMP and / or etching processes to form semiconductor layer 833.

[0121] Method 1000 proceeds to operation 1014, such as Figure 10As shown, in this operation, an interconnect layer is formed on the thinned first or second substrate. As shown Figure 8A As shown, a pad-out interconnect layer 850 is formed over the semiconductor layer 848 (top substrate after thinning). Similarly, as shown Figure 8B As shown, a pad-out interconnect layer 843 is formed over the semiconductor layer 833 (top substrate after thinning).

[0122] According to one aspect of the disclosure, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit having recessed gate transistors. The peripheral circuits also include a second peripheral circuit having planar gate transistors.

[0123] In some implementations, the first peripheral circuit includes a page buffer. The page buffer can include a recessed gate transistor.

[0124] In some implementations, the array of memory cells includes a plurality of NAND memory strings, the memory device also includes a plurality of bit lines respectively coupled to the plurality of NAND memory strings, and the page buffer is coupled to the plurality of bit lines.

[0125] In some implementations, the second peripheral circuit includes I / O circuitry.

[0126] In some implementations, the recessed gate transistor includes a well having a recess, a recessed gate structure protruding into the recess of the well and including a first gate dielectric and a first gate electrode on the first gate dielectric, and a source and a drain separated by the recessed gate structure.

[0127] In some implementations, the recessed gate transistor protrudes below the source and the drain.

[0128] In some implementations, the planar gate transistor includes a well, a planar gate structure on the well and including a second gate dielectric and a second gate electrode on the second gate dielectric, and a source and a drain. A depth of the well of the recessed gate transistor is greater than a depth of the well of the planar gate transistor.

[0129] In some implementations, the recessed gate transistor includes a pair of adjacent P-type and N-type recessed gate transistors.

[0130] In some implementations, the memory device also includes a bonding interface. The array of memory cells and the peripheral circuits can be located on opposite sides of the bonding interface, respectively.

[0131] In some embodiments, the recessed gate transistor and the planar gate transistor are located on a same substrate.

[0132] In some embodiments, the memory device is a 3D memory device.

[0133] According to another aspect of the present disclosure, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of NAND memory strings. The second semiconductor structure includes a page buffer having a recessed gate transistor. The array of NAND memory strings is coupled to the page buffer across the bonding interface.

[0134] In some embodiments, the array of NAND memory strings is arranged in a plurality of planes, and the page buffer includes a plurality of page buffers respectively coupled to the plurality of planes.

[0135] In some embodiments, the recessed gate transistor includes a well having a recess, a recessed gate structure protruding into the recess of the well and including a gate dielectric and a gate electrode located on the gate dielectric, and a source and a drain separated by the recessed gate structure.

[0136] In some embodiments, the first semiconductor structure further includes a first bonding layer having a plurality of first bonding contacts, the second semiconductor structure further includes a second bonding layer having a plurality of second bonding contacts, and the first bonding contacts contact the second bonding contacts at the bonding interface.

[0137] In some embodiments, the second semiconductor structure includes a first device layer and a second device layer stacked one on top of the other, the first device layer includes the recessed gate transistor, and the second device layer includes a planar gate transistor.

[0138] In some embodiments, the first device layer does not include any planar gate transistor, and the second device layer does not include any recessed gate transistor.

[0139] In some embodiments, the first semiconductor structure includes a first device layer, the second semiconductor structure includes a second device layer, the first device layer includes a planar gate transistor, and the second device layer includes the recessed gate transistor.

[0140] In some embodiments, the first device layer does not include any recessed gate transistor, and the second device layer does not include any planar gate transistor.

[0141] According to yet another aspect of the present disclosure, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first well in the substrate and having a recess, a recessed gate structure that protrudes into the recess of the first well, and a source and a drain separated by the recessed gate structure. The recessed gate structure includes a first gate dielectric and a first gate electrode on the first gate dielectric. The second transistor includes a second well in the substrate, a planar gate structure on the second well, and a second source and a second drain. The planar gate structure includes a second gate dielectric and a second gate electrode on the second gate dielectric.

[0142] In some embodiments, a depth of the first well is greater than a depth of the second well.

[0143] In some embodiments, the first gate dielectric is on sidewalls and a bottom surface of the recess in the substrate.

[0144] In some embodiments, a depth of the recess is between 50 nm and 100 nm.

[0145] In some embodiments, each of the first transistor and the second transistor includes a pair of adjacent P-type transistor and N-type transistor.

[0146] In some embodiments, the first transistor is part of a page buffer.

[0147] In some embodiments, a size of the second transistor is greater than a size of the first transistor in a plan view.

[0148] According to yet another aspect of the present disclosure, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit having a recessed gate transistor. The peripheral circuits also include a second peripheral circuit having a planar gate transistor.

[0149] In some embodiments, the system further includes a host coupled to the memory controller and configured to send or receive the data.

[0150] Modifications and / or adjustments to the descriptions of the specific embodiments provided herein can be readily made by a person skilled in the art based on the teachings and guidance provided herein. Accordingly, such modifications and adjustments are intended to fall within the scope of the disclosed embodiments and equivalents.

[0151] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: a substrate; and a first transistor comprising: a first well in the substrate and having a recess; a recessed gate structure having a protruding structure that protrudes into the recess of the first well, and the recessed gate structure comprising a first curved gate dielectric and a first gate electrode on the first curved gate dielectric; and a first source and a first drain separated by the recessed gate structure, wherein the protruding structure comprises a first end and a second end along a first direction, the first end is connected to the first well, and a length of the first end along a second direction is less than a length of the second end along the second direction; and wherein the first direction is perpendicular to the second direction.

2. The semiconductor device of claim 1, wherein, a depth of the protruding structure along the first direction to the recess is greater than a thickness of the first source along the first direction, and greater than a thickness of the first drain along the first direction.

3. The semiconductor device of claim 1, wherein, the semiconductor device further comprising: a second transistor; and an isolation structure between the first transistor and the second transistor.

4. The semiconductor device according to claim 3, wherein, the second transistor comprising: a second well in the substrate; a planar gate structure on the second well and comprising a second gate dielectric and a second gate electrode on the second gate dielectric; and a second source and a second drain.

5. The semiconductor device of claim 4, wherein, a width of the recessed gate structure along a third direction is less than a width of the planar gate structure along the third direction; wherein the first direction is perpendicular to the third direction.

6. The semiconductor device of claim 4, wherein, a depth of the first well along the first direction is greater than a depth of the second well along the first direction.

7. The semiconductor device of any one of claims 1-6, wherein, the first curved gate dielectric is on sidewalls and a bottom surface of the recess in the substrate, and the second gate dielectric is on a top surface of the substrate.

8. The semiconductor device of any one of claims 1-6, wherein, a depth of the recess is between 50 nm and 100 nm.

9. The semiconductor device of claim 4, wherein, each of the first and second transistors comprises a pair of adjacent P-type and N-type transistors.

10. The semiconductor device of any one of claims 1-6, wherein, the semiconductor device comprises a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure; wherein the first semiconductor structure comprises the plurality of first transistors, and the second semiconductor structure comprises a memory array.

11. A memory device comprising: a first semiconductor structure comprising: a substrate; and a first transistor comprising: a first well in the substrate and having a recess; a recessed gate structure having a protruding structure that protrudes into the recess of the first well, and the recessed gate structure comprising a first curved gate dielectric and a first gate electrode on the first curved gate dielectric; and a first source and a first drain separated by the recessed gate structure; and a second semiconductor structure comprising a memory array; wherein the first semiconductor structure and the second semiconductor structure are bonded together. wherein the protruding structure includes a first end and a second end along a first direction, the first end is connected to the first well, and a length of the first end along a second direction is less than a length of the second end along the second direction; and wherein the first direction is perpendicular to the second direction.

12. The memory device of claim 11, wherein, The first semiconductor structure includes a page buffer including a plurality of the first transistors spaced apart.

13. The memory device of claim 11, wherein, The protruding structure extends into the recess along the first direction to a depth that is greater than a thickness of the first source along the first direction and greater than a thickness of the first drain along the first direction.

14. The memory device of any one of claims 11-13, wherein, The first semiconductor structure further includes: a second transistor; and an isolation structure between the first transistor and the second transistor.

15. The memory device of claim 14, wherein, The second transistor includes: a second well in the substrate; a planar gate structure on the second well and including a second gate dielectric and a second gate electrode on the second gate dielectric; and a second source and a second drain.

16. The memory device of claim 14, wherein, The protruding structure extends into the recess along the first direction, a width of the recessed gate structure along a third direction is less than a width of a planar gate structure along the third direction; wherein the first direction is perpendicular to the third direction.

17. The memory device of claim 14, wherein, A depth of the first well along the first direction is greater than a depth of the second well along the first direction.

18. The memory device of claim 14, wherein, The first curved gate dielectric is on sidewalls and a bottom surface of the recess in the substrate, and the second gate dielectric is on a top surface of the substrate.

19. The memory device of claim 14, wherein, Each of the first and second transistors includes a pair of adjacent P-type and N-type transistors.

20. The memory device of claim 15, wherein, The first semiconductor structure includes a first device layer and a second device layer stacked; the first device layer includes the first transistor, and the second device layer includes the second transistor.

21. The memory device of any one of claims 11-13, wherein, The depth of the recess is between 50 nm and 100 nm.

22. The memory device of any one of claims 11-13, wherein The first semiconductor structure further includes a first bonding layer having a plurality of first bonding contacts; The second semiconductor structure further comprises a second bonding layer having a plurality of second bonding contacts; wherein, The first bonding layer and the second bonding layer are bonded together, and the first bonding contacts are in contact with the second bonding contacts.

23. A method of forming a semiconductor device, comprising: forming a first well having a recess on a substrate; forming a recessed gate structure in the recess of the first well; the recessed gate structure has a protruding structure that extends into the recess of the first well, and the recessed gate structure includes a first curved gate dielectric and a first gate electrode on the first curved gate dielectric, wherein the protruding structure includes a first end and a second end along a first direction, the first end is connected to the first well, and a length of the first end along a second direction is less than a length of the second end along the second direction, and wherein the first direction is perpendicular to the second direction; and forming a first source and a first drain, wherein the recessed gate structure is spaced between the first source and the first drain.

24. The method of claim 23, wherein, The depth of the protruding structure extending along the first direction into the recess is greater than the thickness of the first source electrode along the first direction and greater than the thickness of the first drain electrode along the first direction.

25. The method of claim 23, wherein, The method further includes: A second transistor is formed; wherein an isolation structure is included between the first transistor and the second transistor.

26. The method of claim 23, wherein, Forming the second transistor includes: A second well is formed in the substrate; A flat gate structure is formed on the second well; the flat gate structure includes a second gate dielectric and a second gate electrode located on the second gate dielectric; and This forms the second source and the second drain.

27. The method of claim 23, wherein, The protruding structure extends into the recess along the first direction, and the width of the recessed gate structure along the third direction is smaller than the width of the flat gate structure along the third direction. Wherein, the first direction is perpendicular to the third direction.

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