For maintenance operations on the storage system

Abstract

The present application is directed to maintenance operations for a memory system. Methods, systems, and apparatus are described for performing the following operations: performing an access operation on a memory cell; incrementing a value of a first counter based on performing the access operation on the memory cell; determining that the incremented value of the first counter satisfies a threshold; incrementing a value of a second counter based on determining that the incremented value of the first counter satisfies the threshold; and performing a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 202010674972.4, application date July 14, 2020, and invention name “Maintenance operations for memory systems”.

[0003] Cross-references

[0004] This patent application claims priority to U.S. patent application No. 16 / 913,753, filed by CHEN et al. on June 26, 2020, entitled “MAINTENANCE OPERATIONS FOR MEMORY SYSTEMS,” which claims the benefit of U.S. Provisional Patent Application No. 62 / 874,451, filed by CHEN et al. on July 15, 2019, entitled “MAINTENANCE OPERATIONS FOR MEMORY DEVICES,” each of which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The following relates generally to memory subsystems, and more specifically, to maintenance operations for memory systems. Background Art

[0006] A memory subsystem can be a storage device, a memory module, or a combination of both. A memory subsystem can include one or more memory components that store data. Memory components can include, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize the memory subsystem to store data in and retrieve data from the memory components.

[0007] Access operations may be performed on a memory device. These access operations may reduce the effectiveness of memory cells within the memory device over time. In some cases, some memory cells may wear out differently than other memory cells within the memory device. Uneven wear of individual memory cells may be due to some memory cells wearing out at a faster rate than other memory cells within the memory device, resulting in a shortened device lifespan. Summary of the Invention

[0008] A method is described. The method may include performing an access operation on a memory cell; incrementing a value of a first counter based at least in part on performing the access operation on the memory cell; determining that the incremented value of the first counter satisfies a threshold; incrementing a value of a second counter based at least in part on determining that the incremented value of the first counter satisfies the threshold; and performing a maintenance operation on the memory cell based at least in part on determining that the incremented value of the first counter satisfies the threshold.

[0009] A method is described. The method may include determining that a first number of access operations performed on a memory cell satisfies a first threshold; performing a first wear leveling operation on the memory cell based at least in part on determining that the first number of access operations performed on the memory cell satisfies the first threshold; receiving a message indicating a second threshold; determining that a second number of access operations performed on the memory cell after performing the first wear leveling operation satisfies the second threshold; and performing a second wear leveling operation on the memory cell based at least in part on determining that the second number of access operations satisfies the second threshold.

[0010] A method is described. The method may include identifying a global counter associated with performing a wear leveling procedure on a set of memory cells in a memory device, a value of the global counter indicating a baseline number of access operations performed on the set of memory cells; determining a difference between a value of a set-specific counter and a value of an offset counter, the set-specific counter associated with a first set of the memory cells, the offset counter indicating a global offset value relative to the value of the global counter; identifying a remainder and a parameter of the difference; identifying a number of access operations performed on the first set based at least in part on adding the remainder to the value of the global counter; and performing a wear leveling operation on the first set based at least in part on the number of access operations performed on the first set satisfying a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a computing environment according to examples as disclosed herein is described.

[0012] Figure 2 An example of a method of supporting maintenance operations for a memory system according to examples as disclosed herein is described.

[0013] Figure 3 An example of a counting system supporting maintenance operations for a memory system according to examples as disclosed herein is described.

[0014] Figure 4An example of a counting system supporting maintenance operations for a memory system according to examples as disclosed herein is described.

[0015] Figures 5 to 8 A flowchart illustrating one or more methods of supporting maintenance operations for a memory system according to examples as disclosed herein is shown.

[0016] Figure 9 An example machine is illustrated of a computer system supporting maintenance operations for a memory system according to examples as disclosed herein. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure are directed to maintenance operations for a memory subsystem. The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data for storage at the memory subsystem and can request retrieval of data from the memory subsystem.

[0018] Memory components can include nonvolatile and volatile memory devices. A nonvolatile memory device is a package of one or more dies. The dies in the package can be assigned to one or more channels for communication with the memory subsystem controller. A nonvolatile memory device includes cells (i.e., electronic circuits that store information) grouped into pages to store data bits.

[0019] The non-volatile memory device may include a three-dimensional cross-point ("3D cross-point") memory device as a cross-point array of non-volatile memory, which may be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Although non-volatile memory components such as 3D cross-point type memories are described, the memory device may be based on any other type of non-volatile memory, such as negative-and (NAND), and as described below in combination Figure 1 Other examples described.

[0020] Access operations can be performed on a memory device by a memory subsystem and can include read operations, erase operations, write operations, and rewrite operations. Access operations can cause wear in memory cells. In some cases, the wear of some memory cells may be different from the wear of other memory cells within the memory device. The uneven wear of memory cells may be due to some memory cells being accessed more frequently than other memory cells. In this example, memory cells within the memory device that are accessed more frequently may have a lower read / write lifespan. As a result, memory cells that are accessed more frequently may adversely affect the overall lifespan of the memory device.

[0021] Aspects of the present disclosure address the above-mentioned and other deficiencies by including a memory subsystem that includes a counter configured to count the number of access operations. The memory subsystem can coordinate the number of access operations on a particular set of memory cells, thereby mitigating the reduction in the life of the memory device. For example, the number of access operations experienced by a set of memory cells is counted, and when a threshold number (e.g., a number limit) of access operations are performed, consecutive access operations are changed to memory cells in a different set. Additionally, in some cases, maintenance operations, such as wear leveling operations, can be initiated on memory cells of the set that have reached a threshold. In some instances, the threshold number can be variable to accommodate different numbers of access operations, which can be based on the age of the memory device. The maintenance operations can balance wear across the entire memory device and increase the life of the memory device.

[0022] In some cases, counters can be implemented using global counters, offset counters, and set-specific counters. Some nonvolatile memory devices, such as 3D cross-point memory devices, may group pages across dies and channels to form management units (MUs). MUs may include user data and corresponding metadata. The memory subsystem controller may send and receive user data and corresponding metadata to and from the memory device as a management unit. A super management unit (SMU) may be a group of one or more MUs managed together. For example, the memory subsystem controller may perform media management operations (e.g., wear leveling operations, refresh operations, etc.) on the SMUs. Other types of nonvolatile memory devices may include one or more planes. Planes may be grouped into logical units (LUNs). For some types of nonvolatile memory devices (e.g., NAND devices), each plane may include a set of physical blocks, which may be the smallest area that can be erased. Set-specific counters may be MU-specific counters, SMU-specific counters, or block-specific counters.

[0023] The memory subsystem can be configured to use the value of the global counter, the value of the offset counter, and the value of the set-specific counter to determine a count of access operations performed on each set of memory units. A set of memory units can be a MU, SMU, or memory bank. The counting system can be configured to allow updating of the global least significant value without having to update each of the set-specific counters.

[0024] First, in reference Figure 1 The features of the present disclosure are described in the context of the computing environment described. Figure 2 、 3 The features of the present disclosure are described in the context of the systems and timing diagrams described in and 4. References to references Figure 5-9These and other features of the present disclosure are further illustrated and described with reference to device diagrams, computer diagrams, and flow charts for maintenance operations of a memory system.

[0025] Figure 1 An example of a computing environment 100 according to an example disclosed herein is illustrated. The computing environment can include a host system 105 and a memory subsystem 110. The memory subsystem 110 can include media such as one or more non-volatile memory devices (e.g., memory device 130), one or more volatile memory devices (e.g., storage device 140), or a combination thereof.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a combination of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual inline memory modules (NVDIMMs).

[0027] The computing environment 100 can include a host system 105 coupled to a memory system. The memory system can be one or more memory subsystems 110. In some examples, the host system 105 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 105 coupled to a memory subsystem 110 is illustrated. The host system 105 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0028] Host system 105 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), an embedded system, an Internet of Things (IoT) device, or any other computing device that includes memory and processing devices. Host system 105 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), and the like. The physical host interface can be used to transmit data between host system 105 and memory subsystem 110. When memory subsystem 110 is coupled to host system 105 via a PCIe interface, host system 105 can further utilize an NVM Express (NVMe) interface to access memory components (e.g., memory device 130). The physical host interface can provide an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 105.

[0029] The memory device may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Examples of nonvolatile memory devices (e.g., memory device 130) include three-dimensional (3D) cross-point ("3D cross-point") type flash memory, which is a cross-point array of nonvolatile memory cells. The cross-point array of nonvolatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, where nonvolatile memory cells can be programmed without previously erasing the nonvolatile memory cells.

[0031] Although a non-volatile memory component such as a 3D cross-point type memory is described, the memory device 130 can be based on any other type of non-volatile memory, such as NAND, read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), or a combination thereof. In some instances, a particular memory component may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. Each of the memory cells may store one or more data bits for use by the host system 105. Furthermore, the memory cells of the memory devices 130 may be grouped into memory pages or sets of memory cells, which may refer to units used to store data. Pages may be grouped across dies and channels to form management units (MUs). MUs may include user data and corresponding metadata. A super management unit (SMU) is a group of one or more MUs that are managed together.

[0033] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0034] The memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125. In the illustrated example, the local memory 125 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including controlling communications between the memory subsystem 110 and the host system 105.

[0035] In some instances, local memory 125 may include memory registers that store memory pointers, fetched data, etc. Local memory 125 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another example of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0036] In general, the memory subsystem controller 115 may receive commands or operations from the host system 105 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses (e.g., logical block addresses (LBAs)) and physical addresses. The memory subsystem controller 115 may also include host interface circuitry to communicate with the host system 105 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions for accessing the memory device 130, and convert responses associated with the memory device 130 into information for the host system 105.

[0037] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some examples, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0038] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory units of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage media device 130 (e.g., perform media management operations on media device 130). In some embodiments, memory device 130 can be a locally managed memory device, which is a raw memory device combined with a local media controller 135 that performs memory management operations on memory device 130 within the same memory device package.

[0039] The memory subsystem 110 includes a counter 150 that can count the number of access operations performed on a set of memory cells in the memory device and initiate maintenance operations on the memory cells, which can be based on a threshold number of access operations that can be modifiable. Coordinating (e.g., counting) the number of access operations on a particular set of memory cells can mitigate against a reduction in the lifespan of the memory subsystem 110. For example, counting the number of access operations experienced by a set of memory cells can allow wear-leveling operations to be performed on certain sets of memory cells (e.g., a set of memory cells that has reached the threshold number of access operations). Such wear-leveling operations can increase the lifespan of the memory subsystem 110.

[0040] In some cases, the counter 150 may count any number of access operations performed on the memory unit until a threshold number of access operations is reached. The counter 150 may also count any number of maintenance operations performed on the memory unit. The number of maintenance operations performed on the memory unit may be based on the amount of time that has elapsed while the counter 150 counts the number of access operations from 0 to the threshold number of access operations. In some examples, the memory subsystem controller 115 includes at least a portion of the counter 150. For example, the memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in the local memory 125 for performing the operations described herein. In some examples, the counter 150 is part of the host system 105, an application, or an operating system.

[0041] Counter 150 can count the number of access operations performed on a memory cell and can initiate a wear-leveling operation based on a criterion (e.g., a threshold for access operations). Counting the number of access operations can be accomplished by multiple portions of counter 150. In some embodiments, the counter includes two portions. A first portion of counter 150 can count the number of access operations until a criterion (e.g., a threshold) is met. Once the threshold is met, the first portion can restart counting. Once the first portion meets the threshold, the second portion of counter 150 can increment. The second portion can then initiate switching access operations to a different portion of the memory device (e.g., a different cell) and / or trigger a maintenance operation (e.g., a wear-leveling operation) on the memory cell. The second portion of counter 150 can store the number of times the criterion (e.g., the threshold) has been met. In some examples, the threshold is configurable, user / system-defined, and / or changeable. Further details regarding the operation of counter 150 are described below.

[0042] Figure 2 An example of a method 200 for determining coordination of wear leveling operations in a memory subsystem according to an embodiment of the present disclosure is described. The method 200 may be performed by a memory subsystem, which may be a reference Figure 1 An example of a memory subsystem 110 is described.

[0043] Method 200 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 200 may be performed by Figure 1150. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other approaches are possible.

[0044] The memory subsystem may receive access commands from the host system. Such access commands may be read commands, write commands, or erase commands that can read, erase, write, and / or rewrite data to specific memory cells in the memory devices of the memory subsystem. In some cases, accessing, erasing, or writing data in a memory cell may cause the memory cell to wear out, which may limit the lifespan of the memory cells within the memory subsystem. In some cases, if the memory subsystem is allowed to wear out, the lifespan of the memory subsystem may be reduced.

[0045] Maintenance operations may be used to reduce the impact of wear caused by access operations on memory cells in a memory subsystem. Maintenance operations may include various operations that reduce wear on the memory subsystem, including wear-leveling operations. In some examples, wear-leveling may limit the impact of wear caused by erasing, writing, and rewriting data to memory cells in the memory subsystem. Wear-leveling may be a process that helps reduce premature wear in a memory device by distributing write operations across the memory device. Wear-leveling may include determining which physical medium (e.g., a set of memory cells) to use for a set of operations. Each time data is programmed to help ensure that certain sets of physical memory cells are not written and erased more frequently than other sets of physical memory cells. Wear-leveling may ensure that wear on a particular memory cell is similar to wear experienced by other memory cells within the memory subsystem (e.g., wear across different cells can be balanced). In some examples, evenly distributing access operations across different cells in the memory subsystem may ensure that certain memory cells are not erased and rewritten more frequently than other memory cells. In some cases, a wear-leveling operation may be performed after a set number of access operations are performed on the memory cells. Thus, the wear experienced in the accessed memory cells of the memory subsystem may be evenly distributed across a different set of memory cells within the memory subsystem. This even distribution of wear experienced by the memory cells may extend the life of the memory subsystem.

[0046] The host system can send access requests to the memory subsystem to store data in the memory subsystem and read data from the memory subsystem. The data to be read and written is referred to as "user data" below. The host request can include the logical address of the user data (e.g., logical block address (LBA)), which is the location of the host system associated with the user data. The logical address (e.g., LBA) can be part of the metadata of the user data. The request can be in the form of an access operation command (e.g., a read command, a write command).

[0047] For example, at operation 215, the memory subsystem may receive an access operation command, for example, from a host system. The access operation command may initiate an access operation to a memory cell within a specific set of the memory subsystem. The access operation may include a read operation, an erase operation, a write operation, a rewrite operation, other operations, or a combination thereof, which may cause wear in the memory cell. The memory subsystem may continuously receive consecutive access operations for the same memory cell within the same set of cells on the memory subsystem, which may cause additional wear. In some cases, the consecutive access operations on the memory cells within the set may occur before the memory subsystem performs access operations on the memory cells in other sets of the memory subsystem. Additionally or alternatively, the access operation may be performed without performing periodic wear leveling operations on the accessed memory cells. This may cause the accessed memory cells to wear out prematurely compared to the non-accessed memory cells in other sets of the memory subsystem.

[0048] Wear leveling operations may be performed on memory cells within a set of memory subsystems, and the wear leveling operations may be performed after a specific number of access operations have been performed on the memory cells. Counting the number of access operations performed on individual memory cells within the set may allow the memory subsystem to coordinate wear leveling operations performed on different sets of memory cells. To reduce wear on specific memory cells in a set, counting the number of access operations performed on the memory cells may be used. Additionally, the memory subsystem may determine a threshold number of access operations performed on the memory cells before performing wear leveling operations on previously accessed cells. Counting the number of access operations performed on the memory cells may prevent the accessed memory cells from wearing out at a higher rate than other less accessed cells in the memory subsystem. Thus, after a specific access operation count has occurred, the memory subsystem may suspend access operations on the accessed cells within the memory subsystem and, in some instances, initiate wear leveling operations.

[0049] The memory subsystem may identify a limit on the number of access operations that may be performed on memory cells within a particular set. The number of access operations (e.g., count / value) that a set of the memory subsystem may experience before a wear leveling operation is initiated may be a fixed number. In some examples, this number may be considered a threshold. The threshold of access operations that a set may experience before initiating a wear leveling operation may be hundreds, thousands, tens of thousands, or hundreds of thousands of access operations. The threshold may be stored in a register of the memory subsystem. In some cases, the value of the threshold may be configurable so that the memory subsystem can be configured to modify the threshold. In some embodiments, the memory subsystem receives one or more threshold values ​​from a host system and may store the values ​​in a register of the memory subsystem.

[0050] For example, at operation 220, the memory subsystem determines a first threshold, such as by using a threshold in an access register. The memory subsystem may use the first threshold as the number of access operations that occur on the memory cells within the set before switching access operations to a new set and initiating a wear-leveling operation. In some cases, the threshold may be variable, adapting to different values ​​to reduce or increase the number of access operations performed on the memory cells within the set. For example, when the memory subsystem is new (e.g., the number of access operations performed on the memory cells is low), the threshold may be high. However, as the memory subsystem ages (e.g., the memory cells experience more access operations), the threshold may be reduced to allow for more frequent wear-leveling operations to occur within the memory subsystem. This reduction in the threshold may extend the life of the memory subsystem. However, in some instances, the threshold may remain the same throughout the life of the memory subsystem. In other instances, the threshold may increase. Thus, in some instances, the memory subsystem may determine a second threshold at any time that may be different from the first threshold. The second threshold may be stored in a register. The second threshold may replace the first threshold and may be used in continuous wear leveling coordination operations (eg, operations 235-255). In some cases, the first threshold may be used in all wear leveling operations without using any other (eg, second) threshold.

[0051] The memory subsystem may identify a count of the number of access operations performed on memory cells within the set of memory subsystems. In some examples, the count may be checked based on the divisibility of the number by a threshold to determine whether the count has met the threshold (which may initiate a wear leveling operation). In some cases, this may be implemented by a divider circuit. The divider circuit may utilize a divisor that corresponds to the threshold. However, the divider circuit may be limited to a particular divisor. For example, the divisor may be limited to a power of two (e.g., 2 nIn this case, a divisor that is not a power of two cannot be used as a divisor by the divider circuit. Consequently, the divider circuit may be inflexible with respect to the thresholds that can be used. Furthermore, the divider circuit may be expensive, which may be due to the complexity of the divider circuit's circuitry. For example, the divider circuit may use multiple gates, thereby increasing the area of ​​the divider circuit or consuming a significant amount of power. Therefore, it may be advantageous to determine the access operation count by other methods.

[0052] The use of a divider circuit to count the number of access operations performed on memory cells within a set of memory subsystems can be avoided by utilizing a combinational counter. Figure 3 The described combinatorial counter 305 may be an example of such a combinatorial counter. Each set of memory cells within a memory subsystem may include its own combinatorial counter that can count the number of access operations performed on the memory cells within the set. For example, the combinatorial counter can identify (e.g., determine) a count of the number of access operations performed on the memory cells within the set.

[0053] The combined counter may have a first counter and a second counter. Figure 3 Describing in more detail, the first counter may be an example of the first counter 315 and the second counter may be an example of the second counter 345. The first counter may count the number of access operations performed on the memory cells in the set. The first counter may count the number of access operations from zero to a defined number (e.g., a threshold of access operations) and determine whether the threshold of access operations has been reached. For example, a comparator may be used to compare the count of access operations performed on the memory cells in the set with the threshold. Reference Figure 3 The described comparator 330 may be an example of such a comparator. At operation 235, the first counter may increment the count by an integer (e.g., 1) and transmit the incremented value to the comparator. At operation 240, the comparator may compare the incremented value with a threshold. In some examples, at operation 240, the comparator may determine that the incremented count has not yet met (e.g., is less than) the threshold. In this example, at operation 245, the first counter may receive a returned incremented count value, which may be selected based on the incremented count not meeting (e.g., being less than) the threshold. However, in some cases, at operation 240, the comparator may determine that the incremented value meets (e.g., matches or exceeds) the threshold. In this case, at operation 245, the first counter may be reset to a zero value. The zero value may then be incremented, which may be based on successive access operations performed on the memory cells in the set. The first counter may then repeatedly increment the count until the threshold is reached again.

[0054] The second counter of the combined counter may trigger a wear leveling operation on the set and, in addition or alternatively, count the number of wear leveling operations performed on the set. The wear leveling operation count may initially be 0, which may indicate that a wear leveling operation has not previously been performed on the memory cells in the set (e.g., a threshold has not yet been met). At operation 250, the second counter may increment the value from 0 to 1. However, in some instances, the increment may increase to a non-zero number when the threshold has not previously been reached. In instances where the comparator has determined that the incremented first counter value (e.g., the number of access operations) is less than the threshold, at operation 255, the second counter may receive a returned selected non-incremented count (e.g., 0). However, in instances where the comparator has determined that the first counter count value matches the threshold, at operation 255, the second counter may receive a returned selected incremented count (e.g., 1).

[0055] In the event that the comparator has received an incremented count, a maintenance operation may be triggered, which may include a wear leveling operation. The maintenance operation may be performed by the memory subsystem. The operation may be initiated by firmware of the memory subsystem. Triggering the maintenance operation may be initiated by the second counter indicating that the second counter has incremented (e.g., indicating that the comparator has determined that the first counter has reached a threshold).

[0056] To initiate a maintenance operation, at operation 260, the memory subsystem may transmit an indicator to the memory subsystem. An example of such an indication may be a specific physical address of the set at which the second counter has indicated an increment (e.g., the first counter has met a threshold). This may trigger the memory subsystem to initiate a maintenance operation at operation 265, which may be a wear-leveling operation. Additionally or alternatively, the memory subsystem may suspend access operations on the memory cells within the set and move the access operations to a different set of memory cells in the memory subsystem. At operation 270, the memory subsystem may perform a maintenance operation on the memory cells within the set. The maintenance operation may be a wear-leveling operation, or another type of maintenance operation. The maintenance operation may prevent access operations from being performed on the memory cells within the set. Once access operations are performed on the memory cells, the previously described process for triggering maintenance operations may be repeatedly performed, which may be after wear-leveling has been completed.

[0057] As previously discussed, the memory subsystem may change the first threshold to a second threshold that may be different from the first threshold. In some examples, the memory subsystem may change the threshold to the second threshold. The change in threshold may be based on a variety of factors, including the age of the memory subsystem, the number of access operations performed on the memory subsystem, or other considerations. At operation 280, the memory subsystem may receive the second threshold. In some examples, the threshold may be stored in a register of the memory subsystem. In some cases, the memory subsystem may receive the new threshold via a message from the host system.

[0058] Similar to operation 220, a second threshold value may be used as a threshold value for the combined counter. Successive operations (e.g., 235-270) may be performed again using the second threshold value. In one example, the second threshold value may be less than the first threshold value and may be recognized by the memory subsystem when the number of access operations performed on the set of memory cells has previously exceeded the second threshold value. In this case, the comparator may determine that the threshold value has been met. For example, matching of the threshold value to the access operation count may not be used in a case where the modified second threshold value is less than the current access operation count value. The comparator may determine that the access operation count is greater than the threshold value, which may satisfy the threshold value. In some examples, operation 280 may be performed in a case other than Figure 2 For example, at any point during method 200, the first threshold may be changed to a second threshold and determined by the memory subsystem (e.g., operation 280). Thus, the changed threshold (whether the second threshold, such as Figure 2 , or a third threshold, or any other number of consecutive thresholds) may be determined by the memory subsystem and used as thresholds for consecutive wear leveling operation coordination steps.

[0059] Figure 3 An example of a counting system 300 that supports maintenance operations for a memory system according to examples as disclosed herein is illustrated. The counting system 300 may be an example of a counting system for a collection of individual memory cells within a memory subsystem. Figure 2 The described memory subsystem may be an example of such a memory subsystem. In some examples, each set of memory cells may utilize a corresponding counting system (e.g., each set of memory cells may have a corresponding combinational counter 305). Thus, multiple counting systems may exist in a memory subsystem.

[0060] The counting system 300 may include a combined counter 305 and a memory subsystem controller 310. Figure 1The depicted memory subsystem controller 115 may be an example of a memory subsystem controller. The memory subsystem controller 310 may receive commands (access operation commands and wear leveling operation commands) from the host system. The combined counter 305 may be coupled to the memory subsystem controller 310, which may allow the memory subsystem controller 310 and the combined counter 305 to transfer information between the memory subsystem controller 310 and the combined counter 305. Examples of the transferred information may be access operation commands, wear leveling operation commands, thresholds, increment indications, and / or other information.

[0061] A memory subsystem including the counting system 300 may receive access operation commands from a host system. The memory subsystem controller 310 may perform access operations (e.g., reading, erasing, writing, and / or rewriting data) on specific memory cells corresponding to a memory set associated with the combinational counter 305. In some examples, the combinational counter 305 may receive access operation commands from the memory subsystem controller 310, which may be directed to memory cells within the corresponding set of the combinational counter. The combinational counter 305 may include a first counter 315 and a second counter 345. The first counter 315 may count the number of access operation commands received by the combinational counter 305. For example, the first counter 315 may receive access operation commands from the memory subsystem controller 310. After receiving the access operation commands, the first counter 315 may output the current access operation count to the first incrementer 325. The first incrementer 325 may increment the value of the number of access operations by a fixed number (e.g., 1) based on the current count of access operations (e.g., to a value of 2 when the number of access operations may be 1). The first incrementer 325 may output the incremented access operation count to the comparator 330 and the first selector 335.

[0062] The memory subsystem may determine one or more thresholds. Figure 2As described, the threshold value may correspond to the number of access operations performed on the memory cells in the set before a maintenance operation can be performed. A wear-leveling operation is an example of such a maintenance operation. While a wear-leveling operation is described herein, any other type of maintenance operation may be performed in addition or alternatively. The memory subsystem controller 310 may transmit the threshold value to the combined counter 305. Threshold value 320 may be an example of such a threshold value. In some examples, threshold value 320 may be a variety of threshold values. For example, threshold value 320 may be 1,000, 5,000, 30,000, or other higher or lower values. Thus, in some examples, threshold value 320 may set the number of bits used by the first counter 315 to count the number of access operations. For example, eleven bits may be used to count up to the corresponding threshold value of 30,000. However, in some examples, the lower threshold value (e.g., 5,000) may use fewer bits. However, in some examples, the number of bits used for the threshold value may be set by the highest threshold value (e.g., 30,000).

[0063] The memory subsystem controller 310 may transmit the threshold 320 to the comparator 330. The comparator 330 may be an example of a variety of comparator circuits. The comparator 330 may use the threshold 320 to compare with the incremented count of the access operation received from the first incrementer 325. The comparator 330 may compare two values ​​(e.g., the threshold and the incremented count) and determine whether the incremented value matches the threshold 320. In some examples, the threshold 320 may be greater than the incremented count. In this example, the comparator 330 may output a low signal (e.g., 0) to two selector components: the first selector 335 and the second selector 340. However, in some examples, the threshold 320 may meet the incremented count (e.g., the same number, or greater than the incremented count). In this example, the comparator 330 may output a high signal (e.g., 1) to the first selector 335 and the second selector 340.

[0064] The first selector 335 can select a count value to be output to the first counter 315. The first selector 335 can be an example of a variety of selector-type circuits, such as a multiplexer, a switch, or other types of selector circuits. The count output by the first selector 335 can be based on a high signal or a low signal (e.g., 1 or 0, respectively) received from the comparator 330. For example, the first selector 335 can receive an incremented count from the first incrementer 325 at a second input 337. The first selector 335 can also receive a null (e.g., 0) value at a first input 336. The first selector 335 can also receive an output from the comparator 330 at a selector input 338. The selector input 338 can be used to determine which count value (e.g., the first input 336 or the second input 337) is output from the first selector 335 (e.g., via an output 339) and returned to the first counter 315. The count value may be 0 (eg, from a null input) or it may be an incremented count from the first incrementer 325 (eg, the second input 337).

[0065] The selection between 0 or the incremented count can depend on the value received at the selector input 338. For example, when the selector input 338 (e.g., the output of the comparator 330) is a low value (e.g., 0), the first selector 335 can output the incremented count from the output 339 to the first counter 315. This incremented count can then be used as the current count of the number of access operations performed on the memory cells within the set by the first counter 315. The count value can be repeatedly incremented using similar steps as previously described until the comparator 330 determines that the incremented count matches the threshold 320. In another case, when the selector input 338 is a high value (e.g., 1), the first selector 335 can output a 0 value from the output 339 to the first counter 315. The 0 value can be used to reset the first counter 315's count of the number of access operations performed on the memory cells within the set. The reset of the first counter 315 count to 0 can indicate that a wear leveling operation can occur. For example, resetting the current count to 0 may indicate that the value of the count has been incremented from 0 to the threshold 320, and a wear-leveling operation may be initiated. The current count (e.g., 0) may be repeatedly incremented using similar steps as previously described until the threshold is reached again (e.g., the comparator 330 determines that the incremented count matches the threshold 320). In some cases, the first selector 335 and the second selector 340 may additionally or alternatively include more inputs than the first inputs 336 and 341, the second inputs 337 and 342, and the selector inputs 338 and 343, respectively. For example, the first selector 335 and the second selector 340 may receive more inputs from other components, such as incrementers, comparators, counters, or other types of counting components.

[0066] The combined counter 305 may include a second counter 345, a second incrementer 350, and a second selector 340. These components may be used to count the number of maintenance operations that can be performed on the memory cells in the set. In some examples, the second counter 345 may count the current value of the maintenance operations (e.g., the number of maintenance operations that can be performed). The second counter 345 may output the count of wear-leveling operations to the second incrementer 350 and the second selector 340. The second incrementer 350 may increment the count of the number of wear-leveling operations by a fixed number (e.g., 1) based on the current count of wear-leveling operations (e.g., incrementing to 2 when the number of wear-leveling operations is 1). The second incrementer 350 may output the incremented count of wear-leveling operations to the second selector 340.

[0067] The second selector 340 can select a value for the wear-leveling operation count to output to the second counter 345. Similar to the first selector 335, the second selector 340 can be a variety of selector-type circuits, such as a multiplexer, a switch, or other types of selector circuits. As previously discussed, the count output by the second selector 340 can be based on a high or low signal (e.g., 1 or 0, respectively) received from the comparator 330. For example, the second selector 340 can receive an incremented count from the second incrementer 350 at a second input 342. The second selector 340 can also receive the current count from the second counter 345 at a first input 341. The second selector 340 can also receive the output from the comparator 330 at a selector input 343. The selector input 343 can be used to determine which count value (e.g., the first input 341 or the second input 342) to return to the second counter 345. The wear-leveling operation count value can be the current count (e.g., from the first input 341) or it can be the incremented count (from the second input 342).

[0068] The selection between the current count or the incremented count can depend on the value received at the selector input 343. For example, when the selector input 343 (e.g., the output of the comparator 330) is a low value (e.g., 0), the second selector 340 can output the current count from the output 344 to the second counter 345. This count can be used as the current count of the number of wear-leveling operations performed on the memory cells in the set. This count value cannot be incremented because it has not yet passed through the second incrementer 350. Thus, in this example, the count value can remain the same when the selector input 343 receives a low signal (e.g., 0). In another case, when the selector input 343 is a high value (e.g., 1), the second selector 340 can output the incremented count to the second counter 345 at the output 344. Incrementing the current count to a higher value (e.g., from 0 to 1 at the second selector 340) can indicate that a wear-leveling operation can occur for the memory cells in the set. In this example, the second counter 345 can communicate with the memory subsystem controller 310, which can include information about triggering a wear leveling operation, and the memory subsystem controller 310 can initiate a maintenance operation in the aggregated memory cells, as described with reference to FIG. Figure 2 described.

[0069] In some examples, a total count of the number of access operations performed on the memory cells within the set corresponding to the combinatorial counter 305 can be determined. In some cases, as previously discussed, the first counter 315 and the first incrementer 325 can increment the count of access operations until the comparator 330 determines that the incremented count matches the threshold 320. In some examples, when the comparator 330 compares the incremented count value with the threshold 320 and determines that the value meets the threshold 320, the count of the first counter 315 can return to 0. In this case, the second selector 340 can return the incremented count of the wear-leveling operation to the second counter 345. The second counter 345 can output the address of the set to the memory subsystem controller 310, which can initiate the wear-leveling operation. In some examples, when the comparator 330 subsequently determines that the incremented count of access operations (e.g., the output of the first incrementer 325) meets the threshold 320, the second counter 345 can be incremented again using this incremented value of the wear-leveling operation. However, the current count of wear-leveling operations (e.g., the count of the second counter 345) may additionally or alternatively allow for the determination of the total count of access operations performed on the memory cells in the set. For example, the first counter 315 may increment from 0 to a threshold 320. Once the threshold 320 is met (which may indicate the current number of access operations), the second counter 345 may increment the count. The incremented count of the second counter 345 may be considered the number of times the count of access operations has reached the threshold 320. Thus, in some examples, the count of the second counter 345 may be the number of repetitions of the access operation value of the threshold 320. In other words, the count of the second counter 345 may be considered the wear-leveling operation count multiplied by the threshold 320. In this example, the total count of the combined counter 305 may be determined by adding the count of the first counter 315 (e.g., the current number of access operations below the threshold 320) to the product of the count of the second counter 345 and the threshold 320 (e.g., the number of wear-leveling operations multiplied by the threshold for wear-leveling operations). Therefore, the total number of access operations for the combined counter 305 may be determined by utilizing the count of the first counter 315 , the count of the second counter 345 , and the threshold 320 .

[0070] Figure 4 An example of a counting system 400 supporting maintenance operations for a memory system according to examples disclosed herein is described. The counting system 400 can be configured to track access operations on a set of memory cells as part of performing maintenance operations, such as wear leveling operations. The counting system 400 can be implemented by a controller, software, firmware, hardware, or a combination thereof.

[0071] In some counting systems, the counting system can be used to track wear-leveling operations for sets of memory cells, using a global minimum counter and one or more set-specific counters to track the difference between the global minimum and the specific set. The global minimum counter can track the value of the access operation on the memory set with the least number of access operations. The set-specific counter can track the difference between the specific count of the set and the global minimum. Using this type of counting system, the total number of bits used to implement the counters can be reduced. For example, instead of maintaining a 16-bit counter for each set, the system can maintain a much smaller counter (e.g., two, three, four, five, six, seven, or eight bits) for the 16-bit global minimum counter and a difference counter for the specific set. In such a system, when the global minimum counter is updated or incremented, each of the set-specific difference counters can also be updated. Such operations can consume power and computing resources.

[0072] Aspects of the present disclosure address the above and other deficiencies by including a memory subsystem configured to track counters for access operations on a set using a global counter 405, an offset counter 410, and one or more set-specific counters 415. An algorithm 420 can use the values ​​of each of the global counter 405, the offset counter 410, and the one or more set-specific counters 415 to determine a count 425 of access operations performed on each set. The counting system 400 can be configured to allow the global counter 405 (e.g., a global minimum counter) to be updated without having to update each of the set-specific counters 415. Any number of set-specific counters (e.g., set-specific counters 415-a, set-specific counters 415-b, set-specific counters 415-c, ..., set-specific counters 415-N) can be present to identify any number of counts (e.g., counts 425-a, 425-b, 425-c, ..., 425-N) for any number of sets of memory cells.

[0073] The global counter 405 may be an example of a global minimum counter. The global counter 405 may track the value of the access operation on the memory set with the least amount of access operations. The controller may identify which set has the least amount of access operations and set the global counter 405 to the access operation value. In some cases, as the number of access operations performed on the memory unit set increases, it may be necessary to update the global counter 405.

[0074] The offset counter 410 can be configured to update the global counter 405 without affecting the set-specific counters 415. The offset counter 410 can be an instance of a global counter and can be used to determine the count 425 for one or more sets. The value of the global counter 405 and the value of the offset counter 410 can be used to determine the global lowest significant value of access operations performed on the set of memory cells. In some cases, the global lowest significant value is equivalent to the value of the global minimum counter. In some embodiments, when the global lowest significant value changes, the controller can update or modify the value of the offset counter 410 instead of modifying or updating the value of the global counter 405. In this way, at least in some cases, the controller can update the global lowest significant value without updating the value of the set-specific counter 415.

[0075] The set-specific counter 415 may be an example of a counter that tracks at least some aspects of the difference between the actual count 425 of access operations performed on a particular set and the global counter 405. The set-specific counter 415 may be configured to cooperate with the offset counter 410 and the global counter 405 to determine the count 425 associated with the particular set.

[0076] Algorithm 420 may be configured to determine a count 425 of access operations performed on each set using the values ​​of global counter 405, offset counter 410, and set-specific counter 415. Equation 1 illustrates an example of a procedure that may be used as part of algorithm 420.

[0077] Count=α+((β-γ)mod(δ)) (1)

[0078] In Equation 1, the term α may refer to the value of the global counter 405 ; the term β may refer to the value of the set-specific counter 415 ; the term γ may refer to the value of the offset counter 410 ; and the term δ may refer to the modifier value.

[0079] A controller implementing algorithm 420 to determine a count 425 of access operations on a set can be configured to identify a value of global counter 405. The value of global counter 405 can indicate a baseline number of access operations performed on a set of memory cells. As part of determining a count 425-a associated with a particular set of memory cells, the controller can determine a difference between the value of set-specific counter 415-a and the value of offset counter 410. Set-specific counter 415-a can be associated with a first set of memory cells. Offset counter 410 can be used to indicate a global offset value relative to the value of global counter 405.

[0080] A controller implementing algorithm 420 may be configured to identify the remainder using a modulo operation. For example, the controller may apply a modulo operation using the difference between the value of the set-specific counter 415-a and the value of the offset counter 410 and a modifier value or parameter. The modifier value may be any value. In some cases, the modifier value may be associated with an upper limit on the difference between the value of the global counter 405 and the value of the set-specific counter 415 that the counting system will tolerate. In some cases, the modifier value may be associated with the number of bits associated with the value of the set-specific counter 415.

[0081] A controller implementing algorithm 420 may be configured to add the value of global counter 405 to the earlier determined remainder. The sum of the value of global counter 405 and the remainder may be a count 425-a (eg, number) of access operations performed on a particular set.

[0082] The controller may use the count 425 to determine whether to perform a maintenance operation (eg, a wear leveling operation). The controller may compare the count 425 to a threshold value (eg, a reference value). Figure 2 and 3 described) and maintenance operations may be initiated based on the comparison.

[0083] Figure 5 A flowchart illustrating one or more methods 500 for supporting maintenance operations for a memory system according to aspects of the present disclosure is shown. The method 500 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 may be performed by Figure 1 150. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other approaches are possible.

[0084] At 505 , a processing device may perform an access operation on a memory unit.

[0085] At 510 , the processing device may increment a value of a first counter based on performing an access operation on a memory unit.

[0086] At 515 , the processing device may determine that the incremented value of the first counter satisfies a threshold.

[0087] At 520 , the processing device may increment the value of the second counter based on determining that the incremented value of the first counter satisfies the threshold.

[0088] At 525 , the processing device may perform a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold.

[0089] In some examples, an apparatus as described herein can perform one or more methods, such as method 500. The apparatus can include a controller operable to cause the apparatus to perform the methods described herein. For example, the controller can cause the apparatus to perform an access operation on a memory cell; increment a value of a first counter based on performing the access operation on the memory cell; determine that the incremented value of the first counter satisfies a threshold; increment a value of a second counter based on determining that the incremented value of the first counter satisfies the threshold; and perform a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold.

[0090] In other examples, the apparatus may include features, means, or instructions (eg, a non-transitory computer-readable medium storing instructions executable by a processor) for performing the features of the methods described herein.

[0091] An apparatus is described for performing method 500. The apparatus may include means for performing an access operation on a memory cell; means for incrementing a value of a first counter based at least in part on performing the access operation on the memory cell; means for determining that the incremented value of the first counter satisfies a threshold; means for incrementing a value of a second counter based at least in part on determining that the incremented value of the first counter satisfies the threshold; and means for performing a maintenance operation on the memory cell based at least in part on determining that the incremented value of the first counter satisfies the threshold.

[0092] In some examples, the apparatus may support means for setting the value of the first counter to the incremented value based at least in part on determining that the incremented value of the first counter fails to satisfy a threshold.

[0093] In some examples, the apparatus may support means for setting the value of the first counter to a baseline value associated with the first counter based at least in part on determining that the incremented value of the first counter satisfies a threshold.

[0094] In some examples, the apparatus may support means for setting the value of the second counter to the incremented value based at least in part on determining that the incremented value of the first counter satisfies a threshold.

[0095] In some examples, the apparatus may support means for setting the value of the second counter to a current value of the second counter based at least in part on determining that the incremented value of the first counter fails to satisfy a threshold.

[0096] In some instances, the apparatus may support means for receiving a message indicating that a second threshold is different than the threshold and means for determining that the incremented value of the first counter satisfies the second threshold received in the message, wherein performing the maintenance operation is based at least in part on determining that the incremented value of the first counter satisfies the second threshold.

[0097] In some examples, the apparatus may support means for comparing the incremented value of the first counter to a threshold, wherein determining that the incremented value of the first counter satisfies the threshold is based at least in part on the comparison, wherein a comparator circuit compares the incremented value of the first counter to the threshold.

[0098] In some examples, the maintenance operation includes a wear leveling operation. In some examples, the first selector circuit sets the value of the first counter based at least in part on determining whether the incremented value of the first counter satisfies a threshold. In some examples, the first selector circuit includes a multiplexer having a first data input, a second data input, and a select input, the first data input being configured to receive the incremented value of the first counter, the second data input being configured to receive a baseline value associated with the first counter, and the select input being configured to receive a Boolean value indicating whether the incremented value of the first counter satisfies the threshold.

[0099] In some instances, the second selector circuit sets the value of the second counter based at least in part on determining whether the incremented value of the first counter satisfies a threshold, and the second selector circuit includes a multiplexer having a first data input, a second data input, and a select input, wherein the first data input is configured to receive the incremented value of the second counter, the second data input is configured to receive the value of the second counter, and the select input is configured to receive a Boolean value indicating whether the incremented value of the first counter satisfies the threshold.

[0100] Figure 6 A flowchart illustrating one or more methods 600 for supporting maintenance operations for a memory system according to aspects of the present disclosure is shown. The method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 may be performed by Figure 1 150. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other approaches are possible.

[0101] At 605 , a processing device may perform an access operation on a memory unit.

[0102] At 610 , the processing device may increment a value of a first counter based on performing an access operation on a memory unit.

[0103] At 615 , the processing device may determine that the incremented value of the first counter satisfies a threshold.

[0104] At 620 , the processing device may set the value of the first counter to the incremented value based on determining that the incremented value of the first counter fails to satisfy the threshold.

[0105] At 625 , the processing device may increment the value of the second counter based on determining that the incremented value of the first counter satisfies the threshold.

[0106] At 630 , the processing device may perform a maintenance operation on the memory cell based on determining that the incremented value of the first counter satisfies the threshold.

[0107] Figure 7 A flowchart illustrating one or more methods 700 for supporting maintenance operations for a memory system according to aspects of the present disclosure is shown. The method 700 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 700 may be performed by Figure 1 150. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other approaches are possible.

[0108] At 705 , the processing device may determine that a first number of access operations performed on a memory unit satisfies a first threshold.

[0109] At 710 , the processing device may perform a first wear leveling operation on the memory cell based on determining that a first number of access operations performed on the memory cell satisfies a first threshold.

[0110] At 715 , the processing device may receive a message indicating a second threshold.

[0111] At 720 , the processing device may determine that a second number of access operations performed on the memory unit after performing the first wear leveling operation satisfies a second threshold.

[0112] At 725 , the processing device may perform a second wear leveling operation on the memory cell based on determining that the second number of access operations satisfies the second threshold.

[0113] The apparatus may include a controller operable to cause the apparatus to perform the method described herein. For example, the controller may cause the apparatus to determine that a first number of access operations performed on a memory cell satisfies a first threshold; perform a first wear leveling operation on the memory cell based on determining that the first number of access operations performed on the memory cell satisfies the first threshold; determine a second threshold; determine that a second number of access operations performed on the memory cell after performing the first wear leveling operation satisfies the second threshold; and perform a second wear leveling operation on the memory cell based on determining that the second number of access operations satisfies the second threshold.

[0114] In other examples, the apparatus may include features, means, or instructions (eg, a non-transitory computer-readable medium storing instructions executable by a processor) for performing the features of the methods described herein.

[0115] An apparatus is described for performing method 700. The apparatus may include means for determining that a first number of access operations performed on a memory cell satisfies a first threshold; means for performing a first wear leveling operation on the memory cell based at least in part on determining that the first number of access operations performed on the memory cell satisfies the first threshold; means for receiving a message indicating a second threshold; means for determining that a second number of access operations performed on the memory cell after performing the first wear leveling operation satisfies a second threshold; and means for performing a second wear leveling operation on the memory cell based at least in part on determining that the second number of access operations satisfies the second threshold.

[0116] In some examples, the apparatus may support means for determining that a second number of access operations exceeds a second threshold, wherein determining that the second number of access operations satisfies the second threshold is based at least in part on determining that the second number of access operations exceeds the second threshold.

[0117] In some examples, the apparatus may support means for determining that the second number of access operations matches a second threshold, wherein determining that the second number of access operations satisfies the second threshold is based at least in part on determining that the second number of access operations matches the second threshold.

[0118] In some examples, the apparatus may support means for modifying, by the memory device, the first threshold to a second threshold based at least in part on receiving the message, wherein determining that the second number of access operations satisfies the second threshold is based at least in part on modifying the first threshold to the second threshold.

[0119] In some examples, the apparatus may support means for performing an access operation on the memory unit after receiving the message, wherein determining that the second number of access operations satisfies the second threshold occurs after performing the access operation.

[0120] Figure 8 A flowchart illustrating one or more methods 800 for supporting maintenance operations for a memory system according to aspects of the present disclosure is shown. The method 800 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 800 may be performed by Figure 1 150. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other approaches are possible.

[0121] At 805 , the processing device may identify a global counter associated with performing a wear leveling procedure on a set of memory cells, a value of the global counter indicating a baseline number of access operations performed on the set of memory cells.

[0122] At 810 , the processing device may determine a difference between a value of a set-specific counter associated with a first set of sets of memory cells and a value of an offset counter indicating a global offset value relative to the value of the global counter.

[0123] At 815 , the processing device may identify a remainder and a parameter of the difference.

[0124] At 820 , the processing device may identify a number of access operations performed on the first set based on adding the remainder to the value of the global counter.

[0125] At 825 , the processing device may perform a wear leveling operation on the first set based on the number of access operations performed on the first set satisfying a threshold.

[0126] The apparatus may include a controller operable to cause the apparatus to perform the method described herein. For example, the controller may cause the apparatus to identify a global counter associated with performing a wear leveling procedure on a set of memory cells in a memory device, the value of the global counter indicating a baseline number of access operations performed on the set of memory cells; determine a difference between a value of a set-specific counter and a value of an offset counter, the set-specific counter being associated with a first set of the memory cells, the offset counter indicating a global offset value relative to the value of the global counter; identify a remainder and a parameter of the difference; identify a number of access operations performed on the first set based on adding the remainder to the value of the global counter; and perform a wear leveling operation on the first set based on the number of access operations performed on the first set satisfying a threshold.

[0127] In other examples, the apparatus may include features, means, or instructions (eg, a non-transitory computer-readable medium storing instructions executable by a processor) for performing the features of the methods described herein.

[0128] An apparatus is described for performing method 800. The apparatus may include means for identifying a global counter associated with performing a wear leveling procedure on a set of memory cells in a memory device, a value of the global counter indicating a baseline number of access operations performed on the set of memory cells; means for determining a difference between a value of a set-specific counter and a value of an offset counter, the set-specific counter being associated with a first set of the memory cells, the offset counter indicating a global offset value relative to the value of the global counter; means for identifying a remainder and a parameter of the difference; means for identifying a number of access operations performed on the first set based at least in part on adding the remainder to the value of the global counter; and means for performing a wear leveling operation on the first set based at least in part on the number of access operations performed on the first set satisfying a threshold.

[0129] In some examples, the apparatus may support means for performing a modulo operation on the difference using the parameter, wherein identifying the number of access operations to perform on the first set is based at least in part on performing the modulo operation and means for adding a remainder to a value of the global counter, wherein identifying the number of access operations to perform on the first set is based at least in part on adding the remainder to the value.

[0130] In some examples, the apparatus may support means for identifying a second set of the sets of memory cells having a least number of access operations; means for identifying that additional access operations are performed on the second set; and means for incrementing a value of an offset counter based at least in part on identifying that additional access operations are performed on the second set.

[0131] In some examples, a global least significant value for access operations performed on a set of memory cells is based at least in part on a value of a global counter and a value of an offset counter, and the global least significant value for access operations performed on the set of memory cells is updated without modifying one or more values ​​of set-specific counters.

[0132] Figure 9 An example machine of a computer system 900 supporting maintenance operations for a memory system according to examples as disclosed herein is illustrated. The computer system 900 may include an instruction set for causing the machine to perform any one or more of the techniques described herein. In some examples, the computer system 900 may correspond to a host system (e.g., a reference Figure 1 host system 105) that includes, is coupled to, or uses a memory subsystem (e.g., reference Figure 1 The memory subsystem 110 described herein may be used to perform operations of the controller (eg, to execute an operating system to execute operations corresponding to the reference Figure 1 In some examples, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a server or a client machine in a peer-to-peer (or distributed) network environment.

[0133] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0134] The example computer system 900 includes a processing device 905, a main memory 910 (e.g., read-only memory (ROM), flash memory, DRAM, such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 915 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 925, which communicate with each other via a bus 945.

[0135] The processing device 905 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements another instruction set, or a processor that implements a combination of instruction sets. The processing device 905 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 905 is configured to execute instructions 935 for performing the operations and steps discussed herein. The computer system 900 may further include a network interface device 920 for communicating over a network 940.

[0136] The data storage system 925 may include a machine-readable storage medium 930 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 935 or software embodying any one or more of the methods or functions described herein. The instructions 935 may also reside, completely or at least partially, within the main memory 910 and / or within the processing device 905 during execution by the computer system 900, with the main memory 910 and the processing device 905 also constituting machine-readable storage media. The machine-readable storage medium 930, the data storage system 925, and / or the main memory 910 may correspond to a memory subsystem.

[0137] In one example, the instructions 935 include implementing a method corresponding to the counting device 950 (e.g., referring to Figure 1 The machine-readable storage medium 930 is a device that stores instructions for performing the functions of the counting device 950 described herein. Although the machine-readable storage medium 930 is shown as a single medium, the term "machine-readable storage medium" may include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" may also include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0138] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have multiple bit widths.

[0139] As used herein, the term "virtual ground" refers to a circuit node that is maintained at approximately zero volts (0V) without being directly coupled to ground. Thus, the voltage of the virtual ground can fluctuate over time and return to approximately 0V in a steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. A "virtual ground" or "virtual earth ground" refers to a connection to approximately 0V.

[0140] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device containing the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some cases, for example, one or more intermediate components such as switches or transistors may be used to interrupt the flow of signals between the connected components for a period of time.

[0141] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to communicate between the components via the conductive paths, to a closed-circuit relationship between the components, in which signals can communicate between the components via the conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive paths that previously did not permit signal flow.

[0142] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0143] As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, etc., that provides an electrically conductive path between elements or components of a memory array.

[0144] The devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0145] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., most of the carriers are signals), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated."

[0146] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" and is not "preferred" or "advantageous" to other examples. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0147] In the accompanying drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference numerals with dashed lines and second labels that distinguish among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral regardless of the second reference numeral.

[0148] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0149] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software, hardware, firmware, hard wiring, or any combination thereof executed by a processor. The features of the implementation functions can also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), "or" indicates a list containing endpoints, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0150] Computer-readable media include both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disc storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code devices in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0151] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: a memory subsystem controller configured to receive access commands and wear leveling operation commands from a host device; a first counter coupled to the memory subsystem controller and configured to count the number of the access commands received by the memory subsystem controller; a comparator circuit coupled to the first counter and configured to compare the incremented value of the first counter to a threshold value; a first selector circuit coupled to the comparator circuit, wherein the first selector circuit includes a second data input and a select input, and wherein: The second data input is configured to receive a baseline value for resetting the first counter when the incremented value of the first counter meets the threshold, and the select input being configured to receive a value indicating whether the incremented value of the first counter satisfies the threshold; as well as A second counter is coupled to the memory subsystem controller and the first counter, wherein the second counter is configured to count the number of the wear leveling operation commands.

2. The memory device according to claim 1, Wherein the first selector circuit further includes a multiplexer and a first data input. 3 . The memory device of claim 2 , wherein the first selector circuit is configured to determine an incremented counter value of the first counter based at least in part on an output of the comparator circuit.

4. The memory device of claim 2, wherein: The first data input is configured to receive the incremented value of the first counter, wherein the value is a Boolean value.

5. The memory device of claim 1 , further comprising: A second selector circuit is coupled to the comparator circuit, wherein the second selector circuit is configured to determine an incremented counter value of the second counter based at least in part on an output of the comparator circuit.

6. A memory device comprising: a first counter associated with performing an access operation on a set of memory cells in the memory device; a second counter coupled to the first counter; a third counter associated with performing a wear leveling operation on the set of memory cells in the memory device; a fourth counter associated with a first one of the sets of memory cells; a fifth counter for indicating a global offset value relative to the value of the third counter; a second incrementer coupled to the second counter and configured to increment a value of the number of wear leveling operations; a comparator coupled to the first counter and configured to compare a value of the first counter with a threshold; as well as One or more selection circuits coupled to the comparator and configured to determine incremented counter values ​​for the first counter and the second counter based at least in part on an output of the comparator.

7. The memory device of claim 6, further comprising: A first incrementer is coupled to the first counter and configured to increment a value of a number of access operations based at least in part on a number of access commands received by the first counter.

8. The memory device of claim 6, wherein the one or more selection circuits include a first selection circuit, and wherein the first selection circuit is configured to set the value of the first counter based at least in part on determining that the incremented value of the first counter satisfies the threshold.

9. The memory device of claim 6, wherein the one or more selection circuits include a second selection circuit, and wherein the second selection circuit is configured to set the value of the second counter based at least in part on determining whether the incremented value of the first counter satisfies the threshold.

10. A memory device comprising: a first counter; a second counter; a second incrementer coupled to the second counter, wherein the second counter is configured to output a count of wear leveling operations to the second incrementer; a second selector circuit coupled to the second counter, wherein the second selector circuit includes a second data input and a select input, and wherein: The second data input is configured to receive the count of the second counter, and The select input is configured to receive a value indicating whether the incremented count of the first counter satisfies a threshold; and a controller coupled to the first counter and the second counter and operable to cause the memory device to: Tracking access operations performed on memory cells; incrementing a count of the first counter based at least in part on tracking the access operations performed on the memory cell; incrementing a count of the second counter based at least in part on the incremented count of the first counter satisfying the threshold; and Whether to perform a wear leveling operation on the memory cell is determined based at least in part on incrementing a count of the first counter and a count of the second counter.

11. The memory device of claim 10, further comprising: A first incrementer is coupled to the first counter. 12 . The memory device of claim 11 , wherein the first counter is configured to output a current access operation count to the first incrementer.

13. The memory device of claim 11, further comprising: a first selector circuit coupled to the first incrementer; and A comparator is coupled to the first incrementer and the first selector circuit, wherein the first incrementer is configured to output an incremented access operation count to the comparator and the first selector circuit.

14. The memory device of claim 13, wherein: The second selector circuit is coupled to the second incrementer and the comparator, wherein the second incrementer is configured to output an incremented wear-leveling operation count to the second selector circuit.

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