A compact CMOS-based RF transceiver switch

Abstract

The present invention discloses a compact CMOS-based radio frequency transceiver switch. The switch comprises a voltage source V1 and a radio frequency transceiver switch circuit. The switch circuit comprises an antenna port pin 1, a transmit path port pin 2, and a receive path port pin 3. A first nth-order lumped inductor-capacitor equivalent network is provided between the antenna port pin 1 and the transmit path port pin 2. A switch comprising an NMOS transistor NM1 is provided at the transmit path port pin 2 and connected in parallel to GND. A second nth-order lumped inductor-capacitor equivalent network is provided between the antenna port pin 1 and the receive path port pin 3. A switch comprising a PMOS transistor PM1 is provided at the receive path port pin 3 and connected in parallel to GND. The ground level of the radio frequency transceiver switch circuit is GND, and the power supply voltage is the power supply terminal VDD. The present invention reduces the chip area of ​​the switch, reduces the insertion loss introduced when the radio frequency signal passes through the transceiver switch, and improves the linearity performance of the switch in transmit mode.

Description

Technical Field

[0001] The present invention belongs to the field of CMOS radio frequency integrated circuit design, and in particular relates to a compact radio frequency transceiver switch based on CMOS. Background Art

[0002] For time division duplex radio frequency communication systems, the transceiver switch is a key component for the radio frequency system to switch between receiving and transmitting functions. Figure 1 The transmit-receive switch is a three-port device consisting of a transmit branch switch and a receive branch switch, where pin 1 is the antenna port, pin 2 is the transmit path port, and pin 3 is the receive path port. During normal operation, one and only one of the transmit branch switch and the receive branch switch is in the on state, and the other switch is in the off state. When the RF communication system operates in the transmit mode, the transmit branch switch is turned on and the receive branch switch is turned off, so that the signal of the transmit channel can be transmitted to the antenna end through the transmitted branch switch, and the received branch that is turned off can prevent the signal from entering the receive channel. When the RF communication system operates in the receive mode, the receive branch switch is turned on and the transmit branch switch is turned off, so that the signal received by the antenna end can be transmitted to the receive channel through the received branch switch, and the received branch that is turned off can prevent the signal from entering the transmit channel.

[0003] In order to improve energy efficiency and reduce interference, communication systems usually need to adopt low-loss, high-isolation transceiver switches. In the following analysis, the port impedance of pin1, pin2, and pin3 all default to the standard 50 ohms. Specifically, in the receiving mode: Since the receiving path side pays more attention to low noise and the suppression of the transmission leakage signal, this requires the lowest possible insertion loss between pin1 and pin3, and the highest possible isolation between pin1 and pin2, and pin1 and pin3 must have good port standing wave performance. In the transmitting mode: Since the transmitting path side pays more attention to high linearity and high output power, this requires the highest possible linearity and low insertion loss between pin1 and pin2, and pin1 and pin2 must have good port standing wave performance.

[0004] The radio frequency transceiver switch designed with the cheap CMOS process can improve the system integration, reduce the size of the communication system, and reduce the production cost. Based on the CMOS process, there is a transceiver switch that uses a transmission line-parallel switch structure. Figure 2Pins 1 and 2 are separated by a 1 / 4λ transmission line T1 with a characteristic impedance of 50 ohms. At pin 2, a switch consisting of an NMOS transistor NM1 is added and connected in parallel to GND. NM1's drain is connected to pin 2, its source is connected to ground, and its gate is controlled by the voltage level at node A. Pins 1 and 3 are separated by a 1 / 4λ transmission line T2 with a characteristic impedance of 50 ohms. At pin 3, a switch consisting of an NMOS transistor NM2 is added and connected in parallel to GND. NM2's drain is connected to pin 3, its source is connected to ground, and its gate is controlled by the voltage level at node B. The circuit ground level = GND, and the supply voltage = VDD. In the following analysis, the port impedances of pins 1, 2, and 3 are all assumed to be standard 50 ohms. In receive mode: the voltage level at node A = VDD, NM1 operates in the deep linear region, the switch it forms is in the on state, and the on-resistance of NM1 is close to 0 ohm. The impedance transformation effect of the 1 / 4λ transmission line T1 makes the impedance seen from pin 1 to pin 2 approach infinity, thereby preventing the RF signal from flowing from pin 1 into transmission line T1; the voltage level at node B = GND, NM2 operates in the cutoff region, and the switch it forms is in the off state; the RF signal can be transmitted from pin 1 to pin 3 through transmission line T2. In transmit mode: the voltage level at node B = VDD, NM2 operates in the deep linear region, the switch it forms is in the on state, and the on-resistance of NM2 is close to 0 ohm. The impedance transformation effect of the 1 / 4λ transmission line T2 makes the impedance seen from pin 1 to pin 3 theoretically approach infinity, thereby preventing the RF signal from flowing from pin 1 to transmission line T2; the voltage level at node A = GND, NM1 operates in the cutoff region, and the switch it forms is in the off state; the RF signal can be transmitted from pin 2 to pin 1 through transmission line T1.

[0005] The problems with the above solution are:

[0006] 1) The 1 / 4λ transmission line based on CMOS technology is long, resulting in high loss and large occupied area.

[0007] 2) In transmit mode, NMOS transistor NM1 should always operate in the cutoff region. However, due to the parasitic capacitance between the drain and gate of NM1, when the transmit signal increases to a certain level, the transient voltage generated by the transmit signal leaking to the gate causes NM1's operating region to shift to the linear region, causing NM1's on-resistance to change from high resistance to low resistance. As the transmit signal continues to increase, an increasing proportion of the transmit signal at pin 2 will be shunted to GND through NM1, resulting in gain compression of the transmit signal. This phenomenon limits the high linearity performance of the transmit path.

[0008] 3) In transmit mode, the gate voltage threshold that enables NM1's operating region to transition to the linear region can be increased by adding static level-switching ports to the drain and source of NM1, thereby alleviating the gain compression phenomenon that occurs when the transmit signal increases and improving the linearity performance of the switch in transmit mode. However, in order to ensure the normal operation of NM2, it is necessary to add a DC blocking capacitor in series in the signal path of the transmit branch, which will cause additional losses and increase the chip area. Summary of the Invention

[0009] The present invention aims to overcome the problems of the prior art by disclosing a compact CMOS-based radio frequency transceiver switch. This reduces the switch's chip area, minimizes the insertion loss introduced when the radio frequency signal passes through the transceiver switch, and improves the switch's linearity performance in transmit mode.

[0010] The object of the present invention is achieved through the following technical solutions:

[0011] A compact CMOS-based radio frequency transceiver switch, comprising: a voltage source V1 and a radio frequency transceiver switch circuit;

[0012] The negative electrode of the voltage source V1 is connected to the ground terminal GND, and the positive electrode of the voltage source V1 is connected to the power supply terminal VDD;

[0013] The RF transceiver switching circuit includes: antenna port pin1, transmitting path port pin2, receiving path port pin3,

[0014] A first n-order lumped inductor-capacitor equivalent network is provided between antenna port pin 1 and transmit path port pin 2. A switch comprising an NMOS transistor NM1 is provided at transmit path port pin 2 and connected in parallel to GND via capacitor C1. The drain of NMOS transistor NM1 is connected to transmit path port pin 2, the source of NMOS transistor NM1 is connected to ground via capacitor C1, and the gate of NMOS transistor NM1 is controlled by the voltage level at node A.

[0015] A second nth-order lumped inductor-capacitor equivalent network is provided between antenna port pin 1 and receiving path port pin 3. A switch comprising a PMOS transistor PM1 is provided at receiving path port pin 3 and connected in parallel to GND via capacitor C6. The drain of the PMOS transistor PM1 is connected to receiving path port pin 3. The drain of the PMOS transistor PM1 is connected to ground via capacitor C6. The gate of the PMOS transistor PM1 is controlled by the voltage level at node B.

[0016] The ground level of the RF transceiver switching circuit is GND, and the power supply voltage is the power supply terminal VDD.

[0017] According to a preferred embodiment, the source of the NMOS transistor NM1 and the drain of the PMOS transistor PM1 are respectively provided with a static level switching port D and a static level switching port E.

[0018] According to a preferred embodiment, the first n-order lumped inductor-capacitor equivalent network and the second n-order lumped inductor-capacitor equivalent network are third-order lumped inductor-capacitor equivalent networks, wherein the unit inductance value of the third-order lumped inductor-capacitor equivalent network is L0 and the unit capacitance value is C0.

[0019] According to a preferred embodiment, the antenna port pin1 is connected to the center tap end of the inductor L2 and one end of the capacitor Cp2, and the inductance value of the inductor L2 is 2L0;

[0020] One end of the capacitor Cp2 is connected to GND, and the other end is connected to the center tap end of the inductor L2 and the antenna port pin1. The capacitance value of the capacitor Cp2 is the parasitic capacitance from the port pad of the antenna port pin1 to GND, which is the unit capacitance value C0.

[0021] According to a preferred embodiment, the first n-order lumped inductor-capacitor equivalent network includes capacitor Cp1, capacitor C2, capacitor C3 and inductor L1, and capacitor Cp2 and inductor L2 shared with the second n-order lumped inductor-capacitor equivalent network;

[0022] Among them, one end of capacitor C3 is connected to GND, and the other end is connected to inductor L2 and inductor L1;

[0023] One end of the capacitor C2 is connected to GND, and the other end is connected to the center tap end of the inductor L1;

[0024] One end of the capacitor Cp1 is connected to GND, and the other end is connected to the drain of the NMOS transistor NM1 and the emission path port pin2.

[0025] According to a preferred embodiment, the capacitance of the capacitor Cp1 is the sum of the parasitic capacitance from the port pad of the transmitting path port pin2 to GND and the parasitic capacitance from the drain of the NMOS transistor NM1 to GND, which is C0 / 2;

[0026] The inductance value of the inductor L1 is 2L0; the capacitance value of the capacitor C2 is the unit capacitance value C0 / 2; and the capacitance value of the capacitor C3 is C0 / 2.

[0027] According to a preferred embodiment, the second n-order lumped inductor-capacitor equivalent network includes capacitor Cp3, capacitor C4, capacitor C5 and inductor L3, as well as capacitor Cp2 and inductor L2 shared with the first n-order lumped inductor-capacitor equivalent network;

[0028] Among them, one end of capacitor C4 is connected to GND, and the other end is connected to inductor L2 and inductor L3;

[0029] One end of the capacitor C5 is connected to GND, and the other end is connected to the center tap end of the inductor L3;

[0030] One end of the capacitor Cp3 is connected to GND, and the other end is connected to the source of the PMOS transistor PM1 and the receiving path port pin3.

[0031] According to a preferred embodiment, the capacitance of the capacitor Cp3 is the sum of the parasitic capacitance from the port pad of the receiving channel port pin3 to GND and the parasitic capacitance from the source of the PMOS transistor PM1 to GND, which is C0 / 2;

[0032] The inductance value of the inductor L3 is 2L0; the capacitance value of the capacitor C4 is C0 / 2; and the capacitance value of the capacitor C5 is C0 / 2.

[0033] According to a preferred embodiment, the RF transceiver switching circuit further includes: a capacitor C1, a capacitor C6, a resistor R1, a resistor R2, and a resistor R3;

[0034] One end of the capacitor C1 is connected to GND, and the other end is connected to the source of the NMOS transistor NM1 and R2, so as to block the DC path between the source of the NMOS transistor NM1 and GND, while providing an AC path for the RF signal between the source of the NMOS transistor NM1 and GND;

[0035] One end of the capacitor C6 is connected to GND, and the other end is connected to the drain of the PMOS transistor PM1 and R3, so as to block the DC path between the drain of the PMOS transistor PM1 and GND, while providing an AC path for the RF signal between the drain of the PMOS transistor PM1 and GND;

[0036] One end of the resistor R1 is connected to the inductor L1, the inductor L2, and the capacitor C3, and the other end is connected to the node C, for preventing the RF signal from being diverted to point C, while providing a DC level to the drain of the NMOS transistor NM1 and the source of the PMOS transistor PM1 through point C;

[0037] One end of the resistor R2 is connected to the node D, and the other end is connected to the source of the NMOS transistor NM1 and the DC blocking capacitor C1, so as to prevent the RF signal from being shunted from the drain of the NMOS transistor NM1 to point D, and at the same time provide a DC level to the source of the NMOS transistor NM1 through point D;

[0038] One end of the resistor R3 is connected to the node E, and the other end is connected to the drain of the PMOS transistor PM1 and the DC blocking capacitor C6, so as to prevent the RF signal from being shunted from the drain of the PMOS transistor PM1 to point E, and at the same time provide a DC level to the drain of the PMOS transistor PM1 through point E.

[0039] The aforementioned main solution of the present invention and its various further options can be freely combined to form multiple solutions, all of which can be adopted and protected by the present invention. After understanding the solutions of the present invention, those skilled in the art will understand that there are many combinations based on existing technology and common knowledge, all of which are technical solutions to be protected by the present invention, and these are not exhaustive here.

[0040] The beneficial effects of the present invention are as follows: The present invention improves the transceiver switching switch structure of the transmission line-parallel switch type structure based on the CMOS process, reduces the chip area of ​​the switch, reduces the insertion loss introduced when the RF signal passes through the transceiver switching switch, and improves the linearity performance of the switch in the transmission mode.

[0041] Specifically, the present invention uses an n-order lumped inductor-capacitor equivalent network consisting of a tapped inductor and capacitor to replace a 1 / 4λ transmission line to reduce insertion loss. The tapped inductor can further save chip area compared to an ordinary inductor. The NMOS transistor NM2 of the receiving branch is replaced with a PMOS transistor PM1, and static level switching ports are added to the drain and source of NM1 and PM1. In the transmission mode, the gate voltage threshold that enables the NM1 working area to transition to the linear region is increased, thereby alleviating the gain compression phenomenon that occurs when the transmission signal increases and improving the linearity performance of the switch in the transmission mode. At the same time, PM1 can also operate normally after the level switching, avoiding the additional loss and chip area occupied by introducing a series DC blocking capacitor in the signal path. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a schematic diagram of the location of the transmit / receive switch in the radio frequency communication system;

[0043] Figure 2 This is a schematic diagram of a transceiver switch structure using a transmission line-parallel switch type structure;

[0044] Figure 3 This is a schematic diagram of the relationship between a 1 / 4λ transmission line and an n-order tapped inductor-capacitor equivalent network;

[0045] Figure 4 It is a structural diagram of a compact CMOS-based radio frequency transceiver switch of the present invention. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0048] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on the positions shown in the accompanying drawings, or the positions or locations in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0049] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0050] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0051] In addition, the present invention would like to point out that, in the present invention, unless the specific structure, connection relationship, positional relationship, power source relationship, etc. are specifically written out, the structure, connection relationship, positional relationship, power source relationship, etc. involved in the present invention are all known to those skilled in the art based on the existing technology without creative work.

[0052] Example 1

[0053] refer to Figure 3 As shown in the figure, a third-order lumped inductor-capacitor equivalent network consisting of tapped inductors and capacitors is used in the transmitting and receiving branch switching circuits to replace the 1 / 4λ transmission line. In practical applications, a fifth-order or higher-order lumped inductor-capacitor equivalent network can also be used. The relationship between the unit inductance value L0 and the unit capacitance value C0 of the 1 / 4λ transmission line and the n-order lumped inductor-capacitor equivalent network is determined by the following relationship:

[0054]

[0055] Among them, T D is the transmission delay of the 1 / 4λ transmission line, f0 is the characteristic frequency of the 1 / 4λ transmission line, and Z0 is the characteristic impedance of the 1 / 4λ transmission line.

[0056] refer to Figure 4 As shown, the present invention discloses a compact CMOS-based radio frequency transceiver switch, comprising: a voltage source, a radio frequency transceiver switch circuit, wherein the negative electrode of the voltage source V1 is connected to the ground terminal GND, and the positive electrode of the voltage source V1 is connected to the power supply terminal VDD.

[0057] The RF transceiver switching circuit includes:

[0058] The receiving channel signal port pin3 is connected to the PM1 source and one end of L3.

[0059] A PMOS transistor PM1 has a source connected to pin3, a gate connected to node B, and a drain connected to one end of R3 and one end of a DC blocking capacitor C6.

[0060] Resistor R3 has one end connected to node E and the other end connected to the PM1 drain and DC blocking capacitor C6. Its function is to prevent the RF signal from being shunted from the PM1 drain to point E, and at the same time provide a DC level to the PM1 drain through point E.

[0061] One end of the DC blocking capacitor C6 is connected to GND, and the other end is connected to the PM1 drain and R3. Its function is to block the DC path between the PM1 drain and GND, and at the same time provide an AC path for the RF signal between the PM1 drain and GND.

[0062] One end of the capacitor is connected to GND, and the other end is connected to the source of PM1 and pin3. This capacitor Cp3 is not an independent component, but the sum of the parasitic capacitance from the pin3 port pad to GND and the parasitic capacitance from the source of PM1 to GND. Under the premise of determining the size of the port pad, by reasonably selecting the size of the PMOS tube PM1, the capacitance value of Cp3 is made equal to 1 / 2*unit capacitance value C0.

[0063] One end is connected to pin3 and PM1 source, the other end is connected to one end of C4 and one end of L2, and the center tap end is connected to one end of C5. The inductance value of L3 is 2*unit inductance value L0.

[0064] One end of the capacitor C4 is connected to GND, and the other end is connected to L2 and inductor L3. The capacitance value of the capacitor C4 is 1 / 2*the unit capacitance value C0.

[0065] One end of the capacitor is connected to GND, and the other end is connected to the center tap end of L3. The capacitance value of the capacitor C5 is 1 / 2*the unit capacitance value C0.

[0066] One end is connected to one end of L3 and one end of C4, the other end is connected to L1, resistor R1 and C3, and the center tap end is connected to pin1 of inductor L2. The inductance value of L2 = 2*unit inductance value L0.

[0067] One end of the capacitor is connected to GND, and the other end is connected to the center tap of L2 and pin1. The capacitor Cp2 is not an independent device, but a parasitic capacitor from the pin1 port pad to GND. The capacitance value of Cp2 is equal to the unit capacitance value C0.

[0068] Transmitter channel signal port pin2 connected to the drain of NM1 and one end of L1.

[0069] An NMOS transistor NM1 has a drain connected to pin2 and one end of L1, a gate connected to node A, and a source connected to R2 and a DC blocking capacitor C1.

[0070] Resistor R2 has one end connected to node D and the other end connected to the source of NM1 and DC blocking capacitor C1. Its function is to prevent the RF signal from being shunted from the drain of NM1 to point D, and at the same time provide a DC level to the source of NM1 through point D.

[0071] One end of the DC blocking capacitor C1 is connected to GND, and the other end is connected to the source of NM1 and the resistor R2. Its function is to block the DC path between the source of NM1 and GND, and at the same time provide an AC path for the RF signal between the source of NM1 and GND.

[0072] One end of the capacitor Cp1 is connected to GND and the other end is connected to the drain of NM1. This capacitor Cp1 is not an independent component, but the sum of the parasitic capacitance from the pin2 port pad to GND and the parasitic capacitance from the drain of NM1 to GND. Under the premise of determining the size of the port pad, by reasonably selecting the size of the NMOS tube NM1, the capacitance value of Cp1 is made equal to 1 / 2 * unit capacitance value C0.

[0073] One end is connected to pin2 and the drain of NM1, the other end is connected to resistor R1, inductor L2 and capacitor C3, and the center tap end is connected to the tapped inductor L1 connected to C2. The inductance value of L1 = 2*unit inductance value L0.

[0074] One end of the capacitor C2 is connected to GND, and the other end is connected to the center tap of L1. The capacitance value of C2 = 1 / 2 * unit capacitance value C0.

[0075] One end of the capacitor C3 is connected to GND, and the other end is connected to the inductor L1, the inductor L2, and the resistor R1. The capacitance value of C3 is 1 / 2*the unit capacitance value C0.

[0076] Resistor R1 , one end of which is connected to inductor L1 , inductor L2 , and capacitor C3 , and the other end of which is connected to node C, prevents the RF signal from being diverted to point C and provides a DC level to the drain of M1 through point C.

[0077] Antenna signal port pin1 connected to the center tap end of L2.

[0078] Based on the above circuit structure, the working mechanism of the RF transceiver switch of the present invention is as follows:

[0079] In the following analysis, the DC blocking capacitors C1 and C6 are set to larger values, which are equivalent to a short circuit for RF; the port impedance of pin1, pin2, and pin3 all default to the standard 50 ohms.

[0080] In receive mode, the voltage level at node A = VDD, the voltage level at node C = GND, and the voltage level at node D = GND. NM1 operates in the deep linear region, the switch it forms is in the on state, and M1's on-resistance is close to 0 ohms. The impedance transformation effect of the third-order lumped inductor-capacitor network equivalent to a 1 / 4λ transmission line composed of Cp1, L1, C2, C3, L2, and Cp2 makes the impedance seen from pin 1 to pin 2 approach infinity, thereby preventing the RF signal from flowing from pin 1 to pin 2. The voltage level at node B = VDD, the voltage level at node E = GND, PM1 operates in the cutoff region, and the switch it forms is in the off state. The RF signal can be transmitted from pin 1 to pin 3 through the equivalent 1 / 4λ transmission line composed of Cp2, L2, C4, L3, C5, and Cp3.

[0081] In transmit mode, the voltage level at node B = GND, the voltage level at node C = VDD, and the voltage level at node E = VDD. PM1 operates in the deep linear region, the switch it forms is in the on state, and PM1's on-resistance is close to 0 ohms. The impedance transformation effect of the third-order lumped inductor-capacitor network equivalent to a 1 / 4λ transmission line, consisting of Cp2, L2, C4, L3, C5, and Cp3, theoretically makes the impedance seen from pin 1 to pin 3 approach infinity, thereby preventing the RF signal from flowing from pin 1 to pin 3. The voltage level at node A = GND, the voltage level at node D = VDD, NM1 operates in the cutoff region, and the switch it forms is in the off state. The RF signal can be transmitted from pin 2 to pin 1 through the equivalent 1 / 4λ transmission line formed by Cp1, L1, C2, C3, L2, and Cp2.

[0082] The present invention uses an n-order lumped inductor-capacitor equivalent network composed of a tapped inductor and a capacitor to replace a 1 / 4λ transmission line to reduce insertion loss. Compared with ordinary inductors, the tapped inductor can further save chip area.

[0083] The NMOS transistor NM2 in the receiving branch is replaced with the PMOS transistor PM1, and static level switching ports are added to the drain and source of NM1 and PM1. In the transmit mode, the gate voltage threshold that enables the NM1 operating area to transition to the linear region is increased, thereby alleviating the gain compression phenomenon that occurs when the transmit signal increases and improving the linearity performance of the switch in the transmit mode. At the same time, PM1 can also operate normally after the level switching, avoiding the additional loss and chip area occupied by introducing a series DC blocking capacitor in the signal path.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A compact CMOS-based radio frequency transceiver switch, characterized in that: The compact RF transceiver switch includes: a voltage source V1 and a RF transceiver switch circuit; The negative electrode of the voltage source V1 is connected to the ground terminal GND, and the positive electrode of the voltage source V1 is connected to the power supply terminal VDD; The radio frequency transceiver switching circuit includes: antenna port pin1, transmission path port pin2, and reception path port pin3; A first n-order lumped inductor-capacitor equivalent network is provided between antenna port pin 1 and transmit path port pin 2. A switch comprising an NMOS transistor NM1 is provided at transmit path port pin 2 and connected in parallel to GND via capacitor C1. The drain of NMOS transistor NM1 is connected to transmit path port pin 2, the source of NMOS transistor NM1 is connected to ground via capacitor C1, and the gate of NMOS transistor NM1 is controlled by the voltage level at node A. A second nth-order lumped inductor-capacitor equivalent network is provided between antenna port pin 1 and receiving path port pin 3. A switch comprising a PMOS transistor PM1 is provided at receiving path port pin 3 and connected in parallel to GND via capacitor C1. The drain of the PMOS transistor PM1 is connected to receiving path port pin 3. The drain of the PMOS transistor PM1 is connected to ground via capacitor C1. The gate of the PMOS transistor PM1 is controlled by the voltage level at node B. The ground level of the RF transceiver switching circuit is GND, and the power supply voltage is the power supply terminal VDD; The antenna port pin1 is connected to the center tap end of the inductor L2 and one end of the capacitor Cp2, and the inductance value of the inductor L2 is 2L0; One end of the capacitor Cp2 is connected to GND, and the other end is connected to the center tap end of the inductor L2 and the antenna port pin1. The capacitance value of the capacitor Cp2 is the parasitic capacitance from the port pad of the antenna port pin1 to GND, which is the unit capacitance value C0; The first n-order lumped inductor-capacitor equivalent network includes capacitor Cp1, capacitor C2, capacitor C3 and inductor L1, and capacitor Cp2 and inductor L2 shared with the second n-order lumped inductor-capacitor equivalent network; Among them, one end of capacitor C3 is connected to GND, and the other end is connected to inductor L2 and inductor L1; One end of the capacitor C2 is connected to GND, and the other end is connected to the center tap end of the inductor L1; One end of the capacitor Cp1 is connected to GND, and the other end is connected to the drain of the NMOS transistor NM1 and the emission path port pin2; The second n-order lumped inductor-capacitor equivalent network includes capacitor Cp3, capacitor C4, capacitor C5 and inductor L3; Among them, one end of capacitor C4 is connected to GND, and the other end is connected to inductor L2 and inductor L3; One end of the capacitor C5 is connected to GND, and the other end is connected to the center tap end of the inductor L3; One end of the capacitor Cp3 is connected to GND, and the other end is connected to the source of the PMOS transistor PM1 and the receiving path port pin3.

2. The compact RF transceiver switch according to claim 1, wherein: The source of the NMOS transistor NM1 and the drain of the PMOS transistor PM1 are respectively provided with a static level switching port D and a static level switching port E.

3. The compact RF transceiver switch according to claim 1, wherein: The first n-order lumped inductor-capacitor equivalent network and the second n-order lumped inductor-capacitor equivalent network are third-order lumped inductor-capacitor equivalent networks; The unit inductance value of the third-order lumped inductor-capacitor equivalent network is L0, and the unit capacitance value is C0.

4. The compact RF transceiver switch according to claim 1, wherein: The capacitance value of the capacitor Cp1 is the sum of the parasitic capacitance from the port pad of the transmitting path port pin2 to GND and the parasitic capacitance from the drain of the NMOS tube NM1 to GND, which is C0 / 2; The inductance value of the inductor L1 is 2L0; the capacitance value of the capacitor C2 is C0 / 2; and the capacitance value of the capacitor C3 is C0 / 2.

5. The compact RF transceiver switch according to claim 1, wherein: The capacitance of the capacitor Cp3 is the sum of the parasitic capacitance from the port pad of the receiving channel port pin3 to GND and the parasitic capacitance from the source of the PMOS transistor PM1 to GND, which is C0 / 2; The inductance value of the inductor L3 is 2L0; the capacitance value of the capacitor C4 is C0 / 2; and the capacitance value of the capacitor C5 is C0 / 2.

6. The compact RF transceiver switch according to claim 1, wherein: The RF transceiver switching circuit further includes: a capacitor C1, a capacitor C6, a resistor R1, a resistor R2, and a resistor R3; One end of the capacitor C1 is connected to GND, and the other end is connected to the source of the NMOS transistor NM1 and R2, so as to block the DC path between the source of the NMOS transistor NM1 and GND, while providing an AC path for the RF signal between the source of the NMOS transistor NM1 and GND; One end of the capacitor C6 is connected to GND, and the other end is connected to the drain of the PMOS transistor PM1 and R3, so as to block the DC path between the drain of the PMOS transistor PM1 and GND, while providing an AC path for the RF signal between the drain of the PMOS transistor PM1 and GND; One end of the resistor R1 is connected to the inductor L1, the inductor L2, and the capacitor C3, and the other end is connected to the node C, for preventing the RF signal from being diverted to point C, while providing a DC level to the drain of the NMOS transistor NM1 and the source of the PMOS transistor PM1 through point C; One end of the resistor R2 is connected to the node D, and the other end is connected to the source of the NMOS transistor NM1 and the DC blocking capacitor C1, so as to prevent the RF signal from being shunted from the drain of the NMOS transistor NM1 to point D, and at the same time provide a DC level to the source of the NMOS transistor NM1 through point D; One end of the resistor R3 is connected to the node E, and the other end is connected to the drain of the PMOS transistor PM1 and the DC blocking capacitor C6, so as to prevent the RF signal from being shunted from the drain of the PMOS transistor PM1 to point E, and at the same time provide a DC level to the drain of the PMOS transistor PM1 through point E.

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