A method and apparatus for adjusting a tearing effect (TE) signal

Abstract

The application provides a method and device for adjusting a TE signal. The starting time of the TE signal corresponding to first image frame data is adjusted according to the coordinates of the first image frame data. The adjusted starting time of the TE signal is used to send the TE signal, and the first image frame data is received. After the screen is started to refresh, the current image frame data is not written into the new image frame data in the storage space corresponding to the data that has not been refreshed on the screen, so that the phenomenon of the screen being filled with flowers is avoided, and the display effect of the screen and the service experience of the user are ensured.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a method and apparatus for adjusting the tearing effect TE signal. Background Technology

[0002] Currently, mobile devices (e.g., terminal devices) primarily use the Mobile Industry Processor Interface (MIPI) as the transmission interface between the application processor (AP) and the display chip. The "command mode" of the MIPI transmission interface uses a tearing effect (TE) signal from the display chip to indicate whether the AP can send data to the display chip. With high refresh rates (e.g., 120Hz, 144Hz) becoming mainstream on mobile devices, while improving display response time and smoothness, high refresh rates also pose greater challenges to the display output performance of the AP. In some cases, the AP may not be able to guarantee that a frame of data is completely sent to the display chip within the display time of one frame (e.g., 8.3ms at a refresh rate of 120Hz). For example, this could be due to the excessive instantaneous load of double data rate (DDR), preventing a frame of data from being completely sent within 8.3ms, potentially leading to display anomalies. To address this issue, the existing solution is to use a built-in buffer in the display chip to cache a frame of data, and then send the TE signal to the AP in advance. This allows the AP to send data before the "display refresh data signal" (e.g., the vertical synchronization (Vsync) signal), thus ensuring that the AP has more time to send data.

[0003] Since multi-frame video data includes both dynamic and static images, there are two display scenarios: "global refresh" and "partial refresh." Using "partial refresh" on a portion of the screen can reduce power consumption. For example, the area playing the video is refreshed normally, while other static areas remain unchanged, preserving their previous static content. This partial refresh reduces the power consumption of the display chip and panel by decreasing the amount of data refreshed. However, in partial refresh scenarios, if the coordinates of a partial refresh corresponding to a frame are located relatively late in the frame's content, the existing solution of sending the TE signal to the AP in advance, allowing the AP more time to send data, may result in the next image frame being written to the buffer before the current image frame data is fully displayed on the screen. This means the screen may display the content of the next image frame within the current image frame's display cycle, resulting in the current image frame data not being fully refreshed, which can still lead to display anomalies.

[0004] Therefore, ensuring the display effect of the screen in scenarios with partial refreshes becomes a technical problem that needs to be solved. Summary of the Invention

[0005] This application provides a method for adjusting the tearing effect TE signal. Based on the coordinates of the first image frame data, the start time of the TE signal corresponding to the first image frame data is adjusted, and the TE signal is sent based on the adjusted start time of the TE signal, thereby ensuring the display effect of the screen.

[0006] In one aspect, an adjustment method for the tearing effect TE signal is provided. For example, this method can be performed by a display chip, or by a component of the display chip (e.g., a circuit).

[0007] The method includes: adjusting the start time of a tearing effect TE signal corresponding to the first image frame data according to the coordinates corresponding to the first image frame data, wherein a first difference between the start time of the adjusted TE signal corresponding to the first image frame data and the start time of the vertical synchronization Vsync signal corresponding to the first image frame data is variable. The first difference is related to the coordinates corresponding to the first image frame data. Based on the adjusted start time of the TE signal, a tearing effect TE signal is sent, which is used to indicate the transmission of the first image frame data. The adjusted start time of the TE signal ensures that the first image frame data does not overwrite data of the current image frame data that has not yet been refreshed on the display screen. The current image frame data is the previous image frame data of the first image frame data. The first image frame data is then received.

[0008] In this application, the first image frame data can be global refresh data of the display screen or partial refresh data of the display screen. Specifically, the first image frame data can be flexibly switched based on business needs and is not limited.

[0009] It should be noted that the "first image frame data" in this application can be understood as any single image frame data, or as each image frame data in the scheme. For example, if the scheme is understood from a timing perspective, the first image frame data could be the Nth image frame data, or the (N+1)th image frame data, or the (N+2)th image frame data, and so on. In this case, it is equivalent to the difference #1 (an example of the first difference) between the start time of the TE signal corresponding to the Nth image frame and its corresponding Vsync signal being variable, and the difference #1 being related to the coordinates corresponding to the Nth image frame data. Similarly, the difference #2 (another example of the first difference) between the start time of the TE signal corresponding to the (N+1)th image frame data and its corresponding Vsync signal being variable, and the difference #2 being related to the coordinates corresponding to the (N+1)th image frame data.

[0010] For example, suppose the rate at which the AP writes data to the graphics random access memory (GRAM) is... The display chip reads data from GRAM at a rate that is Assuming the total number of rows on the display screen is... Line, the starting coordinates of the first image frame data are To ensure normal display, the maximum value at which the TE signal precedes the Vsync signal is [value missing]. , .

[0011] Based on the above technical solution, in this application, the start time of the TE signal corresponding to the first image frame data is adjusted according to the coordinates of the first image frame data. The TE signal is sent based on the adjusted start time of the TE signal, and the first image frame data is received. This ensures that after the screen refresh is initiated, new image frame data will not be written into the storage space corresponding to the data that has not yet been refreshed on the screen, thereby solving the display abnormality problem and ensuring the screen display effect and user experience.

[0012] In conjunction with the first aspect, in one possible implementation, the first difference is less than or equal to And greater than or equal to 0, where, To ensure normal display, the TE signal is earlier than the maximum value of the Vsync signal.

[0013] In conjunction with the first aspect, in one possible implementation, when the first image frame data is the global refresh data of the display screen, the first difference is M, where M is less than or equal to P, and P is the maximum value at which the TE signal precedes the Vsync signal while ensuring normal display.

[0014] In this application, M is the maximum value of the first difference that the system configuration ensures can display correctly.

[0015] In conjunction with the first aspect, in one possible implementation, when the first image frame data is a partial refresh data of the display screen, the first difference is N, N is less than M, M is less than or equal to P, and P is the maximum value of the TE signal being earlier than the Vsync signal while ensuring normal display.

[0016] For example, P and M can be time granularities, such as M (or P) being 1ms; P and M can also be row-count granularities, such as M (or P) being 300 rows. It can also be understood that the number of rows moved forward and the time moved forward are equivalent and can be converted to each other.

[0017] In conjunction with the first aspect, in one possible implementation, when all parameters in the display system are the same (e.g., display frame rate, AP data transmission rate, etc.), if the starting coordinate of the first image frame data shows an increasing trend, the first difference shows a decreasing trend; or, if the starting coordinate of the first image frame data shows a decreasing trend, the first difference shows an increasing trend.

[0018] For example, suppose the Nth image frame data, the (N+1)th image frame data, and the (N+2)th image frame data can all be considered as the first image frame data. Suppose the coordinates of the Nth image frame data are [1000~2000], the coordinates of the (N+1)th image frame data are [1800~2000], and the coordinates of the (N+2)th image frame data are [1600~2000]. Suppose the first difference between the start time of the TE signal corresponding to the Nth image frame data and the start time of its corresponding Vsync signal is k1, for example, 1ms; the first difference between the start time of the TE signal corresponding to the (N+1)th image frame data and the start time of its corresponding Vsync signal is k2, for example, 500µs; and the first difference between the start time of the TE signal corresponding to the (N+2)th image frame data and the start time of its corresponding Vsync signal is k3, for example, 600µs. It can be seen that k2 < k3 < k1. This is because the larger the starting coordinate of the first image frame data, the later the local refresh data is. In this case, the first difference should be reduced. It can also be understood that the TE signal corresponding to the first image frame data should be started later. Otherwise, it is very likely that the first image frame data will overwrite the content that has not yet been refreshed in the currently refreshed image frame data cached in GRAM.

[0019] In summary, in this application, the first difference between the start time of the TE signal corresponding to each image frame data and the start time of its corresponding Vsync signal can be dynamically changed, or in other words, this first difference can be dynamically adjusted. Specifically, this first difference can be adjusted based on the coordinates corresponding to each image frame data. In this application, because the start time of the TE signal corresponding to each image frame data can be dynamically adjusted, the display effect of the screen can be guaranteed, and abnormal display situations can be avoided.

[0020] Secondly, this application proposes an apparatus for adjusting the tearing effect TE signal, which is used to perform the method described in the first aspect above. Specifically, the apparatus may include units and / or modules for performing the method described in the first aspect of this application, such as a transceiver module and / or a processing module. For example, the apparatus may display a chip.

[0021] Thirdly, this application provides a display device, comprising: at least one processor for executing a computer program or instructions stored in a memory to perform the method described in the first aspect. Optionally, the device further comprises a memory for storing the computer program or instructions. Optionally, the device further comprises a communication interface through which the processor reads the computer program or instructions stored in the memory.

[0022] In one implementation, the display device includes means for implementing the functions of the methods described in the first aspect above.

[0023] In one implementation, the display device includes the apparatus provided in the second aspect described above.

[0024] Fourthly, this application provides a processor, including: an input circuit, an output circuit, and a processing circuit. The processing circuit is used to receive signals through the input circuit and to transmit signals through the output circuit, causing the processor to execute the method described in the first aspect.

[0025] In specific implementation, the processor can be one or more chips, the input circuit can be input pins, the output circuit can be output pins, and the processing circuit can be transistors, gate circuits, flip-flops, and various logic circuits. The input signal received by the input circuit can be received and input by, for example, but not limited to, a transceiver, and the signal output by the output circuit can be, for example, but not limited to, output to and transmitted by a transmitter. Furthermore, the input circuit and the output circuit can be the same circuit, which is used as both the input circuit and the output circuit at different times. This application does not limit the specific implementation of the processor and various circuits.

[0026] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0027] Fifthly, a processing apparatus is provided, including a processor and a memory. The processor is used to read instructions stored in the memory and to receive signals via a transceiver and transmit signals via a transmitter to execute the method described in the first aspect.

[0028] Optionally, the processor may be one or more, and the memory may be one or more.

[0029] Optionally, the memory may be integrated with the processor, or the memory may be separated from the processor.

[0030] In the specific implementation process, the memory can be a non-transitory memory, such as read-only memory (ROM), which can be integrated with the processor on the same chip or set on different chips. The embodiments of this application do not limit the type of memory or the way the memory and processor are set.

[0031] It should be understood that the relevant data interaction process, such as sending the first information, can be the process of the processor outputting the first information, and the receiving capability information can be the process of the processor receiving input capability information. Specifically, the data output by the processor can be sent to the transmitter, and the input data received by the processor can come from the transceiver. Here, the transmitter and the transceiver can be collectively referred to as the transceiver.

[0032] The processing device mentioned in the fifth aspect above can be one or more chips. The processor in the processing device can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0033] In a sixth aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including the method described in the first aspect.

[0034] In a seventh aspect, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method described in the first aspect.

[0035] Eighthly, a chip system is provided, including a processor for calling and running a computer program from a memory, causing a device equipped with the chip system to perform the method of the first aspect described above. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a display screen with global refresh and partial refresh provided in this application.

[0037] Figure 2 This is a schematic block diagram of a system architecture to which this application applies.

[0038] Figure 3 This is a schematic diagram of an existing solution provided in this application.

[0039] Figure 4 This is another schematic diagram of an existing solution in a different scenario provided by this application.

[0040] Figure 5 This is a schematic flowchart of a method 500 for adjusting the TE signal provided in this application.

[0041] Figure 6 This is a schematic diagram of a method for adjusting the TE signal provided in this application.

[0042] Figure 7This is a schematic block diagram of a device 700 for adjusting the TE signal provided in this application.

[0043] Figure 8 This is a schematic block diagram of a display device 800 provided in this application. Detailed Implementation

[0044] To facilitate understanding of the technical solution of this application, a brief introduction to some of the technical terms involved in this application will be given below.

[0045] 1. Tearing effect (TE): Within an image frame, the read pointer and write pointer of the frame memory overlap, resulting in a phenomenon where parts of the old and new images appear on the display screen.

[0046] 2. TE signal: This signal is generated by the display driver integrated circuit (DDIC) and is used to prevent screen tearing during image refresh. When ready to refresh the next image frame, the DDIC chip generates a TE signal and synchronously sends it to the application processor (AP). Upon detecting the TE signal trigger edge, the corresponding AP can send the next image frame data to the DDIC chip.

[0047] 3. Vertical Synchronization (Vsync) Signal: A signal used to indicate the end of scanning the previous image frame and the start of scanning the next image frame. The frequency of this signal, also known as the frame rate, is the number of image frames that the DDIC can display per second. Typically, one or more TE signal cycles can exist within one Vsync signal cycle.

[0048] In the following schematic diagrams of this application, the TE signal period and the Vsync signal period are used as examples for illustration.

[0049] 4. Refresh rate: Defined as the frequency at which the display panel displays images per second, measured in Hertz (Hz). For example, a refresh rate of 120Hz means that 120 frames are displayed per second, or 120 refreshes per second.

[0050] 5. Refresh cycle: This is the time required for the display screen to complete the display of one frame of image. For example, when the refresh rate is 120Hz, the refresh time of one frame is 8.3ms.

[0051] 6. Display Refresh: Because multi-frame video data includes both dynamic and static images, the display driver performs both "global refresh" and "partial refresh" when displaying the image. In related technologies, for a specific display interface, for example... Figure 1 As shown in (a), the shaded area is playing a video, which is the refresh area. It can be seen that this interface is displayed on the full screen of the terminal device. This can be understood as a "global refresh" scenario, where the coordinates of the full-screen refresh are [1, H]. Figure 1 As shown in (b), the interface is playing a video, where the shaded area represents the playback area of ​​the video. Figure 1 In display interfaces like (b), terminal devices can reduce power consumption by using partial refresh on a portion of the screen. For example, the area playing video is refreshed normally, while the content in other areas of the display screen remains static. This scenario can be understood as a "partial refresh" scenario, where the coordinates of the partial refresh are [y1, y2]. This partial refresh method reduces the power consumption of the display chip and panel by decreasing the amount of data refreshed.

[0052] In this embodiment, the display device can be any device with a display screen. For example, the device includes, but is not limited to, a device that provides voice / data to a user, such as a handheld device with wireless connectivity, an in-vehicle device, etc. For example, it could also include mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving vehicles, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes (such as game consoles, smart TVs, smart speakers, smart refrigerators, and fitness equipment), cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, transportation vehicles with wireless communication capabilities, communication modules, and roadside units with terminal functionality. The embodiments of this application do not limit this to RSU (Remote Land Unit), terminal equipment in 5G networks, or terminal equipment in future evolved public land mobile networks (PLMNs).

[0053] By way of example and not limitation, in this embodiment, the display device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0054] Furthermore, in this embodiment, the display device can also be a terminal device in an IoT system. IoT is an important component of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object interconnection.

[0055] Figure 2 This is a schematic block diagram of a system architecture to which this application applies, such as Figure 2 As shown, typically, the display chip sends a TE signal to the application processor (AP). Upon receiving the TE signal, the display output module in the AP sends image frame data to the graphics random access memory (GRAM) in the display chip. The display chip then controls the screen to refresh each image frame. It should be understood that when the next image frame is sent, the data in the current GRAM is overwritten by the content of the next image frame. For example, once the Nth image frame begins to be sent, the (N-1)th image frame data cached in the GRAM can be overwritten from the beginning, for example, starting from the first row, and the (N-1)th image frame data stored in the GRAM is completely overwritten within one Vsync signal display cycle.

[0056] It should be noted that, Figure 2 The specific names of the various modules can vary. For example, in some scenarios, a "display chip" might be named a "display module," an "application processor" might be named a "processor," and so on. This application does not limit the specific names of the various modules; any display device that can implement the functions of the aforementioned modules can execute the technical solution provided in this application.

[0057] Currently, mobile devices (e.g., terminal devices) primarily use the Mobile Industry Processor Interface (MIPI) as the transmission interface between the application processor (AP) and the display chip. The "command mode" of the MIPI transmission interface instructs the AP whether to send image frame data to the display chip by sending a TE signal. With high refresh rates (e.g., 120Hz, 144Hz) becoming mainstream on display devices, while improving display response time and smoothness, high refresh rates also pose greater challenges to the display output performance of the AP. In certain extreme performance display frames, the AP may not be able to guarantee that a frame of data is completely sent to the display chip within the refresh time of one frame (e.g., at a refresh rate of 120Hz, the refresh time of one frame is 8.3ms), potentially leading to display anomalies. For example, as... Figure 3 As shown in (a), an abnormal event occurred in the data transmission time corresponding to the Nth image frame. It can be seen that when the Vsync signal corresponding to the original (N+1)th image frame was activated, the Nth image frame data was still not fully transmitted (for example, the instantaneous load of the DDR might be too large, causing a frame of data to be unable to be fully transmitted within 8.3ms, i.e., the image content of a frame is too complex, resulting in the inability to transmit a frame of data within 8.3ms). Therefore, when the TE signal corresponding to the original (N+1)th image frame was activated, the remaining data of the Nth image frame was still being transmitted. Since the Nth image frame data was not fully transmitted, after the TE signal corresponding to the Nth image frame was activated, the data stored in the GRAM at this time consisted of part of the currently transmitted Nth image frame data and the content of the N-1th image frame data that had not yet been covered. Therefore, in this scenario, part of the display screen would show the current image frame data (e.g., the Nth image frame data), while the other part of the display screen would still show the previous image frame data (e.g., the N-1th image frame data). Figure 3 As shown in (b) of the diagram.

[0058] To address the aforementioned display anomaly, the existing solution involves using a built-in buffer in the display chip to cache one frame of data. Then, the TE signal is sent to the AP in advance, allowing the AP to send data more time before the "display refresh data signal" (e.g., the Vsync signal), thus ensuring that the AP has more time to send data.

[0059] The above solution effectively resolves display anomalies in global refresh scenarios, such as... Figure 4As shown in (a), since the start time of the TE signal is T1 time intervals earlier than the start time of the Vsync signal (for example, T1 is 1ms, it can be seen that T1 is greater than...), Figure 3 In (a) of the diagram, T0 (e.g., T0 is 100 us), assuming the period for displaying one frame of data is 8.3ms (i.e., the display period of the Vsync signal is 8.3ms), this is equivalent to the time it takes for the AP to send one frame of data without abnormal display increasing from (8.3+T0)ms to (8.3+T1)ms (e.g., the AP's data transmission time increasing from 8.4ms to 9.3ms). Figure 4 As shown in (a), because the AP can send data in advance during the T1 time period, the Nth image frame data is sent before the Vsync signal corresponding to the original N+1th image frame data is activated. The content of the Nth image frame data is also stored in the GRAM, and the screen can display normally at this time. Additionally, it can be seen that when the TE signal corresponding to the original N+1th image frame data is activated, only the remaining part of the Nth image frame data is sent (therefore, the Nth image frame data is still displayed within the display cycle of the Vsync signal corresponding to the original N+1th image frame data, which can also be understood as the frame rate slowing down), and the N+1th image frame data is not sent, so the screen display is normal.

[0060] As mentioned above Figure 1 As described in the examples, the system uses a global refresh scenario at certain times and a partial refresh scenario at other times. In most cases, the system frequently switches between these two scenarios. However, if we follow... Figure 4 Scheme (a) presents a problem when switching from a global refresh scenario to a partial refresh scenario. For example, in a partial refresh scenario, if the coordinates of a partial refresh corresponding to a certain image frame are located relatively late in the content of a frame, the solution described above, which sends the TE signal to the AP a time interval T1 in advance, giving the AP (8.3+T1) ms to send data, may result in the next image frame being written to GRAM before the previous image frame data has finished refreshing on the screen. This means that while the screen is refreshing the current image frame data (e.g., the Nth image frame data), the next partial image frame data (e.g., the N+1th image frame data) is also being refreshed, leading to display abnormalities. Figure 4As shown in (b), the (N+1)th image frame data is partially refreshed. Assuming the (N+1)th image frame data is meant to refresh the last 200 rows of the Nth image frame data (for example, the display has 2000 rows in total), it can be seen that because the TE signal corresponding to the N+1th image frame data is within the refresh time period of the Vsync signal corresponding to the Nth image frame data, when the N+1th TE signal is activated, the AP can send data to the GRAM in the display chip. Therefore, the GRAM will buffer the N+1th image frame data at the corresponding location. At this time, the refresh of the N+1th image frame data will begin before the last 200 rows of the Nth image frame data are completely refreshed, resulting in the Nth image frame data not being fully refreshed. This phenomenon is equivalent to showing the user the N+1th frame in advance, but the Nth frame is never fully displayed to the user. Therefore, in partial refresh scenarios, ensuring the screen display effect becomes a technical problem that needs to be solved.

[0061] In view of this, this application proposes a method for adjusting the TE signal. Based on the coordinates of the first image frame data, the start time of the TE signal corresponding to the first image frame data is adjusted. The adjusted TE signal is then sent, and the first image frame data is received. This ensures that after a refresh is initiated on the screen, new image frame data will not be written to the storage space corresponding to the data that has not yet been refreshed on the screen. This solves the display anomaly problem and guarantees the screen display effect and the user's business experience.

[0062] The following is combined with Figure 2 The system architecture shown provides a detailed description of the technical solution proposed in this application. Figure 5 This is a schematic flowchart of an image processing method 500 proposed in this application, such as... Figure 5 As shown, the method includes:

[0063] 510, AP sends the coordinates corresponding to the first image frame data to the display chip.

[0064] Correspondingly, the display chip receives the coordinates corresponding to the first image frame data.

[0065] In this application, the first image frame data can be either global refresh data of the display screen or partial refresh data of the display screen, and can be flexibly switched based on business needs without limitation.

[0066] 520, the display chip adjusts the start time of the TE signal corresponding to the first image frame data according to the coordinates corresponding to the first image frame data.

[0067] In this application, the first difference between the start time of the adjusted TE signal corresponding to the first image frame data and the start time of the Vsync signal corresponding to the first image frame data can be based on the coordinate changes corresponding to the first image frame data.

[0068] It should be noted that the "first image frame data" in this application can be understood as any single image frame data, or as each image frame data in the scheme. For example, if the scheme is understood from a timing perspective, the first image frame data could be the Nth image frame data, or the (N+1)th image frame data, or the (N+2)th image frame data, and so on. In this case, it is equivalent to the difference #1 (an example of the first difference) between the start time of the TE signal corresponding to the Nth image frame and its corresponding Vsync signal being variable, and the difference #1 being related to the coordinates corresponding to the Nth image frame data. Similarly, the difference #2 (another example of the first difference) between the start time of the TE signal corresponding to the (N+1)th image frame data and its corresponding Vsync signal being variable, and the difference #2 being related to the coordinates corresponding to the (N+1)th image frame data.

[0069] For example, suppose the rate at which the AP writes data to the GRAM is The display chip reads data from GRAM at a rate that is Assuming the total number of rows on the display screen is... Line, the starting coordinates of the first image frame data are To ensure normal display, the maximum value at which the TE signal precedes the Vsync signal is... , It should be noted that this application does not limit the scope of the application. The calculation formula is merely illustrative; any variations or calculations thereof are not permitted. All similar ideas fall within the scope of protection of this application.

[0070] In this application, M is the maximum value of the first difference to ensure normal display when the system is configured, and M is less than or equal to P. In this application, the value of the first difference varies between 0 and M depending on the coordinates corresponding to the first image frame data.

[0071] For example, P and M can be time granularities, such as M (or P) being 1ms; P and M can also be row-count granularities, such as M (or P) being 300 rows. It can also be understood that the number of rows moved forward and the time moved forward are equivalent and can be converted to each other.

[0072] In one possible implementation, when all parameters on the display screen are the same (e.g., display frame rate, AP data transmission rate, etc.), if the starting coordinate of the first image frame data shows an increasing trend, the first difference shows a decreasing trend; or, if the starting coordinate of the first image frame data shows a decreasing trend, the first difference shows an increasing trend. Figure 6 As shown, Figure 6 The Nth, N+1th, and N+2th image frame data can all be considered as the first image frame data. Assuming the coordinates of the Nth image frame data are [1000~2000], the N+1th image frame data are [1800~2000], and the N+2th image frame data are [1600~2000], we can see that the first differences between each of these three image frame data and its corresponding Vsync signal are k1 (e.g., 1ms), k2 (e.g., 500ms), and k3 (e.g., 600ms), respectively. We can see that k2 < k3 < k1. This is because a larger starting coordinate of the first image frame data indicates that the local refresh data is later. In this case, the first difference should decrease. This can also be understood as the TE signal corresponding to the first image frame data should be started later; otherwise, it is highly likely that the first image frame data will overwrite the content that has not yet been refreshed in the currently refreshed image frame data cached in the GRAM.

[0073] In another possible implementation, the first difference can be M in the scenario of a global refresh of the display; and the first difference can be 0 in the scenario of a partial refresh of the display.

[0074] 530, the display chip sends the TE signal to the AP according to the adjusted TE signal start time.

[0075] Correspondingly, the AP receives the TE signal from the display chip.

[0076] 540, AP sends the first image frame data to the display chip based on the TE signal.

[0077] Correspondingly, the display chip receives the first image frame data from the AP.

[0078] In this application, if the Nth image frame data (e.g., the previous image frame number of the first image frame data) has not been completely transmitted when the TE signal is received, the remaining part of the Nth image frame data will continue to be transmitted within the transmission cycle, without transmitting the N+1th image frame (which can also be understood as the first image frame data). For example, the N+1th image frame data can be transmitted after the next TE signal is initiated.

[0079] Based on the above technical solution, in this application, the start time of the TE signal corresponding to the first image frame data can be adjusted according to the coordinates of the first image frame data. Thus, the first image frame data sent based on the adjusted start time of the TE signal will not cover the unrefreshed content in the current image frame data, which can ensure the display effect of the display screen and improve the user experience.

[0080] Those skilled in the art will recognize that, based on the units and algorithm steps described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] This application embodiment can divide the device for adjusting the TE signal into functional modules according to the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of functional modules according to each function as an example.

[0082] Figure 7 This is a schematic block diagram of a device 700 for adjusting a TE signal provided in this application. As shown in the figure, the device 700 may include a transceiver unit 710 and a processing unit 720.

[0083] The modules described above are used to execute the respective steps of the methods mentioned above, which will not be elaborated here.

[0084] It should also be understood that the device 700 here is embodied in the form of a functional unit. The term "unit" here may refer to application-specific integrated circuits (ASICs), electronic circuits, processors (e.g., shared processors, proprietary processors, or group processors) and memories for executing one or more software or firmware programs, combined logic circuits, and / or other suitable components that support the described functions.

[0085] The apparatus 700 of each of the above-described schemes has the function of implementing the corresponding steps of the method 500 described above. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the determining unit can be replaced by a processor to execute the transmit / receive operations and related processing operations in each method embodiment. Furthermore, the determining unit can be a processing circuit.

[0086] Figure 8 This is a schematic block diagram of a display device 800 provided in an embodiment of this application. As shown, the device 800 includes at least one processor 820. The processor 820 is coupled to a memory and is used to execute instructions stored in the memory to transmit and / or receive signals. Optionally, the device 800 also includes a memory 830 for storing instructions. Optionally, the device 800 also includes a transceiver 810, and the processor 820 controls the transceiver 810 to transmit and / or receive signals.

[0087] It should be understood that the processor 820 and memory 830 described above can be combined into a single processing device, with the processor 820 executing the program code stored in the memory 830 to achieve the aforementioned functions. In specific implementations, the memory 830 can be integrated into the processor 820 or independent of the processor 820.

[0088] It should also be understood that transceiver 810 may include a transceiver (or receiver) and a transmitter (or transmitter). The transceiver may further include an antenna, and the number of antennas may be one or more. Transceiver 810 may have a communication interface or interface circuitry.

[0089] Specifically, the processor 820 in the device 800 may correspond to the processing unit 720 in the device 700. The transceiver 810 in the device 800 may correspond to the transceiver unit 710 in the device 700.

[0090] As one approach, the device 800 is used to implement the steps corresponding to the display chip and the AP in the above method 500 embodiment.

[0091] For example, processor 820 is used to execute computer programs or instructions stored in memory 830 to implement the various steps in method 500 above.

[0092] In this embodiment, a computer program product containing instructions is also provided. The computer program product may be a software or program product containing instructions capable of running on a computing device cluster or stored on any available medium. When run by the computing device cluster, it causes the computing device cluster to perform the methods provided above, or causes the computing device cluster to implement the functions of the apparatus provided above.

[0093] In this embodiment, a computer-readable storage medium is also provided. This computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that, when executed on a computing device, cause the computing device to perform the method described above.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0096] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0097] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0098] In addition, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0099] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for adjusting the tearing effect TE signal, characterized in that, include: Based on the coordinates corresponding to the first image frame data, the start time of the tearing effect TE signal corresponding to the first image frame data is adjusted. The first difference between the start time of the adjusted TE signal corresponding to the first image frame data and the start time of the vertical synchronization Vsync signal corresponding to the first image frame data is variable, and the first difference is related to the coordinates corresponding to the first image frame data. According to the adjusted start time of the TE signal, the tearing effect TE signal is sent. The tearing effect TE signal is used to indicate the transmission of the first image frame data. The adjusted start time of the TE signal ensures that the first image frame data will not overwrite the data of the current image frame data that has not yet been refreshed on the display screen. The current image frame data is the image frame data preceding the first image frame data. Receive the first image frame data.

2. The method according to claim 1, characterized in that, The first difference is less than or equal to P and greater than or equal to 0, wherein P is the maximum value of the TE signal being earlier than the Vsync signal while ensuring normal display.

3. The method according to claim 1 or 2, characterized in that, When the first image frame data is the global refresh data of the display screen, the first difference is M, where M is less than or equal to P, and P is the maximum value at which the TE signal is earlier than the Vsync signal while ensuring normal display.

4. The method according to claim 1 or 2, characterized in that, When the first image frame data is the partial refresh data of the display screen, the first difference is N, where N is less than M, M is less than or equal to P, and P is the maximum value where the TE signal is earlier than the Vsync signal while ensuring normal display.

5. The method according to claim 1 or 2, characterized in that, When the starting coordinates of the first image frame data show an increasing trend, the first difference shows a decreasing trend; or, when the starting coordinates of the first image frame data show a decreasing trend, the first difference shows an increasing trend.

6. A device for adjusting the tearing effect TE signal, characterized in that, include: The transceiver unit and the processing unit, wherein, The processing unit is used to adjust the start time of the tearing effect TE signal corresponding to the first image frame data according to the coordinates corresponding to the first image frame data. The first difference between the start time of the adjusted TE signal corresponding to the first image frame data and the start time of the vertical synchronization Vsync signal corresponding to the first image frame data is variable, and the first difference is related to the coordinates corresponding to the first image frame data. The processing unit is used to control the transceiver unit to send the tearing effect TE signal according to the adjusted start time of the TE signal. The tearing effect TE signal is used to indicate the transmission of the first image frame data. The adjusted start time of the TE signal ensures that the first image frame data will not overwrite the data of the current image frame data that has not yet been refreshed on the display screen. The current image frame data is the image frame data preceding the first image frame data. The transceiver unit is used to receive the first image frame data.

7. The apparatus according to claim 6, characterized in that, The first difference is less than or equal to P and greater than or equal to 0, wherein P is the maximum value of the TE signal being earlier than the Vsync signal while ensuring normal display.

8. The apparatus according to claim 6 or 7, characterized in that, When the first image frame data is the global refresh data of the display screen, the first difference is M, where M is less than or equal to P, and P is the maximum value at which the TE signal is earlier than the Vsync signal while ensuring normal display.

9. The apparatus according to claim 6 or 7, characterized in that, When the first image frame data is the partial refresh data of the display screen, the first difference is N, where N is less than M, M is less than or equal to P, and P is the maximum value where the TE signal is earlier than the Vsync signal while ensuring normal display.

10. The apparatus according to claim 6 or 7, characterized in that, When the starting coordinates of the first image frame data show an increasing trend, the first difference shows a decreasing trend; or, when the starting coordinates of the first image frame data show a decreasing trend, the first difference shows an increasing trend.

11. A display device, characterized in that, It includes a first module, which is used to perform the method according to any one of claims 1 to 5.

12. A chip system, characterized in that, The system includes a processor for retrieving and running a computer program from memory, causing a device equipped with the chip system to perform the method described in any one of claims 1 to 5.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 5.

14. A computer program product, characterized in that, Includes instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1 to 5.

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