Exclusive access control method for multi-core processor, multi-core processor and electronic device

Abstract

The embodiment of the present invention provides an exclusive access control method for a multi-core processor, a multi-core processor and an electronic device, the method comprising: when a local monitor receives a mutually exclusive read request from a cache module, determining whether the mutually exclusive read request hits the cache; when the mutually exclusive read request does not hit the cache, the local monitor sends a first request to a global monitor; when the global monitor receives the first request, the global register is set, and the first target data recorded in the first request address is sent to the local monitor according to the processor core identifier; after receiving the first target data, the local monitor sets the local register and saves the cache line state corresponding to the first target data and the request address. The embodiment of the present invention reduces the message requests sent by the processor to the CHI bus, can alleviate bus congestion, and improve the efficiency of mutually exclusive access.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an exclusive access control method for a multi-core processor, a multi-core processor and an electronic device. Background Art

[0002] In a multi-core processor system, exclusive access control is an essential mechanism to ensure that access to shared memory data is exclusive, that is, only one processor core can access specific memory data within a certain period of time under the effective addition of a lock. This mechanism is particularly important in a multi-core processor system because it can avoid data consistency issues and other potential concurrent access conflicts.

[0003] However, in a high-concurrency environment, frequent lock contention will lead to frequent exclusive access failures and retries, reducing system performance; and when the number of processor cores increases, the complexity of many exclusive access control strategies increases significantly, increasing the difficulty of development and maintenance. Summary of the invention

[0004] The embodiment of the present invention provides an exclusive access control method of a multi-core processor, a multi-core processor and an electronic device, which can implement exclusive access control in a multi-core processor system.

[0005] On the one hand, an embodiment of the present invention discloses an exclusive access control method for a multi-core processor, which is applied to a multi-core processor, wherein the multi-core processor includes at least two local monitors and one global monitor, and each local monitor corresponds to a processor core; the method includes:

[0006] The local monitor, upon receiving a mutually exclusive read request from a memory access module, determines whether the mutually exclusive read request hits a cache;

[0007] When the exclusive read request misses the cache, the local monitor sends a first request to the global monitor, wherein the first request carries an exclusive flag, a first request address of the exclusive read request, and a processor core flag corresponding to the local monitor; the exclusive flag is used to indicate exclusive access;

[0008] When receiving the first request, the global monitor sets a global register and sends the first target data recorded in the first request address to the local monitor according to the processor core identifier;

[0009] After receiving the first target data, the local monitor sets a local register and saves the cache line state corresponding to the first target data and the request address.

[0010] Optionally, the method further comprises:

[0011] The local monitor queries the state of the local register when receiving a mutually exclusive write request from the memory access module;

[0012] The local monitor queries the second cache line state corresponding to the second request address of the mutually exclusive write request when the local register is set;

[0013] When the second cache line state is a shared state, the local monitor sends a second request to the global monitor, wherein the second request carries an exclusive flag, the second request address, and a processor core flag corresponding to the local monitor;

[0014] After receiving the second request, if there is no global register matching the second request in the global monitor, the global monitor sets the global register and sends a first message to the local monitor; the first message is used to notify the local monitor to re-initiate a mutual exclusion request.

[0015] Optionally, the method further comprises:

[0016] After receiving the first message, the local monitor ping-pongs a first operation and a second operation;

[0017] The first operation includes: clearing the local register and returning a first response message to the memory access module, wherein the first response message is used to indicate that the mutually exclusive write request has failed; the second operation includes: maintaining the current state of the local register and resending the second request to the global monitor.

[0018] Optionally, the method further comprises:

[0019] In the case that a global register matching the second request exists in the global monitor, the global monitor clears the global registers corresponding to other processor cores matching the second request address, maintains the global registers corresponding to the second request address of the processor core of the local monitor, and sends a second message to the local monitor; the second message is used to notify the local monitor that the mutually exclusive write request is successful.

[0020] Optionally, the method further comprises:

[0021] When the local register is not set, the local monitor returns a first response message to the memory access module, wherein the first response message is used to indicate that the mutually exclusive write request fails;

[0022] When the first condition is met, the local monitor writes the second target data carried in the mutually exclusive write request back to the cache, and returns a second response message to the memory access module, where the second response message is used to indicate that the mutually exclusive write request is successful;

[0023] The first condition includes any one of the following:

[0024] The local monitor receives a second message sent by the global monitor, where the second message is used to indicate that the mutually exclusive write request is successful;

[0025] The second cache line state corresponding to the second request address of the mutually exclusive write request is a modified state or an exclusive state.

[0026] Optionally, the method further comprises:

[0027] When the local monitor receives the response message corresponding to the second request, the local monitor sets the priority of the mutually exclusive write request corresponding to the processor core identifier in the second request to the highest priority.

[0028] Optionally, when receiving a mutually exclusive read request from a memory access module, the local monitor determines whether the mutually exclusive read request hits a cache, including:

[0029] When receiving a mutually exclusive read request from a memory access module, the local monitor queries a first cache line state corresponding to a first request address of the mutually exclusive read request;

[0030] When the first cache line state is any one of a modified state, an exclusive state, and a shared state, determining that the mutually exclusive read request hits the cache;

[0031] When the first cache line state is an invalid state, it is determined that the exclusive read request misses the cache.

[0032] On the other hand, an embodiment of the present invention discloses a multi-core processor, the multi-core processor comprising at least two local monitors and one global monitor, each local monitor corresponding to a processor core;

[0033] The local monitor is used to:

[0034] In the case of receiving a mutually exclusive read request from a memory access module, determining whether the mutually exclusive read request hits the cache;

[0035] In the case where the mutually exclusive read request misses the cache, sending a first request to the global monitor, wherein the first request carries an exclusive flag, a first request address of the mutually exclusive read request, and a processor core flag corresponding to the local monitor; the exclusive flag is used to indicate exclusive access;

[0036] The global monitor is configured to, upon receiving the first request, set a global register and send the first target data recorded in the first request address to the local monitor according to the processor core identifier;

[0037] The local monitor is used to set a local register after receiving the first target data, and save the cache line state corresponding to the first target data and the request address.

[0038] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned exclusive access control method for a multi-core processor.

[0039] The embodiment of the present invention further discloses a readable storage medium. When the instructions in the readable storage medium are executed by the processor of the electronic device, the electronic device can execute the above-mentioned exclusive access control method for the multi-core processor.

[0040] The embodiments of the present invention include the following advantages:

[0041] An embodiment of the present invention provides an exclusive access control method for a multi-core processor, which implements exclusive access control for a multi-core processor through the collaboration of a local monitor and a global monitor. When a mutually exclusive read request received by a local monitor misses a cache, the local monitor initiates a first request to the global monitor, triggering the global monitor to set a global register without having to wait for a subsequent mutually exclusive write to set the global register, thereby reducing message requests sent by the processor to a CHI bus, alleviating bus congestion, and improving the efficiency of mutually exclusive access. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0043] Figure 1 It is a flowchart of the steps of an embodiment of an exclusive access control method for a multi-core processor of the present invention;

[0044] Figure 2 It is a schematic diagram of a processing flow of a mutually exclusive read request of the present invention;

[0045] Figure 3It is a schematic diagram of a processing flow of a mutually exclusive write request of the present invention;

[0046] Figure 4 is a structural block diagram of a multi-core processor of the present invention;

[0047] Figure 5 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0050] Method Embodiment

[0051] First, some key terms involved in the embodiments of the present invention are explained:

[0052] The Coherent Hub Interface (CHI) protocol is a protocol for building high-performance, low-power multi-processor systems. It provides an efficient, low-latency method to connect multiple processors, accelerators, memory, and other system components to achieve shared memory access and cache consistency. The CHI protocol is an evolution of the AXI Coherence Extension (ACE) protocol and is part of Arm's AMBA bus, designed to solve cache consistency issues in multi-core processor systems.

[0053] The MESI (Modified, Exclusive, Shared, Invalid) protocol is a common cache consistency protocol used for cache consistency management in multi-processor systems. It ensures that the cache contents of multiple processors remain consistent by attaching status information to each cache line.

[0054] Cache is a high-speed storage device with an access speed faster than system memory and comparable to the processing speed of the CPU. However, the cache capacity is much smaller than the system memory. The cache is based on the principle of "local behavior of program execution and data access" in memory, that is, within a certain program execution time and space, the accessed code and data will be concentrated in one part.

[0055] Network-on-Chip (NoC) is a communication network structure implemented on an integrated circuit chip, which is used to connect various functional modules, processor cores, storage units and other important components on the chip. With the increase in chip integration and the rise of multi-core processors, NoC has become increasingly important because it provides an efficient and low-latency communication method within the chip.

[0056] Load Exclusive (LE, also known as Load-Reserved or LR) is a special instruction provided in processor architectures such as RISC-V and ARMv8 to implement atomic operations and memory synchronization. The Load Exclusive instruction reads a value from memory and stores it in a register. Unlike ordinary read instructions, it also marks the memory address as "reserved" or "exclusive", which means that other processors or threads should not modify the value of the memory address until the subsequent Store Exclusive instruction is executed.

[0057] Store Exclusive (SE, also known as Store-Conditional or SC) is a special instruction used with the Load Exclusive (LE) instruction. It is commonly found in processors such as the ARMv8 (also known as AArch64) architecture and RISC-V, and is used to implement atomic operations in lock-free programming. The Store Exclusive instruction attempts to store a value into a memory address that was previously marked as "exclusive" or "reserved" by a Load Exclusive instruction. If the memory address has not been modified by other processors or threads since the Load Exclusive instruction was executed (that is, it is still in the "exclusive" state), the Store Exclusive instruction successfully stores the value at the address and clears its "exclusive" state. If the state of the memory address has changed (that is, it is no longer in the "exclusive" state), the Store Exclusive instruction fails.

[0058] Snoop message: plays an important role in multi-processor systems and is used to maintain the consistency of shared data. It ensures that the cache states of each processor remain consistent by notifying other processors of changes to shared data, thereby improving system reliability and performance. During system design and optimization, the transmission method, type, and application scenario of Snoop messages need to be considered to achieve efficient cache consistency management.

[0059] Home Node (HN or HNF): A node that manages and stores data within a specific address range and processes requests from other nodes. HN plays a vital role in maintaining cache consistency and managing memory access.

[0060] Request Node (RN or RHF): refers to the node responsible for generating transaction requests and sending these requests to other nodes in the system. In the ARM AMBA CHI protocol, RN is the key component responsible for initiating transaction requests and interacting with other system nodes. Its main functions include generating transaction requests, address translation and routing, transaction management, and maintaining cache consistency. Through these functions, RN ensures the efficiency and consistency of data transmission in high-performance computing systems.

[0061] Reference Figure 1 , shows a flowchart of an embodiment of an exclusive access control method for a multi-core processor of the present invention, and the method may specifically include the following steps:

[0062] Step 101: When receiving a mutually exclusive read request from a memory access module, the local monitor determines whether the mutually exclusive read request hits the cache;

[0063] Step 102: When the exclusive read request does not hit the cache, the local monitor sends a first request to the global monitor; the first request carries an exclusive flag, a first request address of the exclusive read request, and a processor core flag corresponding to the local monitor; the exclusive flag is used to indicate exclusive access;

[0064] Step 103: When receiving the first request, the global monitor sets a global register and sends the first target data recorded in the first request address to the local monitor according to the processor core identifier;

[0065] Step 104 : After receiving the first target data, the local monitor sets a local register and saves the cache line status corresponding to the first target data and the request address.

[0066] The exclusive access control method for a multi-core processor provided in an embodiment of the present invention can be applied to a multi-core processor, wherein the multi-core processor includes a local monitor (LM) and a global monitor (GM), and each local monitor corresponds to a processor core.

[0067] It should be noted that architectures such as ARM and RISC-V have introduced an exclusive type of memory access instruction, defining an exclusive read (load-exclusive) instruction, which is similar to an ordinary read instruction and performs a read operation on the memory. An exclusive write (store-exclusive) instruction is also defined, which is similar to an ordinary write instruction, but it may not be successfully executed. The exclusive write instruction will write back the success or failure flag of the operation to its result register. If the execution fails, it means that the memory is not actually written. Generally speaking, Load-Exclusive instructions and Store-Exclusive instructions should be used in pairs. The use of this pair of instructions can realize an optimistic locking mechanism. Specifically, when obtaining data through the Load-Exclusive instruction, the state of the memory location where the data is located is recorded at the same time; then the data is processed; finally, when writing the data back through the Store-Exclusive instruction, the previously recorded state is checked, and it can only be successfully written back if the state has not been modified.

[0068] The mutually exclusive read request in the present invention refers to the Load-Exclusive instruction, and the mutually exclusive write request refers to the Store-Exclusive instruction. The multi-core processor in the present invention can be a processor in an architecture such as ARM, RISC-V, etc. Exemplarily, taking the ARMv8-A architecture as an example, an ARM multi-core processor (such as Cortex-A57MPCore and Cortex-A53MPCore processor) can include one to four cores. A multi-core processor may include multiple cores that can execute instructions independently, and these cores can be regarded as a single unit or a cluster. The multi-core processor in the present invention can also be a large-scale processor core of a network on chip (NoC).

[0069] The exclusive access control mechanism in a multi-core processor is usually implemented through the collaborative processing of local monitors and global monitors. Specifically, in a multi-core processor, each processor core has its own local monitor to manage the exclusive access of the processor core. There is generally a global monitor in a multi-core processor to globally coordinate the exclusive access requests of each processor core.

[0070] In the embodiment of the present invention, the implementation of the global monitor is relatively simple, and is responsible for coordinating the mutually exclusive access requests issued by all local monitors, and initiating snoop messages to the target local monitors. The global monitor includes multiple global registers (GM entry) for recording the status of mutually exclusive access, and the number of global registers is generally equal to the number of processor cores.

[0071] The local monitor receives and processes mutually exclusive read and write requests from the memory access module, and sends requests to the global monitor based on the current cache status. The local monitor is also responsible for processing Snoop messages from the CHI bus, modifying the cache status, and maintaining the content of the LM entry. The local monitor contains a local register (LM entry) to record the status of mutually exclusive access, and its number is generally 1.

[0072] The exclusive access control method for a multi-core processor provided in an embodiment of the present invention modifies the monitor operation of the exclusive read in the CHI protocol, and the local monitor and the global monitor cooperate to implement exclusive access control. Specifically, in an embodiment of the present invention, when the local monitor receives an exclusive read request from the memory access module, it first determines whether the exclusive read request hits the cache. When the exclusive read request does not hit the cache, it sends a first request to the global monitor, and the first request carries an exclusive flag, the first request address of the exclusive read request, and the processor core flag corresponding to the local monitor, and the exclusive flag is used to indicate exclusive access. Exemplarily, the first request in the present invention can be ReadNotSharedDirty, and the excl field is set (indicating that the read request is an exclusive read request). It should be noted that ReadNotSharedDirty is a type of data read request transaction. The local monitor initiates a ReadNotSharedDirty request to indicate that any type of cache line is accepted, except for the Shared Dirty type, that is, only clean or exclusive dirty data is accepted.

[0073] When the global monitor receives the first request, it sets the global register. It should be noted that the global register can be divided into two parts: a valid bit (or enable bit) and a data bit, wherein the data bit is used to record data, and the valid bit is used to indicate the state of the global register. When the valid bit is set (for example, the valid bit is "1"), it indicates that the global register is in a valid state; when the valid bit is cleared (for example, the valid bit is "0"), it indicates that the global register is in an invalid state. The process of setting the global register may include: recording the request address, the processor core identifier, and setting the valid bit (or enable bit). In an embodiment of the present invention, while setting the valid bit of the global register, the first request address and the processor core identifier of the mutually exclusive read request carried in the first request can be recorded in the data bit of the global register. Then, the global monitor will send the first target data recorded in the first request address to the local monitor corresponding to the processor core identifier.

[0074] After receiving the first target data, the local monitor sets the local register and records the first request address, the first target data and the cache line status. The process of setting the local register is: recording the mutually exclusive read request address of the memory access module and setting the valid bit (or enable bit). When judging whether the local register is set, it is also necessary to check whether the request address recorded in the local register matches the received mutually exclusive read request address, and whether the valid bit of the local register is set. Exemplarily, after receiving the first target data, the local monitor sets the valid bit of the local register, records the first request address in the data bit of the local register, and writes the first target data and the cache line status corresponding to the first target data into the local cache, so as to send the first target data to the memory access module at an appropriate time. Alternatively, in an embodiment of the present invention, the local monitor may also set the local register after sending the first request when the mutually exclusive read request misses the cache.

[0075] The local monitor itself does not record cache lines and their status, but can obtain cache lines and their status by accessing the local cache.

[0076] It should be noted that in the current CHI protocol, when processing a mutually exclusive read request, no matter whether the cache hits or not, the global register is not set, and only the local register is set. In the embodiment of the present invention, if the mutually exclusive read request hits the cache, the local register is set; if the mutually exclusive read request does not hit the cache, that is, the cache is missed, the local monitor will initiate a first request to the global monitor, triggering the global monitor to set the global register, without having to wait for the subsequent mutually exclusive write to set the global register, which reduces the message request sent by the processor to the CHI bus, can alleviate bus congestion, and improve the efficiency of mutually exclusive access.

[0077] It can be understood that the local monitor can query the cache according to the first request address of the mutually exclusive read request. If the data corresponding to the first request address exists in the cache, it can be determined that the mutually exclusive read request hits the cache; conversely, if the data corresponding to the first request address does not exist in the cache, it can be determined that the mutually exclusive read request does not hit the cache.

[0078] Of course, it is also possible to determine whether the mutually exclusive read request hits the cache based on the cache line status.

[0079] Optionally, in step 101, when the local monitor receives a mutually exclusive read request from a memory access module, determining whether the mutually exclusive read request hits the cache includes:

[0080] Step S11, when receiving a mutually exclusive read request from a memory access module, the local monitor queries a first cache line state corresponding to a first request address of the mutually exclusive read request;

[0081] Step S12: when the first cache line state is any one of a modified state, an exclusive state and a shared state, determining that the mutually exclusive read request hits the cache;

[0082] Step S13: When the first cache line is in an invalid state, determine that the exclusive read request misses the cache.

[0083] The cache line state in the embodiment of the present invention complies with the MESI-based consistency protocol. In the MESI protocol, each cache line has four states, namely exclusive state (exclusive, E), modified state (modified, M), shared state (shared, S) and invalid state (invalid, I).

[0084] Among them, the M state means that the content of the cache line has been modified, and the cache line is only cached in this CPU. The data in the cache line in this state is different from the data in the memory, and it will be written to the memory at some point in the future (when other CPUs want to read the content of the cache line, or when other CPUs want to modify the content in the memory corresponding to the cache line).

[0085] The E state means that the content of the memory corresponding to the cache line is only cached by this CPU, and other CPUs do not cache the content of the memory line corresponding to the cache line. The content of the cache line in this state is consistent with the content in the memory. The cache line can be changed to the S state when any other CPU reads the content of the memory line corresponding to the cache line, or when the local processor writes the cache line, its state will be changed to the M state.

[0086] The S state means that the data exists not only in the local CPU cache, but also in the cache of other CPUs. The data of the cache line in this state is consistent with the data in the memory. When a CPU modifies the content of the memory line corresponding to the cache line, the state of the cache line will change to the I state.

[0087] The I state indicates that the content in the cache line is invalid.

[0088] In an embodiment of the present invention, if the first cache line state corresponding to the first request address of the mutually exclusive read request is any one of M, E, and S, it can be determined that the mutually exclusive read request hits the cache; if the first cache line state is I state, it can be determined that the mutually exclusive read request does not hit the cache.

[0089] Reference Figure 2 , shows a schematic diagram of a processing flow of a mutually exclusive read request provided by an embodiment of the present invention. Figure 2As shown, when the local monitor receives a mutually exclusive read request from the memory access module, it first queries the first cache line state corresponding to the first request address of the mutually exclusive read request. When the first cache line state is any one of M, E, and S, it indicates a cache hit. At this time, the local monitor sets the local register and records the first request address. At the same time, it directly reads the first target data from the cache and returns it to the memory access module.

[0090] When the first cache line state is in the I state, it indicates a cache miss. At this time, the local monitor will initiate a first request to the global monitor. The first request carries an exclusive flag, the first request address of the mutually exclusive read request, and the processor core ID corresponding to the local monitor. The exclusive flag is used to indicate exclusive access. Exemplarily, the first request in the present invention can be ReadNotShareDirty, and the excl field is set (indicating that the read request is a mutually exclusive read request). When the global monitor receives the first request, it sets the global register, records the first request address, and the processor core ID, and sends the first target data recorded in the first request address to the local monitor. It can be understood that the global monitor can send the first target data to the local monitor through a data response message, such as CompDate (a response message containing data). The respErr field in the data response message is "exclusive ok", indicating that the global monitor has recorded the first request address and the processor core ID carried in ReadNotShareDirty. After receiving the first target data, the local monitor sets the local register, records the first request address, and saves the first target data and the cache line state.

[0091] In an optional embodiment of the present invention, the method further includes:

[0092] Step S21, when the local monitor receives a mutually exclusive write request from a memory access module, it queries the state of the local register;

[0093] Step S22: When the local register is not set, the local monitor returns a first response message to the memory access module, where the first response message is used to indicate that the mutually exclusive write request fails;

[0094] Step S23, the local monitor queries the second cache line state corresponding to the second request address of the mutually exclusive write request when the local register is set;

[0095] Step S24: When the second cache line state is a shared state, the local monitor sends a second request to the global monitor, where the second request carries an exclusive flag, the second request address, and a processor core flag corresponding to the local monitor;

[0096] Step S25: When there is a global register matching the second request in the global monitor, the global monitor clears the global registers corresponding to other processor cores matching the second request address, maintains the global registers corresponding to the second request address of the processor core of the local monitor, and sends a second message to the local monitor; the second message is used to notify the local monitor that the mutually exclusive write request is successful;

[0097] Step S26: After receiving the second request, if there is no global register matching the second request in the global monitor, the global monitor sets the global register and sends a first message to the local monitor; the first message is used to notify the local monitor to re-initiate the mutual exclusion request.

[0098] Reference Figure 3 , shows a schematic diagram of a processing flow of a mutually exclusive write request provided by an embodiment of the present invention. Figure 3 As shown, in the embodiment of the present invention, when the local monitor receives the mutually exclusive write request from the memory access module, it will first query the status of the local register. If the local register is not set, that is, the local register is missing or the valid bit indication is invalid (for example, the valid bit is "0"), the local monitor will directly return a first response message to the memory access module to inform the memory access module that the mutually exclusive write request has failed.

[0099] If the local register is set, that is, the valid bit of the local register indicates that it is valid (for example, the valid bit is "1"), the local monitor will query the second cache line state corresponding to the second request address of the mutually exclusive write request. If the second cache line state is in the S state, the local monitor will initiate a second request to the global monitor, and the second request carries an exclusive flag, the second request address, and the processor core flag corresponding to the local monitor. Exemplarily, the second request in the embodiment of the present invention can be a CleanUnique transaction in the CHI protocol, and the excl field of the instruction is set (indicating that the instruction is mutually exclusive). It should be noted that in the CHI protocol, the CleanUnique transaction is used to clear copies of other CPUs. If other copies are dirty, it is necessary to ensure that the dirty cache lines are written back to the memory. Specifically, RNF (the local monitor is located in RNF) will send a CleanUnique request to HNF (the global monitor is located in HNF). After receiving the CleanUnique request, HNF will send a Snoop message--SnpCleanUnique--to other cores to clear the cache line copies of other processor cores.

[0100] After receiving the second request, the global monitor will first determine whether there is a global register that matches the second request. For example, if there is a request address recorded in any global register that is the same as the second request address carried in the second request, and the processor core identifier recorded in the global register is the same as the processor core identifier carried in the second request, then it can be determined that there is a global register that matches the second request. If there is no global register whose recorded request address and processor core identifier are the same as the second request address and processor core identifier in the second request, then it can be determined that there is no global register that matches the second request.

[0101] If the global register of the mutually exclusive write request is missing, that is, there is no global register matching the mutually exclusive write request, the global monitor sets the global register and sends a first message to the local monitor to notify the local monitor to re-initiate the mutually exclusive request.

[0102] If there is a global register that matches the second request, the global registers corresponding to other processor cores that match the second request address are cleared, and the global register of the processor core that issued the second request is retained. The next time the processor core issues a mutually exclusive request with the same address, it does not need to reset the global register. At the same time, the global monitor sends a second message to the local monitor to notify the local monitor that the mutually exclusive write request is successful.

[0103] In addition, when the global monitor clears the global registers of other processor cores, the cache data corresponding to the second request address in the other processor cores may also be set to invalid data. Exemplarily, the HNF (the global monitor is located in the HNF) may set the cache data to invalid data through a snoop message, for example, the global monitor sends SnpCleanUnique and SnpCleanInvalid messages to other processor cores, and after receiving the messages, the other processor cores will invalidate the cache lines corresponding to the address fields in the snoop messages.

[0104] As an example, when the second request does not have a mutually exclusive attribute (that is, the exclusive flag of the second request is not set), HNF will directly send a Snoop message (SnpCleanUnique) after receiving CleanUnique. When the second request has a mutually exclusive attribute (that is, the exclusive flag of the second request is set), HNF will determine whether to send a Snoop message (SnpCleanUnique) based on the feedback of the global monitor after receiving CleanUnique. If the global register hits, the Snoop message is sent to other processor cores. If it does not hit, the Snoop message is not sent.

[0105] In combination with the above content, it can be seen that in the embodiment of the present invention, the condition for setting the global register is: receiving the first request (such as ReadNotSharedDirty) or the second request (such as CleanUnique) carrying an exclusive flag, and the global register is not hit (that is, no register matching the request address and the processor flag is found in the set global registers). The condition for setting the local register is: receiving a mutually exclusive read request from the memory access module (previously set does not affect the operation).

[0106] Optionally, the method further comprises:

[0107] When the first condition is met, the local monitor writes the second target data carried in the mutually exclusive write request back to the cache, and returns a second response message to the memory access module, where the second response message is used to indicate that the mutually exclusive write request is successful.

[0108] The first condition includes any one of the following:

[0109] A1. The local monitor receives a second message sent by the global monitor, where the second message is used to indicate that the mutually exclusive write request is successful;

[0110] A2. The second cache line state corresponding to the second request address of the mutually exclusive write request is a modified state or an exclusive state.

[0111] After receiving the second message, the local monitor returns a second response message to the memory access module, informing the memory access module that the mutually exclusive write request is successful. At the same time, the local monitor will write the second target data carried in the mutually exclusive write request back to the cache, that is, write it back to the second request address, replace the original data in the second request address, and change the second cache line state corresponding to the second request address to the M state.

[0112] If the local monitor finds that the second cache line state is M or E state after setting the local register, it will directly return a second response message to the memory access module to inform it that the exclusive write request is successful. At the same time, the local monitor will write the second target data carried in the exclusive write request back to the cache and change the second cache line state to M state.

[0113] Optionally, the method further comprises:

[0114] After receiving the first message, the local monitor ping-pongs the first operation and the second operation.

[0115] The first operation includes: clearing the local register and returning a first response message to the memory access module, wherein the first response message is used to indicate that the mutually exclusive write request has failed; the second operation includes: maintaining the current state of the local register and resending the second request to the global monitor.

[0116] It should be noted that, in the embodiment of the present invention, when the local monitor receives the first message (instructing to re-initiate the mutual exclusion request), it will make two responses: 1. The LM entry is cleared and a response to the failure of the mutual exclusion write request is returned (re-initiating mutual exclusion read and mutual exclusion write); 2. The LM entry is maintained and a second request is re-initiated to the global monitor (for example, initiating a CleanUnique transaction).

[0117] These two operations are performed in a ping-pong manner, that is, if the operation corresponding to item A1 is executed last time, the operation corresponding to item A2 is executed next time, and the operation corresponding to item A1 is executed the next time, and so on, and so on, until the mutually exclusive write is successful.

[0118] In the embodiment of the present invention, after receiving the first message, the local monitor ping-pongs and executes the two operations corresponding to A1 and A2, which can change the processing sequence of the local monitor and prevent the deadlock caused by the snoop message.

[0119] It is understandable that the local monitor may receive a snoop message of the address between mutually exclusive read and mutually exclusive write, and needs to be handled with caution. In summary, three types of snoop messages will be received: 1. Invalid messages. After receiving such messages, LMentry will be cleared and the cache status will be set to invalid I; 2. Shared messages. After receiving such messages, LM entry will not change and the cache status will change to S; 3. One-time messages. After receiving such messages, neither LM entry nor cache status will change. Among them, the snoop message contains a special field to indicate the message type. After receiving the snoop message, the local monitor can parse the field and determine the subsequent processing method.

[0120] In most processor architectures, other read and write requests are not allowed between mutually exclusive reads and writes, but when this situation occurs, the local monitor should try to handle it. When the cache is replaced, there are two situations: 1. (M state) replacement of dirty data, the local monitor will issue a WriteBackfull request to write the dirty data to the next level cache; 2. When the cache state is not the M state (that is, the data in the cache line is not dirty data), the cache data will be directly invalidated, for example, the valid bit field of the cache data is set to "0", and in subsequent cache replacements, the cache data will be directly overwritten. When the above two situations occur, the local monitor needs to clear the LM entry, that is, set the valid bit to an invalid state, for example, to "0".

[0121] Optionally, the method further comprises:

[0122] When the local monitor receives the response message corresponding to the second request, the local monitor sets the priority of the mutually exclusive write request corresponding to the processor core identifier in the second request to the highest priority.

[0123] The local monitor uses a flexible arbitration strategy to ensure that mutually exclusive read and write requests are completed as soon as possible. Usually, the highest priority is the processing of snoop messages, followed by the processing of read transactions, write transactions, and dataless transactions received from HNF, and finally the read and write requests from the memory access module.

[0124] In an embodiment of the present invention, when the local monitor receives the RSP message (response message, including the first message and the second message) of the second request (for example, the CleanUnique transaction) and enters the processing unit, the exclusive write request of the memory access unit is given the highest priority. Even if there is a snoop transaction waiting to be processed, the exclusive write request will be processed first. This arbitration strategy will eliminate the time gap from the RSP message to the processing of the snoop transaction of the exclusive write, reduce the phenomenon of exclusive access retries to a certain extent, and improve the efficiency of exclusive access.

[0125] In summary, an embodiment of the present invention provides an exclusive access control method for a multi-core processor, which implements exclusive access control for a multi-core processor through the collaboration of a local monitor and a global monitor. When a mutually exclusive read request received by the local monitor misses the cache, the local monitor initiates a first request to the global monitor, triggering the global monitor to set the global register without having to wait for subsequent mutually exclusive writes to set the global register. This reduces the message requests sent by the processor to the CHI bus, can alleviate bus congestion, and improve the efficiency of mutually exclusive access.

[0126] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0127] Device Embodiment

[0128] Reference Figure 4 , shows a structural block diagram of a multi-core processor of the present invention, wherein the multi-core processor includes at least two local monitors and one global monitor, and each local monitor corresponds to a processor core.

[0129] Wherein, the local monitor is used to:

[0130] In the case of receiving a mutually exclusive read request from a memory access module, determining whether the mutually exclusive read request hits the cache;

[0131] In the case where the mutually exclusive read request misses the cache, sending a first request to the global monitor, wherein the first request carries an exclusive flag, a first request address of the mutually exclusive read request, and a processor core flag corresponding to the local monitor; the exclusive flag is used to indicate exclusive access;

[0132] The global monitor is configured to, upon receiving the first request, set a global register and send the first target data recorded in the first request address to the local monitor according to the processor core identifier;

[0133] The local monitor is used to set a local register after receiving the first target data, and save the cache line state corresponding to the first target data and the request address.

[0134] Optionally, the local monitor is further used for:

[0135] In case of receiving a mutually exclusive write request from a memory access module, querying the state of the local register;

[0136] In the case where the local register is set, querying a second cache line state corresponding to a second request address of the mutually exclusive write request;

[0137] When the second cache line state is a shared state, sending a second request to the global monitor, wherein the second request carries an exclusive flag, the second request address, and a processor core flag corresponding to the local monitor;

[0138] The global monitor is also used for:

[0139] After receiving the second request, if there is no global register matching the second request in the global monitor, the global register is set and a first message is sent to the local monitor; the first message is used to notify the local monitor to re-initiate a mutual exclusion request.

[0140] Optionally, the local monitor is further used for:

[0141] After receiving the first message, ping pong performs a first operation and a second operation;

[0142] The first operation includes: clearing the local register and returning a first response message to the memory access module, wherein the first response message is used to indicate that the mutually exclusive write request has failed; the second operation includes: maintaining the current state of the local register and resending the second request to the global monitor.

[0143] Optionally, the global monitor is further used for:

[0144] In the case that a global register matching the second request exists in the global monitor, the global registers corresponding to other processor cores matching the second request address are cleared, and the global registers corresponding to the second request address of the processor core of the local monitor are maintained, and a second message is sent to the local monitor; the second message is used to notify the local monitor that the mutually exclusive write request is successful.

[0145] Optionally, the local monitor is further used for:

[0146] In the case where the local register is not set, returning a first response message to the memory access module, wherein the first response message is used to indicate that the mutually exclusive write request fails;

[0147] If the first condition is met, writing the second target data carried in the mutually exclusive write request back to the cache, and returning a second response message to the memory access module, where the second response message is used to indicate that the mutually exclusive write request is successful;

[0148] The first condition includes any one of the following:

[0149] The local monitor receives a second message sent by the global monitor, where the second message is used to indicate that the mutually exclusive write request is successful;

[0150] The second cache line state corresponding to the second request address of the mutually exclusive write request is a modified state or an exclusive state.

[0151] Optionally, the local monitor is further used for:

[0152] When a response message corresponding to the second request is received, the priority of the mutually exclusive write request corresponding to the processor core identifier in the second request is set to the highest priority.

[0153] Optionally, the local monitor is specifically used for:

[0154] In case of receiving a mutually exclusive read request from a memory access module, querying a first cache line state corresponding to a first request address of the mutually exclusive read request;

[0155] When the first cache line state is any one of a modified state, an exclusive state, and a shared state, determining that the mutually exclusive read request hits the cache;

[0156] When the first cache line state is an invalid state, it is determined that the exclusive read request misses the cache.

[0157] An embodiment of the present invention provides a multi-core processor, which realizes exclusive access control of the multi-core processor through the collaboration of a local monitor and a global monitor. When a mutually exclusive read request received by the local monitor does not hit the cache, the local monitor will initiate a first request to the global monitor, triggering the global monitor to set the global register without waiting for a subsequent mutually exclusive write to set the global register, thereby reducing the message requests sent by the processor to the CHI bus, alleviating bus congestion and improving the efficiency of mutually exclusive access.

[0158] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0159] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0160] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0161] Reference Figure 5 , is a structural block diagram of an electronic device provided by an embodiment of the present invention. Figure 5 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the exclusive access control method of the multi-core processor of the above-mentioned embodiment.

[0162] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0163] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0164] The memory can be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk and optical data storage device, etc.

[0165] The embodiment of the present invention also provides a non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is able to execute Figure 1 The exclusive access control method of the multi-core processor is shown.

[0166] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0167] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0168] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0169] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0171] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0172] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0173] The above is a detailed introduction to the exclusive access control method for a multi-core processor, a multi-core processor and an electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for exclusive access control of a multi-core processor, characterized in that: Applied to a multi-core processor, the multi-core processor includes at least two local monitors and one global monitor, each local monitor corresponds to a processor core; the method includes: The local monitor, upon receiving a mutually exclusive read request from a memory access module, determines whether the mutually exclusive read request hits a cache; When the exclusive read request misses the cache, the local monitor sends a first request to the global monitor, wherein the first request carries an exclusive flag, a first request address of the exclusive read request, and a processor core flag corresponding to the local monitor; the exclusive flag is used to indicate exclusive access; When receiving the first request, the global monitor sets a global register and sends the first target data recorded in the first request address to the local monitor according to the processor core identifier; the global monitor includes at least one global register; the number of the global registers is equal to the number of processor cores; the global register is used to record the state of mutually exclusive access of each processor core; the global register includes a first valid bit and a first data bit; the first valid bit is used to indicate the state of the global register; After receiving the first target data, the local monitor sets a local register and saves the cache line status corresponding to the first target data and the request address; the local monitor includes a local register; the local register is used to record the status of the corresponding processor core mutual exclusion access; the local register includes a second valid bit and a second data bit; the second valid bit is used to indicate the status of the local register.

2. The method according to claim 1, characterized in that: The method further comprises: The local monitor queries the state of the local register when receiving a mutually exclusive write request from the memory access module; The local monitor queries the second cache line state corresponding to the second request address of the mutually exclusive write request when the local register is set; When the second cache line state is a shared state, the local monitor sends a second request to the global monitor, wherein the second request carries an exclusive flag, the second request address, and a processor core flag corresponding to the local monitor; After receiving the second request, if there is no global register matching the second request in the global monitor, the global monitor sets the global register and sends a first message to the local monitor; the first message is used to notify the local monitor to re-initiate a mutual exclusion request.

3. The method according to claim 2, characterized in that The method further comprises: After receiving the first message, the local monitor ping-pongs a first operation and a second operation; The first operation includes: clearing the local register and returning a first response message to the memory access module, wherein the first response message is used to indicate that the mutually exclusive write request has failed; the second operation includes: maintaining the current state of the local register and resending the second request to the global monitor.

4. The method according to claim 2, characterized in that: The method further comprises: In the case that a global register matching the second request exists in the global monitor, the global monitor clears the global registers corresponding to other processor cores matching the second request address, maintains the global registers corresponding to the second request address of the processor core of the local monitor, and sends a second message to the local monitor; the second message is used to notify the local monitor that the mutually exclusive write request is successful.

5. The method according to claim 2, characterized in that: The method further comprises: When the local register is not set, the local monitor returns a first response message to the memory access module, wherein the first response message is used to indicate that the mutually exclusive write request fails; When the first condition is met, the local monitor writes the second target data carried in the mutually exclusive write request back to the cache, and returns a second response message to the memory access module, where the second response message is used to indicate that the mutually exclusive write request is successful; The first condition includes any one of the following: The local monitor receives a second message sent by the global monitor, where the second message is used to indicate that the mutually exclusive write request is successful; The second cache line state corresponding to the second request address of the mutually exclusive write request is a modified state or an exclusive state.

6. The method according to claim 2, characterized in that The method further comprises: When the local monitor receives the response message corresponding to the second request, the local monitor sets the priority of the mutually exclusive write request corresponding to the processor core identifier in the second request to the highest priority.

7. The method according to claim 1, characterized in that The local monitor, when receiving a mutually exclusive read request from a memory access module, determines whether the mutually exclusive read request hits a cache, including: When receiving a mutually exclusive read request from a memory access module, the local monitor queries a first cache line state corresponding to a first request address of the mutually exclusive read request; When the first cache line state is any one of a modified state, an exclusive state, and a shared state, determining that the mutually exclusive read request hits the cache; When the first cache line state is an invalid state, it is determined that the exclusive read request misses the cache.

8. A multi-core processor, characterized in that: The multi-core processor includes at least two local monitors and one global monitor, each local monitor corresponding to a processor core; The local monitor is used to: In the case of receiving a mutually exclusive read request from a memory access module, determining whether the mutually exclusive read request hits the cache; In the case where the mutually exclusive read request does not hit the cache, sending a first request to the global monitor, wherein the first request carries an exclusive flag, a first request address of the mutually exclusive read request, and a processor core flag corresponding to the local monitor; The exclusive flag is used to indicate exclusive access; The global monitor is used to set a global register when receiving the first request, and send the first target data recorded in the first request address to the local monitor according to the processor core identifier; the global monitor includes at least one global register; the number of the global registers is equal to the number of processor cores; the global register is used to record the state of mutually exclusive access of each processor core; the global register includes a first valid bit and a first data bit; the first valid bit is used to indicate the state of the global register; The local monitor is used to set a local register after receiving the first target data and save the cache line status corresponding to the first target data and the request address; the local monitor includes a local register; the local register is used to record the status of the corresponding processor core mutual exclusion access; the local register includes a second valid bit and a second data bit; the second valid bit is used to indicate the status of the local register.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the exclusive access control method for a multi-core processor as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the exclusive access control method for a multi-core processor as described in any one of claims 1 to 7.

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