A chip verification system and method based on Verilog

Abstract

The present invention provides a chip verification system and method based on Verilog, and relates to the field of chip verification technology. The system includes a verification platform, and the verification platform has a built-in verification module and a physical layer component. Among them, the verification platform is FPGA or EDA. One end of the physical layer component is connected to the verification module, and the other end of the physical layer component is connected to the chip to be tested. Among them, the physical layer component is designed based on the Verilog language, and at least two physical layers are integrated inside the physical layer component. The present invention verifies the chip by replacing the real physical layer model with the physical layer component designed based on the Verilog language, which can not only enable the chip to be simulated on the EDA platform, but also enable the chip to be prototyped on the FPGA platform, thereby verifying the integrity of the chip function and ensuring the high quality of the chip design. And at least two physical layers are integrated inside the physical layer component, making the networking of the entire verification system simpler and more convenient.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a chip verification system and method based on Verilog. Background Art

[0002] In the chip simulation and verification process, Electronic Design Automation (EDA) simulation and Field-Programmable Gate Array (FPGA) verification assume different roles and functions. It is necessary to rely on EDA to complete simulation work from concept to implementation, and also to use FPGA for hardware-level verification, so as to achieve full coverage of chip function verification.

[0003] EDA simulation can find functional defects in the design process to the greatest extent, but since EDA simulation has no timing in the simulation function stage, it is difficult to find deep-seated errors in chip logic design through EDA simulation, and FPGA is needed to prototype the chip.

[0004] In high-speed signal transmission, the high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE) has become the most widely used bus standard due to its fast transmission rate, low latency, and support for hot plugging. Since most FPGAs on the market currently only support the Gen3 rate of the PCIE protocol, that is, the rate of the physical layer in the FPGA platform can only support Gen3, but some chips under test are Gen5 devices, such as retimer chips, so the physical layer in the FPGA platform cannot perform functional verification on the chips under test.

[0005] The physical layer in the prior art is mostly implemented through simulation, that is, a real physical layer circuit is first implemented through simulation, and then the real physical layer circuit is converted into a real physical layer model. Since the development cycle of the real physical layer model is long and difficult, and most of the functions of the real physical layer model are hardcore and cannot be synthesized, the real physical layer model cannot be applied to FPGA for testing.

[0006] In addition, during the chip verification process, one end of the chip to be tested needs to transmit data with the verification module through two physical layers, and the two physical layers need to communicate through the physical layer interface (Physical Interface for PCI Express, PIPE) of the high-speed serial computer expansion bus, which leads to the problems of cumbersome verification environment construction and complex networking.

[0007] In summary, how to improve the integrity of chip function verification and simplify the construction of the verification environment is a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0008] The purpose of the present invention is to provide a chip verification system and method based on Verilog to improve the integrity of chip function verification and simplify the construction of the verification environment.

[0009] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0010] In a first aspect, the present invention provides a Verilog-based chip verification system, the Verilog-based chip verification system comprising a verification platform, the verification platform having a built-in verification module and a physical layer component; wherein the verification platform is an FPGA or EDA; one end of the physical layer component is connected to the verification module, and the other end of the physical layer component is connected to a chip to be tested; wherein the physical layer component is designed based on the Verilog language, and at least two physical layers are integrated inside the physical layer component;

[0011] The verification module is used to send multiple excitation signals that comply with the PCIE protocol to the physical layer component;

[0012] The physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of excitation signals to generate a random excitation signal;

[0013] The chip under test is used to generate a processing signal according to the random excitation signal, and send the processing signal to the physical layer component;

[0014] The physical layer component is also used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the processing signal to generate a random processing signal;

[0015] The verification module is further used to analyze the received random processing signal to determine whether the chip under test meets expectations.

[0016] Optionally, when the verification platform is an EDA platform and the chip to be tested is a Retimer chip, the verification module includes an RC verification environment and an EP verification environment, and the physical layer component includes a first physical layer component and a second physical layer component; wherein the first physical layer component integrates two physical layers, and the second physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC verification environment through the first physical layer component, and the other end of the chip to be tested is connected to the EP verification environment through the second physical layer component;

[0017] The RC verification environment is used to send a plurality of first stimulus signals that comply with the PCIE protocol to the first physical layer component;

[0018] The first physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of first excitation signals to generate a first random excitation signal;

[0019] The chip under test is used for generating a first processing signal according to the first random excitation signal, and sending the first processing signal to the second physical layer component;

[0020] The second physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the first processed signal to generate a first random processed signal;

[0021] The EP verification environment is used to parse the received first random processing signal to determine whether the chip under test meets expectations.

[0022] Optionally, when the verification platform is an EDA platform and the chip to be tested is a Retimer chip, the verification module includes an RC verification environment and an EP verification environment, and the physical layer component includes a first physical layer component and a second physical layer component; wherein the first physical layer component integrates two physical layers, and the second physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC verification environment through the first physical layer component, and the other end of the chip to be tested is connected to the EP verification environment through the second physical layer component;

[0023] The EP verification environment is used to send a plurality of second stimulus signals that comply with the PCIE protocol to the second physical layer component;

[0024] The second physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of second excitation signals to generate a second random excitation signal;

[0025] The chip under test is used for generating a second processing signal according to the second random excitation signal, and sending the second processing signal to the first physical layer component;

[0026] The first physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the second processed signal to generate a second random processed signal;

[0027] The RC verification environment is used to analyze the received second random processing signal to determine whether the chip under test meets expectations.

[0028] Optionally, when the verification platform is an FPGA platform and the chip to be tested is a Retimer chip, the verification module includes an RC device and an EP device, and the physical layer component includes a third physical layer component and a fourth physical layer component; wherein the third physical layer component integrates two physical layers, and the fourth physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC device through the third physical layer component, and the other end of the chip to be tested is connected to the EP device through the fourth physical layer component;

[0029] The RC device is used to send a plurality of third excitation signals conforming to the PCIE protocol to the third physical layer component;

[0030] The third physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of third excitation signals to generate a third random excitation signal;

[0031] The chip under test is used to generate a third processing signal according to the third random excitation signal, and send the third processing signal to the fourth physical layer component;

[0032] The fourth physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the third processed signal to generate a third random processed signal;

[0033] The EP device is used to analyze the received third random processing signal to determine whether the chip under test meets expectations.

[0034] Optionally, when the verification platform is an FPGA platform and the chip to be tested is a Retimer chip, the verification module includes an RC device and an EP device, and the physical layer component includes a third physical layer component and a fourth physical layer component; wherein the third physical layer component integrates two physical layers, and the fourth physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC device through the third physical layer component, and the other end of the chip to be tested is connected to the EP device through the fourth physical layer component;

[0035] The EP device is used to send a plurality of fourth excitation signals conforming to the PCIE protocol to the fourth physical layer component;

[0036] The fourth physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of fourth excitation signals to generate a fourth random excitation signal;

[0037] The chip under test is used for generating a fourth processing signal according to the fourth random excitation signal, and sending the fourth processing signal to the third physical layer component;

[0038] The third physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the fourth processed signal to generate a fourth random processed signal;

[0039] The RC device is used to analyze the received fourth random processing signal to determine whether the chip under test meets expectations.

[0040] In a second aspect, the present invention further provides a Verilog-based chip verification method, which is applied to the Verilog-based chip verification system described in any one of the first aspects above, and the Verilog-based chip verification method includes:

[0041] The verification module sends a plurality of excitation signals conforming to the PCIE protocol to the physical layer component;

[0042] The physical layer component performs parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of excitation signals to generate a random excitation signal;

[0043] The chip under test generates a processing signal according to the random excitation signal, and sends the processing signal to the physical layer component;

[0044] The physical layer component performs parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the processing signal to generate a random processing signal;

[0045] The verification module analyzes the received random processing signal to determine whether the chip under test meets expectations.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The present invention provides a chip verification system and method based on Verilog, which can effectively solve the problems existing in the prior art by replacing the real physical layer model with the physical layer component designed based on the Verilog language to perform functional verification on the chip to be tested. The reasons are as follows:

[0048] (1) Improve the integrity of chip function verification. The physical layer component in the present invention is designed using the Verilog language, which can convert analog signals into digital signals and realize digital processing of signals. In addition, since the Verilog language includes support for synthesis from the beginning of its design, it ensures that the described logic can be mapped to actual hardware resources. Therefore, the physical layer component in the present invention can not only simulate the chip on EDA, but also be applied to FPGA for prototype verification of the chip, thereby verifying the integrity of the chip function and ensuring the high quality of chip design.

[0049] (2) Simplify the construction of the verification environment. Since the physical layer component integrates at least two physical layers, one end of the chip to be tested can transmit data with the verification module through a physical layer component. Since the two physical layers in the prior art still need to communicate through the PIPE interface, the physical layer component in the present invention not only saves the physical layer, but also solves the adaptation problem between the two physical layers, simplifies the networking, and simplifies the construction of the verification environment.

[0050] (3) It is possible to perform functional verification on the Retimer chip. When the chip to be tested is a Retimer chip, by setting a physical layer component and a verification module at each end of the Retimer chip, the Retimer chip can be functionally verified on EDA or FPGA, thereby improving the integrity of the functional verification of the Retimer chip. In addition, since the physical layer components at both ends of the Retimer chip integrate two physical layers (i.e., the two physical layers at one end of the Retimer chip are implemented by one physical layer component, and the two physical layers at the other end of the Retimer chip are implemented by another physical layer component), two physical layers are saved, simplifying the construction of the verification environment.

[0051] (4) Ability to perform abnormal tests and expand the coverage scenarios of chip verification. Physical layer components can delay, inject errors, and randomize the received data to perform abnormal tests to ensure data integrity and reliability. In addition, the physical layer components can also independently control each data channel to increase the control signal delay under each data channel, thereby simulating more extreme scenarios, simulating more realistic behaviors in actual applications, and expanding the coverage scenarios of chip verification.

[0052] (5) Reduce the difficulty of physical layer development and shorten the time of physical layer development. Verilog, as a hardware description language, can accurately describe the behavior and structure of the circuit, which is crucial for physical layer design because the physical layer involves signal transmission and interfaces, which requires precise control of timing and signal integrity. In addition, Verilog has mature simulation tools and verification methodologies, which help to discover and correct errors in the early stages of design. Therefore, using Verilog to design the physical layer can reduce the difficulty of physical layer development and shorten the time of physical layer development. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the present invention will be briefly introduced below. It should be understood that the following drawings only show certain technical solutions of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 One of the structural schematic diagrams of a Verilog-based chip verification system provided by the present invention;

[0055] Figure 2 The second structural diagram of a Verilog-based chip verification system provided by the present invention;

[0056] Figure 3 The third structural diagram of a Verilog-based chip verification system provided by the present invention;

[0057] Figure 4 The present invention provides a flowchart of a chip verification method based on Verilog.

[0058] Figure markings: 100 - chip verification system based on Verilog; 110 - verification platform; 111 - EDA platform; 112 - FPGA platform; 120 - verification module; 121 - RC verification environment; 122 - EP verification environment; 123 - RC device; 124 - EP device; 130 - physical layer component; 131 - first physical layer component; 132 - second physical layer component; 133 - third physical layer component; 134 - fourth physical layer component; 140 - chip to be tested; 150 - verification use case module; 160 - verification environment configuration module. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described technical solutions are part of the technical solutions of the present invention, but not all of the technical solutions. Generally, the components of the technical solutions of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0060] Therefore, the following detailed description of the technical solutions of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected technical solutions of the present invention. Based on the technical solutions in the present invention, all other technical solutions obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0061] In the description of the present invention, terms such as "first", "second" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance. It should be noted that the features of the present invention can be combined with each other without conflict.

[0062] As described in the background technology, most of the existing physical layers are implemented through simulation, that is, a real physical layer circuit is first implemented through simulation, and then the real physical layer circuit is converted into a real physical layer model. Since the research and development cycle of the real physical layer model is long and difficult, and most of the functions of the real physical layer model are hard-core and cannot be logically synthesized, the real physical layer model cannot be applied to FPGA for testing. In addition, during the chip verification process, one end of the chip to be tested needs to transmit data with the verification module through two physical layers, which has the problems of cumbersome verification environment construction and complex networking.

[0063] To solve the above technical problems, please refer to Figure 1 The present invention provides a Verilog-based chip verification system 100. The Verilog-based chip verification system 100 includes a verification platform 110, and the verification platform 110 has a built-in verification module 120 and a physical layer component 130. The verification platform 110 may be FPGA or EDA.

[0064] One end of the physical layer component 130 is connected to the verification module 120, and the other end of the physical layer component 130 is connected to the medium access control (MAC) module in the chip under test 140. The physical layer component 130 is designed based on the Verilog language, and the physical layer component 130 integrates at least two physical layers.

[0065] The workflow of the entire Verilog-based chip verification system 100 is as follows:

[0066] The verification module 120 is used to send a variety of excitation signals that comply with the PCIE protocol to the physical layer component 130 .

[0067] The physical layer component 130 is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a variety of stimulus signals to generate random stimulus signals.

[0068] The chip under test 140 is used to generate a processing signal according to the random excitation signal, and send the processing signal to the physical layer component 130 .

[0069] The physical layer component 130 is further configured to perform parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion operations on the processed signal to generate a random processed signal.

[0070] The verification module 120 is further used to analyze the received random processing signal to determine whether the chip under test 140 meets expectations.

[0071] Based on the above design, by replacing the physical layer components with the real physical layer model to perform functional verification on the chip under test, the drawbacks of the existing technology can be effectively solved for the following reasons:

[0072] First, since at least two physical layers are integrated inside the physical layer component, one end of the chip to be tested can transmit data with the verification module through a physical layer component. Since the two physical layers in the prior art still need to communicate through the PIPE interface, the physical layer component in the present invention not only saves the physical layer, but also solves the adaptation problem between the two physical layers, simplifies the networking, and simplifies the construction of the verification environment.

[0073] Secondly, the physical layer components in the present invention are designed using the Verilog language. As a hardware description language, Verilog can accurately describe the behavior and structure of the circuit, which is crucial for physical layer design because the physical layer involves signal transmission and interfaces, requiring precise control of timing and signal integrity. In addition, Verilog has mature simulation tools and verification methodologies, which help to discover and correct errors in the early stages of design, reduce the difficulty of physical layer research and development, and shorten the time of physical layer research and development.

[0074] In addition, the PCIE protocol requires that data at each rate needs to work normally at the minimum bit error rate. The real physical layer model can meet the requirements through some algorithms, but the real physical layer model cannot actively inject errors and perform abnormal tests. In this embodiment, the received data is delayed, injected, and randomized by the physical layer component, and the data can be tested for abnormalities to ensure the integrity and reliability of the data. In addition, the physical layer component can also independently control each data channel to increase the control signal delay under each data channel, thereby simulating more extreme scenarios, simulating more realistic behaviors in actual applications, and increasing the coverage scenarios of chip verification.

[0075] Finally, since the physical layer components in this embodiment are designed using the Verilog language, analog signals can be converted into digital signals, thus realizing digital processing of signals. Furthermore, since the Verilog language includes support for synthesis from the beginning of its design, it ensures that the described logic can be mapped to actual hardware resources. Therefore, the physical layer components designed using Verilog can not only simulate the chip on EDA, but can also be applied to FPGA for prototype verification of the chip, thereby verifying the integrity of the chip function and ensuring the high quality of the chip design.

[0076] The Verilog-based chip verification system can verify most chips on FPGAs, improving the quality of chip design. However, as the PCIE data transmission rate continues to double, it brings significant signal attenuation and reference clock timing re-adjustment problems. In order to compensate for the loss of high-speed signals and improve signal quality, it is usually necessary to introduce ultra-high-speed timing integration chips, namely Retimer chips, into the link. Therefore, in the embodiments of the present invention, Figure 1 Based on this, we also provide Figure 2 and Figure 3 The Verilog-based chip verification system 100 shown is suitable for a Retimer chip.

[0077] Since the verification platform 110 in the Verilog-based chip verification system 100 in the embodiment of the present invention can be either an EDA platform 111 or an FPGA platform 112, in order to better understand the working principle of the Verilog-based chip verification system 100 under different verification platforms 110, the following first takes the EDA platform 111 as an example for description.

[0078] As an alternative implementation, see Figure 2 When the verification platform 110 is an EDA platform 111, and the chip to be tested 140 is a Retimer chip, since the Retimer chip needs to be set between the root complex (RC) verification environment and the end point (EP) verification environment for verification, the verification module includes an RC verification environment 121 and an EP verification environment 122. The RC verification environment 121 and the EP verification environment 122 are constructed and simulated by the PCIE function model provided by the verification intellectual property core (VIP).

[0079] Since both ends of the Retimer chip need to respectively transmit data with the corresponding verification environment through a physical layer component, in the embodiment of the present invention, the physical layer component includes a first physical layer component 131 and a second physical layer component 132. The first physical layer component 131 integrates two physical layers, and the second physical layer component 132 integrates two physical layers.

[0080] One end of the chip under test 140 is connected to the RC verification environment 121 through the first physical layer component 131 , and the other end of the chip under test 140 is connected to the EP verification environment 122 through the second physical layer component 132 .

[0081] Optionally, the Verilog-based chip verification system 100 further includes a verification case module 150, where the verification case module 150 is used to configure a plurality of first stimulus signals and second stimulus signals that comply with the PCIE protocol.

[0082] Based on the above design, when the verification platform 110 is an EDA platform 111 and the chip under test 140 is a Retimer chip, the workflow of the entire Verilog-based chip verification system 100 is divided into two parts. One part of the workflow is that the RC verification environment 121 exchanges data with the EP verification environment 122, and the other part of the workflow is that the EP verification environment 122 exchanges data with the RC verification environment 121.

[0083] Combine the following Figure 2 , firstly, the specific process of data exchange between the RC verification environment 121 and the EP verification environment 122 is described:

[0084] Since the entire networking environment is based on the PCIE system, there is a link establishment interaction process at the beginning. First, during the link establishment process, the RC verification environment 121 initiates an ordered set interaction, and then sends the encoded and scrambled multiple first excitation signals that comply with the PCIE protocol to the first physical layer component 131.

[0085] The first physical layer component 131 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the first excitation signal to generate a first random excitation signal, and sends it to the MAC module in the chip under test 140 .

[0086] The chip under test 140 receives the first random excitation signal and descrambles it. At the same time, the control end in the chip under test 140 parses and processes the descrambled first random excitation signal to generate a first processed signal, encodes and scrambles the first processed signal, and then sends it to the second physical layer component 132.

[0087] The second physical layer component 132 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the first processed signal to generate a first random processed signal, and sends it to the EP verification environment 122 .

[0088] Finally, the EP verification environment 122 analyzes the received first random processing signal to determine whether the chip under test 140 meets expectations.

[0089] Similarly, combining Figure 2 The specific process of data interaction between the EP verification environment 122 and the RC verification environment 121 is as follows:

[0090] First, the EP verification environment 122 sends the encoded and scrambled multiple second stimulus signals that comply with the PCIE protocol to the second physical layer component 132 .

[0091] The second physical layer component 132 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the second excitation signal to generate a second random excitation signal, and sends it to the MAC module in the chip under test 140 .

[0092] The chip under test 140 receives the second random excitation signal and descrambles it. At the same time, the control end in the chip under test 140 parses and processes the descrambled second random excitation signal to generate a second processed signal, encodes and scrambles the second processed signal, and then sends it to the first physical layer component 131.

[0093] The first physical layer component 131 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the second processed signal to generate a second random processed signal, and sends it to the RC verification environment 121 .

[0094] Finally, the RC verification environment 121 analyzes the received second random processing signal to determine whether the chip under test 140 meets expectations.

[0095] In an embodiment of the present invention, by sequentially setting a first physical layer component and an RC verification environment at one end of the chip to be tested, and sequentially setting a second physical layer component and an EP verification environment at the other end of the chip to be tested, not only can EDA simulation of the Retimer chip be implemented, but also two physical layers can be saved, making networking simpler and more convenient.

[0096] In addition, see Figure 2 In order to improve the randomness and efficiency of EDA simulation, as a feasible implementation, the Verilog-based chip verification system 100 further includes a verification environment configuration module 160. The verification environment configuration module 160 is used to configure the parameters of the RC verification environment 121, the EP verification environment 122, the first physical layer component 131, and the second physical layer component 132.

[0097] Optionally, the verification environment configuration module 160 implements parameter configuration using a configuration file, and the configuration file is written using a script to achieve randomization of configuration parameters.

[0098] In the embodiment of the present invention, the RC verification environment, the EP verification environment, the first physical layer component and the second physical layer component can independently call the verification environment configuration module to dynamically configure parameters. During the simulation process, the change of the stimulus can be achieved by modifying the parameters in the verification environment configuration module, which saves compilation time and improves the efficiency of EDA simulation.

[0099] Although EDA platform simulation can find functional defects in the design process to the greatest extent, it is difficult to find deep-seated errors in chip logic design because EDA simulation has no timing in the simulation function stage. In order to verify the integrity of chip functions, it is necessary to use FPGA platform to prototype the chip.

[0100] As a possible implementation, see Figure 3 When the verification platform 110 is an FPGA platform 112 and the chip under test 140 is a Retimer chip, the verification module includes an RC device 123 and an EP device 124, and the physical layer component includes a third physical layer component 133 and a fourth physical layer component 134. The third physical layer component 133 integrates two physical layers, and the fourth physical layer component 134 integrates two physical layers.

[0101] One end of the chip under test 140 is connected to the RC device 123 through the third physical layer component 133 , and the other end of the chip under test 140 is connected to the EP device 124 through the fourth physical layer component 134 .

[0102] Furthermore, the RC device 123 may be a server or a computer, and the EP device 124 may be a graphics card or a solid state drive.

[0103] Similarly, when the verification platform 110 is an FPGA platform 112 and the chip under test 140 is a Retimer chip, the workflow of the entire Verilog-based chip verification system 100 is also divided into two parts. One part of the workflow is that the RC device 123 exchanges data with the EP device 124, and the other part of the workflow is that the EP device 124 exchanges data with the RC device 123.

[0104] Combine the following Figure 3 , firstly, the specific process of data interaction between the RC device 123 and the EP device 124 is described:

[0105] First, the RC device 123 sends the encoded and scrambled multiple third excitation signals that comply with the PCIE protocol to the third physical layer component 133.

[0106] The third physical layer component 133 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the third excitation signal to generate a third random excitation signal, and sends it to the MAC module in the chip under test 140 .

[0107] The chip under test 140 receives the third random excitation signal and descrambles it. At the same time, the control end in the chip under test 140 parses and processes the descrambled third random excitation signal to generate a third processed signal, encodes and scrambles the third processed signal, and then sends it to the fourth physical layer component 134.

[0108] The fourth physical layer component 134 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the third processed signal to generate a third random processed signal, and sends it to the EP device 124 .

[0109] Finally, the EP device 124 analyzes the received third random processing signal to determine whether the chip under test 140 meets expectations.

[0110] Similarly, combining Figure 3 The specific process of data interaction between the EP device 124 and the RC device 123 is as follows:

[0111] First, the EP device 124 sends the encoded and scrambled multiple fourth excitation signals that comply with the PCIE protocol to the fourth physical layer component 134.

[0112] The fourth physical layer component 134 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the fourth excitation signal to generate a fourth random excitation signal, and sends it to the MAC module in the chip under test 140 .

[0113] The chip under test 140 receives the fourth random excitation signal and descrambles it. At the same time, the control end in the chip under test 140 parses and processes the descrambled fourth random excitation signal to generate a fourth processed signal, encodes and scrambles the fourth processed signal, and then sends it to the third physical layer component 133.

[0114] The third physical layer component 133 performs operations such as parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion on the fourth processed signal to generate a fourth random processed signal, and sends it to the RC device 123 .

[0115] Finally, the RC device 123 analyzes the received fourth random processing signal to determine whether the chip under test 140 meets expectations.

[0116] In an embodiment of the present invention, by sequentially connecting the third physical layer component and the RC device at one end of the chip to be tested, and sequentially connecting the fourth physical layer component and the EP device at the other end of the chip to be tested, since the third physical layer component and the fourth physical layer component are both designed using the Verilog language, they can be synthesized, thereby realizing chip prototype verification on the FPGA.

[0117] Since FPGA verification can be run directly on hardware, it can provide performance data that is closer to the final chip implementation. Subsequent design modifications and verification can be quickly implemented and tested on the FPGA, which can accelerate the iterative optimization process of the design. In addition, FPGA verification can expose hardware-related errors that are difficult to capture in simulation, such as timing violations, signal integrity, and power integrity issues, which helps to more comprehensively verify the robustness of the chip under test.

[0118] In addition, since two physical layers are integrated inside the third physical layer component and two physical layer components are integrated inside the fourth physical layer component, the Retimer chip only needs two physical layer components to transmit data with the RC device and the EP device. Saving two physical layers makes the components of the entire verification system more convenient and simple.

[0119] As an alternative implementation, see Figure 4 The embodiment of the present invention also provides a chip verification method based on Verilog, which is applied to Figure 1 The Verilog-based chip verification system 100 shown in the figure comprises the following steps:

[0120] Step 10: The verification module sends multiple stimulus signals that comply with the PCIE protocol to the physical layer component.

[0121] Step 20: The physical layer component performs parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the multiple excitation signals to generate a random excitation signal.

[0122] Step 30: The chip under test generates a processing signal according to the random excitation signal, and sends the processing signal to the physical layer component.

[0123] Step 40: The physical layer component performs parallel-to-serial conversion, delay, error injection, randomization, and serial-to-parallel conversion operations on the processed signal to generate a random processed signal.

[0124] Step 50: The verification module analyzes the received random processing signal to determine whether the chip under test meets expectations.

[0125] In summary, the embodiment of the present invention provides a chip verification system and method based on Verilog. By replacing the real physical layer model with the physical layer components designed based on the Verilog language to verify the chip, the chip can not only be simulated on the EDA platform, but also be prototyped on the FPGA platform, thereby verifying the integrity of the chip function and ensuring the high quality of the chip design.

[0126] Since Verilog has mature simulation tools and verification methodologies, it helps to discover and correct errors in the early stages of design, reducing the difficulty and time of physical layer development. Physical layer components designed based on Verilog can delay, inject errors, and randomize the received data to ensure that the injected errors are carried out according to the bit error rate required by the PCIE protocol, thereby effectively testing whether the MAC module data path of the chip under test can work normally under the link bit error rate. In addition, physical layer components designed based on Verilog can also independently control each channel to increase the data channel and control signal delay under each channel, and can simulate many extreme scenarios and simulate more realistic behaviors in practice.

[0127] When the chip to be tested is a Retimer chip, a physical layer component is set at each end of the Retimer chip. Both physical layer components are designed in Verilog language, and two physical layers are integrated inside each physical layer component. That is, the two physical layers at one end of the Retimer chip can be implemented with one physical layer component, and similarly, the two physical layers at the other end of the Retimer chip can also be implemented with one physical layer component. Not only does it save the physical layer, but it also solves the adaptation problem between the two physical layers, simplifies networking, and simplifies the construction of the verification environment.

[0128] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0129] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A chip verification system based on Verilog, characterized in that: The Verilog-based chip verification system includes a verification platform, wherein the verification platform has a built-in verification module and a physical layer component; wherein the verification platform is an FPGA or EDA; wherein one end of the physical layer component is connected to the verification module, and the other end of the physical layer component is connected to the chip to be tested; wherein the physical layer component is designed based on the Verilog language, and the physical layer component internally integrates at least two physical layers; The verification module is used to send multiple excitation signals that comply with the PCIE protocol to the physical layer component; The physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of excitation signals to generate a random excitation signal; The chip under test is used to generate a processing signal according to the random excitation signal, and send the processing signal to the physical layer component; The physical layer component is also used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the processing signal to generate a random processing signal; The verification module is also used to analyze the received random processing signal to determine whether the chip under test meets expectations; When the verification platform is an EDA platform and the chip to be tested is a Retimer chip, the verification module includes an RC verification environment and an EP verification environment, and the physical layer component includes a first physical layer component and a second physical layer component; wherein the first physical layer component integrates two physical layers, and the second physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC verification environment through the first physical layer component, and the other end of the chip to be tested is connected to the EP verification environment through the second physical layer component; The RC verification environment is used to send a plurality of first stimulus signals that comply with the PCIE protocol to the first physical layer component; The first physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of first excitation signals to generate a first random excitation signal; The chip under test is used for generating a first processing signal according to the first random excitation signal, and sending the first processing signal to the second physical layer component; The second physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the first processed signal to generate a first random processed signal; The EP verification environment is used to parse the received first random processing signal to determine whether the chip under test meets expectations.

2. The Verilog-based chip verification system according to claim 1, characterized in that: When the verification platform is an EDA platform and the chip to be tested is a Retimer chip, the verification module includes an RC verification environment and an EP verification environment, and the physical layer component includes a first physical layer component and a second physical layer component; wherein the first physical layer component integrates two physical layers, and the second physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC verification environment through the first physical layer component, and the other end of the chip to be tested is connected to the EP verification environment through the second physical layer component; The EP verification environment is used to send a plurality of second stimulus signals that comply with the PCIE protocol to the second physical layer component; The second physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of second excitation signals to generate a second random excitation signal; The chip under test is used for generating a second processing signal according to the second random excitation signal, and sending the second processing signal to the first physical layer component; The first physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the second processed signal to generate a second random processed signal; The RC verification environment is used to analyze the received second random processing signal to determine whether the chip under test meets expectations.

3. The Verilog-based chip verification system according to claim 1 or 2, characterized in that: The Verilog-based chip verification system also includes a verification case module, which is used to configure a plurality of first excitation signals and second excitation signals that comply with the PCIE protocol.

4. The Verilog-based chip verification system according to claim 1 or 2, characterized in that: The Verilog-based chip verification system further includes a verification environment configuration module, and the verification environment configuration module is used to configure parameters of the RC verification environment, the EP verification environment, the first physical layer component, and the second physical layer component.

5. The Verilog-based chip verification system according to claim 4, characterized in that: The verification environment configuration module uses a configuration file to implement parameter configuration, and the configuration file is written in a script to achieve randomization of configuration parameters.

6. The Verilog-based chip verification system according to claim 1, characterized in that: When the verification platform is an FPGA platform and the chip to be tested is a Retimer chip, the verification module includes an RC device and an EP device, and the physical layer component includes a third physical layer component and a fourth physical layer component; wherein the third physical layer component integrates two physical layers, and the fourth physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC device through the third physical layer component, and the other end of the chip to be tested is connected to the EP device through the fourth physical layer component; The RC device is used to send a plurality of third excitation signals conforming to the PCIE protocol to the third physical layer component; The third physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of third excitation signals to generate a third random excitation signal; The chip under test is used to generate a third processing signal according to the third random excitation signal, and send the third processing signal to the fourth physical layer component; The fourth physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the third processed signal to generate a third random processed signal; The EP device is used to analyze the received third random processing signal to determine whether the chip under test meets expectations.

7. The Verilog-based chip verification system according to claim 1, characterized in that: When the verification platform is an FPGA platform and the chip to be tested is a Retimer chip, the verification module includes an RC device and an EP device, and the physical layer component includes a third physical layer component and a fourth physical layer component; wherein the third physical layer component integrates two physical layers, and the fourth physical layer component integrates two physical layers; one end of the chip to be tested is connected to the RC device through the third physical layer component, and the other end of the chip to be tested is connected to the EP device through the fourth physical layer component; The EP device is used to send a plurality of fourth excitation signals conforming to the PCIE protocol to the fourth physical layer component; The fourth physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of fourth excitation signals to generate a fourth random excitation signal; The chip under test is used for generating a fourth processing signal according to the fourth random excitation signal, and sending the fourth processing signal to the third physical layer component; The third physical layer component is used to perform parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the fourth processed signal to generate a fourth random processed signal; The RC device is used to analyze the received fourth random processing signal to determine whether the chip under test meets expectations.

8. The Verilog-based chip verification system according to claim 6 or 7, characterized in that: The RC device is a server or a computer, and the EP device is a graphics card or a solid state drive.

9. A chip verification method based on Verilog, characterized in that: Applied to the Verilog-based chip verification system according to any one of claims 1 to 8, the Verilog-based chip verification method comprises: The verification module sends a plurality of excitation signals conforming to the PCIE protocol to the physical layer component; The physical layer component performs parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on a plurality of excitation signals to generate a random excitation signal; The chip under test generates a processing signal according to the random excitation signal, and sends the processing signal to the physical layer component; The physical layer component performs parallel-to-serial conversion, delay, error injection, randomization and serial-to-parallel conversion operations on the processing signal to generate a random processing signal; The verification module analyzes the received random processing signal to determine whether the chip under test meets expectations.

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