Register sharing method, device, equipment and medium for general graphics processor

Abstract

The present application discloses a register sharing method, device, equipment and medium for a general graphics processor, which relates to the field of chip storage, including: converting received thread register addresses into several hash addresses, and determining whether the key values ​​corresponding to the several hash addresses in the preset shared register match the thread register addresses; if they match, only reading the target register data corresponding to any thread register address from the preset shared register, and transmitting the target register data through the corresponding target thread, and writing the corresponding write-back result into the preset shared register; performing data difference judgment on the write-back data written back to the corresponding thread register by several threads, if there is a data difference, saving the write-back data through the thread registers corresponding to the several threads, and if there is no data difference, only saving the write-back data corresponding to any thread through the preset shared register. In this way, the number of register accesses can be reduced and dynamic power consumption can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip storage, and in particular to a register sharing method, device, equipment and medium for a general-purpose graphics processor. Background Art

[0002] In the field of high-performance computing, the use of general-purpose computing on graphics processing units (GPGPU) has become an important means to accelerate scientific and engineering computing. The core advantage of GPGPU is that it can use graphics processing units (GPU) for non-graphics tasks, thereby achieving large-scale parallel computing, and this advantage is due to the unique storage architecture of GPGPU. In the architectural design of GPGPU, thread-level parallelism (TLP) is achieved by allocating independent register space to each execution thread. Although this design strategy greatly enhances the ability of GPGPU to handle large-scale parallel tasks, it also leads to significant hardware resource consumption.

[0003] Specifically, during the operation of GPGPU, each thread needs to independently maintain dozens of register files to ensure data storage efficiency, which brings huge chip area requirements and directly affects the manufacturing cost and complexity of the chip. In addition, because each thread execution requires a large number of register access operations, the dynamic power consumption of the register file is increased. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a register sharing method, device, equipment and medium for a general graphics processor, which can build a parallel mechanism of independent registers within a thread and shared registers between threads. The mechanism can adapt to different register storage access schemes according to data characteristics, while improving the utilization rate of register file resources, reducing the number of register accesses and reducing dynamic power consumption. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a register sharing method for a general-purpose graphics processor, which is applied to a general-purpose graphics processor, comprising:

[0006] Converting the received thread register addresses into corresponding hash addresses, and determining whether key values ​​corresponding to the hash addresses in a preset shared register match the thread register addresses;

[0007] If the key values ​​corresponding to the plurality of hash addresses in the preset shared register all match the plurality of thread register addresses, then only the target register data corresponding to any one of the plurality of thread register addresses is read from the preset shared register, the target register data is transmitted through the target thread corresponding to any one of the thread register addresses, and the corresponding write-back result is written into the preset shared register;

[0008] A data difference judgment is performed on the write-back data written back to the corresponding thread registers of several threads. If there is a data difference, the write-back data is saved through the thread registers corresponding to the several threads. If there is no data difference, only the write-back data corresponding to any one of the several threads is saved through the preset shared register.

[0009] Optionally, converting the received plurality of thread register addresses into corresponding plurality of hash addresses, and determining whether key values ​​corresponding to the plurality of hash addresses in a preset shared register match the plurality of thread register addresses, includes:

[0010] Receive a number of thread register addresses, calculate a number of hash indexes corresponding to the number of thread register addresses respectively through a hash algorithm, and determine a number of corresponding hash addresses through the number of hash indexes;

[0011] Determine the key values ​​corresponding to the plurality of hash addresses in the preset shared register, and determine whether the key values ​​corresponding to the plurality of hash addresses in the preset shared register match the plurality of thread register addresses.

[0012] Optionally, after converting the received thread register addresses into corresponding hash addresses and determining whether key values ​​corresponding to the hash addresses in a preset shared register match the thread register addresses, the method further includes:

[0013] If the key values ​​corresponding to the plurality of hash addresses in the preset shared register do not completely match the plurality of thread register addresses, then determining the non-matching thread register addresses to obtain non-matching thread register addresses;

[0014] A thread register corresponding to the non-matching thread register address is determined to obtain a non-matching target thread register, so as to transmit data in the non-matching target thread register through a thread corresponding to the non-matching target thread register, and write a corresponding write-back result into the non-matching target thread register.

[0015] Optionally, performing data difference judgment on write-back data written back to corresponding thread registers by a plurality of threads includes:

[0016] Slice the write-back data written back to the corresponding thread register by several threads according to the preset data slicing threshold, and input the obtained sliced ​​data into the AND gate and NOR gate in the preset duplicate data judgment logic bit by bit;

[0017] The difference judgment is performed on the sliced ​​data through the AND gate and the NOR gate.

[0018] Optionally, performing difference judgment on the sliced ​​data through the AND gate and the NOR gate includes:

[0019] If the outputs of the AND gate and the NOR gate are both 0, it indicates that there is a data difference in the current bit, and the data difference judgment is stopped;

[0020] If the output of the AND gate is 1, it indicates that there is no data difference in the current bit, and the plurality of write-back data corresponding to the plurality of threads are all 1 in the current bit;

[0021] If the output of the NOR gate is 1, it indicates that there is no data difference in the current bit position, and the plurality of write-back data are all 0 at the current bit position.

[0022] Optionally, the preset data slicing threshold is 8 bits.

[0023] Optionally, if there is no data difference, saving only the write-back data corresponding to any one of the plurality of threads through the preset shared register includes:

[0024] Extracting target write-back data corresponding to any thread among the plurality of threads, and determining a target register address corresponding to the target write-back data;

[0025] A target hash index corresponding to the target register address in the preset shared register is calculated, and the target write-back data is saved to a location corresponding to the target hash index.

[0026] In a second aspect, the present application discloses a register sharing device for a general-purpose graphics processor, which is applied to a general-purpose graphics processor, comprising:

[0027] An address matching judgment module, used for converting the received thread register addresses into corresponding hash addresses, and determining whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses;

[0028] an execution result saving module, configured to read only the target register data corresponding to any one of the thread register addresses from the preset shared register if the key values ​​corresponding to the plurality of hash addresses in the preset shared register all match the plurality of thread register addresses, transmit the target register data through the target thread corresponding to any one of the thread register addresses, and write the corresponding write-back result into the preset shared register;

[0029] A write-back data saving module is used to perform data difference judgment on the write-back data written back by several threads to the corresponding thread registers. If there is a data difference, the write-back data is saved through the thread registers corresponding to the several threads. If there is no data difference, only the write-back data corresponding to any one of the several threads is saved through the preset shared register.

[0030] In a third aspect, the present application discloses an electronic device, comprising:

[0031] Memory, used to store computer programs;

[0032] The processor is used to execute the computer program to implement the register sharing method of the general graphics processor as mentioned above.

[0033] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the register sharing method of the general-purpose graphics processor as described above.

[0034] In the present application, firstly, the received thread register addresses are converted into corresponding hash addresses, and it is determined whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses; if the key values ​​corresponding to the hash addresses in the preset shared register all match the thread register addresses, then only the target register data corresponding to any thread register address among the thread register addresses is read from the preset shared register, the target register data is transmitted through the target thread corresponding to any thread register address, and the corresponding write-back result is written into the preset shared register; data difference judgment is performed on the write-back data written back to the corresponding thread registers by the threads, if there is a data difference, the write-back data is saved through the thread registers corresponding to the threads, and if there is no data difference, only the write-back data corresponding to any thread among the threads is saved through the preset shared register. It can be seen that through the method of the present application, after receiving several thread register addresses, the thread register addresses can be converted into hash addresses, and then it is determined whether the key values ​​corresponding to the obtained several hash addresses in the preset shared register match the several thread register addresses. If they match, only the target register data corresponding to any thread register address can be read in the preset shared register, and the target register data can be transmitted through the corresponding thread, and then the write-back result can be written into the preset shared register. In the write-back stage, the write-back data of several threads can be judged for data differences, and when there are data differences, the write-back data can be saved through the thread register corresponding to the thread, and when there are no data differences, the write-back data corresponding to any thread can be saved through the preset shared register. In this way, a parallel mechanism of independent registers within a thread and shared registers between threads can be constructed. The mechanism can adapt to different register storage access schemes according to data characteristics, while improving the utilization rate of register file resources, reducing the number of register accesses and reducing dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0036] Figure 1 A flow chart of a register sharing method for a general graphics processor disclosed in this application;

[0037] Figure 2 A conventional register architecture diagram disclosed in this application;

[0038] Figure 3A diagram of an improved register architecture disclosed in this application;

[0039] Figure 4 A flow chart of a specific register sharing method for a general-purpose graphics processor disclosed in this application;

[0040] Figure 5 A schematic diagram of the structure of a register sharing device for a general-purpose graphics processor disclosed in this application;

[0041] Figure 6 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In the prior art, each thread needs to independently maintain dozens of register files to ensure data storage efficiency, which brings huge chip area requirements and directly affects the manufacturing cost and complexity of the chip. In addition, because each thread execution requires a large number of register access operations, the dynamic power consumption of the register file is increased.

[0044] In order to overcome the above technical problems, the present application discloses a register sharing method, device, equipment and medium for a general graphics processor, which can construct a parallel mechanism of independent registers within a thread and shared registers between threads. The mechanism can adapt to different register storage access schemes according to data characteristics, thereby improving the utilization rate of register file resources while reducing the number of register accesses and reducing dynamic power consumption.

[0045] See also Figure 1 As shown, an embodiment of the present invention discloses a register sharing method of a general-purpose graphics processor, which is applied to a general-purpose graphics processor, and includes:

[0046] Step S11: converting the received thread register addresses into corresponding hash addresses, and determining whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses.

[0047] In this embodiment, Figure 2As shown in the figure, it is the overall architecture of the traditional GPGPU register implementation solution. During the emission phase, each thread bundle will force all threads to read the registers of the same number of threads. During the write-back phase, all threads will also be forced to write the registers of the same number of threads. This brings about huge dynamic power consumption, and it will increase sharply with the increase of the number of threads. In addition, in actual engineering practice, since the threads within a thread bundle are highly synchronized, that is, the data maintained at the same register address within the thread is likely to be the same, if the registers are read and written in the traditional GPGPU register method, it will not only bring about high power consumption, but also waste a lot of register resources. And as Figure 3 As shown, the overall architecture of the GPGPU register implementation solution of the present application is provided, wherein, based on the original architecture, a parallel mechanism of independent registers within a thread and shared registers between threads is constructed, thereby effectively reducing the repeated writing and reading processes of register data.

[0048] Furthermore, the computing operation of GPGPU needs to go through five processes: instruction fetch, decoding, emission, execution and write back. In the emission stage, the information extracted in the decoding stage can be received, and the received information includes several thread register addresses, and then enters the hash address judgment module, and calculates several hash indexes corresponding to several thread register addresses through the hash algorithm, and determines the corresponding several hash addresses through the several hash indexes, and then determines the key values ​​corresponding to the several hash addresses in the preset shared register, and judges whether the key values ​​corresponding to the several hash addresses in the preset shared register match the several thread register addresses.

[0049] Step S12: If the key values ​​corresponding to the several hash addresses in the preset shared register all match the several thread register addresses, then only the target register data corresponding to any thread register address among the several thread register addresses is read from the preset shared register, the target register data is transmitted through the target thread corresponding to any thread register address, and the corresponding write-back result is written into the preset shared register.

[0050] In this embodiment, if the key values ​​corresponding to all hash addresses in the preset shared register match the corresponding several thread register addresses, it indicates that all data comes from the preset shared register. In this case, only the data of one thread needs to be transmitted and the difference signal needs to be pulled high. Because the calculation type and calculation data of all threads are consistent, only one thread needs to be executed, and the write-back result of the thread needs to be written into the thread shared register. Therefore, only the target register data corresponding to any thread register address among the several thread register addresses can be read from the preset shared register, and then the target register data is transmitted through the target thread corresponding to any thread register address, and the corresponding write-back result is written into the preset shared register.

[0051] In another case, if the key values ​​corresponding to several hash addresses in the preset shared register do not completely match the several thread register addresses, it is necessary to determine the unmatched thread register addresses and use the unmatched thread register addresses as non-matching thread register addresses, and then it is necessary to determine the thread register corresponding to the non-matching thread register address to obtain the non-matching target thread register, and finally it is necessary to transmit the data in the non-matching target thread register through the thread corresponding to the non-matching target thread register, and write the corresponding write-back result into the non-matching target thread register.

[0052] In this way, when each thread accesses a register, it will first perform a thread-shared register judgment based on the register address. If there is data in the thread-shared register that maintains the register address, it means that for this register address, the data accessed by all threads is the same, so it is only necessary to read the thread-shared register once, and there is no need to read all registers in the thread; if there is no data in the thread-shared register that maintains the register address, it means that there are differences in the data read by the thread, so it is necessary to read the register in the thread. In this way, the corresponding mechanism can be matched according to different situations, and there is no need to force all threads to perform register read operations for the number of threads, which effectively improves processing efficiency.

[0053] Step S13, performing data difference judgment on the write-back data written back to the corresponding thread registers by the several threads, if there is a data difference, saving the write-back data through the thread registers corresponding to the several threads, if there is no data difference, saving only the write-back data corresponding to any one of the several threads through the preset shared register.

[0054] In this embodiment, in the write-back stage, after each thread in a thread bundle carries data to write back to the register, it is necessary to perform data difference judgment on the write-back data written back to the corresponding thread register by several threads. If it is judged that there are differences in the write-back data of each thread, the independent register storage and access mechanism in the thread is adapted, and the data is written back to the internal register maintained by each thread according to the register address. If it is judged that the write-back data of each thread is completely consistent, or the difference signal is high, the thread-level shared register storage and access scheme is adapted, and the write-back register address and write-back data are sent to the hash address mapping module. The hash address mapping module is responsible for mapping the input write-back register address to the hash address, storing the write-back data in the thread shared register cache row corresponding to the hash address, and assigning the corresponding hash key value to the row of data.

[0055] It can be seen that through the method of the present application, after receiving several thread register addresses, the thread register addresses can be converted into hash addresses, and then it is determined whether the key values ​​corresponding to the obtained several hash addresses in the preset shared register match the several thread register addresses. If they match, only the target register data corresponding to any thread register address can be read in the preset shared register, and the target register data can be transmitted through the corresponding thread, and then the write-back result can be written into the preset shared register. In the write-back stage, the write-back data of several threads can be judged for data differences, and when there are data differences, the write-back data can be saved through the thread register corresponding to the thread, and when there are no data differences, the write-back data corresponding to any thread can be saved through the preset shared register. In this way, a parallel mechanism of independent registers within a thread and shared registers between threads can be constructed. The mechanism can adapt to different register storage access schemes according to data characteristics, effectively reducing the writing and reading processes of repeated register data, while improving the utilization rate of register file resources, reducing the number of register accesses and reducing dynamic power consumption.

[0056] See also Figure 4 As shown, an embodiment of the present invention discloses a register sharing method of a general-purpose graphics processor, which is applied to a general-purpose graphics processor, and includes:

[0057] Step S21: convert the received thread register addresses into corresponding hash addresses, and determine whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses.

[0058] Step S22: If the key values ​​corresponding to the several hash addresses in the preset shared register all match the several thread register addresses, then only the target register data corresponding to any thread register address among the several thread register addresses is read from the preset shared register, the target register data is transmitted through the target thread corresponding to any thread register address, and the corresponding write-back result is written into the preset shared register.

[0059] Step S23, slicing the write-back data written back to the corresponding thread registers by several threads according to the preset data slicing threshold, and inputting the obtained sliced ​​data into the AND gate and NOR gate in the preset duplicate data judgment logic bit by bit.

[0060] In this embodiment, the duplication judgment of multi-threaded read and write data can be implemented through a combination of an AND gate and a NOR gate. Specifically, when the thread in the image processor saves the carried write-back data to the corresponding thread register, it is necessary to perform a duplication judgment on the write-back data. First, the write-back data needs to be sliced ​​bit by bit to obtain the sliced ​​data, and then the obtained sliced ​​data is input bit by bit into the AND gate and NOR gate in the preset duplication data judgment logic. It should be noted that in this embodiment, data slicing is performed in units of 8 bits. In this way, the data is sliced ​​by 8 bits, and the hardware needs to perform fewer operations in one data duplication judgment process, which reduces resource usage and lowers dynamic power consumption.

[0061] Step S24, performing difference judgment on the sliced ​​data through the AND gate and the NOR gate.

[0062] Step S25: If there is a data difference, the write-back data is saved through the thread registers corresponding to the plurality of threads.

[0063] In this embodiment, if the outputs of the AND gate and the NOR gate are both 0, it indicates that there is a data difference in the current bit, and the data difference judgment is stopped. That is, when there is a difference in all thread data of the bit input into the judgment logic, the outputs of the AND gate and the NOR gate are both 0, then the duplicate data judgment output of the bit is 0, and the final duplicate data judgment result is also 0. At this time, the difference data of the bit needs to be saved through the thread register corresponding to each thread. In this way, when it is judged that there is a difference data, the duplicate judgment result can be directly output, and the subsequent judgment is stopped, which further saves computing resources.

[0064] Step S26: If there is no data difference, extract the target write-back data corresponding to any thread among the plurality of threads, and determine the target register address corresponding to the target write-back data.

[0065] In this embodiment, if the output of the AND gate is 1, it indicates that there is no data difference in the current bit, and the several write-back data corresponding to the several threads are all 1 in the current bit, that is, when all the thread data of the bit input into the judgment logic are 1, the output of the AND gate is 1, then the duplicate data judgment output of the bit is 1, if the duplicate data judgment output of all bits is 1, then the final duplicate data judgment result is 1, in another case, if the output of the NOR gate is 1, it indicates that there is no data difference in the current bit, and the several write-back data are all 0 in the current bit, that is, when all the thread data of the bit input into the judgment logic are 0, the output of the NOR gate is 1, then the duplicate data judgment output of the bit is 1, if the duplicate data judgment output of all bits is 1, then the final duplicate data judgment result is also 1. At this time, it indicates that there is no data difference.

[0066] It should be noted that, when there is no data difference, the target write-back data corresponding to any thread can be extracted, that is, the write-back data of any thread of this bit, and the target register address corresponding to the target write-back data can be determined.

[0067] Step S27: Calculate the target hash index corresponding to the target register address in the preset shared register, and save the target write-back data to a location corresponding to the target hash index.

[0068] In this embodiment, data can be saved by an address mapping logic unit based on a hash algorithm, wherein the address mapping logic unit based on a hash algorithm supports a variety of hardware mappable hash functions, which are divided into a hash algorithm insertion operation and a hash algorithm query operation, corresponding to the write-back process and the emission process, respectively. In the thread write-back process, the hash index position is first calculated based on the input register address using a specific hash function, that is, the corresponding address of the register address in the shared register. If the address is empty, the written-back register data is inserted. If the position already has data, the next free position is found according to the hash function exploration strategy until an empty position is found, and the write-back data is stored in the thread shared register cache row corresponding to the data, and the corresponding hash key value is assigned to the row of data. In the thread emission process, the hash index position is also calculated based on the input register address using a hash function, and the key value of the position is checked to see if it matches the input address. If it matches, it is a hit and the corresponding data is returned. If it does not match, the hash algorithm exploration strategy is used to continue searching until a matching position is found or it is determined that the address does not exist.

[0069] It can be seen that through the method of the present application, on the one hand, simple logical judgment can be used to perform data difference judgment, which effectively improves the circuit execution efficiency and reduces the hardware resource utilization; on the other hand, through the present application, the high-performance query efficiency of the hash algorithm is fully utilized to quickly and cheaply complete the query and matching of thread-level shared register storage information, and determine whether the data reading location is a shared register or a thread register, and can be dynamically selected according to the output range of the selected hash algorithm.

[0070] See also Figure 5 As shown, an embodiment of the present invention discloses a register sharing device for a general-purpose graphics processor, which is applied to a general-purpose graphics processor, including:

[0071] An address matching judgment module 11 is used to convert the received thread register addresses into corresponding hash addresses, and determine whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses;

[0072] An execution result saving module 12 is configured to read only the target register data corresponding to any one of the thread register addresses from the preset shared register if the key values ​​corresponding to the plurality of hash addresses in the preset shared register all match the plurality of thread register addresses, transmit the target register data through the target thread corresponding to any one of the thread register addresses, and write the corresponding write-back result into the preset shared register;

[0073] The write-back data saving module 13 is used to perform data difference judgment on the write-back data written back by several threads to the corresponding thread registers. If there is a data difference, the write-back data is saved through the thread registers corresponding to the several threads. If there is no data difference, only the write-back data corresponding to any one of the several threads is saved through the preset shared register.

[0074] In this embodiment, the received thread register addresses are first converted into corresponding hash addresses, and it is determined whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses; if the key values ​​corresponding to the hash addresses in the preset shared register all match the thread register addresses, only the target register data corresponding to any thread register address among the thread register addresses is read from the preset shared register, the target register data is transmitted through the target thread corresponding to any thread register address, and the corresponding write-back result is written into the preset shared register; data difference judgment is performed on the write-back data written back to the corresponding thread registers by the threads, and if there is a data difference, the write-back data is saved through the thread registers corresponding to the threads; if there is no data difference, only the write-back data corresponding to any thread among the threads is saved through the preset shared register. It can be seen that through the method of the present application, after receiving several thread register addresses, the thread register addresses can be converted into hash addresses, and then it is determined whether the key values ​​corresponding to the obtained several hash addresses in the preset shared register match the several thread register addresses. If they match, only the target register data corresponding to any thread register address can be read in the preset shared register, and the target register data can be transmitted through the corresponding thread, and then the write-back result can be written into the preset shared register. In the write-back stage, the write-back data of several threads can be judged for data differences, and when there are data differences, the write-back data can be saved through the thread register corresponding to the thread, and when there are no data differences, the write-back data corresponding to any thread can be saved through the preset shared register. In this way, a parallel mechanism of independent registers within a thread and shared registers between threads can be constructed. The mechanism can adapt to different register storage access schemes according to data characteristics, while improving the utilization rate of register file resources, reducing the number of register accesses and reducing dynamic power consumption.

[0075] In some embodiments, the address matching judgment module 11 may specifically include:

[0076] An address conversion unit, configured to receive a plurality of thread register addresses, calculate a plurality of hash indexes respectively corresponding to the plurality of thread register addresses through a hash algorithm, and determine a plurality of corresponding hash addresses through the plurality of hash indexes;

[0077] The address matching judgment unit is used to determine the key values ​​corresponding to the plurality of hash addresses in the preset shared register, and to judge whether the key values ​​corresponding to the plurality of hash addresses in the preset shared register match the plurality of thread register addresses.

[0078] In some embodiments, the register sharing device of the general graphics processor may further include:

[0079] a first address determining unit, configured to determine unmatched thread register addresses to obtain non-matching thread register addresses if key values ​​corresponding to the plurality of hash addresses in the preset shared register do not completely match the plurality of thread register addresses;

[0080] The first result writing unit is used to determine the thread register corresponding to the non-matching thread register address, obtain the non-matching target thread register, transmit the data in the non-matching target thread register through the thread corresponding to the non-matching target thread register, and write the corresponding write-back result into the non-matching target thread register.

[0081] In some embodiments, the write-back data saving module 13 may specifically include:

[0082] A data input submodule, used for slicing the write-back data written back to the corresponding thread registers by several threads according to a preset data slicing threshold, and inputting the obtained sliced ​​data into the AND gate and NOR gate in the preset duplicate data judgment logic bit by bit;

[0083] The difference judgment submodule is used to perform difference judgment on the sliced ​​data through the AND gate and the NOR gate.

[0084] In some embodiments, the difference determination submodule may specifically include:

[0085] A first difference judgment unit, configured to indicate that a data difference exists in the current bit if the outputs of the AND gate and the NOR gate are both 0, and stop the data difference judgment;

[0086] A second difference judgment unit, configured to indicate that if the output of the AND gate is 1, then there is no data difference in the current bit, and the plurality of write-back data corresponding to the plurality of threads are all 1 in the current bit;

[0087] The third difference judgment unit is used for indicating that if the output of the NOR gate is 1, it indicates that there is no data difference in the current bit position, and the plurality of write-back data are all 0 in the current bit position.

[0088] In some embodiments, the write-back data saving module 13 may specifically include:

[0089] A second address determination unit, configured to extract target write-back data corresponding to any thread among the plurality of threads, and determine a target register address corresponding to the target write-back data;

[0090] The second result writing unit is used to calculate the target hash index corresponding to the target register address in the preset shared register, and save the target write-back data to a position corresponding to the target hash index.

[0091] Furthermore, the present application also discloses an electronic device. Figure 6 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0092] Figure 6 The present invention provides a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the register sharing method of the general graphics processor disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0093] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0094] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0095] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, and may be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the register sharing method of the general graphics processor executed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 may further include a computer program that can be used to complete other specific tasks.

[0096] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the register sharing method of the general-purpose graphics processor disclosed above is implemented. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the above embodiments, and no further description will be given here.

[0097] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0098] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0099] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0100] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0101] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A register sharing method for a general graphics processor, characterized in that: Applicable to general-purpose graphics processors, including: Converting the received thread register addresses into corresponding hash addresses, and determining whether key values ​​corresponding to the hash addresses in a preset shared register match the thread register addresses; If the key values ​​corresponding to the plurality of hash addresses in the preset shared register all match the plurality of thread register addresses, then only the target register data corresponding to any one of the plurality of thread register addresses is read from the preset shared register, the target register data is transmitted through the target thread corresponding to any one of the thread register addresses, and the corresponding write-back result is written into the preset shared register; Performing data difference judgment on write-back data written back to corresponding thread registers by a plurality of threads, if there is a data difference, saving the write-back data through the thread registers corresponding to the plurality of threads, and if there is no data difference, saving only the write-back data corresponding to any one of the plurality of threads through the preset shared register; After converting the received thread register addresses into corresponding hash addresses and determining whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses, the method further includes: If the key values ​​corresponding to the plurality of hash addresses in the preset shared register do not completely match the plurality of thread register addresses, then determining the non-matching thread register addresses to obtain non-matching thread register addresses; A thread register corresponding to the non-matching thread register address is determined to obtain a non-matching target thread register, so as to transmit data in the non-matching target thread register through a thread corresponding to the non-matching target thread register, and write a corresponding write-back result into the non-matching target thread register.

2. The register sharing method of a general purpose graphics processor according to claim 1, characterized in that: The step of converting the received plurality of thread register addresses into corresponding plurality of hash addresses, and determining whether key values ​​corresponding to the plurality of hash addresses in a preset shared register match the plurality of thread register addresses includes: Receive a number of thread register addresses, calculate a number of hash indexes corresponding to the number of thread register addresses respectively through a hash algorithm, and determine a number of corresponding hash addresses through the number of hash indexes; Determine the key values ​​corresponding to the plurality of hash addresses in the preset shared register, and determine whether the key values ​​corresponding to the plurality of hash addresses in the preset shared register match the plurality of thread register addresses.

3. The register sharing method of a general purpose graphics processor according to claim 1, characterized in that: The step of performing data difference judgment on the write-back data written back to the corresponding thread register by the plurality of threads includes: Slice the write-back data written back to the corresponding thread register by several threads according to the preset data slicing threshold, and input the obtained sliced ​​data into the AND gate and NOR gate in the preset duplicate data judgment logic bit by bit; The difference judgment is performed on the sliced ​​data through the AND gate and the NOR gate.

4. The register sharing method of a general purpose graphics processor according to claim 3, characterized in that: The performing difference judgment on the sliced ​​data by using the AND gate and the NOR gate includes: If the outputs of the AND gate and the NOR gate are both 0, it indicates that there is a data difference in the current bit, and the data difference judgment is stopped; If the output of the AND gate is 1, it indicates that there is no data difference in the current bit, and the plurality of write-back data corresponding to the plurality of threads are all 1 in the current bit; If the output of the NOR gate is 1, it indicates that there is no data difference in the current bit position, and the plurality of write-back data are all 0 at the current bit position.

5. The register sharing method of a general purpose graphics processor according to claim 3, characterized in that: The preset data slicing threshold is 8 bits.

6. The register sharing method of a general purpose graphics processor according to any one of claims 1 to 5, characterized in that: If there is no data difference, only saving the write-back data corresponding to any one of the plurality of threads through the preset shared register includes: Extracting target write-back data corresponding to any thread among the plurality of threads, and determining a target register address corresponding to the target write-back data; A target hash index corresponding to the target register address in the preset shared register is calculated, and the target write-back data is saved to a location corresponding to the target hash index.

7. A register sharing device for a general-purpose graphics processor, characterized in that: Applicable to general-purpose graphics processors, including: An address matching judgment module, used for converting the received thread register addresses into corresponding hash addresses, and determining whether the key values ​​corresponding to the hash addresses in the preset shared register match the thread register addresses; an execution result saving module, configured to read only the target register data corresponding to any one of the thread register addresses from the preset shared register if the key values ​​corresponding to the plurality of hash addresses in the preset shared register all match the plurality of thread register addresses, transmit the target register data through the target thread corresponding to any one of the thread register addresses, and write the corresponding write-back result into the preset shared register; A write-back data saving module, used for judging data difference between write-back data written by several threads to corresponding thread registers, and if there is data difference, saving the write-back data through the thread registers corresponding to the several threads; if there is no data difference, saving only the write-back data corresponding to any one of the several threads through the preset shared register; Wherein, the register sharing device of the general graphics processor further includes: a first address determining unit, configured to determine unmatched thread register addresses to obtain non-matching thread register addresses if key values ​​corresponding to the plurality of hash addresses in the preset shared register do not completely match the plurality of thread register addresses; The first result writing unit is used to determine the thread register corresponding to the non-matching thread register address, obtain the non-matching target thread register, transmit the data in the non-matching target thread register through the thread corresponding to the non-matching target thread register, and write the corresponding write-back result into the non-matching target thread register.

8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the register sharing method for a general-purpose graphics processor according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the register sharing method for a general-purpose graphics processor according to any one of claims 1 to 6.

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