Display device and electronic terminal

Abstract

The application provides a display device and an electronic terminal, comprising a display panel, a peep-proof circuit located in the display panel and a peep-proof layer located on the light-emitting side of the display panel, the peep-proof circuit is used for generating a peep-proof signal, the peep-proof layer is electrically connected to the peep-proof circuit, and the peep-proof layer is used for controlling the viewing angle range of the display device according to the peep-proof signal, so that a module for generating the peep-proof signal is avoided to be added in a chip in the display device, and the driving cost of the display device is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and an electronic terminal. BACKGROUND

[0002] In the current privacy display device, whether the liquid crystal in the privacy box is flipped is controlled by controlling whether a square wave signal is output, so as to realize the switching between the sharing state and the privacy state. However, the square wave signal needs to be generated by a separately arranged level conversion chip, resulting in a high cost of the display device. SUMMARY

[0003] Embodiments of the present application provide a display device and an electronic terminal to solve the technical problem of high cost of the existing privacy display device due to the need to separately arrange a level conversion chip.

[0004] The present application provides a display device and an electronic terminal, comprising:

[0005] a display panel comprising a privacy circuit for generating a privacy signal;

[0006] a privacy layer arranged on the light exit side of the display panel, the privacy layer being electrically connected to the privacy circuit, and the privacy layer being configured to control the viewing angle range of the display device according to the privacy signal;

[0007] The privacy circuit comprises a level conversion circuit or a Schmitt trigger circuit.

[0008] In some embodiments, the privacy circuit comprises the level conversion circuit, and the display device comprises:

[0009] a timing control chip configured to generate a first signal, the first signal having a first potential and a second potential arranged alternately;

[0010] a power management chip configured to generate a second signal and a third signal, the second signal and the third signal being two constant voltage signals with different amplitudes;

[0011] The level conversion circuit is configured to generate the privacy signal according to the first signal, the second signal and the third signal.

[0012] In some embodiments, the power management chip is further configured to generate a fourth signal and a fifth signal, the fourth signal and the fifth signal both being constant voltage signals, and the amplitudes of the first signal, the second signal, the fourth signal and the fifth signal are all different;

[0013] The level conversion circuit is configured to generate the privacy signal according to the first signal, the second signal, the third signal, the fourth signal and the fifth signal.

[0014] In some embodiments, the level conversion circuit includes a plurality of transistors, a gate of at least one of the transistors is electrically connected to a first signal line for transmitting the first signal, a source of at least one of the transistors is electrically connected to a second signal line for transmitting the second signal, a drain of at least one of the transistors is electrically connected to a third signal line for transmitting the third signal, a source of at least one of the transistors is electrically connected to a fourth signal line for transmitting the fourth signal, and a drain of at least one of the transistors is electrically connected to a fifth signal line for transmitting the fifth signal.

[0015] In some embodiments, the anti-peep circuit includes the Schmitt trigger circuit, and the display device includes:

[0016] A power management chip is configured to generate a second signal and a third signal, the second signal and the third signal being two constant voltage signals with different amplitudes.

[0017] The Schmitt trigger circuit is configured to generate the anti-peep signal according to the second signal and the third signal.

[0018] In some embodiments, the Schmitt trigger circuit includes an operational amplifier, a resistive element electrically connected to the operational amplifier, and a capacitive element.

[0019] The period of the anti-peep signal is determined by the resistive element and the capacitive element.

[0020] In some embodiments, the capacitive element is electrically connected between an inverting input terminal of the operational amplifier and a ground.

[0021] The resistive element includes a second resistive element, a first resistive element, and a third resistive element, the second resistive element is electrically connected between a non-inverting input terminal of the operational amplifier and the ground, the first resistive element is electrically connected between an output terminal of the operational amplifier and the non-inverting input terminal of the operational amplifier, and the third resistive element is electrically connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier.

[0022] In some embodiments, the Schmitt trigger circuit includes a plurality of transistors, a second resistive element, a first resistive element, a third resistive element, and a capacitive element.

[0023] Gates of at least two of the transistors are electrically connected between the second resistive element and the first resistive element, gates of at least two of the transistors are electrically connected between the third resistive element and the capacitive element, and the second resistive element and the capacitive element are grounded.

[0024] In some embodiments, the anti-peep layer includes:

[0025] a first electrode layer electrically connected to the privacy circuit to load the privacy signal;

[0026] a second electrode layer for loading a common voltage signal;

[0027] a liquid crystal layer between the first electrode layer and the second electrode layer, for deflecting according to the common voltage signal and the privacy signal, to control the viewing angle range of the display device.

[0028] The present application also provides an electronic terminal comprising the display device as described in any one of the above.

[0029] The present application provides a display device and an electronic terminal, by arranging a privacy circuit for generating a privacy signal in a display panel, while taking into account transmitting the privacy signal to a privacy layer, so that the privacy layer is used to control the viewing angle range of the display device according to the privacy signal, the present application also avoids adding a module for generating a privacy signal in a chip in the display device, and reduces the driving cost of the display device. BRIEF DESCRIPTION OF DRAWINGS

[0030] The present application will be further described below with reference to the drawings. It should be noted that the drawings in the following description are only used to explain some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0031] Figure 1 A cross-sectional view of the display device provided by the embodiment of the present application.

[0032] Figure 2 And Figure 3 An architecture diagram of the display device provided by the embodiment of the present application.

[0033] Figure 4 A waveform diagram of part of the signals of the display device provided by the embodiment of the present application.

[0034] Figures 5 to 8 A circuit diagram of the privacy circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] The terms "first", "second", and the like in the description do not necessarily connote an ordinal or chronological relationship. Furthermore, the terms "comprise", "comprising", and the like are intended to encompass non-exclusive inclusions. For example, processes, methods, articles, or apparatuses that comprise a list of steps or modules are not limited to those steps or modules which are recited, but can also include additional steps or modules not expressly listed or inherent to such processes, methods, articles, or apparatuses.

[0037] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment. It is explicitly contemplated that embodiments described herein can be combined with each other.

[0038] Embodiments of the application provide display devices, including but not limited to the following embodiments and combinations of the following embodiments.

[0039] In some embodiments, in combination with Figures 1 to 3 As shown in the figure, the display device 100 includes a substrate 10, a privacy circuit 20 on the substrate 10 for generating a privacy signal Out, and a privacy layer 30 on the substrate 10 and electrically connected to the privacy circuit 20, the privacy layer 30 being configured to control the viewing angle range of the display device 100 according to the privacy signal Out. In this embodiment, the display device 100 can be a liquid crystal display device or a self-luminous display device, i.e., the pixel layer in the display device 100 includes a plurality of liquid crystal molecules or self-luminous devices, and the privacy layer 30 can include a plurality of liquid crystal molecules or self-luminous devices.

[0040] Specifically, the display device 100 can include a display panel 40 and a chip 50, and the chip 50 can be configured to control the display panel 40 to display a picture according to a signal output by a signal source. The display panel 40 can include a plurality of film layers arranged in a stack, and the plurality of film layers include the substrate 10, a circuit layer on the substrate 10, a pixel layer on the circuit layer, and the privacy layer 30 on the pixel layer. That is, the display panel 40 in the display device 100 includes the privacy circuit 20 for generating the privacy signal Out, and the privacy layer 30 is arranged on the light exit side of the display panel 40, and the privacy layer 30 can be considered to be arranged independently of the display panel 40.

[0041] The substrate 10 can be a flexible substrate or a rigid substrate; the circuit layer can include a privacy circuit 20 and a gate drive circuit, both of which can be located in a non-display area, and a plurality of pixel circuits can also be arranged in the display area, the above-mentioned chip can drive the gate drive circuit to work, the gate drive circuit can drive a plurality of pixel circuits to work and thus control the brightness of a plurality of sub-pixels in the pixel layer; at the same time, the privacy signal Out generated by the privacy circuit 20 acts on the privacy layer 30, for example, controls the flip state of liquid crystal molecules in the privacy layer 30, and for example, controls the light-emitting state of the self-luminous device in the privacy layer 30, thereby controlling the viewing angle range (referring to the angle at which the user can clearly observe all the contents on the screen from different directions) of the display device 100, so as to control the display panel 40 in the display device 100 to be in a privacy state or a sharing state.

[0042] It can be understood that in the embodiment, the privacy circuit 20 for controlling the viewing angle range of the display device 100 is integrated in the display panel 40 in the display device 100, which can avoid increasing a module for generating a privacy signal Out in the chip 50 in the display device 100, thereby reducing the driving cost of the display device 100.

[0043] It can be understood that in the embodiment, the privacy circuit 20 for controlling the viewing angle range of the display device 100 is integrated in the display panel 40 in the display device 100, which can avoid increasing a module for generating a privacy signal Out in the chip 50 in the display device 100, thereby reducing the driving cost of the display device 100. Figures 1 to 3 As shown in Figure 2 , the privacy circuit 20 includes a level conversion circuit 201 (for example Figure 3 ) or a Schmidt trigger circuit 202 (for example ). Specifically, the level conversion circuit 201 can process the amplitude of the original signal (having a corresponding frequency) by the reference voltage signal to obtain the privacy signal Out meeting the amplitude requirement, and the Schmidt trigger circuit 202 can directly generate the privacy signal Out meeting the amplitude requirement and having a corresponding frequency according to the reference voltage signal.

[0044] In some embodiments, as shown in Figure 2 , Figure 4 and Figure 5 , the privacy circuit 20 includes the level conversion circuit 201, and the chip 50 (in the display device 100) includes: a timing control chip 501 for generating a first signal In, the first signal In having alternately arranged first and second potentials V1 and V2; a power management chip 502 for generating a second signal VGHH and a third signal VGLL, the second signal VGHH and the third signal VGLL being two constant voltage signals with different amplitudes; wherein the level conversion circuit 201 is configured to generate the privacy signal Out according to the first signal In, the second signal VGHH and the third signal VGLL.

[0045] Specifically, the power management chip 502 can supply power to the display panel 40 and other chips, such as the gate driving circuit, pixel circuit, timing control chip, and source driving chip, so that they can work; the timing control chip 501 can transmit gate control signals to the gate driving circuit, and transmit source control signals and grayscale signals to the source driving chip. The gate driving circuit can generate multiple gate signals according to the gate control signals to act on the multi-row pixel circuits corresponding to the multi-row sub-pixels respectively, so as to control the multi-row sub-pixels to turn on sequentially. The source driving chip can generate multiple data signals corresponding to the multi-column sub-pixels according to the grayscale signals, and output multiple data signals according to the source control signals, so as to cooperate with the multiple gate signals to control each sub-pixel to present the corresponding brightness.

[0046] Among them, combined Figure 2 , Figure 4 and Figure 5 As shown, the first signal In can be a periodic signal, and the amplitude in each period can be a first potential V1 and a second potential V2 arranged sequentially. The frequency of the first signal In can be 50Hz to 60Hz, the first potential V1 can be 0V, and the second potential V2 can be greater than 0V (for example, 1.8V). The amplitude of the second signal VGHH can be greater than the amplitude of the third signal VGLL.

[0047] Understandably, the level conversion circuit 201 in this embodiment needs to rely on the frequency of the first signal In (i.e. the above-mentioned "original signal") generated by the timing control chip 501, and process the amplitude of the first signal In according to the second signal VGHH and the third signal VGLL (both of which are included in the above-mentioned "reference voltage signal") generated by the power management chip 502, so as to obtain a privacy signal Out with both amplitude and frequency meeting the requirements.

[0048] Furthermore, in combination Figure 2 , Figure 4 and Figure 5 As shown, the power management chip 502 is also used to generate a fourth signal VGH and a fifth signal VGL, both of which are constant voltage signals. The amplitudes of the second signal VGHH, the third signal VGLL, the fourth signal VGH, and the fifth signal VGL are all different. The level conversion circuit 201 is used to generate the privacy signal Out based on the first signal In, the second signal VGHH, the third signal VGLL, the fourth signal VGH, and the fifth signal VGL.

[0049] The fourth signal VGH and the fifth signal VGL (both included in the above-mentioned "reference voltage signal") can be generated by the power management chip 502 or other chips or other modules according to the voltage signals generated by the power management chip 502. The amplitude of the fourth signal VGH can be greater than the second potential V2 (for example, 3.3V), the amplitude of the fifth signal VGL can be 0V, the amplitude of the second signal VGHH can be greater than the second potential V2 (for example, 5V), and the amplitude of the third signal VGLL can be equal to the opposite of the amplitude of the second signal VGHH (for example, -5V).

[0050] As shown in Figure 5 , the level conversion circuit 201 can process the first signal In according to the fourth signal VGH and the fifth signal VGL to obtain a transition signal, and process the transition signal according to at least the second signal VGHH and the third signal VGLL to obtain a required privacy signal Out.

[0051] In some embodiments, as shown in Figure 2 , Figure 4 and Figure 5 , the level conversion circuit 201 includes a plurality of transistors, at least one gate of the transistors is electrically connected to a first signal line for transmitting the first signal, at least one source of the transistors is electrically connected to a second signal line for transmitting the second signal, at least one drain of the transistors is electrically connected to a third signal line for transmitting the third signal, at least one source of the transistors is electrically connected to a fourth signal line for transmitting the fourth signal, and at least one drain of the transistors is electrically connected to a fifth signal line for transmitting the fifth signal.

[0052] For example, the level conversion circuit 201 can include at least one first N-type transistor NT1, at least one second N-type transistor NT2, at least one third N-type transistor NT3, at least one fourth N-type transistor NT4, at least one fifth N-type transistor NT5, at least one first P-type transistor PT1, at least one second P-type transistor PT2, at least one third P-type transistor PT3, at least one fourth P-type transistor PT4, and at least one fifth P-type transistor PT5. It can be considered that each of the above-mentioned second potential V2, the amplitude of the fifth signal VGL, and the amplitude of the third signal VGLL can be used to control the conduction of the above-mentioned at least one P-type transistor, and each of the above-mentioned first potential V1, the amplitude of the fourth signal VGH, and the amplitude of the second signal VGHH can be used to control the conduction of the above-mentioned at least one N-type transistor. The sizes of the different P-type transistors can be the same or different, and the sizes of the different N-type transistors can be the same or different.

[0053] When the first signal In is the first potential V1 (for example, 0V), the fourth P-type transistor PT4 of the first stage is turned on to transmit the fourth signal VGH to control the fourth N-type transistor NT4 of the second stage to be turned on to transmit the fifth signal VGL to control the first P-type transistor PT1 of the third stage to be turned on to transmit the second signal VGHH to control the second N-type transistor NT2 of the fourth stage to be turned on to transmit the fifth signal VGL to control the second P-type transistor PT2 of the fifth stage and the fourth P-type transistor PT4 of the seventh stage to be turned on, and the fourth P-type transistor PT4 of the sixth stage to be turned off, and transmit the second signal VGHH to control the fifth N-type transistor NT5 of the eighth stage to be turned on, so that the amplitude of the anti-peep signal Out is the third signal VGLL.

[0054] When the first signal In is the second potential V2 (for example, 5V), the third N-type transistor NT3 of the first stage is turned on to transmit the fifth signal VGL to control the fourth N-type transistor NT4 and the third N-type transistor NT3 of the second stage to be turned off, the fourth P-type transistor PT4 of the second stage is turned on to transmit the fourth signal VGH to control the fourth N-type transistor NT4 of the third stage to be turned on to transmit the fifth signal VGL to control the second P-type transistor PT2 of the fourth stage and the first P-type transistor PT1 of the second stage to be turned on to transmit the second signal VGHH to control the second N-type transistor NT2 of the fifth stage to be turned on, and also transmit the second signal VGHH to control the first P-type transistor PT1 of the third stage to be turned off to transmit the fifth signal VGL to control the fourth P-type transistor PT4 of the sixth stage to be turned on to transmit the second signal VGHH to control the first N-type transistor NT1 of the seventh stage to be turned on to transmit the third signal VGLL to control the first N-type transistor NT1 of the sixth stage to be turned off and the fifth P-type transistor PT5 of the eighth stage to be turned on, so that the amplitude of the anti-peep signal Out is the second signal VGHH.

[0055] In summary, the anti-peep signal Out generated by the above-mentioned level conversion circuit 201 can have the amplitude of the second signal VGHH and the amplitude of the third signal VGLL arranged alternately, and the frequency thereof can be equal to the frequency of the first signal In.

[0056] In some embodiments, in combination with Figure 3 , Figure 4 , Figures 6 to 8 as shown, the anti-peep circuit 20 includes the Schmitt trigger circuit 202, and the display device 100 includes a power management chip 502 for generating the second signal VGHH and the third signal VGLL, the second signal VGHH and the third signal VGLL being two constant voltage signals with different amplitudes; wherein the Schmitt trigger circuit 202 is configured to generate the anti-peep signal Out according to the second signal VGHH and the third signal VGLL.

[0057] Unlike the embodiments shown in Figure 5 In this embodiment, the Schmidt trigger circuit 202 is used as the privacy circuit 20, so the timing control chip 501 does not need to generate the first signal In, but can directly generate the privacy signal Out with the required amplitude and frequency according to the second signal VGHH and the third signal VGLL (both of which are included in the above-mentioned "reference voltage signal") generated by the power management chip 502, thereby reducing the cost of the timing control chip 501.

[0058] In some embodiments, as shown in Figure 3 、 Figure 4 、 Figure 6 and Figure 7 The Schmidt trigger circuit 202 includes an operational amplifier 2021, a resistance element (including a third resistance element R3) electrically connected to the operational amplifier 2021, and a capacitor element C; wherein the period of the privacy signal Out is determined by the resistance value of the resistance element and the capacitance value of the capacitor element C. In this embodiment, the operational amplifier 2021, the resistance element, and the capacitor element C are directly used to constitute a Schmidt trigger as a Schmidt trigger circuit, so that the circuit architecture is relatively simple. The operational amplifier 2021 outputs different voltages according to the difference between the voltage of its non-inverting input and the voltage of its inverting input and the threshold voltage, and the charging and discharging characteristics of the resistance element and the capacitor element C, and relies on the above-mentioned second signal VGHH and third signal VGLL, so as to generate the privacy signal Out with the required amplitude and frequency.

[0059] Specifically, as shown in Figure 6 and Figure 7 The capacitor element C is electrically connected between the inverting input of the operational amplifier 2021 and the ground; the resistance element includes a second resistance element R2, a first resistance element R1, and a third resistance element R3, the second resistance element R2 is electrically connected between the non-inverting input "+" of the operational amplifier 2021 and the ground, the first resistance element R1 is electrically connected between the output Vo of the operational amplifier 2021 and the non-inverting input "+" of the operational amplifier 2021, and the third resistance element R3 is electrically connected between the inverting input "-" of the operational amplifier 2021 and the output Vo of the operational amplifier 2021.

[0060] It should be noted that the common comparator only contains a threshold signal and compares the threshold signal with the input signal, but if the input signal has noise, the output signal can be affected. However, the Schmidt trigger circuit 202 in the embodiment has an upper threshold voltage and a lower threshold voltage. When the amplitude of the input signal is higher than the upper threshold voltage, the output signal can be a low potential. When the amplitude of the input signal is lower than the lower threshold voltage, the output signal can be a high potential. When the amplitude of the input signal is between the upper threshold voltage and the lower threshold voltage, the potential of the output signal remains its current value. This double threshold action is called hysteresis. Therefore, even if the input signal has noise, the Schmidt trigger can still give the correct result and has better anti-noise ability.

[0061] Specifically, as shown in Figure 6 and Figure 7 When the power is just on (it can be understood that the second signal VGHH and the third signal VGLL are respectively provided to the positive voltage pin and the negative voltage pin in the operational amplifier 2021), the signal Vc of the inverting input terminal “-” of the operational amplifier 2021 is a corresponding low level, and the signal Vo of the output terminal of the operational amplifier 2021 is a corresponding high level. The corresponding high level of the signal Vo of the output terminal of the operational amplifier 2021 charges the capacitor element C through the third resistance element R3. When the potential of the inverting input terminal “-” of the operational amplifier 2021 rises to the upper threshold voltage, the signal Vo of the output terminal of the operational amplifier 2021 changes from high level to low level. At this time, the capacitor element C is discharged through the third resistance element R3. When the potential of the inverting input terminal “-” of the operational amplifier 2021 drops to the lower threshold voltage, the signal Vo of the output terminal of the operational amplifier 2021 changes from low level to high level, and the charging of the capacitor element C is restarted. The above process is repeated to form an oscillation, and the output is a square wave signal of the privacy protection signal Out.

[0062] The high level and the low level of the signal Vo of the output terminal of the operational amplifier 2021 can be equal to the amplitude of the second signal VGHH and the amplitude of the third signal VGLL respectively. Therefore, the privacy protection signal Out has the amplitude of the second signal VGHH and the amplitude of the third signal VGLL arranged alternately. Moreover, the frequency of the privacy protection signal Out can be determined by the resistance value r of the third resistance element R3 and the capacitance value c of the capacitor element C. For example, the frequency of the privacy protection signal Out can be equal to k / (r×c), where k is a constant and the range can be between 0.2 and 1.

[0063] Specifically, as shown in Figure 7As shown, in the stable state, according to the virtual short characteristic, the signal Vf at the non-inverting input terminal “+” of the operational amplifier 2021 in the Schmitt trigger circuit 202 can be considered the same as the signal Vc at its inverting input terminal “-”. Therefore, Vc = Vf = R2×Vo / (R1 + R2). Combining the above discussion, when just powered on, Vo = VGHH and Vc = 0V. Vo charges the capacitor element C through the third resistor element R3, and the potential of Vc rises until Vc > Vf (at this time, it is equal to R2×VGHH / (R1 + R2), which can be called the above-mentioned “upper threshold voltage”). Then, Vo = VGLL, and the capacitor element C discharges to Vo through the third resistor element R3, and the potential of Vc drops until Vc < Vf (at this time, it is equal to R2×VGLL / (R1 + R2), which can be called the above-mentioned “lower threshold voltage”). Then, Vo = VGHH, and the above steps are repeated to output the anti-peeping signal Out.

[0064] Among them, Figure 7 and Figure 6 The difference is only that the second resistor element R2, the first resistor element R1, and the non-inverting input terminal “+” of the operational amplifier 2021 in Figure 7 are all arranged inside the operational amplifier 2021. That is, by retaining only the inverting input terminal “-” and the output terminal of the operational amplifier 2021 outside, Figure 6 can be formed.

[0065] In some embodiments, as shown in <​​​​​​​​​​​​​​​​​The AVBN1, AVBP1, AVBN3, AVBP3, ABN, AA, AB, etc. in the figure can represent signals loaded to corresponding terminals, and the Q1, Q2, Q3, Q4, Q11, Q21, Q31, etc. can represent corresponding nodes.

[0067] It can be considered that each of the above-mentioned second potential V2, the amplitude of the fifth signal VGL, and the amplitude of the third signal VGLL can be used to control the conduction of the above-mentioned at least one P-type transistor, and each of the above-mentioned first potential V1, the amplitude of the fourth signal VGH, and the amplitude of the second signal VGHH can be used to control the conduction of the above-mentioned at least one N-type transistor. The sizes of the different P-type transistors can be the same or different, and the sizes of the different N-type transistors can be the same or different.

[0068] It can be considered that each of the above-mentioned second potential V2, the amplitude of the fifth signal VGL, and the amplitude of the third signal VGLL can be used to control the conduction of the above-mentioned at least one P-type transistor, and each of the above-mentioned first potential V1, the amplitude of the fourth signal VGH, and the amplitude of the second signal VGHH can be used to control the conduction of the above-mentioned at least one N-type transistor. The sizes of the different P-type transistors can be the same or different, and the sizes of the different N-type transistors can be the same or different. Figure 8 The gate of the group of sixth N-type transistors N1 and the gate of the group of sixth P-type transistors P1 in the figure are electrically connected to Figure 7 the non-inverting input terminal "+" of the operational amplifier 2021 in the figure, Figure 8 the gate of the group of sixth N-type transistors N1 and the gate of the group of sixth P-type transistors P1 in the figure are electrically connected to Figure 7 the inverting input terminal "-" of the operational amplifier 2021 in the figure, and the ninth N-type transistor N5 and the ninth P-type transistor P5 are both electrically connected to the output terminal of the operational amplifier 2021 so that the output signal Vo is the anti-peep signal Out. The tenth N-type transistor N2, the seventh N-type transistor N3, and the ninth N-type transistor N5 are all electrically connected to the negative voltage pin of the operational amplifier 2021 to load the third signal VGLL, and the tenth P-type transistor P2, the seventh P-type transistor P3, and the ninth P-type transistor P5 are all electrically connected to the positive voltage pin of the operational amplifier 2021 to load the second signal VGHH.

[0069] Further, as shown in the figure, Figure 4 for any of the above Figures 5 to 8 circuits, a control unit (not shown) can be arranged between the anti-peep circuit 20 and the anti-peep layer 30 to generate an anti-peep control signal Con according to the above-mentioned anti-peep signal Out and the gate signal EN. The anti-peep control signal Con can only be the waveform of the current anti-peep signal Out (for example, arranged alternately with +5V and -5V) when the gate signal EN is the corresponding high potential or low potential (for example, the latter in the figure), Figure 4 otherwise, the anti-peep common voltage signal Vcon, which can be a constant voltage signal, the amplitude of the anti-peep common voltage signal Vcon can be between the high potential and the low potential of the anti-peep signal Out, for example, can be the average of the two.

[0070] Specifically, the privacy layer 30 comprises: a first electrode layer electrically connected to the privacy circuit 20 to load the privacy signal Out; a second electrode layer for loading a common voltage signal Vcon; a liquid crystal layer between the first electrode layer and the second electrode layer, for deflecting according to the common voltage signal Vcon and the privacy signal Out, to control the viewing angle range of the display device 100. That is, when the privacy layer 30 comprises a plurality of liquid crystal molecules, one side of the privacy layer 30 can load the above-mentioned privacy common voltage signal Vcon, and the other side can load a privacy control signal Con; when the privacy control signal Con is the same as the privacy common voltage signal Vcon, it can be considered that the liquid crystal molecules do not deflect, and the display device 100 is in a privacy state; when the privacy control signal Con is the same as the privacy signal Out, it can be considered that the liquid crystal molecules deflect, and the display device 100 is in a sharing state.

[0071] Of course, for Figure 5 the control unit can also be changed to be arranged between the timing control chip 501 and the privacy circuit 20, that is, the gate signal EN can be used to control whether the control unit transmits the first signal In to the level conversion circuit 201; at this time, the signal received by the level conversion circuit 201 is the same as the first signal In only when the gate signal EN is the corresponding high or low potential; similarly, the level conversion circuit 201 can also output the above-mentioned privacy control signal Con.

[0072] The embodiment of the present application also provides an electronic terminal, comprising: the display device 100 described in any of the above; and an input / output device for interacting with the display device 100.

[0073] The present application provides a display device and an electronic terminal, by arranging a privacy circuit for generating a privacy signal in a display panel, while taking into account transmitting the privacy signal to a privacy layer, so that the privacy layer is used to control the viewing angle range of the display device according to the privacy signal, the present application also avoids adding a module for generating a privacy signal in a chip in the display device, and reduces the driving cost of the display device.

[0074] The display device and the electronic terminal provided by the embodiment of the present application are described in detail above, and in this paper, specific examples are applied to describe the principles and implementation modes of the present application, and the above-mentioned embodiment is

[0075] only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand: the technical solutions recorded in the above-mentioned embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized by comprising: The display device comprises: a display panel comprising a privacy circuit for generating a privacy signal; a privacy layer arranged on the light exit side of the display panel, the privacy layer being electrically connected to the privacy circuit, and the privacy layer being configured to control the viewing angle range of the display device according to the privacy signal; wherein the privacy circuit comprises a level conversion circuit, and the level conversion circuit is configured to obtain the privacy signal by processing the amplitude of an original signal which is a periodic signal through a reference voltage signal; The display device comprises: a timing control chip configured to generate a first signal as the original signal, the first signal having a first potential and a second potential arranged alternately; a power management chip configured to generate a second signal and a third signal included in the reference voltage signal, the second signal and the third signal being two constant voltage signals with different amplitudes; wherein the level conversion circuit is configured to generate the privacy signal according to the first signal, the second signal and the third signal; wherein the power management chip is configured to supply power to the display panel, the timing control chip and a source driving chip, the timing control chip is configured to drive the source driving chip and a gate driving circuit in the display panel, the gate driving circuit is configured to control a plurality of rows of sub-pixels in the display panel to be turned on in sequence, and the source driving chip is configured to transmit respective data signals to a plurality of columns of sub-pixels in the display panel.

2. The display device according to claim 1, wherein The power management chip is further configured to generate a fourth signal and a fifth signal, the fourth signal and the fifth signal are both constant voltage signals, and the amplitudes of the first signal, the second signal, the fourth signal and the fifth signal are all different; wherein the level conversion circuit is configured to generate the privacy signal according to the first signal, the second signal, the third signal, the fourth signal and the fifth signal.

3. The display device according to claim 2, wherein The level conversion circuit comprises a plurality of transistors, a gate of at least one of the transistors is electrically connected to a first signal line for transmitting the first signal, a source of at least one of the transistors is electrically connected to a second signal line for transmitting the second signal, a drain of at least one of the transistors is electrically connected to a third signal line for transmitting the third signal, a source of at least one of the transistors is electrically connected to a fourth signal line for transmitting the fourth signal, and a drain of at least one of the transistors is electrically connected to a fifth signal line for transmitting the fifth signal.

4. The display device according to any one of claims 1 to 3, wherein The privacy layer comprises: a first electrode layer electrically connected to the privacy circuit to load the privacy signal; a second electrode layer for loading a common voltage signal; a liquid crystal layer located between the first electrode layer and the second electrode layer, and configured to deflect according to the common voltage signal and the privacy signal to control the viewing angle range of the display device.

5. A display device, characterized by comprising: The display device comprises: a display panel comprising a privacy circuit for generating a privacy signal; a privacy layer arranged on the light exit side of the display panel, the privacy layer being electrically connected to the privacy circuit, and the privacy layer being configured to control the viewing angle range of the display device according to the privacy signal; The anti-peep circuit includes a Schmitt trigger circuit, which is configured to process a reference voltage signal to obtain the anti-peep signal as a periodic signal. The display device includes: A power management chip configured to generate a second signal and a third signal included in the reference voltage signal, the second signal and the third signal being two constant voltage signals with different amplitudes. The Schmitt trigger circuit is configured to generate the anti-peep signal according to the second signal and the third signal. The power management chip is configured to supply power to the display panel, a timing control chip, and a source driving chip, the timing control chip is configured to drive the source driving chip and a gate driving circuit in the display panel, the gate driving circuit is configured to control a plurality of rows of sub-pixels in the display panel to be turned on in sequence, and the source driving chip is configured to transmit respective data signals to a plurality of columns of sub-pixels in the display panel.

6. The display device according to claim 5, wherein The Schmitt trigger circuit includes an operational amplifier, a resistive element, and a capacitive element electrically connected to the operational amplifier. The period of the anti-peep signal is determined by the resistive element and the capacitive element.

7. The display device according to claim 6, wherein The capacitive element is electrically connected between the inverting input terminal of the operational amplifier and the ground. The resistive element includes a second resistive element, a first resistive element, and a third resistive element, the second resistive element is electrically connected between the non-inverting input terminal of the operational amplifier and the ground, the first resistive element is electrically connected between the output terminal of the operational amplifier and the non-inverting input terminal of the operational amplifier, and the third resistive element is electrically connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier.

8. The display device according to claim 5, wherein The Schmitt trigger circuit includes a plurality of transistors, a second resistive element, a first resistive element, a third resistive element, and a capacitive element. The gates of at least two of the transistors are electrically connected between the second resistive element and the first resistive element, the gates of at least two of the transistors are electrically connected between the third resistive element and the capacitive element, and the second resistive element and the capacitive element are grounded.

9. The display device according to any one of claims 5 to 8, wherein The anti-peep layer includes: A first electrode layer electrically connected to the anti-peep circuit to load the anti-peep signal; A second electrode layer configured to load a common voltage signal; A liquid crystal layer located between the first electrode layer and the second electrode layer, configured to deflect according to the common voltage signal and the anti-peep signal to control the viewing angle range of the display device.

10. An electronic terminal, characterized in that The display device includes any one of claims 1 to 9.

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