A display panel driving apparatus and method

Abstract

Embodiments of the present application provide a display panel driving device and method, wherein the display panel driving device comprises a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors arranged in an array, and a gate driving circuit. Each thin film transistor is connected to a data line and a scan line. The gate driving circuit is connected to all or part of the scan lines and is configured to output gate driving signals based on N clock signals with phase differences to drive corresponding scan lines, thereby activating corresponding rows of thin film transistors. N is an integer greater than or equal to 2. The gate driving circuit is configured to output gate driving signals in a manner that each round of driving corresponding N rows of scan lines is based on N clock signals. In each round of driving, the scan lines driven by adjacent clock signals are mutually distant according to a preset rule. The technical solution of the embodiments of the present application balances the difference in pixel leakage between the near and far ends of the display panel by causing the scan lines driven by adjacent clock signals to be mutually distant according to a preset rule.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel driving device and method. BACKGROUND

[0002] With the rapid development of display technology, consumers' requirements for display quality are continuously improved, and in response to low-carbon green energy, low-frequency display panels gradually appear in the public eye. At present, low-frequency display panels have problems such as panel flicker and poor flicker consistency. SUMMARY

[0003] Embodiments of the present application provide a display panel driving device and method to solve or alleviate one or more technical problems in the prior art.

[0004] As an aspect of the embodiments of the present application, the embodiments of the present application provide a display panel driving device, comprising:

[0005] a plurality of scan lines for providing scan signals;

[0006] a plurality of data lines for providing data signals, the data lines being arranged perpendicularly to the scan lines;

[0007] a plurality of thin film transistors arranged in an array, each thin film transistor being connected to one data line and one scan line;

[0008] a gate drive circuit connected to all or part of the scan lines, configured to output gate drive signals based on N clock signals with phase difference respectively to drive corresponding scan lines, thereby activating corresponding rows of thin film transistors, N being an integer greater than or equal to 2;

[0009] wherein the gate drive circuit is configured to output the gate drive signals in a manner that each round of driving N rows of scan lines is based on N clock signals, and in each round of driving process, the scan lines driven by adjacent clock signals are mutually away according to a preset rule.

[0010] In an embodiment, the gate drive circuit comprises a first drive circuit and a second drive circuit.

[0011] The first drive circuit is configured to drive the scan lines of odd rows or even rows in a forward direction or a reverse direction.

[0012] The second drive circuit is configured to drive the scan lines of the remaining rows in a direction opposite to the first drive circuit.

[0013] wherein the first drive circuit and the second drive circuit drive corresponding scan lines alternately.

[0014] In an embodiment, the gate driving circuit has n rows, the N clock signals with phase difference include first clock, second clock, third clock and fourth clock which are sequentially adjacent in phase, wherein in the i-th scanning, the first driving circuit drives the 4i-3th row scanning line in the first clock, the second driving circuit drives the n-4i+4th row scanning line in the second clock, the first driving circuit drives the 4i-1th row scanning line in the third clock, and the second driving circuit drives the n-4i+2th row scanning line in the fourth clock.

[0015] In an embodiment, the gate driving circuit has n rows, the N clock signals with phase difference include first clock, second clock, third clock, fourth clock, fifth clock, sixth clock, seventh clock and eighth clock which are sequentially adjacent in phase, wherein in the i-th scanning, the first driving circuit drives the 8i-7th row scanning line in the first clock, the second driving circuit drives the n-8i+8th row scanning line in the second clock, the first driving circuit drives the 8i-5th row scanning line in the third clock, the second driving circuit drives the n-8i+6th row scanning line in the fourth clock, the first driving circuit drives the 8i-3th row scanning line in the fifth clock, the second driving circuit drives the n-8i+4th row scanning line in the sixth clock, the first driving circuit drives the 8i-1th row scanning line in the seventh clock, and the second driving circuit drives the n-8i+2th row scanning line in the eighth clock.

[0016] In an embodiment, the channel size of the thin film transistors in odd rows increases in order of row number, the channel size of the thin film transistors in even rows decreases in order of row number, and the channel size of the thin film transistors in the first row is consistent with the channel size of the thin film transistors in the last row.

[0017] In an embodiment, the display panel driving device further comprises:

[0018] The multiplexing circuit is connected with the multiplexer, the source driving circuit and all or part of the data lines, and is configured to output the data signal output by the source driving circuit to the corresponding data line under the control of the multiplexer.

[0019] The source driving circuit is configured to drive the corresponding data line to output the data signal.

[0020] In an embodiment, the multiplexing circuit corresponds to at least two columns of the thin film transistors, and the multiplexing circuit is further configured to apply a first voltage to the corresponding column of the thin film transistors in the positive frame and a second voltage to the corresponding column of the thin film transistors in the negative frame, so that the difference between the gate-source voltage corresponding to the corresponding column of the thin film transistors in the positive frame and the gate-source voltage corresponding to the corresponding column of the thin film transistors in the negative frame is not greater than a predetermined gate-source voltage difference.

[0021] As an aspect of the embodiments of the present application, the embodiments of the present application provide a display panel driving method, comprising:

[0022] The gate driving circuit is configured to output the gate driving signals in a manner that each round is based on N clock signals to drive corresponding N rows of scan lines, and in each round of driving process, the scan lines driven by adjacent clock signals are mutually away according to a preset rule.

[0023] In an embodiment, the gate driving circuit has n rows, and the N clock signals with phase difference include a first clock, a second clock, a third clock and a fourth clock with adjacent phases, wherein in the i-th round of scanning, the first clock drives the 4i-3-th row of scan lines, the second clock drives the n-4i+4-th row of scan lines, the third clock drives the 4i-1-th row of scan lines, and the fourth clock drives the n-4i+2-th row of scan lines.

[0024] In an embodiment, the gate driving circuit has n rows, and the N clock signals with phase difference include a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock and an eighth clock with adjacent phases, wherein in the i-th round of scanning, the first clock drives the 8i-7-th row of scan lines, the second clock drives the n-8i+8-th row of scan lines, the third clock drives the 8i-5-th row of scan lines, the fourth clock drives the n-8i+6-th row of scan lines, the fifth clock drives the 8i-3-th row of scan lines, the sixth clock drives the n-8i+4-th row of scan lines, the seventh clock drives the 8i-1-th row of scan lines, and the eighth clock drives the n-8i+2-th row of scan lines.

[0025] In an embodiment, the gate driving circuit has n rows, and the N clock signals with phase difference include a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock and an eighth clock with adjacent phases, wherein in the i-th round of scanning, the first clock drives the 8i-7-th row of scan lines, the second clock drives the n-8i+8-th row of scan lines, the third clock drives the 8i-5-th row of scan lines, the fourth clock drives the n-8i+6-th row of scan lines, the fifth clock drives the 8i-3-th row of scan lines, the sixth clock drives the n-8i+4-th row of scan lines, the seventh clock drives the 8i-1-th row of scan lines, and the eighth clock drives the n-8i+2-th row of scan lines.

[0026] As an aspect of the embodiments of the present application, the embodiments of the present application provide a display, comprising: the display comprises a display panel and a display panel driving device of the above aspect.

[0027] The above technical solution can balance the difference in pixel leakage between the near end and the far end of the display panel by making the scan lines driven by adjacent clock signals mutually away according to a preset rule.

[0028] The above summary is intended to illustrate, but not limit, the present application. Further aspects, implementations and features of the present application will be apparent from the detailed description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0029] In the drawings, like reference numerals refer to same or similar components throughout the several views. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the application. It should be understood that the drawings are merely depictions of some embodiments of the application and should not be construed as limiting the scope of the application.

[0030] Figure 1 A structural diagram of a display panel driving device according to an embodiment of the present application is shown;

[0031] Figure 2 A structural diagram of a display panel driving device according to an embodiment of the present application is shown;

[0032] Figure 3 A diagram showing the double-side alternating driving of scan lines by a gate driving circuit according to an embodiment of the present application is shown;

[0033] Figure 4 A diagram showing the double-side alternating driving of scan lines by 4 clock signals according to an embodiment of the present application is shown;

[0034] Figure 5 A diagram showing another double-side alternating driving of scan lines by 4 clock signals according to an embodiment of the present application is shown;

[0035] Figure 6 A diagram showing the double-side alternating driving of scan lines by 8 clock signals according to an embodiment of the present application is shown;

[0036] Figure 7 A diagram showing another double-side alternating driving of scan lines by 8 clock signals according to an embodiment of the present application is shown;

[0037] Figure 8 A diagram showing the charging phase and the discharging phase of thin film transistors of the first row according to an embodiment of the present application is shown;

[0038] Figure 9 A diagram showing the charging phase and the discharging phase of thin film transistors of the last row according to an embodiment of the present application is shown;

[0039] Figure 10 A structural diagram of a display panel driving device according to an embodiment of the present application is shown;

[0040] Figure 11 A structural diagram of a multiplexing circuit according to the prior art is shown;

[0041] Figure 12 A structural schematic diagram of a multiplexing circuit of an embodiment of the present application is shown.

[0042] Figure 13 A flow chart of a display panel driving method of an embodiment of the present application is shown.

[0043] Legend of reference numerals:

[0044] 100 - display panel driving apparatus; 101 - scan line; 102 - data line; 103 - thin film transistor; 104 - gate driving circuit; 105 - multiplexing circuit; 106 - source driving circuit; 801 - charging phase; 802 - discharging phase; VD - source voltage; VGH1 - gate high voltage; VGH2 - gate high voltage; VGS1 - gate-source voltage. DETAILED DESCRIPTION

[0045] In the following, only certain exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0046] Figure 1 A structural block diagram of a display panel driving apparatus of an embodiment of the present application is shown. Figure 2 A structural schematic diagram of a display panel driving apparatus of an embodiment of the present application is shown. Refer to Figure 1 and Figure 2 The display panel driving apparatus 100 comprises a plurality of scan lines (Gate Line) 101, a plurality of data lines (Data Line) 102, a plurality of thin film transistors (Thin Film Transistor, TFT) 103 and a gate driving circuit 104, wherein the scan lines 101 and the data lines 102 are arranged perpendicularly, the thin film transistors 103 are arranged in an array, each thin film transistor 103 is connected to one scan line 101 and one data line 102, and the gate driving circuit 104 is connected to all or part of the scan lines 101.

[0047] The scan lines 101 and the data lines 102 work together to complete charging of the thin film transistors 103, so as to change the voltage across the thin film transistors 103, which affects the degree of rotation of liquid crystal molecules in the thin film transistors 103, which affects the light transmittance, thereby controlling the display brightness of the thin film transistors 103.

[0048] The scan line 101 is configured to provide a scan signal. Specifically, the scan line 101 controls the opening and closing of the thin film transistor 103. When the voltage on the scan line 101 is high, the thin film transistor 103 connected thereto will open, thereby allowing the data signal on the data line 102 to pass to the electrode of the thin film transistor 103. The scan line 101 activates the corresponding thin film transistor 103 one by one in the order of rows, which means that only the thin film transistors 103 of one row are open at any given time, so as to ensure that the data signal transmitted on the data line 102 can be accurately written into all the thin film transistors 103 of the row.

[0049] The data line 102 is configured to provide a data signal. Specifically, the data line 102 is responsible for transmitting a data signal representing image color and brightness information. Each data line 102 corresponds to a column of thin film transistors 103, and the data signal carries the voltage information of all the thin film transistors 103 in the column. When the scan line 101 of a row activates the thin film transistor 103, the voltage transmitted on the data line 102 will be transmitted to the open thin film transistor 103, thereby charging the thin film transistor 103 and determining the brightness and color displayed by the thin film transistor 103.

[0050] The gate drive circuit 104 is configured to drive all or part of the scan lines 101 to scan to activate the corresponding row of thin film transistors 103 in a precise scan time sequence. The scan time sequence refers to the clock configuration for driving the scan line 101.

[0051] Specifically, the gate drive circuit 104 is configured to output a gate drive signal based on N clock signals with a phase difference to drive the corresponding scan line 101 to scan the corresponding row of thin film transistors 103, where N is an integer greater than or equal to 2.

[0052] Common clock configurations can include 4-clock, 8-clock, and more clock signal configurations. In one period, the more clock signals, the faster the driving speed, the higher the refresh rate and the frame rate, and the higher the hardware requirements. The appropriate clock configuration can be selected by comprehensively considering the hardware cost and performance requirements of the display panel.

[0053] Exemplarily, the gate driving circuit 104 adopts a 4-clock configuration, and the gate driving circuit 104 outputs gate driving signals based on four clock signals with phase difference to drive corresponding scan lines 101 to scan corresponding rows of thin film transistors 103. In the 4-clock configuration, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal correspond to the same waveform, and the phase sequence is different by one fourth. The gate driving circuit 104 adopts an 8-clock configuration, and the gate driving circuit 104 outputs gate driving signals based on eight clock signals with phase difference to drive corresponding scan lines 101 to scan corresponding rows of thin film transistors 103. The eight clock signals in the 8-clock configuration correspond to the same waveform, and the phase sequence is different by one eighth.

[0054] The gate driving circuit 104 is configured to output gate driving signals in a manner that each round of driving corresponding N rows of scan lines 101 is based on N clock signals, and in each round of driving, the scan lines 101 driven by adjacent clock signals are away from each other according to a preset rule.

[0055] In an embodiment, the gate driving circuit 104 drives the scan lines 101 in a manner of bilateral alternating driving, so as to realize that the scan lines 101 driven by adjacent clock signals are away from each other according to a preset rule. Specifically, the gate driving circuit 104 includes a first driving circuit and a second driving circuit, the first driving circuit is configured to drive the scan lines 101 of odd rows or even rows in a forward direction or a reverse direction, and the second driving circuit is configured to drive the scan lines 101 of the remaining rows in a direction opposite to the first driving circuit, wherein the first driving circuit and the second driving circuit alternately drive corresponding scan lines 101.

[0056] Optionally, the first driving circuit is configured to drive the scan lines 101 of odd rows in a forward direction, and the second driving circuit is configured to drive the scan lines 101 of even rows in a reverse direction.

[0057] Optionally, the first driving circuit is configured to drive the scan lines 101 of even rows in a forward direction, and the second driving circuit is configured to drive the scan lines 101 of odd rows in a reverse direction.

[0058] Optionally, the first driving circuit is configured to drive the scan lines 101 of odd rows in a reverse direction, and the second driving circuit is configured to drive the scan lines 101 of even rows in a forward direction.

[0059] Optionally, the first driving circuit is configured to drive the scan lines 101 of even rows in a reverse direction, and the second driving circuit is configured to drive the scan lines 101 of odd rows in a forward direction.

[0060] Figure 3 A schematic diagram of the bilateral alternating driving direction of the gate driving circuit 104 of the embodiment of the present application is shown. As shown in FIG. 2, the gate driving circuit 104 includes a first driving circuit and a second driving circuit. The first driving circuit is configured to drive the scan lines 101 of odd rows in a forward direction, and the second driving circuit is configured to drive the scan lines 101 of even rows in a reverse direction. Figure 3As shown, the gate drive circuit 104 drives the odd-numbered rows of scan lines 101 to scan forwardly, and drives the even-numbered rows of scan lines 101 to scan reversely, or, drives the even-numbered rows of scan lines 101 to scan forwardly, and drives the odd-numbered rows of scan lines 101 to scan reversely. Meanwhile, the gate drive circuit 104 also controls the odd-numbered rows of scan lines 101 and the even-numbered rows of scan lines 101 to scan alternately.

[0061] As an example, the case of driving the scan lines 101 by using 4 clock signals is described. The gate drive circuit 104 has n rows, and the 4 clock signals with phase difference include a first clock, a second clock, a third clock and a fourth clock, which are sequentially adjacent in phase. In the ith scanning round, the first drive circuit drives the 4i-3th row of scan lines 101 by using the first clock, the second drive circuit drives the n-4i+4th row of scan lines 101 by using the second clock, the first drive circuit drives the 4i-1th row of scan lines 101 by using the third clock, and the second drive circuit drives the n-4i+2th row of scan lines 101 by using the fourth clock, where i is a positive integer less than or equal to (n+3) / 4. If (n+3) / 4 is not an integer, in the last scanning round, some clock signals drive the scan lines 101. For example, if n is 17, in the last scanning round, only the first clock drives the corresponding scan lines 101, or, if n is 18, in the last scanning round, only the first clock and the second clock drive the corresponding scan lines 101.

[0062] Figure 4 A schematic diagram of driving the scan lines 101 by using 4 clock signals according to an embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, n is an even number, and the last driven scan line 101 is the 2th row of scan lines 101. The gate drive circuit 104 drives the scan lines 101 driven by the adjacent clock signals to move away from each other according to a preset rule. For example, in the first scanning round, the first drive circuit drives the 1th row of scan lines 101 by using the first clock, the second drive circuit drives the nth row of scan lines 101 far away from the 1th row by using the second clock, the first drive circuit drives the 3th row of scan lines 101 far away from the nth row by using the third clock, and the second drive circuit drives the n-2th row of scan lines 101 far away from the 3th row by using the fourth clock. The following 2th to the last scanning round are scanned according to the above rule. Figure 4

[0063] A schematic diagram of driving the scan lines 101 by using 4 clock signals according to another embodiment of the present application is shown in FIG. 5. As shown in FIG. 5, n is an even number, and the last driven scan line 101 is the 2th row of scan lines 101. The gate drive circuit 104 drives the scan lines 101 driven by the adjacent clock signals to move away from each other according to a preset rule. For example, in the first scanning round, the first drive circuit drives the 1th row of scan lines 101 by using the first clock, the second drive circuit drives the nth row of scan lines 101 far away from the 1th row by using the second clock, the first drive circuit drives the 3th row of scan lines 101 far away from the nth row by using the third clock, and the second drive circuit drives the n-2th row of scan lines 101 far away from the 3th row by using the fourth clock. The following 2th to the last scanning round are scanned according to the above rule. Figure 5 Figure 5 ​As shown, n is an odd number, the last driven scan line 101 is the nth row scan line 101, and the gate drive circuit 104 drives the scan lines 101 driven by adjacent clock signals away from each other according to a preset rule, for example, in the first round of scanning, the first drive circuit drives the first row of scan lines 101 at the first clock, the second drive circuit drives the nth-1 row of scan lines 101 away from the first row at the second clock, the first drive circuit drives the third row of scan lines 101 away from the nth-1 row at the third clock, and the second drive circuit drives the nth-3 row of scan lines 101 away from the third row at the fourth clock. The next round to the last round of scanning uses the above-mentioned rule to scan the corresponding scan lines 101.

[0064] As an example, the 8 clock signals are used to drive the scan lines 101 in a double-sided alternating manner. The gate drive circuit 104 has n rows, and the 8 clock signals with phase difference include first clock, second clock, third clock, fourth clock, fifth clock, sixth clock, seventh clock and eighth clock, wherein in the ith round of scanning, the first drive circuit drives the 8i-7 row of scan lines 101 at the first clock, the second drive circuit drives the nth-8i+8 row of scan lines 101 at the second clock, the first drive circuit drives the 8i-5 row of scan lines 101 at the third clock, the second drive circuit drives the nth-8i+6 row of scan lines 101 at the fourth clock, the first drive circuit drives the 8i-3 row of scan lines 101 at the fifth clock, the second drive circuit drives the nth-8i+4 row of scan lines 101 at the sixth clock, the first drive circuit drives the 8i-1 row of scan lines 101 at the seventh clock, and the second drive circuit drives the nth-8i+2 row of scan lines 101 at the eighth clock, i is a positive integer less than or equal to (n+7) / 8. If (n+7) / 8 is not an integer, in the last round of scanning, some clock signals drive the scan lines 101, for example, n is 17, in the last round of scanning, only the first clock drives the corresponding scan lines 101, or n is 60, in the last round of scanning, only the first clock, the second clock, the third clock and the fourth clock drive the corresponding scan lines 101.

[0065] Figure 6 A schematic diagram of the embodiment of the application is shown, which is used to drive the scan lines 101 in a double-sided alternating manner with 8 clock configurations. As shown in FIG. 6, the gate drive circuit 104 has n rows, and the 8 clock signals with phase difference include first clock, second clock, third clock, fourth clock, fifth clock, sixth clock, seventh clock and eighth clock, wherein in the ith round of scanning, the first drive circuit drives the 8i-7 row of scan lines 101 at the first clock, the second drive circuit drives the nth-8i+8 row of scan lines 101 at the second clock, the first drive circuit drives the 8i-5 row of scan lines 101 at the third clock, the second drive circuit drives the nth-8i+6 row of scan lines 101 at the fourth clock, the first drive circuit drives the 8i-3 row of scan lines 101 at the fifth clock, the second drive circuit drives the nth-8i+4 row of scan lines 101 at the sixth clock, the first drive circuit drives the 8i-1 row of scan lines 101 at the seventh clock, and the second drive circuit drives the nth-8i+2 row of scan lines 101 at the eighth clock, i is a positive integer less than or equal to (n+7) / 8. Figure 6As shown, n is even, the last driven scan line 101 is the second row scan line 101, the gate drive circuit 104 drives the scan lines 101 driven by adjacent clock signals away from each other according to a preset rule, for example, in the first round of scanning, the first drive circuit drives the first row of scan lines 101 at the first clock, the second drive circuit drives the nth row of scan lines 101 away from the first row at the second clock, the first drive circuit drives the third row of scan lines 101 away from the nth row at the third clock, the second drive circuit drives the n-2th row of scan lines 101 away from the third row at the fourth clock, the first drive circuit drives the fifth row of scan lines 101 away from the n-2th row at the fifth clock, the second drive circuit drives the n-4th row of scan lines 101 away from the fifth row at the sixth clock, the first drive circuit drives the seventh row of scan lines 101 away from the n-4th row at the seventh clock, the second drive circuit drives the n-6th row of scan lines 101 away from the seventh row at the eighth clock, and the next second round to the last round uses the above rule to scan the corresponding scan lines 101.

[0066] Figure 7 Another schematic diagram of the embodiment of the application is shown, which drives the number of scan lines 101 in two sides alternately with 8 clock signals. Figure 7 As shown, n is odd, the last driven scan line 101 is the nth row of scan lines 101, the gate drive circuit 104 drives the scan lines 101 driven by adjacent clock signals away from each other according to a preset rule, for example, the first drive circuit drives the first row of scan lines 101 at the first clock, the second drive circuit drives the n-1th row of scan lines 101 away from the first row at the second clock, the first drive circuit drives the third row of scan lines 101 away from the nth row at the third clock, the second drive circuit drives the n-3th row of scan lines 101 away from the third row at the fourth clock, the first drive circuit drives the fifth row of scan lines 101 away from the n-3th row at the fifth clock, the second drive circuit drives the n-6th row of scan lines 101 away from the fifth row at the sixth clock, the first drive circuit drives the seventh row of scan lines 101 away from the n-6th row at the seventh clock, the second drive circuit drives the n-8th row of scan lines 101 away from the seventh row at the eighth clock, and the next second round to the last round uses the above rule to scan the corresponding scan lines 101.

[0067] During the charging process of the thin-film transistor 103, the gate driving circuit 104 drives the scan line 101 to scan each row of thin-film transistors 103 according to a preset driving sequence. After the first row of thin-film transistors 103 scanned by the scan line 101 is fully charged, the source voltage does not flip for nearly one frame, maintaining the same polarity as the charging voltage of the thin-film transistor 103, thus resulting in less leakage. After the last row of thin-film transistors 103 scanned by the scan line 101 is fully charged, the source voltage briefly enters the blanking region after charging and then flips from a high source voltage to a low source voltage. The flipped voltage has the opposite polarity to the pixel voltage, thus resulting in more leakage.

[0068] Figure 8 This diagram illustrates the charging and leakage phases of the first row of thin-film transistors scanned according to an embodiment of this application. Figure 8 As shown, the charging phase 801 and the leakage phase 802 of the first row of thin film transistors 103 scanned are both within the positive frame range. The voltage range of the positive frame range is from the source high voltage to the drain voltage, and the voltage does not flip. Therefore, the leakage of the first row of thin film transistors 103 scanned is less in the leakage phase 802.

[0069] Figure 9 This diagram illustrates the charging and leakage phases of the last scanned row of thin-film transistors in an embodiment of this application. Figure 9 As shown, the charging phase 801 of the last row of thin-film transistors 103 being scanned is located at the end of the positive frame, and the leakage phase 802 is within the negative frame range. After the last row of thin-film transistors 103 is charged, it immediately enters the negative frame, and the voltage flips. Therefore, the last row of thin-film transistors 103 being scanned has more leakage in the leakage phase 802.

[0070] In current display panels, the scanning line 101 is driven unidirectionally, that is, from top to bottom or from bottom to top. Taking the scanning line 101 driven in the order of top to bottom as an example, the first row of the display panel is the first row of thin film transistors 103 to be scanned, and the last row is the last row of thin film transistors 103 to be scanned. As a result, the leakage of thin film transistors 103 in each row from top to bottom becomes more and more serious. The more leakage there is, the lower the brightness of the thin film transistors 103, thus causing the display panel to flicker.

[0071] The gate driving circuit 104 drives the scan lines 101 in a bilateral alternating driving manner, thereby charging the thin-film transistors 103. Bilateral alternating driving means that the scan lines of odd-numbered rows and even-numbered rows alternately drive the corresponding two rows of thin-film transistors 103 in reverse. Bilateral alternating driving causes the rows of thin-film transistors 103 with more leakage current and the rows with less leakage current to be arranged alternately, so that the difference between the sum of the charges of the storage capacitors corresponding to each pair of adjacent rows of thin-film transistors 103 and the sum of the charges of the storage capacitors corresponding to each pair of adjacent rows of thin-film transistors 103 is controlled within a preset range. Due to visual persistence, the alternating arrangement of the rows of thin-film transistors 103 with more leakage current and the rows of thin-film transistors 103 with less leakage current will make the overall brightness of the display screen more uniform.

[0072] by Figure 4 For example, the thin-film transistor 103 of G1 completes charging first with the least leakage, the thin-film transistor 103 of G2 completes charging last with the most leakage, the thin-film transistor 103 of Gn-1 completes charging second to last with slightly better leakage than the second row, and the thin-film transistor 103 of Gn completes charging after G1 with slightly worse leakage than G1. Therefore, the sum of the charges of the storage capacitors corresponding to the thin-film transistors 103 of G1 and G2 is close to the sum of the charges of the storage capacitors corresponding to the thin-film transistors 103 of Gn-1 and Gn, and the difference between the two is controlled within a preset range.

[0073] In one embodiment, the gate driving circuit 104 drives the scan lines 101 in a reverse dual-drive manner, thereby causing the scan lines 101 driven by adjacent clock signals to move away from each other according to a preset rule. Specifically, the gate driving circuit 104 includes a first driving circuit and a second driving circuit. The first driving circuit is used to drive the scan lines 101 of odd or even rows in a forward or reverse direction, and the second driving circuit is used to drive the scan lines 101 of the remaining rows in the opposite direction to the first driving circuit. The first driving circuit and the second driving circuit use the same clock configuration and start driving the corresponding scan lines 101 simultaneously. Using a dual-drive configuration to drive the scan lines 101 can speed up the overall response speed of the display panel and improve the refresh rate of the display panel.

[0074] In one embodiment, the gate driving circuit 104 may also employ other preset rules to keep the scan lines driven by adjacent clock signals away from each other. For example, in two adjacent scan cycles, the gate driving circuit 104 drives the scan line 101 with odd position numbers and the scan line 101 with even position numbers, respectively.

[0075] Optionally, the gate drive circuit 104 has n rows, and the 4 clock signals with phase difference include first clock, second clock, third clock and fourth clock in turn with adjacent phase, wherein in the i-th scanning, if i is odd, the gate drive circuit 104 drives the 2i-1-th row scanning line 101 in the first clock, the n-2i+2-th row scanning line 101 in the second clock, the 2i+1-th row scanning line 101 in the third clock, and the n-2i-th row scanning line 101 in the fourth clock; if i is even, the gate drive circuit 104 drives the n-2i+1-th row scanning line 101 in the first clock, the 2i-th row scanning line 101 in the second clock, the n-2i+3-th row scanning line 101 in the third clock, and the 2i-2-th row scanning line 101 in the fourth clock.

[0076] Optionally, the gate drive circuit 104 has n rows, and the 8 clock signals with phase difference include first clock, second clock, third clock, fourth clock, fifth clock, sixth clock, seventh clock and eighth clock in turn with adjacent phase, wherein in the i-th scanning, if i is odd, the gate drive circuit 104 drives the 4i-3-th row scanning line 101 in the first clock, the n-4i+4-th row scanning line 101 in the second clock, the 4i-1-th row scanning line 101 in the third clock, the n-4i+2-th row scanning line 101 in the fourth clock, the 4i+1-th row scanning line 101 in the fifth clock, the n-4i-th row scanning line 101 in the sixth clock, the 4i+3-th row scanning line 101 in the seventh clock, and the n-4i-2-th row scanning line 101 in the eighth clock; if i is even, the gate drive circuit 104 drives the n-4i+1-th row scanning line 101 in the first clock, the 4i-th row scanning line 101 in the second clock, the n-4i+3-th row scanning line 101 in the third clock, the 4i-2-th row scanning line 101 in the fourth clock, the n-4i+5-th row scanning line 101 in the fifth clock, the 4i-4-th row scanning line 101 in the sixth clock, the n-4i+7-th row scanning line 101 in the seventh clock, and the 4i-6-th row scanning line 101 in the eighth clock.

[0077] The gate drive circuit 104 adopts the above preset rule, and the scanning lines driven by the adjacent clock signals are far away from each other, so that the overall brightness of the display panel is relatively uniform.

[0078] In an embodiment, since the size of the thin film transistor 103 affects the leakage of the thin film transistor 103, the larger the size, the less the leakage, and the smaller the size, the more the leakage, therefore, according to the scanning sequence of the thin film transistor 103, that is, the driving sequence of the scanning line 101 corresponding to the thin film transistor 103, the thin film transistor 103 of corresponding size is configured to each row of scanning line 101 in the display panel. The size of the thin film transistor 103 corresponding to the scanning line 101 with earlier driving sequence is smaller, and the size of the thin film transistor 103 corresponding to the scanning line 101 with later driving sequence is larger.

[0079] When the scanning line 101 is driven in the way of double-side alternating driving or reverse double driving, the size of the thin film transistor 103 of the odd-numbered row increases in the order of row number, the size of the thin film transistor 103 of the even-numbered row decreases in the order of row number, and the size of the thin film transistor 103 of the first row is consistent with the size of the thin film transistor 103 of the last row. By determining the size of the thin film transistor 103 according to the driving sequence, the difference in leakage caused by different driving sequences can be reduced, and the overall brightness of the display panel is more uniform. In addition, when the scanning line 101 is driven in the way of double-side alternating driving or reverse double driving, the difference in leakage between adjacent odd-numbered rows and even-numbered rows is reduced, and the horizontal stripe defect caused by the large difference in leakage between adjacent rows is reduced.

[0080] In an embodiment, the display panel driving device 100 further comprises a multiplexing circuit 105 and a source driving circuit 106.

[0081] Figure 10 A structure schematic diagram of a display panel driving device according to an embodiment of the present application is shown. As shown in the figure, the display panel driving device 100 comprises, in addition to the scanning line 101, the data line 102, the thin film transistor 103 and the gate driving circuit 104, a multiplexing circuit 105 and a source driving circuit 106. Figure 10

[0082] The multiplexing circuit 105 is connected with the multiplexer, the source driving circuit 106 and all or part of the data line respectively, and is used to output the data signal output by the source driving circuit to the corresponding data line under the control of the multiplexer.

[0083] The source driving circuit 106 is used to drive the data signal output by the corresponding data line.

[0084] The multiplexer (MUX) is a common digital electronic circuit, which functions to select one or several signals from multiple input signals and output the selected signal. The multiplexer can select 1:2 MUX, 1:3 MUX or 1:6 MUX, etc. The following takes the multiplexer as an example of 1:2 MUX. ​

[0085] In one embodiment, the multiplexing circuit 105 corresponds to at least two columns of thin-film transistors 103. The multiplexing circuit 105 is further configured to apply a first voltage to the thin-film transistors 103 in the column corresponding to the positive frame and a second voltage to the thin-film transistors 103 in the column corresponding to the negative frame, so that the difference between the gate-source voltage corresponding to the thin-film transistors 103 in the column corresponding to the positive frame and the gate-source voltage corresponding to the thin-film transistors 103 in the column corresponding to the negative frame is not greater than a predetermined gate-source voltage difference.

[0086] Figure 11 A schematic diagram of a prior art multiplexing circuit is shown. For example... Figure 11 As shown, assuming that in the multiplexing circuit 105, in the first frame, the gate high voltage VGH1 and VGH2 of the MUX signal are 16V, the source voltage of the MUX signal on one data line 102 is the source high voltage VD1 = 5V, and the source voltage of the MUX signal on another data line 102 adjacent to this data line 102 is the source low voltage VD2 = -5V, then the two input signals of the MUX are the gate-source voltages VGS1 = VGH1 - VD1 = 11V and VGS2 = VGH2 - VD2 = 21V. The inconsistency between VGS1 and VGS2 will cause a difference in the charging rate between the adjacent odd-numbered thin-film transistors 103 and the even-numbered thin-film transistors 103, resulting in flicker. After jumping to the second frame, the gate voltage of the MUX signal remains unchanged, while the source voltage flips. At this time, VD1 = -5V and VD2 = 5V. The two input signals of the MUX are the gate-source voltages VGS1 = VGH1 - VD1 = 21V and VGS2 = VGH2 - VD2 = 11V, respectively. The different gate-source voltages corresponding to the positive and negative frames cause only the positive or negative frame to be charged, resulting in a difference in brightness between adjacent frames and a worse flicker.

[0087] Figure 12 A schematic diagram of the multiplexing circuit according to an embodiment of the present invention is shown. Figure 12As shown, in the first frame, the multiplexing circuit 105 in the embodiment of the present application adjusts the gate high voltage of the MUX signal to make VGH1=6V and VGH2=16V, the source voltage of the MUX signal on one data line 102 is the source high voltage VD1=5V, the source voltage of the MUX signal on another data line 102 adjacent to the data line 102 is the source low voltage VD2=-5V, then the two input signals of the MUX are gate-source voltages VGS1=VGH1-VD1=11V and VGS2=VGH2-VD2=11V respectively, VGS1 is consistent with VGS2, then the charging rates of the thin film transistors 103 in the adjacent odd columns and the thin film transistors 103 in the even columns are consistent, and the picture brightness is relatively uniform. After jumping to the second frame, the gate high voltage of the MUX signal is adjusted to make VGH1=16V and VGH2=6V, and after entering the adjacent frame, the source voltage is flipped, VD1=-5V and VD2=5V, then the two input signals of the MUX are gate-source voltages VGS1=VGH1-VD1=11V and VGS2=VGH2-VD2=11V respectively, the gate voltage is adjusted to keep the corresponding gate-source voltage unchanged, so that the picture brightness of the positive frame and the negative frame is different, and the Flicker is optimized.

[0088] The display panel driving device in the embodiment of the present application can be used for a low-frequency display panel, while reducing the energy consumption of the display panel, the gate driving sequence is set, such as double-side alternating driving, the leakage difference of the far-end thin film transistor of the display panel is balanced, the panel flicker problem that may occur in the low-frequency display panel is solved, in addition, the thin film transistor of the corresponding size is configured according to the driving sequence, the panel flicker can also be avoided, the horizontal stripe defect caused by the double-side driving can also be avoided, the gate voltage is adjusted by adjusting the circuit signal of the MUX, and then the charging difference of the thin film transistors in the odd rows and the even rows in one frame is reduced, and the charging difference of the thin film transistors in the same row in adjacent frames is reduced, and the Flicker is optimized.

[0089] The display panel driving device in the embodiment of the present application includes a plurality of data lines, a plurality of scan lines, a plurality of thin film transistors arranged in an array, and a gate driving circuit, each thin film transistor is connected to one data line and one scan line, the gate driving circuit is connected to all or part of the scan lines, and is configured to output gate driving signals based on N clock signals with phase difference to drive corresponding scan lines to scan corresponding rows of thin film transistors, N is an integer greater than or equal to 2, and the gate driving circuit is configured to output the gate driving signals in a manner that each round of driving corresponds to N rows of scan lines based on the N clock signals, and in each round of driving, the scan lines driven by adjacent clock signals are away from each other according to a preset rule. The technical scheme of the embodiment of the present application balances the leakage difference of the pixels at the near and far ends of the display panel by making the scan lines driven by adjacent clock signals away from each other according to a preset rule.

[0090] Figure 13 A flow chart of a display panel driving method of an embodiment of the present application is shown. As shown in the figure, the display panel driving method comprises: Figure 13

[0091] Step S1301: outputting gate driving signals based on N clock signals with phase difference respectively to drive corresponding scan lines.

[0092] Step S1302: activating the thin film transistors of the corresponding row.

[0093] wherein N is an integer greater than or equal to 2, each thin film transistor is connected to a data line and a scan line, the gate driving circuit is configured to output gate driving signals in a manner that each round is based on N clock signals to drive corresponding N rows of scan lines, and in each round of driving process, the scan lines driven by adjacent clock signals are mutually away according to a preset rule.

[0094] It is worth noting that the concepts and purposes of the words in the method of the embodiments of the present application are as described in the above-mentioned embodiments of the display panel driving device, which will not be repeated here.

[0095] In an embodiment, the scan lines 101 are driven in a double-sided alternating driving manner. For example, the first odd row is driven in a forward direction, the last even row is driven in a reverse direction, the second odd row is driven in a forward direction, the second last even row is driven in a reverse direction, and so on, until all scan lines 101 are driven.

[0096] For example, the gate driving circuit has n rows, and N is 4, so the clock signals with phase difference include first clock, second clock, third clock and fourth clock with adjacent phases. Step S1301 is specifically: in the i-th round of scanning, the 4i-3 row scan line is driven by the first clock, the n-4i+4 row scan line is driven by the second clock, the 4i-1 row scan line is driven by the third clock, and the n-4i+2 row scan line is driven by the fourth clock.

[0097] For example, the gate driving circuit has n rows, and N is 8, so the clock signals with phase difference include first clock, second clock, third clock, fourth clock, fifth clock, sixth clock, seventh clock and eighth clock with adjacent phases. Step S1301 is specifically: in the i-th round of scanning, the 8i-7 row scan line is driven by the first clock, the n-8i+8 row scan line is driven by the second clock, the 8i-5 row scan line is driven by the third clock, the n-8i+6 row scan line is driven by the fourth clock, the 8i-3 row scan line is driven by the fifth clock, the n-8i+4 row scan line is driven by the sixth clock, the 8i-1 row scan line is driven by the seventh clock, and the n-8i+2 row scan line is driven by the eighth clock. ​

[0098] In an embodiment, the scan lines 101 are driven in a reverse double drive manner. For example, the first odd-numbered rows are driven forwardly and the last even-numbered rows are driven reversely, then the second odd-numbered rows are driven forwardly and the second last even-numbered rows are driven reversely, and so on until all the scan lines 101 are driven.

[0099] In an embodiment, other preset rules can also be used to make the scan lines driven by the adjacent clock signals move away from each other.

[0100] For example, the gate drive circuit has n rows, and N is 4, the clock signals with phase difference include a first clock, a second clock, a third clock and a fourth clock with adjacent phases. The step S1301 is specifically: in the i-th round of scanning, if i is odd, the gate drive circuit 104 drives the (2i-1)-th row of scan lines 101 in the first clock, drives the (n-2i+2)-th row of scan lines 101 in the second clock, drives the (2i+1)-th row of scan lines 101 in the third clock, and drives the (n-2i)-th row of scan lines 101 in the fourth clock; if i is even, the gate drive circuit 104 drives the (n-2i+1)-th row of scan lines 101 in the first clock, drives the (2i)-th row of scan lines 101 in the second clock, drives the (n-2i+3)-th row of scan lines 101 in the third clock, and drives the (2i-2)-th row of scan lines 101 in the fourth clock.

[0101] For example, the gate drive circuit has n rows, and N is 8, the clock signals with phase difference include a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock and an eighth clock with adjacent phases. The step S1301 is specifically: in the i-th round of scanning, if i is odd, the gate drive circuit 104 drives the (4i-3)-th row of scan lines 101 in the first clock, drives the (n-4i+4)-th row of scan lines 101 in the second clock, drives the (4i-1)-th row of scan lines 101 in the third clock, drives the (n-4i+2)-th row of scan lines 101 in the fourth clock, drives the (4i+1)-th row of scan lines 101 in the fifth clock, drives the (n-4i)-th row of scan lines 101 in the sixth clock, drives the (4i+3)-th row of scan lines 101 in the seventh clock, and drives the (n-4i-2)-th row of scan lines 101 in the eighth clock; if i is even, the gate drive circuit 104 drives the (n-4i+1)-th row of scan lines 101 in the first clock, drives the (4i)-th row of scan lines 101 in the second clock, drives the (n-4i+3)-th row of scan lines 101 in the third clock, drives the (4i-2)-th row of scan lines 101 in the fourth clock, drives the (n-4i+5)-th row of scan lines 101 in the fifth clock, drives the (4i-4)-th row of scan lines 101 in the sixth clock, drives the (n-4i+7)-th row of scan lines 101 in the seventh clock, and drives the (4i-6)-th row of scan lines 101 in the eighth clock.

[0102] The display panel driving method in the embodiments of the present application drives the scan lines according to the preset rule that the scan lines driven by adjacent clock signals are far away from each other, so that the thin film transistor 103 rows with high leakage current and the thin film transistor 103 rows with low leakage current are arranged in a staggered manner, and thus the overall brightness of the display panel is relatively uniform.

[0103] The embodiments of the present application also provide a display. The display comprises a display panel and a display panel driving device as any of the above embodiments. The display panel driving device can comprise a communication interface for communicating with a processor or an external device to perform data interaction transmission. The display panel driving device can comprise a memory and a processor, and the memory stores instructions executable on the processor. The processor executes the instructions to implement the display panel driving method in the above embodiments. The number of the memory and the processor can be one or more.

[0104] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It should be noted that the processor can be a processor supporting an advanced RISC machine (ARM) architecture.

[0105] Optionally, the memory can include a program storage area and a data storage area, wherein the program storage area can store an operating system and application programs required by at least one function; and the data storage area can store data created according to the use of the display panel driving device, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely arranged relative to the processor, and these remote memories can be connected to the control device through a network. Examples of the network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0106] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "central", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0107] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0108] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection, or communication; it can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0109] In the present application, unless otherwise explicitly specified and limited, the first feature "above" or "below" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "above", "above" and "above" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0110] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. The above drawings are merely illustrative of the processes included in the method according to exemplary embodiments of this application and are not intended to be limiting. It is readily understood that the processes shown in the above drawings do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be performed synchronously or asynchronously in multiple modules, for example.

[0111] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0112] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel driving device, characterized in that, The display panel driving device includes: Multiple scan lines providing scan signals; Multiple data lines providing data signals are arranged perpendicularly to the scan lines; Multiple thin-film transistors arranged in an array, each of the thin-film transistors being connected to a data line and a scan line; A gate driving circuit, connected to all or part of the scan lines, is used to output gate driving signals based on N clock signals with phase differences to drive the corresponding scan lines, thereby activating the thin-film transistors of the corresponding rows, where N is an integer greater than or equal to 2. The gate driving circuit is configured to output the gate driving signal in each round by driving N rows of scan lines based on N clock signals. In each round of driving, the scan lines driven by adjacent clock signals move away from each other according to a preset rule.

2. The display panel driving device according to claim 1, characterized in that, The gate driving circuit includes a first driving circuit and a second driving circuit. The first driving circuit is used to drive the scan lines of odd or even rows in either the forward or reverse direction. The second driving circuit is used to drive the scan lines of the remaining rows in the opposite direction to that of the first driving circuit; The first driving circuit and the second driving circuit alternately drive the corresponding scan lines.

3. The display panel driving device according to claim 2, characterized in that, The gate driving circuit has n rows, and the N clock signals with phase differences include a first clock, a second clock, a third clock, and a fourth clock with sequentially adjacent phases. In the i-th scan round, the first driving circuit drives the 4i-3 scan line in the first clock, the second driving circuit drives the n-4i+4 scan line in the second clock, the first driving circuit drives the 4i-1 scan line in the third clock, and the second driving circuit drives the n-4i+2 scan line in the fourth clock.

4. The display panel driving device according to claim 2, characterized in that, The gate driving circuit has n rows, and the N clock signals with phase differences include a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock, and an eighth clock with sequentially adjacent phases. In the i-th scan round, the first driving circuit drives the 8i-7th scan line at the first clock, the second driving circuit drives the (n-8i+8)th scan line at the second clock, the first driving circuit drives the 8i-5th scan line at the third clock, the second driving circuit drives the (n-8i+6)th scan line at the fourth clock, the first driving circuit drives the 8i-3rd scan line at the fifth clock, the second driving circuit drives the (n-8i+4)th scan line at the sixth clock, the first driving circuit drives the 8i-1st scan line at the seventh clock, and the second driving circuit drives the (n-8i+2)th scan line at the eighth clock.

5. The display panel driving device according to claim 1, characterized in that, The body size of the thin-film transistors in odd-numbered rows increases sequentially according to the row number, while the body size of the thin-film transistors in even-numbered rows decreases sequentially according to the row number. The body size of the thin-film transistors in the first row is the same as that in the last row.

6. The display panel driving device according to claim 1, characterized in that, The display panel driving device further includes: A multiplexing circuit is connected to a multiplexer, a source drive circuit, and all or part of the data lines, respectively, and is used to output the data signal output by the source drive circuit to the corresponding data line under the control of the multiplexer; The source drive circuit is used to drive the corresponding data line to output the data signal.

7. The display panel driving device according to claim 6, characterized in that, The multiplexing circuit corresponds to at least two columns of the thin-film transistors. The multiplexing circuit is further configured to apply a first voltage to the thin-film transistors in the column corresponding to the positive frame and a second voltage to the thin-film transistors in the column corresponding to the negative frame, so that the difference between the gate-source voltage corresponding to the thin-film transistors in the column corresponding to the positive frame and the gate-source voltage corresponding to the thin-film transistors in the column corresponding to the negative frame is not greater than a predetermined gate-source voltage difference.

8. A display panel driving method, characterized in that, The display panel driving method includes: Based on N clock signals with phase differences, gate drive signals are output to drive the corresponding scan lines, thereby activating the thin-film transistors in the corresponding rows. N is an integer greater than or equal to 2. Each thin-film transistor is connected to a data line and a scan line. The gate driving circuit is configured to output the gate driving signal in each round based on N clock signals driving N rows of scan lines. In each round of driving, the scan lines driven by adjacent clock signals move away from each other according to a preset rule.

9. The display panel driving method according to claim 8, characterized in that, The gate driving circuit has n rows, and the N clock signals with phase differences include a first clock, a second clock, a third clock, and a fourth clock with sequentially adjacent phases. In the i-th scan, the first clock drives the 4i-3 scan line, the second clock drives the n-4i+4 scan line, the third clock drives the 4i-1 scan line, and the fourth clock drives the n-4i+2 scan line.

10. The display panel driving method according to claim 8, characterized in that, The gate driving circuit has n rows, and the N clock signals with phase differences include a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock, and an eighth clock with sequentially adjacent phases. In the i-th scan round, the first clock drives the scan line of row 8i-7, the second clock drives the scan line of row n-8i+8, the third clock drives the scan line of row 8i-5, the fourth clock drives the scan line of row n-8i+6, the fifth clock drives the scan line of row 8i-3, the sixth clock drives the scan line of row n-8i+4, the seventh clock drives the scan line of row 8i-1, and the eighth clock drives the scan line of row n-8i+2.

11. A display, characterized in that, The display includes a display panel and a display panel driving device according to any one of claims 1-7.

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