Electronic bias control signals for electronically enhanced material processing

Abstract

A system and method for material processing using wafer-level waves of precisely controlled electrons in a DC plasma is presented. The surface floating potential of a substrate placed on top of a stage in a positive column of a DC plasma is adjusted and maintained as a reference potential. A periodic bias signal referenced to the reference potential is capacitively coupled to the stage to control the surface potential at the substrate according to: an activation phase for providing kinetic energy to free electrons in the DC plasma to activate target bonds at the surface of the substrate; a neutralization phase for repelling free electrons from the surface of the substrate; and an initialization phase for restoring the initial condition of the surface floating potential.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 17 / 668,301, filed on February 9, 2022, entitled “Electron Bias Control Signals for Electron Enhanced Material Processing”, and the entire contents of the U.S. Application are incorporated herein by reference. In addition, this application is related to U.S. Application No. 17,524,330, filed on November 11, 2021, entitled “DC Plasma Control for Electron Enhanced Material Processing” (Agent Docket No. P2641-US), the entire contents of the disclosure of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to systems and methods for controlling free electrons in a DC plasma reaction chamber for materials processing, and in particular, for generating waveforms for biasing signals to control the kinetic energy of the free electrons to produce precisely controlled wafer-level waves of electrons in a DC plasma at room temperature (or other temperatures if desired). Background Art

[0004] The manufacture of, for example, integrated circuits may include processing a corresponding substrate within a (direct current) DC plasma reaction chamber, wherein electrons and / or ions are accelerated toward a substrate surface to initiate a reaction that physically transforms the substrate surface. In some cases, and primarily due to the relatively small mass of electrons compared to ions, it may be preferred to perform substrate processing via electrons in order to reduce any damage to the substrate surface beyond the intended targeted physical changes of the processing step itself.

[0005] In some cases, plasma processing may include arranging the substrate in a region of a DC plasma reaction chamber, and therefore the precise value of the floating potential of the substrate surface is not known. Therefore, any externally applied bias signal to the substrate may impart energies to free electrons in a region of the plasma close to the substrate surface that may not be related to the electron energy threshold / energy level of the (atomic) material present at the substrate surface.

[0006] The above-referenced U.S. Application No. 17,524,330, the disclosure of which is hereby incorporated in its entirety, describes methods and systems for precisely and selectively controlling the value of a substrate's surface floating potential, and thus enabling precise and selective control of the energy levels of atoms at the substrate surface. Such precise and selective control of the energy levels of atoms at the substrate surface is utilized in accordance with the teachings of the present disclosure to generate a waveform of corresponding timing and amplitude for a signal used to bias free electrons in a DC plasma chamber, such that a wafer-level wave of electrons is generated that is specifically targeted to the energy levels of atoms at the substrate surface. Summary of the invention

[0007] Systems and methods are presented for material processing at room temperature (or other temperatures where desired) using wafer-scale waves of precisely controlled electrons in a DC plasma. In the present disclosure, such material processing is referred to as electron-enhanced material processing (EEMP), which enables the kinetic energy of free electrons in a DC plasma to be precisely controlled to target (and selectively target) the energy levels of electrons of atoms at the surface of the substrate being processed.

[0008] According to a first embodiment of the present disclosure, a direct current (DC) plasma system for processing a substrate is proposed, comprising: a DC plasma reaction chamber, the DC plasma reaction chamber being configured to accommodate a DC plasma generated between an anode and a cathode of the DC plasma reaction chamber; a substrate support table, the substrate support table being arranged in a region of a positive column of the DC plasma reaction chamber accommodating the DC plasma, a device for presetting a floating potential at a surface of the substrate support table as a reference potential; and a bias signal generator capacitively coupled to the substrate support table, the bias signal generator being configured to generate a periodic bias signal having a voltage referenced to the reference potential, the periodic bias signal comprising: an activation phase having a positive voltage; a neutralization phase having a negative voltage; and an initialization phase having a zero voltage.

[0009] According to a second embodiment of the present disclosure, a method for processing a surface of a substrate is proposed, the method comprising: placing a substrate on a support table in a region of a DC plasma reaction chamber configured to generate a positive column of DC plasma; generating DC plasma; presetting a floating potential at the surface of the substrate as a reference potential; and capacitively coupling a periodic bias signal having a bias voltage to the support table, the bias voltage being referenced to the floating potential, the periodic bias signal comprising: an activation phase having a positive voltage based on a known reaction threshold voltage of a target chemical bond composed of electrons of atoms at the surface of the substrate; a neutralization phase having a negative voltage; and an initialization phase having a zero voltage.

[0010] Other aspects of the disclosure are shown in the description, drawings, and claims of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of the example embodiments, serve to explain the principles and implementations of the present disclosure.

[0012] Figure 1A A simplified schematic diagram of a DC plasma reaction chamber that may be used in a DC plasma processing system is shown.

[0013] Figure 1B Shown in Figure 1A A graph showing the change in the (electric) potential of the plasma during operation of a DC plasma reaction chamber.

[0014] Figure 1C Shown included in Figure 1A Simplified schematic diagram of a DC plasma processing system with a (substrate) table arranged in the area of ​​a DC plasma reaction chamber.

[0015] Figure 1D shows the bias signal generated by an external Figure 1C Figure 2. Example biasing of a stage of a DC plasma processing system.

[0016] Figure 1E Shown by Figure 1D 1 and 2. An exemplary bias signal generated by an external bias signal generator and a corresponding potential generated at the surface of the stage.

[0017] Figure 1F Example performance levels of atoms at the surface of a table are shown.

[0018] Figure 2A A simplified schematic diagram of a DC plasma processing system including an apparatus for controlling the surface potential of a console according to an embodiment of the present disclosure is shown.

[0019] Figure 2B Shown for Figure 2A Graphical representation of the control of the surface potential of the stage by a DC plasma processing system.

[0020] Figure 2C Shown for Figure 2A A graph showing a DC plasma processing system adjusting the surface potential of a stage to a reference ground potential.

[0021] Figure 3A A simplified schematic diagram of a DC plasma processing system including means for controlling the surface potential of a console and means for measuring the surface potential is shown according to an embodiment of the present disclosure.

[0022] Figure 3B A method based on a device for automatically controlling surface potential according to an embodiment of the present disclosure is shown. Figure 3A A simplified schematic diagram of a DC plasma processing system of the system.

[0023] Figure 4A A method based on a method in which a device for biasing a stage is added according to an embodiment of the present disclosure is shown. Figure 3B A simplified schematic diagram of a DC plasma processing system of the system.

[0024] Figure 4B Shows the Figure 4A 0026] An exemplary bias signal provided to a stage of a DC plasma processing system and a corresponding potential generated at the surface of the stage.

[0025] Figure 4C Example performance levels of atoms at the surface of a table are shown.

[0026] Figure 5 is a flow chart illustrating various steps of a method for treating a surface of a substrate according to an embodiment of the present disclosure.

[0027] FIG. 6A to FIG. 6C Shown is a graph representing reaction rates of electronically enhanced material processing (EEMP) according to the present disclosure for different materials.

[0028] FIG. 7A to FIG. 7C Graphs representing waveforms of EEMP bias signals according to some exemplary embodiments of the present disclosure for processing different materials are shown.

[0029] Fig. 8A A graph representing an idealized waveform of an EEMP bias signal is shown.

[0030] Figure 8BA graph representing the actual waveform of the EEMP bias signal is shown.

[0031] Figure 8C A graph representing a simulated waveform under capacitive load conditions is shown.

[0032] Fig.9A shows the representation used to generate Figure 8B Graph of a digitized waveform of an actual waveform, and a graph of a corresponding digitized waveform with predistortion.

[0033] Fig. 9B shows the capacitive load condition from Fig. 9A A graph of a simulated waveform generated from a digitized waveform with predistortion.

[0034] Fig. 10A A graph representing gain versus frequency for a band-limited linear power amplifier according to an embodiment of the present disclosure and a graph representing gain versus frequency for a conventional power amplifier are shown.

[0035] Fig. 10B shows the capacitive load condition through Fig. 10A The band-limited linear power amplifier from Fig. 9A A graph of a simulated waveform generated from a digitized waveform with predistortion.

[0036] Fig.11 is a flow chart illustrating various steps of a method for treating a surface of a substrate according to another embodiment of the present disclosure.

[0037] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0038] Figure 1A A simplified schematic diagram of a prior art (direct current) DC plasma reaction chamber (110) that can be used in a DC plasma processing system is shown. The bias of the DC plasma reaction chamber (110) can be provided by a DC voltage source (150) coupled between an anode A and a cathode C of the DC plasma reaction chamber (110). During operation, a glow discharge (plasma) can be formed in the chamber (110) based on the interaction of the electrons of the gas and current flowing between the anode A and the cathode C. This in turn produces free ions and electrons in the chamber (110). The operating principles of such a DC plasma reaction chamber (110) are known to those skilled in the art, and therefore the relevant details are omitted in the present disclosure.

[0039] like Figure 1AAs shown, the glow discharge formed in the chamber (110) may include glow regions (G1, G2, G3, G4) that emit significant light and dark regions (D1, D2, D3, D4) that may not emit light. Such regions may represent different operating characteristics of the DC plasma reaction chamber (110), including, for example, temperature and potential.

[0040] Figure 1B shows the plasma potential V during operation PP The curve diagram of the change of the axial direction (longitudinal extension direction) X of the chamber (110) is shown. Figure 1B As shown, the plasma potential V PP From the DC voltage source ( Figure 1A The potential value V applied to the cathode C is 150 C changes to represent the DC voltage source ( Figure 1A The potential value V applied to the anode A is 150 A It should be noted that, for example, Figure 1D As shown in , generally, the value V A At zero volts (e.g. reference ground), and the value V C is negative (eg, in the range of approximately 0 (zero) volts to -500 volts).

[0041] Continue to refer to Figure 1B , potential V PP The sudden changes in the regions close to the cathode C (e.g., D1, G1, D2) and in the regions close to the anode A (e.g., G4) may correspond to regions of the chamber (110) with higher operating temperatures. On the other hand, region G3 (also referred to as the positive column) is a region with a quasi-uniform / constant potential V PP and have areas with lower operating temperatures. For example, considering Figure 1B The chamber (110) shown has a section [X G31 ,X G32 ] is contained in the positive column region G3, and the plasma potential V PP Across such sections [X G31 ,X G32 ] changes the least, or in other words, it can be considered that the cross-section [X G31 ,X G32 ] potential V PP is constant. Therefore, Figure 1B As shown, across segments [X G31 ,X G32 ] of the plasma potential V PP can be considered equal to the value V G3 The lower operating temperature and constant potential value of the plasma in the positive column region G3 enable such a region to be used for processing substrates, such as Figure 1C and Figure 1D shown.

[0042] Figure 1C A simplified schematic diagram of a DC plasma processing system (100C) is shown including a (substrate) stage S arranged in a positive column region G3 of a DC plasma reaction chamber (110). The stage S may be designed to support a flat substrate and may therefore include a top flat / planar surface. Figure 1C The stage S shown in FIG. 1 is electrically isolated (not connected to any external potential), and therefore, and as known to those skilled in the art, at the plasma potential V PP In the presence of S , which is called the surface floating potential V FP . (Surface) floating potential V FP and plasma potential V PP The relationship in Figure 1C In particular, Figure 1C As shown, in the area where the stage S is arranged in the chamber (110) [X G31 ,X G32 ] at the plasma potential V PP Equal to V G3 , while the floating potential V FP Below (negative relative to) the plasma potential V G3 .

[0043] Figure 1C The floating potential V FP Can be attributed to the "plasma sheath" generated in the presence of stage S. As is known to those skilled in the art, at the wall or any barrier within the plasma, a negative potential relative to the main body of the plasma is generated. Therefore, an equilibrium potential drop is generated between the main body of the plasma and the wall or barrier. Such a potential drop is confined to a small area of ​​space adjacent to the wall or barrier due to the charge imbalance generated between the plasma and the wall or barrier. This charge imbalance layer has a finite thickness, characterized by a Debye length, and is called a "plasma sheath" or "sheath". The thickness of such a layer is several Debye lengths thick, and the size of this value depends on various characteristics of the plasma. For example, if the size of the main plasma (e.g., chamber 110) is much larger than the Debye length, the Debye length depends on the temperature and electron density of the plasma. In the specific case of DC plasma operating conditions supported by the teachings of the present disclosure (e.g., EEMP systems close to room temperature to appropriately above room temperature), the Debye length is on the order of several millimeters (e.g., less than 10 mm), and V G3 With V FPThe potential difference between the two is on the order of several volts (e.g., less than 10 volts). It should be noted that the plasma sheath can be generated in the presence of any wall or barrier (whether conductive or not). Therefore, once a substrate (whether conductive or insulating) is placed on top of stage S, the potential difference between the two can be generated as described above with reference to Figure 1C The floating potential V FP .

[0044] Figure 1D shows that the capacitor C S An external bias signal generator (180) capacitively coupled to stage S is Figure 1C An exemplary biasing of a DC plasma processing system is performed on a stage S. Figure 1D In the exemplary configuration (100D) shown, the potential V applied to the anode A is A is zero volts (e.g., coupled to reference ground Gnd). Figure 1D As shown, the bias signal V applied to the stage S by the external bias signal generator (180) B The reference ground potential Gnd may be used as a reference. Although in some prior art implementations, the bias signal V B DC coupling to stage S is possible, but such DC coupling to the stage is strictly prohibited according to the teachings of the present disclosure in order to avoid a discharge path for DC current passing through any intermediate point in chamber (110), because such a discharge path may significantly change the operating conditions within chamber (110).

[0045] exist Figure 1D In the DC plasma processing system shown in FIG. B can be used to control the potential (e.g., surface potential V) experienced by free electrons and / or ions in the vicinity of the stage S or the substrate (if present). S ). Thus, the energy of the free electrons and / or ions can be controlled to a material-specific level required for (optimal) substrate processing. Figure 1E As shown in the left graph, the external bias signal generator (for example, Figure 1D The bias signal V generated by B can start from zero and reach a voltage amplitude V in a short period of time (represented by the leading edge slope) B1 When in such Figure 1E The voltage amplitude V during the processing step (a) is shown in the upper right curve of B1 When applied (eg, AC coupling) to stage S, the voltage amplitude V B1 With surface floating potential V FPa Add (or add the voltage amplitude V B1is negative, subtract), to generate the surface potential V in the vicinity of the stage S S However, due to the free electrons and / or ions in the plasma potential V PPa Therefore, only the surface potential V S is higher than the plasma potential V PPa is experienced by free electrons and / or ions. Figure 1E As shown in the upper right graph, the (kinetic) energy of free electrons and / or ions can be determined based on the potential difference V KEa =(V B1 –ΔV FPa ), where ΔV FPa ,=(V PPa –V FPa ).

[0046] On the other hand, considering the Figure 1E The processing step (b) represented by the lower right graph may have operating conditions different from those of the processing step (a), including, for example, a different plasma potential V PPb or different floating potential V FPb , which may result in different difference ΔV FPb ,=(V PPb –V FPb ), then for the same applied voltage amplitude V B1 , obtaining different (kinetic) energies of free electrons and / or ions. The teachings of the present disclosure eliminate the need for chambers (e.g., Figure 1D 110) and / or compensate for such changes, such as enabling, for example, precise control of the energy of free electrons (and / or ions). It should be noted that, given the different types of processing performed within the chamber (110) (e.g., Figure 1E (a) and (b)), including, for example, etching the substrate with different reactive gases, cleaning the substrate, or any other process that may change and / or remove components / materials on the surface of the substrate, changes in operating conditions can be expected. It should be noted that, as known to those skilled in the art, different operating conditions for performing different types of processes may also include corresponding changes and / or adjustments to any of the DC plasma current, temperature, gas mixture or flow rate within the chamber (110).

[0047] When the substrate is placed on top of the stage S surface, the free electrons and / or ions are driven by the bias signal V B The kinetic energy obtained by the application of V can accelerate the free electrons and / or ions toward the substrate surface and collide with the substrate to release the kinetic energy to the atoms at the substrate surface. However, these atoms are at the following energy levels: This energy level is based on the potential at which these atoms are located, or in other words, based on the floating potential VFP .exist Figure 1F The above reference is shown in Figure 1E The various energy levels of such an atom of the treatment type (a) include: the energy level E of the nucleus at the substrate surface n , the energy level E of the electrons bound to the atomic nuclei at the substrate surface B , and the energy level E of the electrons in the orbit of the electrons bound to the atomic nuclei at the substrate surface e .

[0048] like Figure 1F As can be seen, the energy level of the nucleus E n At (negative) potential V FPa and the energy level E of the electron e At (negative) potential (E n +E B ) in order to excite the atom to an energy level that can break the bond between the electron and the nucleus, it is necessary to raise the energy level of the atom to an energy level equal to or greater than the electron's energy level E e Therefore, considering the plasma processing only by free electrons, the bias signal V B The kinetic energy of the free electrons provided by the application of Figure 1F The potential difference V KEa =(V B1 –ΔV FPa ) means) must be equal to or greater than the energy level E e However, due to E e =(E n +E B ) and E n Based on the a priori unknown floating potential V FPa , so it is impossible to precisely control the kinetic energy of the free electrons to precisely target the energy level E e .

[0049] Although the floating potential (e.g., Figure 1F V FPa), but any inconsistency and / or lack of repeatability in such operating conditions may invalidate the determined floating potential. Furthermore, since different types of processing inherently produce different floating potentials, the task of precisely controlling the kinetic energy of the free electrons to exactly target the energy levels of the atoms at the substrate surface may not be feasible. Therefore, the kinetic energy imparted to the atoms at the substrate surface by some prior art implementations may be significantly greater than the energy levels of the target atoms, and thus selectivity may not be achieved (because atoms of different materials / compositions with different energy levels may similarly experience energy levels sufficient to break their orbital bonds). Electronic Enhanced Materials Processing (EEMP) according to the teachings of the present disclosure overcomes this deficiency and thus enables the kinetic energy of the free electrons to be precisely and selectively targeted to the energy levels of the atoms at the substrate surface.

[0050] Figure 2A A simplified schematic diagram of a DC plasma processing system (200A) is shown, including means (250, 260) for controlling the surface potential of a station S when electrically isolated, according to an embodiment of the present disclosure. In other words, these means (250, 260) enable the adjustment of the floating potential V FP .like Figure 2A As shown, the device (250, 260) includes: an adjustable DC voltage source (250) coupled to the anode A of the DC plasma reaction chamber (110), and a DC current source (260) coupled to the cathode C of the DC plasma reaction chamber (110). Therefore, the potential V of the anode A is A The (leakage) current Ip flowing between the anode A and the cathode C through the reaction chamber (110) can be controlled to be within a range from zero volts to upward (positive) relative to the reference ground (Gnd at zero volts), and can be set by the DC current source (260). Therefore, the potential V of the cathode C C is not supplied by an external DC voltage source (e.g. Figure 1D 150) is not mandatory, but (it is floating and) is determined to be based on the adjustable potential V of the anode A. A and the (negative) voltage of the set current Ip. Such a configuration enables independent control / adjustment of the floating potential V while maintaining a constant set current Ip through the reaction chamber (110). FP , thereby establishing and maintaining a high level of processing stability and optimization.

[0051] Figure 2B For the above reference Figure 2A The DC plasma processing system (200A) has a surface potential V FP In particular, Figure 2BTwo graphs are shown, which are distinguished by using a solid line or a dashed line, each representing: for two different voltages (V A1 , V A2 ), the plasma potential V across the longitudinal extension X of the chamber (110) PP Changes. Figure 2B As can be seen, for the anode potential from the voltage V A1 To voltage V A2 A positive step increase of +ΔV 12 , floating potential (V FP1 , V FP2 ) and cathode potential (V C1 , V C2 ) with the same positive step increase of +ΔV 12 In fact, if Figure 2B As shown, the plasma potential V PP The entire curve is a step +ΔV 12 Positive shift. In other words, for the range [X C ,X A ], the corresponding plasma potential V PP (X) Follows a step increase +ΔV 12 The same behavior applies to a negative step change applied to anode A by the adjustable DC voltage source (250). In other words, controlling the potential of anode A by the adjustable DC voltage source linearly affects the plasma potential V at any longitudinal coordinate X. PP , and therefore, linearly affects the floating potential V FP and the voltage V on the top of stage S S As described later in this disclosure, this linear relationship can be used in an EEMP system according to the present teachings to implement a closed-loop control subsystem, thereby setting the floating potential V FP The value of is automatically controlled to a preset value (e.g., zero volts) while operating the DC plasma chamber for different types of material processing.

[0052] Figure 2C Shown with the above reference Figure 2B The graph is similar to the two graphs, including the anode voltage V A1 The specific case where is equal to zero volts (solid line). Figure 2B As can be seen, the floating potential voltage in this case is equal to the negative value V FP1 , and therefore, with respect to the plasma potential V PP Negative (lower than the plasma potential V PP ). In addition, from Figure 2C As can be seen from the figure, for a positive step increase in anode potential +ΔV 13 =(V A1-V FP1 ), the floating potential can be adjusted to a value equal to zero volts V FP3 According to an embodiment of the present disclosure, the floating potential V FP This zeroing of allows precise control of the kinetic energy of the free electrons in the DC plasma to be directed exactly (and selectively) to the energy levels of the atoms at the surface of the substrate being processed (whether conductive or insulating). Figure 1F , by setting the floating potential V FP The zeroing removes the a priori unknown floating potential that determines the energy level E of the nucleus targeted / selected for processing. n . Furthermore, as described later Figure 4B As shown, this enables the energy level E of the target electron to be e , the kinetic energy level of free electrons in DC plasma (e.g., Figure 1F V KEa ) and the bias voltage V applied to the stage S B is related to the same known and fixed zero volt potential reference Gnd. It should be noted that although the floating potential V FP The provision can be provided by zeroing such potential as described above, but such zeroing should not be considered to limit the scope of the present disclosure, since other preset / adjusted non-zero values ​​of the floating potential can be equally used as a reference potential for precisely controlling the kinetic energy of free electrons in a DC plasma to be exactly (and selectively) directed to the energy levels of atoms at the surface of the substrate being processed (whether conductive or insulating).

[0053] Figure 3A A device for measuring the surface potential of a control panel S according to an embodiment of the present disclosure is shown ( Figure 2A 250, 260) and for measuring the surface potential V on the top of the table S (For example, floating potential V FP ) device ( Figure 3A R, 311, V R ) is a simplified schematic diagram of a DC plasma processing system (300A) of the present invention. As will be appreciated by those skilled in the art, the system (300A) represents a simplified schematic diagram of the DC plasma processing system (300A) of the present invention. Figure 2A The improvement of the system (200A) is achieved by adding a device for measuring the surface potential V S , or in other words for measuring the floating potential V on the top (surface) of the stage FP Device (R, 311, V R ). By realizing the floating potential V FP This measurement can be carried out as above with reference to FIG. 2A to FIG. 2CThe regulation of the DC voltage source (250) is performed while monitoring / measuring the surface potential V FP This in turn enables precise control of the floating potential V FP , including, for example, returning the floating potential to zero (V FP =0V).

[0054] Continue to refer to Figure 3A , device (R, 311, V R ) includes a reference plate R, which is placed in the same (ordinate) section [X] as the stage S in the DC plasma chamber (110). G31 ,X G32 ] The reference plate R may be made of any conductive material capable of withstanding the (internal) operating conditions of the chamber (110) and may have any planar shape, including, for example, a square, rectangular, circular, pentagonal, trapezoidal or other planar shape. Since the reference plate R is arranged in the same region as the plate S and is therefore at the same substantially constant plasma potential V PP region, so the reference plate R experiences the same floating potential V as the stage S FP In other words, by measuring the (surface) potential V at the reference plate R R , the floating potential at the station S can be determined. The potential V R Routing / coupling to measurement electronics (eg, sensors) placed outside the chamber (110). It should be noted that such measurement electronics should not provide a DC current path through the plate R to the plasma.

[0055] Continue to refer to Figure 3A , the reference plate R can be placed in the section [X G31 ,X G32 ] is technically feasible and practical. Since the chamber (110) may include a channel door adjacent to the stage S on one side of the chamber (110), in some exemplary embodiments, the reference plate R may be arranged to: abut against the channel door of the chamber (110) and the wall on the opposite side of the stage S, or in the vicinity of the wall. In addition, according to an exemplary embodiment, the center of the reference plate R and the center of the stage S (e.g., the intersection of the two segments constituting the T-shaped stage as shown in the figure) may be contained within a line perpendicular to the axial direction of the chamber (110) (e.g., the center line, the direction of longitudinal extension). The applicant of the present disclosure has verified that the device (R, 311, V R ) High accuracy of tracking the floating potential of stage S.

[0056] Figure 3BThe surface potential V at the automatic control station S is shown based on an embodiment of the present disclosure. FP Device (320, CT) Figure 3A A simplified schematic diagram of a DC plasma processing system (300B) of a system (300A) of FIG. 300B includes a control electronic device (320) configured to implement a closed-loop control system to adjust a floating potential V at a stage S to a value greater than 0.05 V. FP The value of is automatically controlled to a preset value (e.g., zero volts) while operating the DC plasma chamber for different types of processes. Figure 3B As shown, the control electronics (320) obtains the (surface) potential V of the reference plate R via the coupling provided by the insulated conductive wiring (311). R As input, a control (error) signal CT is generated from the input to the adjustable DC voltage source (250) to adjust the voltage V supplied to the anode A. A , and therefore as mentioned above FIG. 2A to FIG. 2C As described above, the floating potential V at the adjustment station S FP The control (error) signal CT may be a floating potential V relative to a desired target value / preset value (such as, for example, zero volts). FP A person skilled in the art will be well aware of design techniques for implementing the control electronics (320), which are outside the scope of the present disclosure. In particular, a person skilled in the art will be well aware of using an operational amplifier or an error amplifier in such a control electronics (320), wherein the input of such an amplifier may be coupled to a potential V R and coupled to a floating potential V of a desired target value / preset value (eg, zero volts). FP , to generate an error signal (e.g., CT) based on the difference in the inputs.

[0057] Figure 4A The embodiment of the present disclosure shows a method of adding a biasing device (C S , 480) Figure 3B A simplified schematic diagram of a DC plasma processing system (400A) of the system. In particular, the bias device (C S , 480) includes a bias signal generator (480) which biases the capacitor C S is coupled to stage S. In other words, the bias signal V generated at the output of the bias signal generator (480) B Through the capacitor C SCapacitively coupled to stage S. As previously described in the present disclosure, such capacitive coupling can enable the removal of any DC current path from or to the DC plasma chamber (110), thereby preventing any undesirable perturbations to the operating conditions of the chamber (110). It should be noted that the bias signal generator (480) can include, for example, a programmable waveform generator configured to output the bias signal V according to desired characteristics, including, for example, amplitude, frequency, duty cycle, and / or rising / falling edge / slope. B It should also be noted that stage S may include a bias signal V B The first conductive portion electrically coupled to the stage S (eg, connected to the capacitor C S vertical leads), and a second portion of the stage (e.g., a horizontal support plate) which may include a conductive material and / or an insulating material.

[0058] Figure 4B Shows the Figure 4A An exemplary bias signal V provided by a stage S of a DC plasma processing system (400A) B1 and the corresponding surface potential V generated at the surface of stage S S As can be clearly understood by those skilled in the art, Figure 4B The graph shown corresponds to a configuration of the system (400) where the floating potential V FP is regulated or controlled to be at zero volts. Therefore and in view of (or relative to) the reference Figure 1E As described above, the (kinetic) energy of the free electrons and / or ions attracted to the surface of the stage S or the substrate on the stage S is based on the potential difference V KE =(V B1 –ΔV FP ), where ΔV FP =(V PP –V FP ). Therefore, due to the actual substrate processing application using a DC plasma chamber, ΔV FP The value of can be significantly smaller than (for example, based on Figure 4C The energy level of the target electron E e V KE value (e.g., a ratio of 1 / 50 or less); it can be considered to be approximately V KE =V B1 This, in turn, makes it possible to simply and directly generate the bias signal V provided to the stage S. B1 , for achieving electron enhanced material processing (EEMP) according to the teachings of the present disclosure, which electron enhanced material processing is precisely and selectively targeted at the energy levels of atoms (e.g., bound electrons) at the substrate surface.

[0059] Also refer to Figure 4A and Figure 4B It should be noted that the excitation of the energy levels of atoms at the surface of the stage S or at the surface of the substrate arranged on top of the stage S can be mainly based on the surface potential V S Therefore, the excitation of the energy level can be achieved when the bias voltage reaches the target value V B1 or, in other words, at the end of the transition Figure 4B The ramp end shown is completed immediately.

[0060] Figure 4C Shows Figure 4A Example performance levels of atoms at the surface of stage S of a DC plasma processing system (400A). Figure 4C The advantages of electronically enhanced material processing (EEMP) according to the teachings of the present disclosure are highlighted, which enables: based on the above reference FIG. 2A to FIG. 2C The floating potential V FP Zeroing, also based on the above reference Figure 3A The reference plate R is also based on the above reference Figure 3B The (optional) closed-loop control system provided by the control electronics (320), and also based on the above reference Figure 4A The bias signal V provided by the bias signal generator (480) B The capacitive coupling is precisely and selectively directed to the energy levels of atoms at the substrate surface (e.g., according to Figure 4C , Ee≈V KE ) adjustment.

[0061] Figure 5 is a flow chart (500) showing various steps of a method for processing a surface of a substrate according to an embodiment of the present disclosure. Figure 5 As shown, such steps include: according to step (510), placing a substrate support table in a region of a DC plasma reaction chamber configured to generate a positive column of a DC plasma; according to step (520), generating a DC plasma by coupling an adjustable DC voltage source to an anode of the DC plasma reaction chamber and coupling a DC current source to a cathode of the DC plasma reaction chamber, respectively; according to step (530), generating a floating potential at the surface of the substrate support table based on the generation; according to step (540), adjusting the potential at the anode via the adjustable DC voltage source, while maintaining a constant DC current between the anode and the cathode via the DC current source; and according to step (550), setting the floating potential to a reference ground potential of the adjustable DC voltage source based on the adjustment and the maintenance.

[0062] FIG. 6A to FIG. 6CA graph showing the reaction rates of electronically enhanced material processing (EEMP) according to the present disclosure for different (classes / types / kinds) of materials, including: single crystal or 2-dimensional (2D) materials ( Fig. 6A ), such as, for example, semiconductor materials or insulator materials; metals and metal alloys ( Figure 6B ); and complex materials ( Figure 6C ), such as polymers, composites, nanomaterials or 3-dimensional (3D) materials. In this case, the reaction or target reaction can be referred to as: placed on the stage (e.g. Figure 4A The chemical bonds of the atoms of the material at the surface of the substrate (e.g., the bonds between electrons and atomic nuclei) on top of the substrate respond to the application of the stage (e.g., Figure 4A S) bias signal V B As can be clearly understood from such a graph, the reaction rate RR can be determined by the reaction threshold voltage V RTH , reaction cut-off voltage V RCO and the response threshold voltage V RTHV It should be noted that for each material or each type of material, such characteristic voltages may be different and are usually part of a priori acquired knowledge base. Fig. 6A ) RTH Can be different from metal materials (such as Figure 6B ) RTH or complex materials (e.g. Figure 6C ) RTH , and crystalline materials (such as Fig. 6A ) RTHV Can be different from metal materials (such as Figure 6B ) or complex materials (e.g. Figure 6C ) RTHV .

[0063] It should be noted that 2D materials compatible with electronic enhanced material processing (EEMP) according to the present disclosure may include, for example, graphene, boron nitride, molybdenum disulfide, tungsten diselenide, or platinum diselenide; nanomaterials compatible with EEMP according to the present disclosure may include, for example, carbon nanotubes, nanosilver particles, titanium oxide particles, or quantum dots; 3D materials compatible with EEMP according to the present disclosure may include any 3D structure formed in the material, for example including polymers, collagen fibers, or metals such as, for example, titanium, or 3D printed polymer / polymer, polymer / carbon, or polymer / metal microstructures. Single crystals compatible with EEMP according to the present disclosure may include: semiconductor single crystals, such as, for example, IV silicon, germanium, III-V gallium arsenide, gallium nitride, silicon carbide, gallium indium arsenide, etc.; II-VI zinc selenide; and quantum well stacks containing layers of alternating III-V compound semiconductors and / or II-VI compound semiconductors. Single crystals compatible with EEMP according to the present disclosure may also include semiconductor single crystals such as, for example, quartz, sapphire, or diamond. Polymers compatible with EEMPs according to the present disclosure may include, for example, polypropylene, polyethylene, polyetheretherketone, polycarbonate. Composite materials compatible with EEMPs according to the present disclosure may include, for example, polymers containing metal particles, carbon particles, carbon fibers, or carbon nanotubes. With respect to the list of EEMP material compatibility according to the present teachings, the materials and structures listed here should be considered non-limiting, and the list may grow as new materials / structures and corresponding binding energies and reaction energies (which may be targeted by the present EEMP) are obtained through advanced methods such as computer simulation of chemical bonds.

[0064] Continue to refer to FIG. 6A to FIG. 6C , when the substrate is placed on the stage (e.g. Figure 4A S) at the top, as described above, for example, refer to Figure 4B , floating potential (e.g. Figure 4B V FP ) can be adjusted (and controlled) to a known potential (e.g., zero volts or other). Thus, the energy levels of the atoms at the surface of the substrate may take on the same potential (e.g., as their ground state), and no reaction may be observed at the surface of the substrate, or in other words, as FIG. 6A to FIG. 6C As shown, the reaction rate RR of the target bond (in the ground state) is zero. B increases, the reaction rate RR of the target bond remains at zero until the reaction cutoff voltage V RCO , after which a small number (e.g., a few) of target bonds slowly begin to react, or in other words, a few target bonds reach their respective excited states. B Increase the reaction cut-off voltage V RCO, the reaction rate RR increases slowly, and gradually more target bonds reach their respective excited states. B Reaching the reaction threshold voltage V RTH When the bias voltage V B As the bias voltage V increases further, the reaction rate RR increases at a (substantially) fixed slope, which continues until the bias voltage V B Reaching the reaction threshold change voltage V RTHV . At the reaction threshold voltage V RTH The threshold voltage V RTHV The reaction rate RR increases until (almost) all target bonds have reacted. FIG. 6A to FIG. 6C As shown, the bias voltage V B Further increase in voltage V beyond the threshold value RTHV , causing the reaction rate RR to increase slightly, or in other words, to the point of "diminishing returns". On the other hand, as the bias voltage V B decreases, the reaction rate RR follows FIG. 6A to FIG. 6C In particular, when the bias voltage V B Reduced to below the reaction cut-off voltage V RCO At a level of , the reaction rate RR drops to zero because all target bonds at the surface of the substrate return to their respective ground states.

[0065] As from FIG. 6A to FIG. 6C As can be clearly understood from the graph shown, the reaction rate RR at voltage V RTH With voltage V RTHV , or in other words, the voltage V RTH With voltage V RTHV The difference between V and V may vary depending on the material used in the substrate being processed. RTH With voltage V RTHV The difference between the two may be due to: single crystal materials such as semiconductors or insulators (e.g. Fig. 6A ) atomic-scale defects on the surface of metals, metal alloys or nanomaterials and related grain boundaries (e.g. Figure 6B ) surfaces; or polymers, composites, or other 3D materials (e.g. Figure 6C ) of the 3-dimensional (3D) structure. As described later in this disclosure, according to the teachings of this disclosure, a method for generating a voltage level V B The waveform of the bias signal of the voltage level is specific to the material used in the substrate, for example to control the activation (or deactivation) of the reaction dominated by the reaction rate RR, the curve diagram is for example in FIG. 6A to FIG. 6C In particular, Fig. 7A , Figure 7B and Figure 7C It is shown in Fig. 6A , Figure 6B and Figure 6C The reaction rate RR of the curve graph represents the specific waveform of each of the materials.

[0066] FIG. 7A to FIG. 7C Graphs representing waveforms of EEMP bias signals V(t) according to some exemplary embodiments of the present disclosure for processing different materials are shown. In particular, Fig. 7A Waveforms for processing single crystal materials such as semiconductors or insulators are shown; Figure 7B Waveforms for processing metals, metal alloys, or nanomaterials are shown; and Figure 7C Waveforms for processing polymers, composite materials or 3D materials are shown. It should be noted that such a graph represents an ideal voltage level (e.g., V B 、V BN ) for use in the above-mentioned EEMP process according to the present disclosure, which EEMP process may include setting the potential V FP is controlled to a known level such as zero volts or other fixed known levels, and by using a potential V FP is the reference voltage / potential level (e.g. V B ) energizes the free electrons in the DC plasma.

[0067] FIG. 7A to FIG. 7C Each of the curves in the graph represents one period of the (periodic) bias signal V(t), denoted as T EEMP Based on the a priori processing knowledge, the EEMP The bias signal V(t) is generated to perform EEMP treatment on the material on the surface of the substrate. In view of the different material layers in the substrate and / or the different operating conditions and / or potential V of the DC plasma reaction chamber, FP Due to the (controlled / preset) levels, different EEMP processes (e.g., with respective RR characteristics) can be performed sequentially on the same substrate.

[0068] Continue to refer to FIG. 7A to FIG. 7C According to an embodiment of the present disclosure, the period T of the waveform of the bias signal V(t) is EEMP It can include three different phases (eg, time intervals, time segments) ΔT BP , ΔT BN and ΔT BZ, which respectively include voltage levels higher than zero volt (or reference voltage level), lower than zero volt and equal to zero volt. In other words, in the time interval ΔT BP During this period, the level of the bias signal V(t) is V B Strictly greater than zero volts (or reference voltage level); in the time interval ΔT BN During this period, the level of the bias signal V(t) is V BN strictly less than zero volts; and during the time interval ΔT BZ During this period, the level of the bias signal V(t) is equal to zero volt.

[0069] According to an embodiment of the present disclosure, FIG. 7A to FIG. 7C The period T of the waveform shown EEMP The duration of the bias signal V(t) may be in the range of 1 μs to 10 μs, or in other words, the frequency of the bias signal V(t) may be in the range of 100 KHz to 1 MHz. According to another embodiment of the present disclosure, the waveform of the bias signal V(t) may have no DC component, or in other words, FIG. 7A to FIG. 7C The integral of the waveform shown in over one period may have a zero value. This DC-free characteristic of the waveform according to the present teachings may enable the average local surface potential of the substrate to be maintained during the application of the bias signal V(t), as described above with reference to, for example Figures 2A to 4C As described above, the average local surface potential is (substantially) equal to the preset / controlled local surface potential of the substrate (e.g. V FP ). In other words, the DC-free nature of the waveform can enable the application of FIG. 7A to FIG. 7C , the (substantially) same voltage levels as shown in B 、V BN ). It should be noted that for the potential V FP is adjusted (eg, preset, controlled) to a (fixed and known) level different from zero volts, the waveform may be adjusted to include a potential equal to V FP The DC component of the level, or in other words, by using the potential V FP Replace the adjustment value FIG. 7A to FIG. 7C The 0V reference in the waveform is used to adjust the waveform.

[0070] According to an embodiment of the present disclosure, FIG. 7A to FIG. 7C The time interval ΔT shown in BP , ΔT BN and ΔT BZ The length of each of may be based on the type of material (at the surface) of the substrate, including the above reference FIG. 6A to FIG. 6C The corresponding reaction rate RR is described. In particular, the time interval ΔT BP The length and time interval ΔT BNThe ratio of the length of may be in the range from (approximately) 1 / 10 to (approximately) 1 / 1. For example, in the case of a crystalline material (e.g. Fig. 7A ), the ratio may be about 10 / 65 (+ / -10%); for the case of metallic materials (e.g. Figure 7B ), the ratio can be about 1 / 2 (+ / -10%); and for complex materials (e.g. Figure 7C ), the ratio may be about 1 / 1 (+ / -10%). FIG. 7A to FIG. 7C As shown, the time interval ΔT BZ The length of the whole cycle is T EEMP The ratio of may be about 1 / 4 (+ / -10%). According to a non-limiting embodiment of the present disclosure, the time interval ΔT BZ The length can be based only on the entire period T EEMP length, but is independent of the time interval ΔT BP and time interval ΔT BN The length of each.

[0071] for FIG. 7A to FIG. 7C In the exemplary non-limiting case shown, the time interval (ΔT BP , ΔT BN , ΔT BZ ) and the entire period T EEMP The ratio of the lengths of can be the following values ​​(eg, + / - 10%): For the case of crystalline materials (eg Fig. 7A ), about (10 / 100, 65 / 100, 25 / 100); for metal materials (such as Figure 7B ), about (25 / 100, 50 / 100, 25 / 100); and for complex materials (e.g. Figure 7C ), about (37.5 / 100, 37.5 / 100, 25 / 100). It should be noted that FIG. 7A to FIG. 7C The period T is 4 μs (frequency is 250 KHz). EEMP , which should not be considered to limit the scope of the present disclosure, since as described above in the present disclosure, such length may be in the range from 1 μs to 10 μs (eg, at a frequency of 100 KHz to 1 MHz).

[0072] Continue to refer to FIG. 7A to FIG. 7C The waveform at stage ΔT BP During this period, the waveform can set the bias voltage V(t) to a (positive) level (e.g. V B ), for activating a (target) EEMP reaction at the substrate surface, the EEMP reaction being based on collisions of energetic (free) electrons at the substrate surface with target bonds (e.g., with Fig. 7A Single crystal, Figure 7B of metal and Figure 7C According to an embodiment of the present disclosure, the (high) level V of the bias voltage V(t) is maintained during the B The length of must be long enough to keep the energized (free) electrons at the surface of the substrate to react with the target bond. It should be noted that such a length may not include FIG. 7A to FIG. 7C The phase ΔT shown BP The rising slope or falling slope (part of it) included in (for example, during which the bias voltage (V(t)) is not at the target high level V B place).

[0073] In addition, in the phase ΔT BN period, FIG. 7A to FIG. 7C The waveform can set the bias signal V(t) to a (negative) level ΔT BN , which serves to deactivate the EEMP reaction on the surface of the substrate and also release any free electrons from the substrate surface (e.g., repel), thereby neutralizing the charge on the substrate. It should be noted that at ΔT BN During this phase, the (negative) level V of the bias signal V(t) can be BN Kinetic energy is imparted to the free ions in the DC plasma, which can thus cause the energized free ions to slowly move toward the substrate surface, thereby further participating in the neutralization of the substrate. It should also be noted that, due to the low energy level of the energized free ions, the energized free ions may (absolutely) not cause any reaction with the bonds at the surface of the substrate. Therefore, the voltage level V of the bias signal V(t) is BN The magnitude of can be high enough (e.g., more negative) to make the free ions move slowly, and the phase ΔT BN The duration can be long enough to match the voltage level V BN The size and phase ΔT BP The combination of durations causes suppression (or control) of the DC component of the bias signal V(t).

[0074] In phase ΔT BZ period, FIG. 7A to FIG. 7C The waveform can set the voltage level of the bias signal V(t) to zero (or set it at a floating potential V FP Therefore, the phase ΔT BZ It can be used to set the bias signal V(t) for each period T EEMP The same initial bias condition of the substrate is restored at the beginning, such initial bias condition is based on the floating potential V FPThis in turn can enable a more stable and precise process (EEMP) when compared to other prior art processes. Therefore, based on the description provided, the period T of the waveform of the bias signal V(t) is described. EEMP Each stage ΔT BP , ΔT BN and ΔT BZ They can be respectively called: the activation (EEMP) reaction phase; the (EEMP) neutralization phase; and the (EEMP) initialization phase, where the latter two phases are non-activation phases relative to the target (EEMP) reaction.

[0075] Fig. 8A Shown is the above reference FIG. 7A to FIG. 7C The idealized waveform of the EEMP bias signal V(t) is shown in the figure, including a graph describing the waveform during the activation phase ΔT. BP Other timing details of the various parts of the period (e.g., time interval t BR ,t BH and t BR ). In particular, the time interval t BR The bias signal V(t) can be limited to reach the target high level V from the starting value at the beginning of the phase (for example, V(t) = 0) B The duration of the transition; time interval t BH It can be defined that the bias signal V(t) is at the target high level V during B The effective duration at; and the time interval t BF The bias signal V(t) can be limited to the activation phase ΔT BP The transition duration taken for the end to return to the starting value (e.g. V(t) = 0). In other words, the time interval t BR The bias signal V(t) can be limited to reach the high level V from the starting value B The rising (for example, leading) edge slope, and the time interval t BF The slope of the falling (eg, trailing) edge of the bias signal V(t) returning to the starting value may be defined.

[0076] Continue to refer to Fig. 8A , at time interval t BH During this period, the bias signal V(t) is higher than (greater than) the reaction threshold voltage V RTH High level V B and therefore, as long as, as above, refer to e.g. FIG. 7A to FIG. 7C The time interval t BH The duration is long enough, then as mentioned above, for example FIG. 6A to FIG. 6CAs described above, the target bonds can reach their respective excited states so that the energized (free) electrons on the substrate surface remain to react with the target bonds. According to an exemplary embodiment of the present disclosure, the time interval t BH The length of the activation phase ΔT BP The ratio of the length of the single crystal material can be in the range of about 1 / 4 (e.g., + / - 10%) to about 3 / 4 (e.g., + / - 10%). Fig. 6A and Fig. 7A ), where the frequency of the periodic bias signal V(t) is 250KHz and therefore the period T EEMP The length is equal to 4μs, then the time interval t BH The length of may be in the range from about 0.1 μs to about 0.3 μs.

[0077] Further references Fig. 8A , as the bias signal V(t) is in the activation phase ΔT BP The rise at the beginning of BR During part of the period, the voltage reaches a value higher than the reaction threshold voltage V RTH Similarly, as the bias signal V(t) changes in time interval t BH decreases at the end of BF During part of the period, the voltage V RTH Therefore, the free electrons in the DC plasma effectively experience Fig. 8A In the ideal case of the voltage level shown, the level of the bias signal V(t) is higher than the reaction threshold voltage V RTH The time interval t BR and t BF A portion of the above reference may be included FIG. 6A to FIG. 6C The determination (or interpretation) of the curve diagram of the reaction rate RR is described. However, due to the time interval t BR and t BF The defined rising and falling slopes can be very steep (high level V B The portion of time that may be in the range from 10 volts to about 200 volts may be considered insignificant / unimportant when compared to the minimum amount of time required to keep energized (free) electrons on the substrate surface to react with the target bond.

[0078] Figure 8B A graph showing the actual waveform of the EEMP bias signal is shown. Such a waveform representation can be based on the above reference Fig. 8A The ideal waveform described above is used to model the actual achievable waveform. In particular, as shown in the figure, Figure 8BThe actual waveform includes to the corresponding steady-state level (such as V B , V BN , zero volts) / gradual and curved transition from the corresponding steady-state level. Such actual waveforms may be generated by electronic equipment, which may include a power amplifier (such as, for example, coupled to Figure 4A A bias signal generator, or Figure 4A The output of the bias signal generator is coupled to the load under perfect matching conditions. However, in the DC plasma processing according to the present disclosure, it may not be possible to generate a bias signal from a capacitive load (e.g. Figure 4A The platform S) provides such a perfect matching condition, and therefore, Figure 8C As shown, after settling to a steady-state level (e.g., V B , V BN , zero volts), signal reflections including ringing and related distortions can be expected.

[0079] Figure 8C The ringing shown may include: the bias signal V(t) is in the activation phase ΔT BP During the period of stabilization to the target high level V B The previous ringing and the neutralization phase ΔT BN During the period of stabilization to the target low level V BN The previous ringing (for example, V BU ).like Figure 8C As shown, in the activation phase ΔT BP The ringing during the period can be caused by the uncertain voltage distribution V BU Indicates that the uncertain voltage distribution V BU With overshoot voltage V BOS Extends to the target high level V B above, and with undershoot voltage V BUS Extends to the target high level V B The following is a brief description of the technical personnel in this field. BU May disturb the activation phase ΔT BP During the activation of the EEMP target reaction, this is because the undershoot voltage V BUS This may cause the level of the bias signal V(t) to drop below the reaction threshold voltage V RTH , and the overshoot voltage V BOS This may cause the level of the bias signal V(t) to reach the reaction threshold voltage V' of non-target bonds that may exist on the surface of the substrate. RTH On the other hand, since the free ions are kept at a reaction energy far below that of any ion-driven reaction (e.g., thermochemical reaction), the neutralization phase ΔT BNThe ringing during the period may not significantly affect the EEMP process. According to an embodiment of the present disclosure, the bias signal V(t) may be provided by pre-distortion (e.g., distortion compensation) Figure 8C The ringing (including the activation phase ΔT BP reduction of ringing during the

[0080] Fig. 9A shows the representation used to generate Figure 8B The digitized waveform of the actual waveform (WF, digital samples are marked by circles), and the corresponding digitized waveform with predistortion (WF P In particular, the corresponding digital samples of the digitized waveform WF can be uploaded to the digital signal generator to provide Figure 8B The output of the digital signal generator may be provided to a power amplifier (such as, for example, coupled to Figure 4A A bias signal generator, or Figure 4A Similarly, the digitized waveform WF with predistortion can be P The digital samples are uploaded to a digital signal generator to provide generation of a corresponding actual waveform with pre-distortion.

[0081] Continue to refer to Fig.9A , predistortion can be used to alter / equalize the digitized waveform WF with predistortion P The slope / transition of the waveform (e.g. WF P ), the predistorted waveform is subjected to a station (e.g., Figure 4A When the capacitive load condition of S is Fig. 9B As shown, a reduction in the amount of ringing can be provided. Fig. 9B As shown, the use of predistortion can make the uncertain voltage distribution V BU decrease, for example, during the entire activation phase ΔT BP During this period, the level of the bias signal V(t) can be kept higher than the target reaction threshold voltage V RTH and is lower than any non-target reaction threshold voltage V' RTH It should be noted that such predistortion can produce a time interval t of the desired length BH The waveform at time interval t BH During this period, the bias signal V(t) is at the target high level V B In other words, predistortion can protect the above reference, for example Fig. 8A The time interval t BH Length.

[0082] Fig. 10AA graph showing the gain of a band-limited linear power amplifier according to an embodiment of the present disclosure versus frequency (e.g., graph G1) and a graph showing the gain of a conventional power amplifier versus frequency (e.g., graph G2) are shown. According to an embodiment of the present disclosure, a band-limited linear power amplifier for EEMP processing may include a gain G1, such as Fig. 10A As shown, the gain G1 is flat within 0.75 dB in the frequency range from 10 KHz to 10 MHz. This operating (bandpass) range of the band-limited linear power amplifier is selected in view of the operating frequency range of the bias signal V(t) of 100 KHz to 1 MHz, for example to reduce any corresponding (higher frequency) harmonics that may be reflected from the capacitive load and produce signal distortion, including Figure 8C and Fig. 9B The ringing part shown (e.g., the uncertain voltage distribution V BU ).

[0083] Fig. 10B shows the capacitive load condition through Fig. 10A The band-limited linear power amplifier from Fig. 9A Digital waveform with pre-distortion WF P In particular, when compared with the above reference Fig. 9B When comparing the waveforms described above, it can be observed that the uncertain voltage distribution V BU This indicates an even larger processing window for controlling / manipulating the target EEMP reaction. It should be noted that Fig. 9B The waveform can be reproduced by a conventional power amplifier, the gain of which is relative to the frequency G2. Fig. 10A In particular, Fig. 10A As shown, the cutoff frequency f of a conventional power amplifier C2 Significantly greater than the cutoff frequency f of the band-limited linear power amplifier according to the present teachings C1 , the cut-off frequency f C2 High frequency harmonics of the bias signal V(t) may be passed through and thus reproduced as distortion.

[0084] Fig.11 1 is a flow chart (1100) showing various steps of a method for processing a surface of a substrate according to an embodiment of the present disclosure. Fig.11As shown, such steps include: according to step (1110), placing the substrate on a support table in a region of a DC plasma reaction chamber configured to generate a positive column of DC plasma; according to step (1120), generating DC plasma; according to step (1130), presetting the floating potential at the surface of the substrate as a reference potential, and; according to step (1140), capacitively coupling a periodic bias signal having a bias voltage to the support table, the bias voltage being referenced to the floating potential, the periodic bias signal including: an activation phase having a positive voltage based on a known reaction threshold voltage of a target chemical bond of atoms at the surface of the substrate; a neutralization phase having a negative voltage; and an initialization phase having a zero voltage.

[0085] Some embodiments of the present disclosure have been described. However, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present disclosure. Therefore, other embodiments are within the scope of the appended claims.

[0086] The above set forth examples are provided to those of ordinary skill in the art as a complete disclosure and description of how to make and use embodiments of the disclosure, and are not intended to limit the scope of what the inventors regard as their disclosure.

[0087] Modifications of the above-described modes for carrying out the methods and systems disclosed herein that are obvious to those skilled in the art are intended to fall within the scope of the appended claims. All patents and publications mentioned in the specification are indicative of the skill levels of those skilled in the art to which the present disclosure pertains. All references cited in the present disclosure are incorporated by reference to the same extent as if each reference had been individually incorporated by reference in its entirety.

[0088] It should be understood that the present disclosure is not limited to a specific method or system, which can certainly vary. It should also be understood that the terms used herein are only used for the purpose of describing a specific embodiment and are not intended to be restrictive. As used in this specification and the appended claims, unless the content clearly stipulates otherwise, the singular forms "a", "an" and "the" include plural indicators. Unless the content clearly stipulates otherwise, the term "multiple" includes two or more indicators. Unless otherwise defined, all technical terms and scientific terms used herein have the same meanings as those of ordinary skill in the art to which the present disclosure belongs.

Claims

1. A direct current (DC) plasma processing system for processing a substrate, comprising: A DC plasma reaction chamber (110) configured to accommodate a DC plasma generated between an anode (A) and a cathode (C) of the DC plasma reaction chamber (110); a substrate support table (S), the substrate support table being arranged in a region (G3) of the DC plasma reaction chamber (110) accommodating a positive column of the DC plasma, A reference plate (R) made of a conductive material, the reference plate being arranged in a region (G3) of the DC plasma reaction chamber (110) containing the positive column of the DC plasma, so that a first surface potential (V R ) is equal to the second surface potential (V FP ), the first surface potential and the second surface potential (V R , V FP ) based on the potential of the DC plasma in the positive column (V PP ); as well as Control electronics (320) configured to measure the first surface potential (V R ) and adjust the potential (V A ) to reduce the second surface potential (V FP ) is adjusted to a reference potential; as well as A bias signal generator (480) capacitively coupled to the substrate support stage (S), the bias signal generator (480) being configured to generate a periodic bias signal (V(t)) having a voltage referenced to the reference potential, the periodic bias signal (V(t)) comprising: With positive voltage (V B ) activation phase (ΔT BP ); With negative voltage (V BN ) in the neutralization phase (ΔT BN );as well as Initialization phase with zero voltage (ΔT BP ).

2. The direct current (DC) plasma processing system of claim 1, wherein: The positive voltage (V B ) is a preset voltage based on a known reaction threshold voltage (V RTH ).

3. The direct current (DC) plasma processing system of claim 1, wherein: The positive voltage (V B ) is equal to or greater than a reaction threshold voltage (V RTH ).

4. A direct current (DC) plasma processing system according to claim 3, wherein: The positive voltage (V B ) is less than a reaction threshold voltage (V'RTH) of non-target chemical bonds of atoms at the surface of the substrate.

5. The direct current (DC) plasma processing system of claim 3, wherein: The positive voltage (V B ) is strictly greater than the reaction threshold voltage (V RTH ) to the total duration of the activation phase (ΔT BP ) in the range of 1 / 4 to 3 / 4 of the duration (t BH ).

6. The direct current (DC) plasma processing system of claim 3, wherein: The negative voltage (V BN ) has a sufficiently low size so that the energy level of the free ions in the positive column remains below the reaction energy level (E) of all chemical bonds of the atoms at the surface of the substrate. B ).

7. A direct current (DC) plasma processing system according to any one of claims 1 to 6, wherein: The DC content of the periodic bias signal (V(t)) is zero.

8. A direct current (DC) plasma processing system according to claim 7, wherein: The frequency of the periodic bias signal (V(t)) is in the range from 100 kHz to 1 MHz.

9. A direct current (DC) plasma processing system according to claim 8, wherein: The activation phase (ΔT BP ) time length (ΔT BP ) and the neutralization stage (ΔT BZ ) time length (ΔT BZ ) is in the range from 1 / 10 to 1 / 1.

10. The direct current (DC) plasma processing system of claim 9, wherein: The initialization phase (ΔT BZ ) time length (ΔT BZ ) to the time length (TEEMP) of one cycle of the periodic bias signal (V(t)) is approximately 1 / 4.

11. A direct current (DC) plasma processing system according to any one of claims 2 to 6, wherein: The target chemical bonds belong to atoms of a material composed of one of the following: a) a single crystal or 2D material; b) a metal; or c) a complex material or a 3D material.

12. The direct current (DC) plasma processing system of claim 11, wherein: The single crystal or 2D material includes a semiconductor material or an insulator material.

13. The direct current (DC) plasma processing system of claim 12, wherein: The activation phase (ΔT BP ) time length (ΔT BP ) and the neutralization stage (ΔT BZ ) time length (ΔT BZ ) is about 1 / 10.

14. The direct current (DC) plasma processing system of claim 11, wherein: The target chemical bond belongs to an atom of a metal or a metal alloy, and The activation phase (ΔT BP ) time length (ΔT BP ) and the neutralization stage (ΔT BZ ) time length (ΔT BZ ) is about 1 / 2.

15. The direct current (DC) plasma processing system of claim 11, wherein: The complex material includes one of a polymer, a composite material, or a three-dimensional material.

16. The direct current (DC) plasma processing system of claim 15, wherein: The activation phase (ΔT BP ) time length (ΔT BP ) and the neutralization stage (ΔT BZ ) time length (ΔT BZ ) is about 1 / 1.

17. A direct current (DC) plasma processing system according to any one of claims 1 to 6, wherein: The periodic bias signal (V(t)) includes a predistortion (WF P ), the predistortion is configured to reduce the activation phase (ΔT BP ) during the ringing period.

18. A direct current (DC) plasma processing system according to any one of claims 1 to 6, wherein: The bias signal generator (480) comprises a digital signal generator configured to receive digital samples, the digital samples comprising a distortion compensation (WF) for generation of the periodic bias signal (V(t)) P ).

19. The direct current (DC) plasma processing system of claim 18, wherein: The bias signal generator (480) further comprises a band-limited linear power amplifier, the band-limited linear power amplifier being configured to receive the output of the digital signal generator to generate the periodic bias signal (V(t)) according to the output, The band-limited linear power amplifier comprises a gain (G1) that is flat within 0.75 dB over a frequency range from 10 KHz to 10 MHz, and The band limited linear power amplifier is configured to substantially block harmonics of the periodic bias signal (V(t)).

20. A method for treating a surface of a substrate, the method comprising: placing a substrate on a substrate support table (S) in a region (G3) of a DC plasma reaction chamber (110) configured to generate a positive column of DC plasma; generating the DC plasma; A reference plate (R) made of a conductive material is arranged in a region (G3) of the DC plasma reaction chamber (110) containing the positive column of the DC plasma, so that a first surface potential (V R ) is equal to the second surface potential (V FP ), the first surface potential and the second surface potential (V R , V FP ) based on the potential of the DC plasma in the positive column (V PP ); as well as Measure the first surface potential (V R ) and adjust the potential (V A ) to reduce the second surface potential (V FP ) is adjusted to a reference potential; as well as Capacitively coupling a periodic bias signal (V(t)) having a bias voltage to the support stage (S), wherein the bias voltage is referenced to the reference potential, the periodic bias signal (V(t)) comprising: With positive voltage (V B ) activation phase (ΔT BP ); With negative voltage (V BN ) in the neutralization phase (ΔT BN );as well as Initialization phase with zero voltage (ΔT BZ ).

21. The method of claim 20, wherein: The positive voltage (V B ) based on the known reaction threshold voltage (V RTH ).

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