Memory cell based on 9T1C structure, its operation method, and memory

Abstract

The present invention discloses an nvsram storage cell based on a 9T1C structure, an operation method thereof, and a memory, including a 6T structure and a 3T1C structure. The 6T structure is the basic storage cell of SRAM and is used for data input and storage of data 0 or 1. The 3T1C structure is used to perform data backup operations when the 6T structure is powered off, store the data in the 6T structure, perform data recovery on the 6T structure after the 6T structure resumes power, and rewrite the data back to the storage cell of the 6T structure. By controlling the plate line signal (PL) through an NMOS transistor, the influence of the PL signal on the ferroelectric capacitor can be avoided when working under this structure, ensuring the stability of the ferroelectric capacitor and reducing power consumption. By isolating the NVM and SRAM with an NMOS transistor at the storage node of the SRAM, the problem of direct current short-circuit current is avoided, the influence of the NVM on the SRAM is relatively small, the storage power consumption is reduced, and the stability of the SRAM working mode is ensured at the same time. NMOS transistors are added at both Q / NQ of the SRAM, maintaining the symmetry of the SRAM storage cell and avoiding the mismatch problem.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor memory, and particularly relates to a memory cell based on a 9T1C structure, an operation method thereof, and a memory. Background Art

[0002] As one of the high-end non-volatile memories, nvSRAM is applied to various normally-off non-volatile fields. It not only preserves the characteristics of SRAM for high-speed and low-power data storage, but also can implement the function of data backup for SRAM when power is off. nvSRAM mainly combines NVM and SRAM to achieve the non-volatile function. Early nvSRAMs mainly adopted a dual-macro structure to achieve the non-volatile function, resulting in the disadvantages of slow data transmission and easy data loss. With the continuous development of process technology, the on-chip integration method of NVM and SRAM is the current mainstream implementation scheme. The NVSRAM cell performs parallel transmission between each cell of the SRAM and the NVM device, and has the characteristics of low power consumption and parallel data recovery, so it is widely favored in the application of the Internet of Things. The principle of nvSRAM not only maintains the working mode of traditional SRAM, but also adds the data preservation and data recovery modes. When the system is working normally, nvSRAM is the same as SRAM, and the NVM is in the off mode, making the static power consumption of the system small. When the system is in the power-off mode, the system switches to the data preservation mode at this time. Under the control of the peripheral circuit, the data in the memory cells are respectively stored in the NVM according to the order of address decoding to achieve the function of data preservation. When the power of the system is restored, the data in the NVM is sequentially restored to the memory cells of the SRAM to achieve the function of data recovery. This parallel connection method has a high data transmission speed and avoids the risk of data loss during long-term data transmission.

[0003] At present, various NVSRAM cells have been developed by using magnetic tunnel combined with resistive memory devices, such as 4T2R, 6T2R, 7T2R, 8T2R and 7T1R NVSRAM cells of various structural forms. However, the NVSRAM cells of various structural forms in the prior art still have various defects: although the NVSRAM cells of 4T2R, 6T2R and 7T2R structural forms have a small area, they suffer from a large DC short-circuit current at the storage nodes (Q and NQ), and the stability of the 6T structural cell is significantly reduced in the SRAM mode; while the 8T2R structure that uses MOS tubes to separate the storage node of SRAM from the NVM avoids the problem of DC short-circuit current, the isolated NVM has little effect on the performance of SRAM, has good stability and achieves a high recovery rate, but at the same time consumes a large memory area, so it consumes a lot of storage and recovery power consumption; the NVSRAM cell of the 7T1R structural form based on RRAM can reduce storage power consumption and avoid DC current of the storage node, but the number of storage and recovery is relatively low.

[0004] With the development of science and technology, the demand for memory in various electronic devices is increasing, and the performance of memory is also receiving more and more attention. Among them, ferroelectric memory has obvious advantages in new memory due to its high erase and write times, high durability and high read and write speed. However, the data of traditional ferroelectric memory will be lost after power failure, which is a problem in applications that require data to be permanently stored. 2) Solutions of the prior art: In order to solve this problem, the existing technical solution usually combines ferroelectric memory with static random access memory (SRAM) to form a non-volatile static random access memory (NVSRAM). This solution utilizes the non-volatile characteristics of ferroelectric memory to save data after power failure, and restore the data to SRAM after power is turned on. 3) Problems of the prior art: However, the existing NVSRAM solution still has some problems in practical applications. First, due to the connection method between ferroelectric memory and SRAM, it may cause the problem of DC short-circuit current and increase storage power consumption. Secondly, the existing solution may destroy the symmetry of SRAM storage cells, resulting in mismatch problems. In addition, the existing solution may cause problems such as slow PL power-on speed, weak recovery ability, and high power consumption during data recovery. Summary of the invention

[0005] The purpose of the present invention is to provide an nvsram storage unit based on a 9T1C structure and an operation method thereof, and a memory, so as to solve the above-mentioned problems existing in the prior art.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The first aspect of the present invention provides a non-volatile static random access memory (nvsram) storage cell based on a 9T1C structure, including a 6T structure and a 3T1C structure. The 6T structure is the basic storage cell of SRAM, used for data input and storage of data 0 or 1. The 3T1C structure is used to perform data backup operations when the 6T structure is powered off, store the data in the 6T structure, and perform data recovery on the 6T structure after the 6T structure resumes power, and rewrite the data back to the storage cell of the 6T structure.

[0008] The 3T1C structure includes a first switching transistor, a second switching transistor, a third switching transistor, and a ferroelectric capacitor.

[0009] The source of the first switching transistor is connected to the first storage point of the 6T structure. The gate of the first switching transistor is electrically connected to the VRCL line, and the VRCL line is used to provide a voltage to the gate of the first switching transistor (NM1). The drain of the first switching transistor is electrically connected to one end of the ferroelectric capacitor. The other end of the ferroelectric capacitor is connected to the drain of the second switching transistor and the drain of the third switching transistor. The source of the second switching transistor is electrically connected to the second storage point of the 6T structure. The gate of the second switching transistor is electrically connected to the VNP line, and the VNP line is used to provide a gate voltage to the second switching transistor (NM2). The source of the third switching transistor is electrically connected to the VCCI line, and the VCCI line is used to provide a source voltage to the third switching transistor (NM3). The gate of the third switching transistor is electrically connected to the VBP line, and the VBP line is used to provide a gate voltage to the third switching transistor (NM3). The first switching transistor is used to transfer the information of the second storage point of the 6T structure to one end of the ferroelectric capacitor. The second switching transistor is used to transfer the information of the second storage point of the 6T structure to the other end of the ferroelectric capacitor. The third switching transistor is used for the switching operation of data recovery.

[0010] According to the above technology, by controlling the plate line signal (PL) of the transistor, the influence of the PL signal on the ferroelectric capacitor can be avoided when working under this structure, ensuring the stability of the ferroelectric capacitor and reducing power consumption. By isolating the NVM and SRAM with NMOS transistors at the storage nodes of the SRAM, the problem of direct current short-circuit current is avoided. The influence of the NVM on the SRAM is relatively small, reducing the storage power consumption, and at the same time ensuring the stability of the SRAM working mode. NMOS transistors are added at both the Q / NQ of the SRAM, which is more friendly to the basic unit structure of the SRAM, maintaining the symmetry of the SRAM storage cell and avoiding the mismatch problem.

[0011] Further, the first switching transistor, the second switching transistor, and the third switching transistor are all NMOS transistors.

[0012] Further, the 6T structure includes:

[0013] The first inverter is configured to provide a first storage node for storing data 1 or 0;

[0014] The second inverter is cross-coupled with the first inverter and symmetrically arranged therewith, and is configured to provide a second storage node, where when the first storage node stores data 0, the second storage node stores data 1, and when the first storage node stores data 1, the second storage node stores data 0.

[0015] Further, the first inverter includes:

[0016] The first upper transistor, whose source is connected to the VCCT line,

[0017] The first lower transistor is symmetrically arranged with the first upper transistor in a first direction. The source of the first lower transistor is connected to the drain of the first upper transistor, the drain is grounded, and the gate is connected to the gate of the first upper transistor.

[0018] Further, the second inverter includes:

[0019] The second upper transistor is symmetrically arranged with the first upper transistor in a second direction, and its source is connected to the VCCT line,

[0020] The second lower transistor is symmetrically arranged with the second upper transistor in the first direction and symmetrically arranged with the first lower transistor in the second direction. The source of the second lower transistor is connected to the drain of the second upper transistor, the drain is grounded, and the gate is connected to the gate of the second upper transistor.

[0021] Further, the 6T structure further includes:

[0022] The first access transistor, whose gate is connected to the word line WL, the source is connected to the first storage node, and the drain is connected to the bit line complementary BLB,

[0023] The second access transistor is symmetrically arranged with the first access transistor in the second direction. The gate is connected to the word line WL, the source is connected to the second storage node, and the drain is connected to the bit line BL.

[0024] Further, the first storage node is connected to the drain of the first upper transistor of the first inverter and the gate of the second upper transistor of the second inverter;

[0025] The second storage node is connected to the gate of the first upper transistor of the first inverter and the drain of the second upper transistor of the second inverter.

[0026] A second aspect of the present invention provides an operation method of an nvsram storage cell based on a 9T1C structure as described in the first aspect and any one of the designs of the first aspect, including:

[0027] When the power supply of the NVRAM is normal, the first switching transistor, the second switching transistor, and the third switching transistor are all turned off, and the NVRAM realizes normal reading and writing of data through 6T memory cells;

[0028] In response to the power-off operation of the NVRAM memory cell, the first switching transistor and the second switching transistor are turned on, and the third switching transistor is turned off; the data of the two storage nodes of the 6T structure are one 0 and one 1, which are input to the two plates of the ferroelectric capacitor to form a voltage difference, and the ferroelectric capacitor changes its polarization state with the voltage difference, so as to store the data of the NQ point for data backup;

[0029] In response to the NVRAM memory cell resuming power-on operation, the first switching transistor and the third switching transistor are turned on, and the second switching transistor is turned off. At this time, VCCI gives a voltage pulse, which is transmitted to the lower plate of the ferroelectric capacitor through NM3, and the ferroelectric capacitor starts to discharge, and the data is read out into the first storage point, and the data is restored through two inverters in two SRAMs.

[0030] The third aspect of the present invention provides a memory based on a 9T1C-structured NVRAM memory cell, which has a memory cell array structure, and the memory cell array structure includes a plurality of first aspects and the 9T1C-structured NVRAM memory cell according to any one of the first aspects.

[0031] Beneficial effects: By isolating the NVM and SRAM with NMOS transistors at the storage nodes of the SRAM, the problem of direct current short-circuit current is avoided. The influence of the NVM on the SRAM is relatively small, the storage power consumption is reduced, and the stability of the SRAM working mode is ensured. NMOS transistors are added at both the Q / NQ of the SRAM, which is more friendly to the basic unit structure of the SRAM, maintains the symmetry of the SRAM memory cell, and avoids the mismatch problem. In other structures, the connection problem of the PL will lead to slow power-on speed, weak recovery ability, and high power consumption. In this 9T1C structure, only in the data recovery stage, the PL is controlled to turn on through an NM3 switch, with faster power-on speed, lower power consumption, and higher data recovery rate. Description of the Drawings

[0032] Figure 1 It is the circuit schematic diagram of the 9T1C-structured NVRAM memory cell provided in the first aspect of the embodiment;

[0033] Figure 2 It is the three working mode diagrams of the operation method of the 9T1C-structured NVRAM memory cell provided in the second aspect of the embodiment;

[0034] Figure 3It is the operation timing diagram of the nvsram memory cell with a 9T1C structure in the embodiment. Detailed implementation manners

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below with reference to the accompanying drawings and the descriptions of the embodiments or the prior art. Obviously, the following descriptions of the structures of the accompanying drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other accompanying drawings can be obtained based on these drawings without creative efforts. It should be noted here that the descriptions of these embodiments are used to help understand the present invention, but do not constitute a limitation to the present invention. It should be noted that the directional terms mentioned in the embodiments, such as "upper" and "lower", are only references to the directions of the accompanying drawings and are not used to limit the protection scope of the present disclosure. Throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. When it may cause confusion in the understanding of the present disclosure, the conventional structures or configurations will be omitted.

[0036] Embodiment:

[0037] With the continuous development of new memories, the ferroelectric memory has obvious advantages in high erase / write times, high durability, and high read / write speed among new memories. The ferroelectric NVM+SRAM solution has natural advantages compared with the NVM+SRAM solutions of other storage media. This embodiment is mainly based on combining a ferroelectric capacitor as a non-volatile storage medium with a 6T memory cell of SRAM.

[0038] As Figure 1 shown, in the first aspect of this embodiment, a nvsram memory cell based on a 9T1C structure is provided, which includes a 6T structure and a 3T1C structure. The 6T structure is the basic memory cell of SRAM and is used for data input and storage of data 0 or 1. The 3T1C structure is used to perform data backup operations when the 6T structure is powered off, store the data in the 6T structure, and perform data recovery on the 6T structure after the 6T structure resumes power, and rewrite the data back to the memory cell of the 6T structure.

[0039] The 3T1C structure includes a first switching transistor NM1, a second switching transistor NM2, a third switching transistor NM3, and a ferroelectric capacitor Cfe.

[0040] The source of the first switching transistor NM1 is connected to the NQ storage point of the 6T structure. The gate of the first switching transistor NM1 is electrically connected to the VRCL line, and the VRCL line is used to provide a voltage to the gate of the first switching transistor (NM1). The drain of the first switching transistor NM1 is electrically connected to one end of the ferroelectric capacitor Cfe. The other end of the ferroelectric capacitor Cfe is connected to the drain of the second switching transistor NM2 and the drain of the third switching transistor NM3. The source of the second switching transistor NM2 is electrically connected to the Q storage point of the 6T structure. The gate of the second switching transistor NM2 is electrically connected to the VNP line, and the VNP line is used to provide a gate voltage to the second switching transistor (NM2). The source of the third switching transistor NM3 is electrically connected to the VCCI line, and the VCCI line is used to provide a source voltage to the third switching transistor (NM3). The gate of the third switching transistor NM3 is electrically connected to the VBP line, and the VBP line is used to provide a gate voltage to the third switching transistor (NM3). The first switching transistor NM1 is used to transfer the NQ storage point information of the 6T structure to one end of the ferroelectric capacitor Cfe. The second switching transistor NM2 is used to transfer the Q storage point information of the 6T structure to the other end of the ferroelectric capacitor Cfe. The third switching transistor NM3 is used for the switching operation of data recovery.

[0041] As Figure 1 shown, where the 6T structures M1 - M6 are the basic storage units of SRAM, used for data input and storage of data 0 or 1. The first switching transistor NM1, the second switching transistor NM2, the third switching transistor NM3, and the ferroelectric capacitor Cfe serve as a backup and recovery unit. NM1 is connected to the NQ storage point, NM2 is connected to the Q storage point, and NM3 is the data recovery switch. This nvsram storage unit has three operating modes: SRAM mode, data backup mode, and data recovery mode, as specifically Figure 2 shown. When it is sensed that the nvsram storage unit is powered off, a data backup operation is performed to store the data in SRAM. After the chip is restored to power, data recovery is carried out to rewrite the data back into the storage unit of SRAM, realizing data reload recovery. By adding the 3T1C structure, without changing the read and write of the existing SRAM, data can be saved when powered off and recovered when powered on through the ferroelectric capacitor. At the same time, the switching transistor is used to isolate the SRAM storage unit and the ferroelectric capacitor to prevent DC short - circuit and ensure the stability of the SRAM storage unit. By adding the NM3 transistor, which is only turned on during the data recovery stage to control the input of the external voltage pulse, the storage power consumption is greatly reduced, the operation speed is faster, and a higher data recovery rate is ensured.

[0042] In this embodiment, considering that the storage nodes of the SRAM store "0" and "1", they can themselves serve as the inputs of the two electrodes of the ferroelectric capacitor. The voltage across the ferroelectric capacitor is input through the two storage nodes, eliminating the need to add a PL pulse. For the backup phase of the NVSRAM, the control is simpler and the power consumption is lower. In the data recovery phase, a voltage pulse is applied to the ferroelectric capacitor by controlling the NM3 switch. Compared with other structures, the PL does not require additional control, and the NM3 is only turned on when recovering the data of this bit, resulting in a faster power-on speed, lower power consumption, and higher recovery rate.

[0043] In a possible implementation manner, the first switching transistor NM1, the second switching transistor NM2, and the third switching transistor NM3 are all NMOS transistors.

[0044] Specifically, the 6T structure includes:

[0045] A first inverter for providing a first storage node NQ to store data 1 or 0;

[0046] A second inverter, cross-coupled with the first inverter and symmetrically arranged with respect to each other, for providing a second storage node Q. When the first storage node NQ stores data 0, the second storage node Q stores data 1, and when the first storage node NQ stores data 1, the second storage node Q stores data 0.

[0047] Specifically, the first inverter includes:

[0048] A first upper transistor M3, whose source is connected to the VCCT line,

[0049] A first lower transistor M5, symmetrically arranged with the first upper transistor M3 in a first direction. The source of the first lower transistor M5 is connected to the drain of the first upper transistor M3, the drain is grounded, and the gate is connected to the gate of the first upper transistor M3.

[0050] Specifically, the second inverter includes:

[0051] A second upper transistor M4, symmetrically arranged with the first upper transistor M3 in a second direction, and whose source is connected to the VCCT line,

[0052] A second lower transistor M6, symmetrically arranged with the second upper transistor M4 in a first direction and symmetrically arranged with the first lower transistor M5 in a second direction. The source of the second lower transistor M6 is connected to the drain of the second upper transistor M4, the drain is grounded, and the gate is connected to the gate of the second upper transistor M4.

[0053] Specifically, the 6T structure further includes:

[0054] The first access transistor M1 has its gate connected to the word line WL, its source connected to the first storage node NQ, and its drain connected to the inverted bit line BLB.

[0055] The second access transistor M2 is symmetrically arranged with the first access transistor M1 in the second direction. Its gate is connected to the word line WL, its source is connected to the second storage node Q, and its drain is connected to the bit line BL.

[0056] Specifically, the first storage node NQ is connected to the drain of the first upper transistor M3 of the first inverter and the gate of the second upper transistor M4 of the second inverter.

[0057] The second storage node Q is connected to the gate of the first upper transistor M3 of the first inverter and the drain of the second upper transistor M4 of the second inverter.

[0058] In the second aspect of this embodiment, a method for operating an nvsram storage cell based on a 9T1C structure is provided. The nvsram storage cell based on the 9T1C structure described in the first aspect is used. The method includes:

[0059] When the power supply of the nvsram storage cell is normal, the nvsram is in the SRAM mode at this time. NM1 to NM3 are turned off, and the nvsram storage cell realizes normal data reading and writing through a 6T storage cell, ensuring the high performance and low power consumption of the storage chip.

[0060] When the induced current detects abnormal power-off of the power supply, the nvsram storage cell is in the data backup mode at this time. NM1 and NM2 are turned on, and NM3 is turned off. One of the data of the two storage nodes of the SRAM storage cell is 0 and the other is 1, which are input to the two plates of the ferroelectric capacitor to form a voltage difference. The ferroelectric capacitor changes its polarization state with the voltage difference, thereby storing the data at the NQ point and realizing data backup, that is, Figure 3 In operation 1 mode, operation 1 mode is the storage mode Store Model in the figure. This structure directly uses the difference between the two storage points of the SRAM storage cell as the input voltage of the ferroelectric capacitor, without an additional PL line input, and the control is simpler and the power consumption is lower.

[0061] When the nvsram storage cell resumes power-on, the induction module senses the power-on recovery. At this time, the nvsram storage cell is in the data recovery mode. NM1 and NM3 are turned on, and NM2 is turned off. At this time, VCCI gives a voltage pulse, which is transmitted to the lower plate of Cfe through NM3, and Cfe starts to discharge. The data is read out into NQ, and the data recovery is realized through two inverters in the two SRAM storage cells, that is, Figure 3In the operation 2 mode, the operation 2 mode is the Restore Model in the figure. Among them, VCCI is actually equivalent to the PL pulse of other structures. The input of the PL pulse is controlled by the switch of NM3, and NM3 is only turned on when the bit data is restored. Compared with the long PL line of other structures, the control is simple, the power-on speed is faster, and the power consumption is lower.

[0062] In a third aspect, the present embodiment provides a memory based on a 9T1C-structured nvsram storage cell, having a storage cell array structure, and the storage cell array structure includes a plurality of first aspects and the 9T1C-structured nvsram storage cells of any one of the implementation manners in the first aspect.

[0063] The nvsram storage cell based on the 9T1C structure provided in this embodiment isolates the NVM and SRAM at the storage nodes Q and NQ of the SRAM by using NMOS transistors, avoiding the problem of direct current short-circuit current. The influence of the NVM on the SRAM storage cell is relatively small, reducing the storage power consumption, and at the same time ensuring the stability of the SRAM working mode. The board line signal (PL) is controlled by the NMOS transistor. When working in this structure, the influence of the PL signal on the ferroelectric capacitor can be avoided, ensuring the stability of the ferroelectric capacitor and reducing the power consumption. NMOS transistors are added at both Q / NQ of the SRAM, which is more friendly to the basic unit structure of the SRAM, maintaining the symmetry of the SRAM storage cell and avoiding the mismatch problem. In other structures, the connection problem of the PL will lead to a slow power-on speed, weak recovery ability, and high power consumption. In this 9T1C structure, only in the data recovery stage, the opening of the PL is controlled by an NM3 switch, with a faster power-on speed, lower power consumption, and higher data recovery rate.

[0064] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A nvsram storage unit based on a 9T1C structure, characterized in that: It includes a 6T structure and a 3T1C structure, wherein the 6T structure is a basic storage unit of SRAM, used for data input and storage of data 0 or 1; the 3T1C structure is used to perform a data backup operation when the 6T structure is powered off, store the data in the 6T structure, and restore the data of the 6T structure after the 6T structure is powered on again, and rewrite the data back to the storage unit of the 6T structure. The 3T1C structure includes a first switch transistor (NM1), a second switch transistor (NM2), a third switch transistor (NM3) and a ferroelectric capacitor (Cfe). The source of the first switch transistor (NM1) is connected to the first storage point (NQ) of the 6T structure, the gate of the first switch transistor (NM1) is electrically connected to the VRCL line, and the VRCL line is used to provide a voltage to the gate of the first switch transistor (NM1), the drain of the first switch transistor (NM1) is electrically connected to one end of the ferroelectric capacitor (Cfe), and the other end of the ferroelectric capacitor (Cfe) is connected to the drain of the second switch transistor (NM2) and the drain of the third switch transistor (NM3), the source of the second switch transistor (NM2) is electrically connected to the second storage point (Q) of the 6T structure, and the gate of the second switch transistor (NM2) is electrically connected to the VNP line, and the VNP line is used to provide a voltage to the second switch transistor The first switch transistor (NM1) is used to transmit the second storage point (Q) information of the 6T structure to one end of the ferroelectric capacitor (Cfe), the second switch transistor (NM2) is used to transmit the second storage point (Q) information of the 6T structure to the other end of the ferroelectric capacitor (Cfe), and the third switch transistor (NM3) is used for switching operation of data recovery.

2. The nvsram storage unit based on the 9T1C structure according to claim 1, characterized in that: The first switch transistor (NM1), the second switch transistor (NM2) and the third switch transistor (NM3) are all NMOS transistors.

3. The nvsram storage unit based on the 9T1C structure according to claim 1, characterized in that: The 6T structure includes: A first inverter, used for providing a first storage node (NQ) to store data 1 or 0; The second inverter is cross-coupled with the first inverter and symmetrically arranged to provide a second storage node (Q). The second storage node (Q) stores data 1 when the first storage node (NQ) stores data 0, and stores data 0 when the first storage node (NQ) stores data 1.

4. The nvsram storage unit based on the 9T1C structure according to claim 3, characterized in that: The first inverter comprises: A first upper transistor (M3) having a source electrically connected to a VCCT line, the VCCT line being used to provide a power supply voltage; The first lower transistor (M5) is symmetrically arranged with the first upper transistor (M3) in the first direction, the source of the first lower transistor (M5) is connected to the drain of the first upper transistor (M3), the drain is grounded, and the gate is connected to the gate of the first upper transistor (M3).

5. The nvsram storage unit based on the 9T1C structure according to claim 4, characterized in that: The second inverter comprises: The second upper transistor (M4) is symmetrically arranged with the first upper transistor (M3) in the second direction, and the source is connected to the VCCT line. The second lower transistor (M6) is symmetrically arranged with the second upper transistor (M4) in the first direction, and is symmetrically arranged with the first lower transistor (M5) in the second direction, the source is connected to the drain of the second upper transistor (M4), the drain is grounded, and the gate is connected to the gate of the second upper transistor (M4).

6. The nvsram storage unit based on the 9T1C structure according to claim 3, characterized in that: The 6T structure further includes: A first access transistor (M1) has a gate connected to the word line WL, a source connected to the first storage node (NQ), and a drain connected to the inverted bit line BLB. The second access transistor (M2) is symmetrically arranged with the first access transistor (M1) in the second direction, has a gate connected to the word line WL, a source connected to the second storage node (Q), and a drain connected to the bit line BL.

7. The nvsram storage unit based on the 9T1C structure according to claim 6, characterized in that: The first storage node (NQ) is connected to the drain of the first upper transistor (M3) of the first inverter and the gate of the second upper transistor (M4) of the second inverter; The second storage node (Q) is connected to a gate of a first upper transistor (M3) of the first inverter and a drain of a second upper transistor (M4) of the second inverter.

8. An operation method of a 9T1C structured nvsram storage unit according to any one of claims 1 to 7, characterized in that: include: When the power supply of the nvsram storage unit is normal, the first switch transistor (NM1), the second switch transistor (NM2) and the third switch transistor (NM3) are all turned off, and the nvsram realizes normal reading and writing of data through the 6T storage unit; In response to the power-off operation of the nvsram storage unit, the first switch transistor (NM1) and the second switch transistor (NM2) are turned on, and the third switch transistor (NM3) is turned off; the data of the two storage nodes of the 6T structure are 0 and 1 respectively, and are input to the two plates of the ferroelectric capacitor (Cfe), forming a voltage difference. The ferroelectric capacitor (Cfe) changes with the voltage difference, thereby changing the polarization state, thereby storing the data of the NQ point, so as to realize data backup; In response to the nvsram storage unit resuming power-on operation, the first switch transistor (NM1) and the third switch transistor (NM3) are turned on, and the second switch transistor (NM2) is turned off. At this time, VCCI gives a voltage pulse, which is transmitted to the lower plate of the ferroelectric capacitor (Cfe) through the third switch transistor (NM3). The ferroelectric capacitor (Cfe) starts to discharge, and the data is read out to the first storage point (NQ). Data recovery is achieved through the two inverters in the two SRAMs.

9. A memory based on a 9T1C structured nvsram storage unit, having a storage unit array structure, characterized in that: The memory cell array structure comprises a plurality of nvsram memory cells of the 9T1C structure according to any one of claims 1 to 7.

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