Semiconductor Devices

Abstract

The present invention relates to a semiconductor device, comprising a high-voltage device region, a low-voltage device region, a first device region and a first isolation structure located between the high-voltage device region and the low-voltage device region, and further comprising a first isolation region, the first isolation region being connected to the first isolation structure, the first isolation region and the first isolation structure together surrounding the first device region; the first isolation region comprising: an isolation well having a second conductivity type and being connected to the first isolation structure; a second isolation structure extending downward from the top of the isolation well and penetrating the bottom of the isolation well, so that the depth of the second isolation structure is greater than the depth of the isolation well, and the second isolation structure comprising an insulating medium. The present invention can reduce leakage current while taking into account the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device. Background Art

[0002] An exemplary high-voltage integrated circuit includes a high-voltage circuit, a low-voltage circuit, and a high-voltage power device. This structure is often used in a level-shifted self-shielded LDMOS, that is, the LDMOS is embedded in an isolation well between a high-voltage region and a low-voltage region, which can avoid high-voltage cross-line. However, due to the leakage of the resistor between the drain end and the high-voltage region, one solution is to insert a P well between the drain end and the high-voltage region to prevent leakage, but this will bring additional electric field peaks due to the introduction of a PN junction. Summary of the invention

[0003] Based on this, the present application provides a semiconductor device that can solve the aforementioned leakage problem while taking into account the breakdown voltage of the device.

[0004] A semiconductor device comprises a high-voltage device region, a low-voltage device region, a first device region and a first isolation structure located between the high-voltage device region and the low-voltage device region, and also comprises a first isolation region, wherein the first isolation region is connected to the first isolation structure, and the first isolation region and the first isolation structure together surround the first device region; the first isolation region comprises: an isolation well having a second conductivity type and being connected to the first isolation structure; a second isolation structure extending downward from the top of the isolation well and penetrating the isolation well, so that the depth of the second isolation structure is greater than the depth of the isolation well, and the second isolation structure comprises an insulating medium; the semiconductor device also comprises: a source region having a first conductivity type and being located in the first isolation structure, and the source region is the source region of the first device; a drain region having a first conductivity type and being located in the first device region, and the drain region is the drain region of the first device; wherein part of the structure of the first device is located in the first device region and part of the structure is located in the first isolation structure at the edge of the first device region, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0005] In the semiconductor device, a first isolation region is provided between the high-voltage device region and the drain region of the first device, and the first isolation region includes a second isolation structure having an insulating medium, which plays an electrical isolation role and can reduce the leakage current between the high-voltage device region and the first device. The second isolation structure has a larger depth and a smaller depth of the isolation well, so that the breakdown voltage of the device can be taken into account while reducing the leakage current.

[0006] In one embodiment, there are a plurality of second isolation structures separated from each other by the isolation well.

[0007] In one embodiment, the second isolation structure includes the insulating medium located in the trench and also includes a conductive structure located in the trench; the insulating medium is a dielectric layer located on the inner wall of the trench, surrounding the bottom and side surfaces of the conductive structure.

[0008] In one embodiment, the material of the dielectric layer includes silicon oxide.

[0009] In one embodiment, the material of the conductive structure includes polysilicon.

[0010] In one embodiment, the first isolation structure includes a second conductivity type well region.

[0011] In one embodiment, the first device is a power device.

[0012] In one embodiment, the first device is a laterally diffused metal oxide semiconductor field effect transistor.

[0013] In one of the embodiments, the first device region further includes: a drift region having a first conductivity type and at least partially located between the source region and the drain region.

[0014] In one embodiment, the first device region further includes: a field oxide layer located on the drift region; and a gate having one end extending onto the field oxide layer and the other end extending toward the source region.

[0015] In one of the embodiments, the first device region further includes: a substrate lead-out region having a second conductivity type and located in the first isolation structure.

[0016] In one of the embodiments, the first device region further includes: a depth of the isolation well is not less than a depth of the drift region.

[0017] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0018] Based on a general inventive concept, the present application provides another semiconductor device.

[0019] A semiconductor device comprises a high-voltage device region, a low-voltage device region, a first device region and a first isolation structure located between the high-voltage device region and the low-voltage device region, and further comprises a first isolation region, wherein the first isolation region is connected to the first isolation structure, and the first isolation region and the first isolation structure together surround the first device region, wherein the first isolation region comprises: a PN junction isolation structure, comprising a first conductive type region and a second conductive type region located above and below the first conductive type region, wherein the PN junction isolation structure is connected to the first isolation structure; a second isolation structure, extending downward from the top of the PN junction isolation structure, wherein the second isolation structure comprises an insulating medium; the semiconductor device further comprises: a source region, having a first conductive type, located in the first isolation structure, wherein the source region is a source region of the first device; a drain region, having a first conductive type, located in the first device region, wherein the drain region is a drain region of the first device; wherein a portion of the structure of the first device is located in the first device region and a portion of the structure is located in the first isolation structure at the edge of the first device region, and the first conductive type and the second conductive type are opposite conductive types.

[0020] In the semiconductor device, a PN junction isolation structure is used in the first isolation region instead of an isolation well of the second conductivity type for isolation. The PN junction isolation structure can form self-depletion, and the isolation leakage effect of the depletion region is better (relative to the isolation well of the second conductivity type). The first isolation region can reduce the leakage current while taking into account the breakdown voltage of the device through the reasonable combination of the PN junction isolation structure and the second isolation structure with an insulating medium.

[0021] In one embodiment, the PN junction isolation structure is a super junction structure.

[0022] In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the PN junction isolation structure is a PNP super junction structure.

[0023] In one embodiment, there are a plurality of second isolation structures separated from each other by the isolation well.

[0024] In one embodiment, the second isolation structure includes the insulating medium located in the trench and also includes a conductive structure located in the trench; the insulating medium is a dielectric layer located on the inner wall of the trench, surrounding the bottom and side surfaces of the conductive structure.

[0025] In one embodiment, the material of the dielectric layer includes silicon oxide.

[0026] In one embodiment, the conductive structure is made of polysilicon.

[0027] In one embodiment, the first isolation structure includes a second conductivity type well region.

[0028] In one embodiment, the first device is a power device.

[0029] In one embodiment, the first device is a laterally diffused metal oxide semiconductor field effect transistor.

[0030] In one of the embodiments, the first device region further includes: a drift region having a first conductivity type and at least partially located between the source region and the drain region.

[0031] In one embodiment, the first device region further includes: a field oxide layer located on the drift region; and a gate having one end extending onto the field oxide layer and the other end extending toward the source region.

[0032] In one of the embodiments, the first device region further includes: a substrate lead-out region having a second conductivity type and located in the first isolation structure.

[0033] In one of the embodiments, the first device region further includes: a depth of the isolation well is not less than a depth of the drift region. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0035] Figure 1 It is a schematic plan view of a partial structure of a semiconductor device in an embodiment of the present application. ;

[0036] Figure 2a is along Figure 1 The cross-sectional view of the A-A' line, Figure 2b is along Figure 1 Sectional view along line B-B';

[0037] Figure 3 is a three-dimensional diagram of a partial structure of a semiconductor device in one embodiment of the present application;

[0038] Figure 4a and Figure 4b It is a cross-sectional view of a semiconductor device at two different positions in another embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0041] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0042] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0045] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0046] Figure 1 1 is a schematic plan view of a partial structure of a semiconductor device in an embodiment of the present application. The semiconductor device includes a high-voltage device region 20, a low-voltage device region 30, a first device region 10, and a first isolation structure 22 located between the high-voltage device region 20 and the low-voltage device region 30. In an embodiment of the present application, the first isolation structure 22 includes a second conductive type well region. The semiconductor device also includes a first isolation region 12. The first isolation region 12 is connected to the first isolation structure 22, and the first isolation region 12 and the first isolation structure 22 together surround the first device region 10.

[0047] Please also see Figure 2a and Figure 2b , Figure 2a is along Figure 1 The cross-sectional view of the A-A' line, Figure 2b is along Figure 1 BB' line cross-sectional view, wherein the first isolation region 12 includes an isolation well 124 and a second isolation structure 122. The isolation well 124 has a second conductivity type and is connected to the first isolation structure 22. The second isolation structure 122 extends downward from the top of the isolation well 124 and penetrates the isolation well 124 (at Figure 2a In the embodiment shown, the second isolation structure 122 penetrates the bottom of the isolation well 124, so that the depth of the second isolation structure 122 is greater than the depth of the isolation well 124. The second isolation structure 122 includes an insulating medium, and the material of the insulating medium can be silicon oxide, such as silicon dioxide.

[0048] The semiconductor device also includes a substrate 110, a source region 146 and a drain region 144. The source region 146 and the drain region 144 are the source region and the drain region of the first device respectively. Most of the structure of the first device is located in the first device region 10, and a small part of the structure is located in the first isolation structure 22 at the edge of the first device region 10. The source region 146 has a first conductivity type and is located in the first isolation structure 22. Figure 2a and Figure 2b In the illustrated embodiment, the first isolation structure 22 includes a second conductivity type well region 126, and the source region 146 is located in the second conductivity type well region 126. The drain region 144 has a first conductivity type and is located in the first device region 10. In one embodiment of the present application, the first device is a power device, for example, a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET), which is a level shift LDMOS in the circuit. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment of the present application, the first conductivity type is P-type and the second conductivity type is N-type.

[0049] In the semiconductor device, a first isolation region 12 is provided between the high-voltage device region 20 and the drain region 144 of the first device. The first isolation region 12 includes a second isolation structure 122 having an insulating medium, which plays an electrical isolation role and can reduce the leakage current between the high-voltage device region 20 and the first device. The second isolation structure 122 has a large depth and the isolation well 124 has a small depth, so that the breakdown voltage (i.e., withstand voltage) of the device can be taken into account while reducing the leakage current.

[0050] Please refer to Figure 1 , Figure 2a and Figure 2bIn one embodiment of the present application, the first device region 10 further includes a drift region 142. The drift region 142 is located in the substrate 110 of the semiconductor device and has a first conductivity type. At least part of the drift region 142 is located between the source region 146 and the drain region 144. In one embodiment of the present application, the depth of the isolation well 124 is not less than the depth of the drift region 142. A second isolation structure 122 having an insulating medium is provided in the isolation well 124, so that the charges between the conductive impurity ions in the drift region 142 and the second isolation structure 122 are more easily balanced, which is conducive to the transfer of the electric field peak of the drift region 142 and the substrate 110 near the drain region 144 to the second isolation structure 122, and can effectively prevent the semiconductor device from being broken down prematurely during reverse withstand voltage.

[0051] In one embodiment of the present application, the second isolation structure 122 is a trench filled with an insulating material. In one embodiment of the present application, the insulating material may be silicon oxide, such as silicon dioxide.

[0052] Figure 3 1 is a perspective view of a part of the structure of a semiconductor device in an embodiment of the present application. In this embodiment, there are multiple second isolation structures 122, which are separated from each other by isolation wells 124. The second isolation structure 122 includes an insulating medium located in the trench and a conductive structure 122b located in the trench. Figure 3 , the insulating medium is a dielectric layer 122a located on the inner wall of the groove, which surrounds the bottom and side surfaces of the conductive structure 122b. The conductive structure 122b, the dielectric layer 122a and the isolation well 124 form a capacitor effect similar to that of a conductive material-dielectric material-semiconductor, which can not only assist in depleting the drift region 142, but also press the equipotential lines at the bottom of the drift region 142 into the second isolation structure 122 when the power device is reversely cut off, greatly reducing the electric field peak caused by the introduction of the isolation well 124. In one embodiment of the present application, the material of the dielectric layer 122a includes silicon oxide, such as silicon dioxide. In one embodiment of the present application, the material of the conductive structure 122b includes polysilicon.

[0053] In one embodiment of the present application, the first device further includes a substrate lead-out region 148, which has a second conductivity type and is located in the first isolation structure 22. Figure 2a and Figure 2b In the illustrated embodiment, the substrate lead-out region 148 is located in the second conductivity type well region 126. Figure 2a and Figure 2b In the embodiment shown, the first device further includes a field oxide layer 164 located on the drift region 142. In one embodiment of the present application, the first device further includes a gate 162. One end of the gate 162 extends onto the field oxide layer 164, and the other end extends toward the source region 146.

[0054] In one embodiment of the present application, the semiconductor device further includes a first conductive type well region 154 located in the high voltage device region 20. The first conductive type well region 154 and the drift region 142 may be formed in the same manufacturing step. Figure 2a and Figure 2b In the illustrated embodiment, the semiconductor device further includes a first conductivity type doping region 156 located in the first conductivity type well region 154. Figure 2a and Figure 2b In the illustrated embodiment, the semiconductor device further includes a second conductive type well 158 located in the high voltage device region 20. The circuits in the high voltage isolation basin can all be arranged in the second conductive type well 158. Figure 2a and Figure 2b In the illustrated embodiment, the semiconductor device further includes a deep well 134 located below the drift region 142, a deep well 136 located below the first conductive type well region 154, and a deep well 132 located below the second conductive type well region 126. The deep wells 134 and 136 have the first conductive type, and the deep well 132 has the second conductive type. The deep wells 132, 134, and 136 can improve the longitudinal withstand voltage of the device.

[0055] In one embodiment of the present application, the depth of the second isolation structure 122 may be greater than the depths of the deep well 134 and the deep well 136 to obtain a better isolation effect (anti-leakage effect).

[0056] exist Figure 2a and Figure 2b In the illustrated embodiment, the semiconductor device further includes an interlayer dielectric (ILD) layer 166 on the field oxide layer 164 and the gate 162, a metal connection 174 on the interlayer dielectric layer 166, and a contact hole 172 that vertically penetrates the interlayer dielectric layer 166 to connect the metal connection 174 to the underlying active region and other structures. The contact hole 172 may be filled with a conductive metal, such as a tungsten plug.

[0057] Based on a general inventive concept, the present application provides another semiconductor device, which also includes a high-voltage device region 20, a low-voltage device region 30, a first device region 10, and a first isolation structure 22 located between the high-voltage device region 20 and the low-voltage device region 30. In one embodiment of the present application, the first isolation structure 22 includes a second conductivity type well region. The semiconductor device also includes a first isolation region 12, which is connected to the first isolation structure 22, and the first isolation region 12 and the first isolation structure 22 together surround the first device region 10.

[0058] The planar structure of the semiconductor device can also refer to Figure 1 , see the cross-sectional structure Figure 4a and Figure 4b, wherein the first isolation region 12 includes a second isolation structure 122 and a PN junction isolation structure. The PN junction isolation structure is connected to the first isolation structure 22. The PN junction isolation structure includes a first conductive type region 124b and a second conductive type region 124a located above and below the first conductive type region 124b. The second isolation structure 122 extends downward from the top of the PN junction isolation structure, and the second isolation structure 122 includes an insulating medium, and the material of the insulating medium can be silicon oxide, such as silicon dioxide. Figure 4b In the illustrated embodiment, the depth of the second isolation structure 122 is greater than the depth of the PN junction isolation structure. In other embodiments, the depth of the second isolation structure 122 may also be less than or equal to the depth of the PN junction isolation structure.

[0059] The semiconductor device also includes a substrate 110, a source region 146 and a drain region 144. The source region 146 and the drain region 144 are the source region and the drain region of the first device respectively. Most of the structure of the first device is located in the first device region 10, and a small part of the structure is located in the first isolation structure 22 at the edge of the first device region 10. The source region 146 has a first conductivity type and is located in the first isolation structure 22. Figure 4a and Figure 4b In the illustrated embodiment, the first isolation structure 22 includes a second conductivity type well region 126, and the source region 146 is located in the second conductivity type well region 126. The drain region 144 has a first conductivity type and is located in the first device region 10. In one embodiment of the present application, the first device is a power device, for example, a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET). In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment of the present application, the first conductivity type is P-type and the second conductivity type is N-type.

[0060] In the above semiconductor device, the first isolation region 12 uses a PN junction isolation structure instead of an isolation well of the second conductivity type for isolation. The PN junction isolation structure can form self-depletion, and the isolation leakage effect of the depletion region is better (relative to the isolation well of the second conductivity type). The first isolation region can reduce the leakage current while taking into account the breakdown voltage of the device through the reasonable combination of the PN junction isolation structure and the second isolation structure with an insulating medium.

[0061] In one embodiment of the present application, the PN junction isolation structure is a PNP super junction structure.

[0062] In one embodiment of the present application, the first device region 10 further includes a drift region 142. The drift region 142 is located in the substrate 110 of the semiconductor device and has a first conductivity type, and at least a portion of the drift region 142 is located between the source region 146 and the drain region 144. In one embodiment of the present application, the depth of the PN junction isolation structure (i.e., the depth of the second conductivity type region 124a at the bottom) is not less than the depth of the drift region 142.

[0063] In one embodiment of the present application, the second isolation structure 122 is a trench filled with an insulating material. In one embodiment of the present application, the insulating material may be silicon oxide, such as silicon dioxide.

[0064] In one embodiment of the present application, there are a plurality of second isolation structures 122 , which are separated from each other by PN junction isolation structures.

[0065] In one embodiment of the present application, the first device further includes a substrate lead-out region 148, which has a second conductivity type and is located in the first isolation structure 22. Figure 4a and Figure 4b In the illustrated embodiment, the substrate lead-out region 148 is located in the second conductivity type well region 126. Figure 4a and Figure 4b In the embodiment shown, the first device further includes a field oxide layer 164 located on the drift region 142. In one embodiment of the present application, the first device further includes a gate 162. One end of the gate 162 extends onto the field oxide layer 164, and the other end extends toward the source region 146.

[0066] In one embodiment of the present application, the semiconductor device further includes a first conductive type well region 154 located in the high voltage device region 20. The first conductive type well region 154 and the drift region 142 may be formed in the same manufacturing step. Figure 4a and Figure 4b In the illustrated embodiment, the semiconductor device further includes a first conductivity type doping region 156 located in the first conductivity type well region 154. Figure 4a and Figure 4b In the illustrated embodiment, the semiconductor device further includes a second conductive type well 158 located in the high voltage device region 20. The circuits in the high voltage isolation basin can all be arranged in the second conductive type well 158. Figure 4a and Figure 4b In the illustrated embodiment, the semiconductor device further includes a deep well 134 located below the drift region, a deep well 136 located below the first conductive type well region 154, and a deep well 132 located below the second conductive type well region 126. The deep wells 134 and 136 have the first conductive type, and the deep well 132 has the second conductive type. The deep wells 132, 134, and 136 can improve the longitudinal withstand voltage of the device.

[0067] In one embodiment of the present application, the depth of the second isolation structure 122 may be greater than the depths of the deep well 134 and the deep well 136 to obtain a better isolation effect (anti-leakage effect).

[0068] exist Figure 4a and Figure 4b In the illustrated embodiment, the semiconductor device further includes an interlayer dielectric (ILD) layer 166 on the field oxide layer 164 and the gate 162, a metal connection 174 on the interlayer dielectric layer 166, and a contact hole 172 that vertically penetrates the interlayer dielectric layer 166 to connect the metal connection 174 to the underlying active region and other structures. The contact hole 172 may be filled with a conductive metal, such as a tungsten plug.

[0069] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0070] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0071] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, comprising a high voltage device region, a low voltage device region, a first device region and a first isolation structure located between the high voltage device region and the low voltage device region, characterized in that: The device further includes a first isolation region, wherein the first isolation region is connected to the first isolation structure, and the first isolation region and the first isolation structure surround the first device region together, and the first isolation region includes: A PN junction isolation structure, comprising a first conductive type region and a second conductive type region located above and below the first conductive type region, the PN junction isolation structure being connected to the first isolation structure; A second isolation structure extending downward from the top of the PN junction isolation structure, wherein the second isolation structure comprises an insulating medium; The semiconductor device further comprises: A source region, having a first conductivity type and located in the first isolation structure, wherein the source region is a source region of a first device; A drain region, having a first conductivity type and located in the first device region, wherein the drain region is a drain region of the first device; Part of the structure of the first device is located in the first device region, and part of the structure is located in a first isolation structure at the edge of the first device region. The first conductivity type and the second conductivity type are opposite conductivity types.

2. The semiconductor device according to claim 1, wherein: There are a plurality of second isolation structures, which are separated from each other by the PN junction isolation structure.

3. The semiconductor device according to claim 1, wherein: The second isolation structure includes the insulating medium located in the trench and also includes a conductive structure located in the trench; the insulating medium is a dielectric layer located on the inner wall of the trench and surrounds the bottom and side surfaces of the conductive structure.

4. The semiconductor device according to claim 3, characterized in that The material of the dielectric layer includes silicon oxide; and / or The conductive structure is made of polysilicon.

5. The semiconductor device according to claim 1, wherein: The first isolation structure includes a second conductivity type well region.

6. The semiconductor device according to claim 1, wherein: The first device is a power device.

7. The semiconductor device according to claim 1, wherein: The first device is a laterally diffused metal oxide semiconductor field effect transistor.

8. The semiconductor device according to claim 6 or 7, characterized in that: The first device area further includes: a drift region having a first conductivity type and at least partially located between the source region and the drain region; A field oxide layer, located on the drift region; A gate, one end of which extends to the field oxide layer and the other end of which extends to the source region; The substrate lead-out region has the second conductivity type and is located in the first isolation structure.

9. The semiconductor device according to claim 8, characterized in that The depth of the PN junction isolation structure is not less than the depth of the drift region.

10. The semiconductor device according to claim 1, wherein: The PN junction isolation structure is a super junction structure.

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