A depletion-mode GaN switching power supply structure

Abstract

The present invention discloses a depletion-type GaN switching power supply structure, which relates to the technical field of integrated circuits and solves the problems in the prior art that the depletion-type GaN switching speed cannot be well controlled and the voltage resistance of the NMOS tube connected in series is too high. The present invention proposes a depletion-type GaN driving method that drives the depletion-type GaN source voltage by adjusting the driving current of the NMOS tube, thereby realizing a controllable switching speed of the power tube. Signal detection can be realized by using the intermediate node of the depletion-type GaN and NMOS tube connected in series, thereby simplifying the valley detection circuit of the system. At the same time, the chip power-on function is realized by utilizing the characteristic of the depletion-type GaN being normally open, thereby simplifying the power-on circuit of the system and reducing the standby power consumption of the system. Furthermore, the chip power supply function can be realized by utilizing the characteristic of the depletion-type GaN being normally open, thereby eliminating the auxiliary winding Laux and the diode D8, simplifying the system circuit and reducing the cost.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a depletion-mode GaN switching power supply structure. Background Art

[0002] The application of GaN power tubes in switching power supplies can significantly reduce the size of the power supply, increase power density and improve efficiency. It is widely used in various switching power supplies, especially in mobile phone fast charging power supplies. Its smaller size and greater charging power are loved by consumers. Most of the existing technologies use enhanced GaN in the normally closed state to be compatible with the existing enhanced NMOS tube (N-type metal oxide transistor) system solutions. Figure 1 The circuit diagram of the switching power supply system with integrated high-voltage startup in the prior art is shown, wherein U1 is the main control chip of the secondary feedback flyback switching power supply, and diodes D5, D6 and resistor R1 are responsible for supplying power to the HV pin of the main control chip when the system is powered on. The HV pin of the main control chip U1 has a depletion-type transistor ND1. When the chip is powered on, ND1 is normally open, and the external energy storage capacitor C0 of the VCC pin is charged through the HV pin. After charging, the main control chip U1 works normally and ND1 is turned off. The depletion-type transistor ND1 needs to withstand high voltage and has a high cost. The auxiliary winding Laux of the transformer T1 and the diode D8 constitute the main power supply circuit of the VCC power supply of the main control chip. When the power tube N1 is turned off, the primary winding Lp stops storing energy, and the auxiliary winding Laux and the secondary output winding Ls output a voltage with a high upper voltage and a low lower voltage, outputting the excitation energy of the transformer. Resistors R2 and R3 are connected in series to the VAUX end of the auxiliary winding and the ZCD end of the main control chip, and the main control chip performs valley detection by detecting the ZCD voltage. Capacitor C2 is a loop compensation capacitor, connected to the FB terminal of the control chip and the output terminal of the optocoupler U3. Resistor Rcs is a current sampling resistor. The absorption circuit is responsible for absorbing the voltage spike generated by the leakage inductance of transformer T1. U2 is a synchronous rectifier chip that realizes the Schottky diode rectification function. U3 is an optocoupler chip responsible for isolating the voltage signal at the output end and transmitting it back to the FB terminal of the original control chip. U4 is a TL431 controllable voltage regulator. The output voltage is divided by R5 and R6, and then output to the voltage regulator U4 for error amplification and output to the optocoupler U3, and then transmitted back to the main control chip. Diodes D1, D2, D3 and D4 are rectifier bridges for AC input voltage. Capacitor C1 is an energy storage capacitor, and the voltage VIN of capacitor C1 is the high-voltage DC input power supply of the fast charging power supply.

[0003] In the prior art, the DRV output of the main control chip U1 (such as NCP1342) generally directly drives the NMOS power tube. If the power tube N1 is adjusted to an enhanced GaN device, it is necessary to add a dedicated GaN drive circuit at the DRV drive output end. The GaN drive circuit usually consists of 3 resistors and 1 diode, and the circuit is relatively simple. The existing system solution for driving the NMOS power tube can be easily switched to drive the enhanced GaN power tube. This makes the enhanced GaN power tube a mainstream application in switching power supply applications. The depletion-type GaN is normally open, and a normally closed low-voltage enhanced NMOS tube must be connected in series to form a cascode structure to achieve the normally closed function, resulting in complex production and driving of the depletion-type GaN package, and is not widely used. In the prior art, the gate drive circuit of the depletion-type GaN mostly refers to the gate drive circuit of the enhanced GaN, and two resistors are designed on the GaN gate to connect to the ground, and the switching speed is slowed down by adjusting the GaN gate voltage. One resistor is connected in series with a diode to turn on the resistor when GaN is turned off, reducing the gate resistance to speed up the shut-down speed of GaN. As shown in patents CN115996050A, CN117878117A and CN116094292A. However, the depletion-type GaN is connected in series with the NMOS switch tube. If only the switching speed of GaN is adjusted, it is easy for the NMOS tube to be turned off first and the GaN to be turned off later, which will cause the drain voltage of the NMOS tube to overshoot and easily damage the NMOS tube. It is necessary to increase the withstand voltage of the NMOS tube. The reason is that the power tube of GaN has a gate-drain capacitor Cgd. When the power tube is turned off, the drain voltage rises, charging the gate-drain capacitor Cgd, resulting in a huge gate-drain charging current. Due to the gate resistance of the depletion-type GaN, the gate-drain charging current causes the GaN gate voltage to rise, which will prolong the depletion-type GaN shutdown time, which will significantly raise the voltage of the depletion-type GaN source. In order to avoid avalanche breakdown of the series-connected NMOS tube, the NMOS tube is required to have a higher withstand voltage, and the corresponding NMOS tube area is larger and the cost is higher. Some patents such as CN116094292A use a capacitor between the source and ground of the depletion-type GaN to reduce the drain voltage of the NMOS switch tube when it is turned off, and at the same time add a voltage regulator tube between the source and gate of GaN. However, when the source voltage is too high, the voltage regulator tube generates a voltage regulator current, which will raise the gate voltage under the action of the gate resistor, thereby increasing the source voltage. In this way, the voltage regulator device cannot effectively stabilize the voltage between the GaN source and the drain of the NMOS tube, and the withstand voltage of the NMOS tube also needs to be increased.

[0004] In view of this, a depletion-mode GaN switching power supply structure is needed. Summary of the invention

[0005] In view of the problems in the prior art that the switching speed of depletion-type GaN cannot be well controlled and the withstand voltage of NMOS tubes connected in series is too high, the present invention provides a depletion-type GaN switching power supply structure, which can use the intermediate node of the depletion-type GaN and NMOS tubes connected in series to realize signal detection and simplify the system valley detection circuit. At the same time, the chip power-on function is realized by utilizing the normally-on characteristic of depletion-type GaN, thereby simplifying the power-on circuit of the system and reducing the standby power consumption of the system. Furthermore, the normally-on characteristic of depletion-type GaN can be used to realize the chip power supply function, thereby eliminating the auxiliary winding Laux and diode D8, simplifying the system circuit and reducing costs. The specific technical scheme is as follows:

[0006] A depletion-type GaN switching power supply structure comprises a rectifier bridge, an absorption circuit, a transformer T1, and a synchronous rectifier chip and its peripheral circuits, wherein the rectifier bridge is connected to the absorption circuit and the transformer T1, and the transformer T1 is also connected to the synchronous rectifier chip and its peripheral circuits, and also comprises a main control chip, the main control chip comprises a power-taking detection and voltage-stabilizing module, a control module and an NMOS switch tube N3, wherein the power-taking detection and voltage-stabilizing module is connected to the source of the NMOS switch tube N3, the control module is connected to the gate of the NMOS switch tube N3, and a driving circuit of the NMOS switch tube N3 is arranged in the control module, the NMOS switch tube N3 is connected to the transformer T1 and the absorption circuit through a depletion-type GaN switch tube ND2, a pin FB of the main control chip is grounded through a loop compensation capacitor C2, and the pin FB of the main control chip is also connected to the peripheral circuit of the synchronous rectifier chip.

[0007] Preferably, the pin VCC of the main control chip is connected to the power detection and voltage stabilizing module and one end of the energy storage capacitor C0, the other end of the energy storage capacitor C0 is grounded, and it also includes an auxiliary winding Laux, which is connected to the capacitor C0 and the pin VCC of the main control chip through a diode D8.

[0008] Preferably, the power-taking detection and voltage-stabilizing module includes a valley detection module and a current detection module connected to the control module, the valley detection module is connected to the source of transistor N4, the current detection module is connected to the drain of transistor N4, the gate of transistor N4 is respectively connected to one end of resistor R41 and the cathode of voltage regulator diode D42, the source of transistor N4 is respectively connected to the other end of resistor R41 and the cathode of voltage regulator D43, the drain of transistor N4 is connected to the anode of voltage regulator diode D41, the cathode of diode D41 is connected to one end of energy storage capacitor C0, the cathode connection of voltage regulator D43, the anode of voltage regulator diode D42, and one end of energy storage capacitor C0 are all grounded.

[0009] Preferably, the pin VCC of the main control chip is connected to the power-taking detection voltage-stabilizing module and one end of the energy storage capacitor C0, and the other end of the energy storage capacitor C0 is grounded.

[0010] Preferably, the power extraction detection and voltage stabilization module includes a valley detection module, a current detection module, a transistor N4, a voltage stabilization module, a charge pump and an anti-backflow charging management module, wherein the source of the transistor N4 is connected to the valley detection module and the voltage stabilization module, the drain of the transistor N4 is connected to the anti-backflow charging management module and the current detection module, the gate of the transistor N4 is connected to the charge pump, and the charge pump, the valley detection module and the current detection module are all connected to the control module.

[0011] Preferably, the backflow charging management module in the power detection and voltage stabilization module includes a power switching module, an operational amplifier U61 and a transistor P1, wherein the gate of the transistor P1 is connected to the output end of the operational amplifier U61, the source of the transistor P1 is connected to the power switching module and one end of the resistor R61, the drain of the transistor P1 is connected to one end of the resistor R63, the in-phase input end of the operational amplifier U61 is respectively connected to the other end of the resistor R63 and one end of the resistor R64, the inverting input end of the operational amplifier U61 is respectively connected to the other end of the resistor R61 and one end of the resistor R62, the negative power supply end of the operational amplifier U61 is respectively connected to the other end of the resistor R62 and the other end of the resistor R64, and the positive power supply end of the operational amplifier U61 is connected to the power switching module.

[0012] Preferably, the current detection module includes an operational amplifier U71, a transistor N71, a transistor N3t and a switch S1, wherein the output end of the operational amplifier U71 is connected to the gate of the transistor N71, the inverting input end of the operational amplifier U71 is connected to one end of the switch S1, the other end of the switch S1 is connected to the gate of the transistor N3t, and the non-inverting input end of the operational amplifier U71 is respectively connected to the source of the transistor N3t and the drain of the transistor N71.

[0013] Preferably, the driving circuit of the NMOS switch tube N3 includes a switch logic control module and a buffer, wherein the input end of the switch logic control module is connected to the switch pulse control signal PWM, the output end of the switch logic control module is connected to the buffer, and the end of the buffer not connected to the switch logic control module is connected to the NMOS switch tube N3.

[0014] Preferably, there are n buffers, and when the driving circuit of the NMOS switch tube N3 is working, the NMOS tube N3 is split into multiple NMOS tubes N31, N32, N33...N3n, and then the switch pulse control signal PWM is processed by the switch logic control module and then driven to turn on and off the multiple NMOS tubes N31, N32, N33...N3n through the buffers U31, U32, U33...U3n respectively, so as to realize the control of the switching current change rate.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The present invention proposes a depletion-type GaN driving scheme with power-taking, detection and voltage-stabilizing functions, which can reduce the withstand voltage requirements of the series-connected NMOS switch tube and realize the controllable switching speed of the depletion-type GaN. This reduces the cost of the driver chip, improves reliability, and improves the EMI characteristics of the system. The present invention also proposes a power-taking, detection and voltage-stabilizing protection method based on depletion-type GaN, which simplifies the system circuit while ensuring system reliability and reducing system costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A circuit diagram of a switching power supply system with integrated high voltage startup for the prior art;

[0019] Figure 2 This is a circuit diagram of a switching power supply system according to an embodiment of the present invention;

[0020] Figure 3 This is a depletion-mode GaN driving circuit diagram of the present invention;

[0021] Figure 4 This is a depletion-mode GaN driving waveform diagram of the present invention;

[0022] Figure 5 The power-taking detection and voltage-stabilizing module of Embodiment 1;

[0023] Figure 6 This is a circuit diagram of a switching power supply system according to an embodiment 2 of the present invention;

[0024] Figure 7 This is the power-taking detection and voltage-stabilizing module embodiment of embodiment 2;

[0025] Figure 8 This is an embodiment of the reverse backflow charging management module in the power taking detection and voltage stabilization module of embodiment 2;

[0026] Fig. 9 This is an embodiment of a current detection module. DETAILED DESCRIPTION

[0027] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0029] Embodiment 1:

[0030] like Figure 2 This is the circuit diagram of the switching power supply system of the present invention. Figure 1Compared with the prior art, the present invention adopts a depletion-type GaN switch tube ND2 to replace the enhanced power tube N1. At the same time, the HV pin and the corresponding circuit of the internal consumption ND1 are omitted, and the D5, D6 diodes, resistors R1, R2, R3 and sampling resistor Rcs are omitted in the system. The secondary feedback main control chip U12 adds a power-taking detection voltage stabilizing module, an NMOS switch tube N3 and a corresponding drive circuit. When the system is powered on, the VIN voltage gradually increases. Since the depletion-type GaN switch tube ND2 is in a normally open state, there will be a current from the VIN end through the primary winding Lp of the transformer, the depletion-type GaN switch tube ND2 and the power-taking detection voltage stabilizing module to charge the energy storage capacitor C0 at the VCC end. When the VCC voltage reaches the set value, the main control chip U12 starts to work, and drives the switch of the depletion-type GaN switch tube ND2 by driving the switch of the NMOS switch tube N3. When the NMOS switch tube N3 is turned on, the Vs node is pulled low, thereby turning on the depletion-type GaN tube ND2, pulling down the Drain end, and increasing the current of the primary winding Lp of the transformer T1. By detecting the current of the NMOS switch tube N3, the detection of the depletion-type GaN or Lp current is realized. This saves the external series Rcs current detection resistor, saves the peripheral circuit components, reduces resistance loss, and improves efficiency. When it is detected that the current reaches the set value, the NMOS switch tube N3 is turned off, and the depletion-type GaN current charges the Vs node and raises the Vs voltage. The increase in Vs voltage will turn off the depletion-type GaN ND2, and then the transformer current will charge the Drain node voltage higher. After the NMOS switch tube N3 and the depletion-type GaN are turned off, the middle Vs node is in a high-impedance state, and its voltage waveform changes with the Drain end. Therefore, the valley waveform of the Drain switch end can be detected by detecting the voltage valley of Vs in the off state, realizing the valley detection and opening function. At the same time, in order to prevent the Vs node voltage from being too high and damaging the NMOS tube N3, it is also necessary to perform a voltage clamping function on the Vs node to prevent the Vs node voltage from being too high. The opening and closing speeds of the depletion-type GaN are actually determined by the pull-down and increase speeds of the Vs node. The pull-down and increase speeds of the Vs node are determined by the difference between the current provided by the depletion-type GaN ND2 and the pull-down current of the NMOS tube N3 to charge and discharge the total parasitic capacitance of the Vs node. The total parasitic capacitance of the Vs node is a fixed value. The smaller the current difference, the slower the charging and discharging speed, and the larger the current difference, the faster the charging and discharging speed. The current provided by the depletion-type GaN ND2 is equal to the transformer current and cannot be adjusted by the control chip, but the pull-down current of the NMOS tube N3 can be controlled by the control chip, and the change speed of the NMOS tube N3 current can be adjusted to control the current difference of the charge and discharge of the Vs node, thereby controlling the change speed of the Vs node voltage. Similarly, the pull-down and increase speed of the Drain node is determined by the charge and discharge speed of the total parasitic capacitance of the Drain node by the difference between the inductor Lp current and the ND2 current.Controlling the change speed of the depletion-type GaN ND2 current can also control the change speed of the Drain node voltage. The change speed of the depletion-type GaN ND2 current is determined by the change speed of the Vs node voltage, so the switching speed of the depletion-type GaN ND2 can be controlled by the NMOS tube N3.

[0031] Figure 3 The figure shows the depletion-type GaN driving circuit proposed by the present invention. Figure 2The NMOS tube N3 shown is split into multiple NMOS tubes N31, N32, N33...N3n, and then the switch pulse control signal PWM is processed by the switch logic control module and then driven by the buffers U31, U32, U33...U3n to turn on and off multiple NMOS tubes N31, N32, N33...N3n, so as to control the rate of change of the switch current. The current of the NMOS switch tube is related to the gate-source voltage Vgs and the device width-to-length ratio W / L. In the prior art, the NMOS switch tube N3 is controlled as a switch tube as a whole, and the current change speed can only be adjusted by the gate-source voltage Vgs of the NMOS switch tube. The gate drive signal of the NMOS switch tube N3 is generally a rectangular wave pulse drive mode, and the gate-source voltage Vgs change speed is the rising and falling edge change speed, which is difficult to accurately control. The present invention splits the NMOS switch tube N3 into multiple switch tubes with a small width-to-length ratio, and the drive current can be controlled by staggering the drive time of the multiple switch tubes. For example, when the switch is turned on, only the N31 tube is turned on first. Since the width and length of the N31 tube are relatively small, the current is small, the Vs voltage decreases slowly, and the depletion-type GaN slowly turns on. After a set time, the N32 tube is turned on, the current increases, the depletion-type GaN turns on to discharge the Drian end, and then the N33 tube and N3n and other transistors are turned on to achieve the full opening of the depletion-type GaN ND2 tube. Similarly, when turning off, first turn off some transistors to reduce the current of the NMOS tube. At this time, the Vs node will be slowly charged and increased, and then turn off more transistors to make the depletion-type GaN completely turned off. In this way, the switching speed of the depletion-type GaN can be controlled, and the rise and fall rates of the Vs and Drain node voltages can be controlled. The power-taking detection and voltage-stabilizing module is connected to the Vs node to achieve the functions of taking power from Vs, detecting the bottom of the Vs voltage when turned off, and stabilizing the Vs voltage. In the figure, Cds is the parasitic drain-source capacitance of the depletion-mode GaN ND2. It is not an external capacitance, but a parasitic capacitance of the device itself. Similarly, the Cs capacitance is the total parasitic capacitance of the Vs node, which is mainly the drain-source parasitic capacitance of the N31, N32, N33...N3n switch tubes. When both the NMOS tube and the depletion-mode GaN are turned off, the voltage at the Drain end will be divided by the Cds and Cs capacitors, so that the voltage waveform at the Vs end is the same as the Drain waveform and is proportional. The valley bottom detection of the Drain end can be achieved by detecting the Vs voltage. The capacitor Cdrain is the total parasitic capacitance of the Drain end, which is composed of the parasitic capacitance of multiple external devices and circuit boards.

[0032] Figure 4The figure shows the depletion-type GaN driving waveform proposed by the present invention. Before the switch is turned on at time t0, the depletion-type GaN ND2 and N31, N32, N33...N3n switch tubes are all in the off state, there is no drain current IDrian=0, and the Drain node voltage oscillates near the input voltage VIN. The Vs voltage is slightly greater than the depletion-type GaN cut-off voltage. At time t0, the drive signal PWM becomes high, and after being processed by the switch logic control module and buffers U31, U32, U33...U3n drive N31_g to output a high level. At this time, the N31 switch tube is turned on, and the N32, N33...N3n switch tubes are all turned off. The N31 switch tube outputs the maximum current, which discharges the Vs node capacitor, gradually lowers the Vs node voltage, and the depletion-type GaN gradually opens, the drain current IDrian gradually increases, and the Drain terminal voltage decreases. At time t1, N32_g outputs a high level to drive the N32 switch tube to turn on, the current of the NMOS tube increases, and the Vs voltage drops faster. During the time t1-t2, the depletion-type GaN ND2 gradually opens, and the overcurrent capability gradually increases, which is greater than the current of the NMOS tube. Therefore, the drain current IDrian is approximately equal to the total current of the NMOS tubes N31 and N32. The drain current IDrian discharges the total parasitic capacitance Cds of the Drain end, and the voltage at the Drain end of the depletion-type GaN switch tube decreases until it is approximately equal to the Vs voltage. At t2, N33_g outputs a high level to drive the N33 switch tube to open, the current of the NMOS tube increases, and the Vs voltage drops faster until it drops to close to the ground level. If working in the discontinuous current mode, the current of the primary winding Lp of the transformer is 0 when the switch tube ND2 is turned on, and the current of the switch tube ND2 starts to increase from 0. If working in the continuous current mode, the current when the switch tube ND2 is turned on is equal to the initial current of the primary winding Lp of the transformer. At t3, N3n_g outputs a high level to turn on the remaining NMOS tube switches, and the NMOS switch tube is fully turned on.

[0033] When the current of the NMOS switch tube increases to the set value, the switch tube is turned off. Similarly, at t4, when the pulse drive signal PWM becomes low, N3n_g is output at a low level to turn off some NMOS switch tubes N3n. As the current of the NMOS tube decreases, the voltage of the Vs node becomes higher, which is equivalent to increasing the Vds voltage of the NMOS tube. At this time, the NMOS switch tube can still pass a large current. At t5, N33_g is output at a low level to continue to turn off some NMOS switch tubes N33. At this time, the Vs voltage is close to the threshold voltage of the depletion-type GaN. The depletion-type GaN is gradually turned off, the current decreases, the Vs voltage increases slowly, and the voltage at the Drain end begins to rise. At t6, N32_g is output at a low level to continue to turn off some NMOS switch tubes N32, and the voltage at the Drain end continues to increase. At t7, N31_g is output at a low level to turn off all NMOS switch tubes. The depletion-type GaN is completely turned off, thus completing the switch-off action. It should be noted that the above-mentioned NMOS tube shutdown sequence of N31-N3n is not necessary, and the NMOS tube shutdown sequence can be selected arbitrarily.

[0034] The depletion-type GaN drive of the present invention is characterized in that the current of the NMOS switch tube can be controlled when opening and closing by controlling the series-connected NMOS switch tube to be opened and closed in time, and the NMOS switch tube is gradually opened and closed, so that the opening and closing speed of the source voltage Vs of the depletion-type GaN can be controlled, and the switching speed of the depletion-type GaN switch control can be controlled. This avoids the problem in the prior art that the improper control of the depletion-type GaN switch speed leads to excessive switching speed of the source voltage Vs and the drain voltage Vdrain, causing obvious voltage overshoot phenomenon of the source voltage Vs and the drain voltage Vdrain. The scheme of the present invention can reduce the drain voltage Vs of the NMOS switch tube and improve the EMI problem of the system circuit.

[0035] Figure 5 The figure shows the power-taking detection and voltage-stabilizing module of the first embodiment of the present invention. Figure 2In the switching power supply system circuit diagram Example 1, the VCC power supply of the main control chip U12 is powered by the source Vs of the depletion-type GaN when the system is powered on, and the auxiliary winding Laux and the diode D8 are used to charge the capacitor C0 for power supply during normal operation. When the system is powered on, due to the normally-on characteristic of the depletion-type GaN, the Vs voltage increases. The Vs voltage is connected to the cathode of the voltage-stabilizing diode D42 and the gate of the transistor N4 through the resistor R41. The transistor N4 is turned on and the source VHC voltage increases. The voltage-stabilizing diode D42 limits the gate voltage of the transistor N4 and also limits the source VHC voltage to a low voltage range. When the VHC voltage is higher than the VCC voltage and exceeds the diode conduction voltage, the diode D41 is turned on. The Vs voltage charges the energy storage capacitor C0 of the chip VCC through the transistor N4 and the diode tube D41. The current detection module detects the current flowing through the switch tube by detecting the VHC voltage when the switch is turned on. When the depletion-type GaN is turned on, Figure 2 The NMOS switch tube N3 shown is also fully turned on, and the Vs voltage is very low. At this time, the transistor N4 is in a fully on state, and the VHC voltage is equal to the Vs voltage. The Vs voltage can be detected by detecting the VHC voltage. The switch tube N3 works in the linear region, and its source-drain voltage Vs is proportional to its on-resistance. The current of the NMOS switch tube N3 can be detected by detecting the Vs voltage. The valley detection module is connected to the Vs terminal. When the switch is closed, Vs is in a high-resistance state. Since the Cds capacitor of the depletion-type GaN and the Cs capacitor of the switch tube N3 form a voltage-dividing relationship, the Vs voltage changes with the change of the Drain terminal voltage. The valley of Vs can be detected to realize the valley detection function. If the Vs voltage is too high when the switch is closed, the regulator D43 starts to work and discharges the Vs terminal voltage to prevent the Vs terminal voltage from being too high.

[0036] Figure 6 This is the circuit diagram of the switching power supply system of the present invention. Figure 2 In the embodiment 1 shown, the present invention omits the auxiliary winding Laux and diode D8 of the transformer, and uses the depletion-type GaN to supply power while taking power from the power-on state. When the switch is closed, Vs is a high voltage, and the energy storage capacitor C0 of the chip VCC is charged through the power-taking detection voltage stabilization module to realize the chip power supply function. Figure 1 Compared with the prior art, the solution of the present invention can save the power supply circuit, greatly simplify the system circuit, and reduce costs.

[0037] Figure 7This is an embodiment of the power-taking detection and voltage-stabilizing module of embodiment 2 of the present invention. When the switch tube is turned on, the Vs voltage decreases, and the VHC voltage is equal to the Vs voltage. The current detection module detects the current of the switch tube N3 by detecting the VHC voltage. The anti-backflow charging management module does not work to prevent the VCC current from backflowing into the VHC terminal. When the switch tube is turned off, the Vs voltage rises, the control module outputs a control signal to turn on the charge pump circuit, the transistor N4 turns on and works, the VHC voltage rises, and when it is higher than the VCC voltage, the anti-backflow charging management module starts to work and charges VCC. After charging is completed, the anti-backflow charging management module is turned off. Figure 5 The bottom detection module shown is the same as that shown in the figure. During the shutdown process, the bottom detection module detects the valley output of Vs. At the same time, the voltage stabilization module implements the voltage limiting and stabilizing function on the Vs terminal voltage to prevent the Vs voltage from being too high.

[0038] Figure 8 This is an embodiment of the reverse backflow charging management module in the power detection and voltage stabilization module of embodiment 2 of the present invention. Resistors R61 and R62 divide the VHC voltage and input it to the negative input terminal of the operational amplifier U61. Resistors R63 and R64 divide the VCC voltage and input it to the positive input terminal of the operational amplifier U61. When the VHC voltage is higher than the VCC set value, the operational amplifier U61 outputs a voltage signal to control the transistor P1 to turn on. When the VCC voltage increases, the operational amplifier U61 outputs a voltage signal to gradually turn off the transistor P1 to prevent the VCC voltage from being too high. At the same time, the operational amplifier U61 receives the ctrl control signal from the controller, and outputs a high level to completely turn off the transistor P1 to prevent VCC from backflowing to the VHC terminal. The power switching module receives the VHC and VCC voltages, and automatically outputs the highest voltage of the two to the operational amplifier U61 to power it. It is ensured that the high level output by the operational amplifier U61 can completely turn off the transistor P1 to prevent VCC from backflowing to the VHC terminal.

[0039] FIG. 9 is a schematic diagram of the present invention. Figure 5 and Figure 7Embodiment of the current detection module in the embodiment. The switch tube control signal N3n_g is connected to the gate of the detection transistor N3t and the control end of the switch S1. When the switch tube N3 is turned on, the detection transistor N3t is controlled to be turned on and the switch S1 is closed. The detection transistor N3t and the switch work in the same linear region. When the source-drain voltage is the same, the on-resistance is proportional. The VHC voltage is connected to the positive input terminal of the operational amplifier U71 through the switch S1. The output terminal of the operational amplifier U71 is connected to the gate of the transistor N71, and the negative input terminal is connected to the source of the transistor N71 and the drain of the detection transistor N3t. The drain of the transistor N71 outputs the detection current. The operational amplifier U71 controls the transistor N71 to turn on, and N71 generates a current. The current flows through the turned-on detection transistor N3t to generate a voltage drop. When the drain-source voltage drop of the detection transistor N3t is equal to the VHC voltage, the output of the operational amplifier U71 is stable, and the current of N71 is the detection current. Since the on-resistance of the detection transistor N3t is proportional to that of the switch tube, the current value is proportional to the current of the switch tube N3, so that accurate detection and sampling of the switch tube current can be achieved.

[0040] In summary, the present invention uses a step-by-step driving method to adjust the NMOS tube driving current, thereby realizing a depletion-type GaN switch speed controllable driving. The present invention also proposes a power supply, detection and voltage stabilization protection method based on depletion-type GaN, which ensures system reliability while simplifying the system circuit and reducing system costs.

[0041] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0042] The terms "first", "second" and "third" etc. in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0044] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A depletion-mode GaN switching power supply structure, including a rectifier bridge, an absorption circuit, a transformer T1, a synchronous rectifier chip and its peripheral circuits, wherein: The rectifier bridge is connected to the absorption circuit and the transformer T1, and the transformer T1 is also connected to the synchronous rectification chip and its peripheral circuits. It is characterized in that it also includes a main control chip, and the main control chip includes a power detection and voltage stabilization module, a control module and an NMOS switch tube N3, wherein the power detection and voltage stabilization module is connected to the source of the NMOS switch tube N3, the control module is connected to the gate of the NMOS switch tube N3, and a driving circuit of the NMOS switch tube N3 is provided in the control module, and the NMOS switch tube N3 is connected to the transformer T1 and the absorption circuit through the depletion-type GaN switch tube ND2, and the pin FB of the main control chip is grounded through the loop compensation capacitor C2, and the pin FB of the main control chip is also connected to the peripheral circuit of the synchronous rectification chip; The power-taking detection and voltage-stabilizing module includes a valley detection module and a current detection module connected to the control module, the valley detection module is connected to the source of the transistor N4, the current detection module is connected to the drain of the transistor N4, the gate of the transistor N4 is respectively connected to one end of the resistor R41 and the cathode of the voltage-stabilizing diode D42, the source of the transistor N4 is respectively connected to the other end of the resistor R41 and the cathode of the voltage regulator D43, the drain of the transistor N4 is connected to the anode of the voltage-stabilizing diode D41, the cathode of the diode D41 is connected to one end of the energy storage capacitor C0, the cathode connection of the voltage regulator D43, the anode of the voltage-stabilizing diode D42, and one end of the energy storage capacitor C0 are all grounded; The driving circuit of the NMOS switch tube N3 includes a switch logic control module and a buffer, wherein the input end of the switch logic control module is connected to the switch pulse control signal PWM, the output end of the switch logic control module is connected to the buffer, and the end of the buffer not connected to the switch logic control module is connected to the NMOS switch tube N3; There are n buffers. When the driving circuit of the NMOS switch tube N3 is working, the NMOS tube N3 is split into multiple NMOS tubes N31, N32, N33...N3n. Then, the switch pulse control signal PWM is processed by the switch logic control module and then drives the multiple NMOS tubes N31, N32, N33...N3n to be turned on and off through the buffers U31, U32, U33...U3n respectively, so as to realize the control of the switching current change rate.

2. A depletion-mode GaN switching power supply structure according to claim 1, characterized in that: The pin VCC of the main control chip is connected to the power detection voltage stabilizing module and one end of the energy storage capacitor C0, and the other end of the energy storage capacitor C0 is grounded. It also includes an auxiliary winding Laux, which is connected to the capacitor C0 and the pin VCC of the main control chip through a diode D8.

3. The depletion-mode GaN switching power supply structure according to claim 1, characterized in that: The pin VCC of the main control chip is connected to the power-taking detection voltage-stabilizing module and one end of the energy storage capacitor C0, and the other end of the energy storage capacitor C0 is grounded.

4. A depletion-mode GaN switching power supply structure according to claim 3, characterized in that: The power-taking detection and voltage-stabilizing module includes a valley detection module, a current detection module, a transistor N4, a voltage-stabilizing module, a charge pump and an anti-backflow charging management module, wherein the source of the transistor N4 is connected to the valley detection module and the voltage-stabilizing module, the drain of the transistor N4 is connected to the anti-backflow charging management module and the current detection module, the gate of the transistor N4 is connected to the charge pump, and the charge pump, the valley detection module and the current detection module are all connected to the control module.

5. A depletion-mode GaN switching power supply structure according to claim 4, characterized in that: The backflow charging management module in the power detection and voltage stabilization module includes a power switching module, an operational amplifier U61 and a transistor P1, wherein the gate of the transistor P1 is connected to the output end of the operational amplifier U61, the source of the transistor P1 is connected to the power switching module and one end of the resistor R61, the drain of the transistor P1 is connected to one end of the resistor R63, the in-phase input end of the operational amplifier U61 is respectively connected to the other end of the resistor R63 and one end of the resistor R64, the inverting input end of the operational amplifier U61 is respectively connected to the other end of the resistor R61 and one end of the resistor R62, the negative power supply end of the operational amplifier U61 is respectively connected to the other end of the resistor R62 and the other end of the resistor R64, and the positive power supply end of the operational amplifier U61 is connected to the power switching module.

6. The depletion-mode GaN switching power supply structure according to claim 4, characterized in that: The current detection module includes an operational amplifier U71, a transistor N71, a transistor N3t and a switch S1, wherein the output end of the operational amplifier U71 is connected to the gate of the transistor N71, the inverting input end of the operational amplifier U71 is connected to one end of the switch S1, the other end of the switch S1 is connected to the gate of the transistor N3t, and the non-inverting input end of the operational amplifier U71 is respectively connected to the source of the transistor N3t and the drain of the transistor N71.

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