Light emitting diode and method of manufacturing light emitting diode

Abstract

The present disclosure provides a light emitting diode and a manufacturing method thereof, and belongs to the field of light emitting devices. The light emitting diode comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence; a transparent conductive layer located on the second semiconductor layer; a dielectric layer covering the transparent conductive layer, the dielectric layer having a plurality of first through holes; a silver reflective layer located on the dielectric layer, the silver reflective layer being connected with the transparent conductive layer through the plurality of first through holes; a first passivation layer covering the transparent conductive layer and the dielectric layer, the first passivation layer having a second through hole and a plurality of passivation layer compensation blocks located in the second through hole, the plurality of passivation layer compensation blocks corresponding to the plurality of first through holes; and an electrode located on the first passivation layer, the electrode being connected with the silver reflective layer through the second through hole.

Description

Technical Field

[0001] This disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for manufacturing a light-emitting diode. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor light-emitting device that can be used in display, lighting, and other display applications.

[0003] Related technology provides a light-emitting diode, which includes: a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially; a transparent conductive layer located on the second semiconductor layer; a dielectric layer covering the transparent conductive layer and having multiple vias; a silver reflective layer located on the dielectric layer and connected to the transparent conductive layer through the multiple vias; a passivation layer covering the transparent conductive layer and the dielectric layer; and an electrode located on the passivation layer and connected to the silver reflective layer through the passivation layer.

[0004] However, the above-described light-emitting diodes suffer from low reliability. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) and a method for manufacturing an LED, which can improve the reliability of the LED. The technical solution is as follows:

[0006] On one hand, a light-emitting diode (LED) is provided, the LED comprising:

[0007] A first semiconductor layer, an active layer, and a second semiconductor layer are stacked sequentially.

[0008] A transparent conductive layer, wherein the transparent conductive layer is located on the second semiconductor layer;

[0009] A dielectric layer covering the transparent conductive layer, the dielectric layer having a plurality of first vias;

[0010] A silver reflective layer is located on the dielectric layer and is connected to the transparent conductive layer through the plurality of first vias;

[0011] A first passivation layer covers the transparent conductive layer and the dielectric layer. The first passivation layer has a second via and a plurality of passivation layer compensation blocks located within the second via. The plurality of passivation layer compensation blocks correspond to the plurality of first vias.

[0012] An electrode is located on the first passivation layer and is connected to the silver reflective layer through the second via.

[0013] Optionally, the plurality of passivation layer compensation blocks correspond one-to-one with the plurality of first vias, and the projection of the plurality of first vias onto the first semiconductor layer is located within the projection of the plurality of passivation layer compensation blocks onto the first semiconductor layer.

[0014] Optionally, the projections of the first via and the passivation layer compensation block onto the first semiconductor layer are both circular, and the diameter of the circle corresponding to the passivation layer compensation block is not less than the diameter of the circle corresponding to the first via.

[0015] Optionally, the diameter of the circle corresponding to the passivation layer compensation block is 10-15 μm, and the diameter of the circle corresponding to the first through hole is 4-5 μm.

[0016] Optionally, the side of the first through hole is a slope, and the inclination angle of the side of the first through hole is 15 to 30°.

[0017] On the other hand, a method for manufacturing a light-emitting diode is provided, the method comprising:

[0018] The first semiconductor layer, the active layer, and the second semiconductor layer are fabricated sequentially.

[0019] A transparent conductive layer is fabricated on the second semiconductor layer;

[0020] A dielectric layer is fabricated, the dielectric layer covering the transparent conductive layer, and the dielectric layer having a plurality of first through-holes;

[0021] A silver reflective layer is fabricated, the silver reflective layer being located on the dielectric layer, and the silver reflective layer being connected to the transparent conductive layer through the plurality of first vias;

[0022] A first passivation layer is fabricated, which covers the transparent conductive layer and the dielectric layer. The first passivation layer has a second via and a plurality of passivation layer compensation blocks located within the second via, wherein the plurality of passivation layer compensation blocks correspond to the plurality of first vias.

[0023] An electrode is fabricated, which is located on the first passivation layer and is connected to the silver reflective layer through the second via.

[0024] Optionally, the plurality of passivation layer compensation blocks correspond one-to-one with the plurality of first vias, and the projection of the plurality of first vias onto the first semiconductor layer is located within the projection of the plurality of passivation layer compensation blocks onto the first semiconductor layer.

[0025] Optionally, the projections of the first via and the passivation layer compensation block onto the first semiconductor layer are both circular, and the diameter of the circle corresponding to the passivation layer compensation block is not less than the diameter of the circle corresponding to the first via.

[0026] Optionally, the diameter of the circle corresponding to the passivation layer compensation block is 10-15 μm, and the diameter of the circle corresponding to the first through hole is 4-5 μm.

[0027] Optionally, the side of the first through hole is a slope, and the inclination angle of the side of the first through hole is 15 to 30°.

[0028] The beneficial effects of the technical solutions provided in this disclosure are:

[0029] In the light-emitting diode provided in the embodiments of this disclosure, a plurality of passivation layer compensation blocks are provided in the second through hole of the first passivation layer. The plurality of passivation layer compensation blocks correspond to the plurality of first through holes, so that the passivation layer compensation blocks of the passivation layer can fill the unevenness caused by the first through hole of the dielectric layer, making the electrode fabricated on this basis more flat, thereby avoiding the problem of electrode breakage caused by uneven electrode and improving the reliability of the light-emitting diode. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0032] Figure 2 This is a partial structural schematic diagram of the passivation layer and dielectric layer provided in the embodiments of this disclosure;

[0033] Figure 3 This is a flowchart illustrating a method for manufacturing a light-emitting diode according to an embodiment of the present disclosure;

[0034] Figure 4 This is a flowchart of another method for manufacturing a light-emitting diode provided in this embodiment.

[0035] The attached figures are labeled as follows:

[0036] 100: Substrate; 101: First semiconductor layer; 102: Active layer; 103: Second semiconductor layer; 104: Transparent conductive layer; 105: Dielectric layer; 151: First via; 106: Silver reflective layer; 107: First passivation layer; 171: Second via; 172: Passivation layer compensation block; 108: Electrode; 181: First electrode; 182: Second electrode; 109: Protective layer; 110: Second passivation layer; 111: First electrode pad; 112: Second electrode pad; 113: Third via; 114: Fourth via; 115: Fifth via. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0038] In related technologies, the unevenness of the multiple small holes in the dielectric layer can affect the flatness of the electrode, resulting in uneven electrodes with varying thicknesses. This can easily lead to electrode breakage, which in turn can cause the chip voltage to rise or even fail.

[0039] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 1 The light-emitting diode includes: a first semiconductor layer 101, an active layer 102, a second semiconductor layer 103, a transparent conductive layer 104, a dielectric layer 105, a silver reflective layer 106, a first passivation layer 107, and an electrode 108.

[0040] The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 are stacked sequentially. The transparent conductive layer 104 is located on the second semiconductor layer 103. The dielectric layer 105 covers the transparent conductive layer 104 and has a plurality of first vias 151. The silver reflective layer 106 is located on the dielectric layer 105 and is connected to the transparent conductive layer 104 through the plurality of first vias 151. The first passivation layer 107 covers the transparent conductive layer 104 and the dielectric layer 105 and has a second via 171 and a plurality of passivation layer compensation blocks 172 located within the second via 171. The plurality of passivation layer compensation blocks 172 correspond to the plurality of first vias 151. The electrode 108 is located on the first passivation layer 107 and is connected to the silver reflective layer 106 through the second via 171.

[0041] In the light-emitting diode provided in the embodiments of this disclosure, a plurality of passivation layer compensation blocks are provided in the second through hole of the first passivation layer. The plurality of passivation layer compensation blocks correspond to the plurality of first through holes, so that the passivation layer compensation blocks of the passivation layer can fill the unevenness caused by the first through hole of the dielectric layer, making the electrode fabricated on this basis more flat, thereby avoiding the problem of electrode breakage caused by uneven electrode and improving the reliability of the light-emitting diode.

[0042] It is worth noting that, Figure 1 This is only a schematic diagram of a layered structure, and does not show the unevenness of other films caused by the influence of the dielectric layer, but this scheme ultimately makes the electrode flatter.

[0043] like Figure 1 As shown, the light-emitting diode may also include a protective layer 109, which covers the silver reflective layer 106.

[0044] In embodiments of this disclosure, the protective layer 109 may include a combination of multiple layers selected from Cr, Al, Ti, Ni, Pt, and Au. For example, the protective layer 109 may include Cr, Al, Ti, Ni, Pt, and Au layers stacked sequentially.

[0045] like Figure 1 As shown, the light-emitting diode also includes a substrate 100, a first semiconductor layer 101, an active layer 102, and a second semiconductor layer 103 are sequentially stacked on the surface of the substrate 100. The first semiconductor layer 101, the active layer 102, and the second semiconductor layer 103 have a stepped structure, with the stepped surface located on the first semiconductor layer 101.

[0046] like Figure 1 As shown, the electrode 108 includes a first electrode 181 and a second electrode 182.

[0047] The first electrode 181 is connected to the first semiconductor 101, and the second electrode 182 is connected through the second through-hole 171 of the first passivation layer 107 and the silver reflective layer 106.

[0048] like Figure 1 As shown, the light-emitting diode may also include a second passivation layer 110, a first electrode pad 111, and a second electrode pad 112.

[0049] The second passivation layer 110 covers the first passivation layer 107, the first electrode 181, and the second electrode 182.

[0050] The first electrode pad 111 penetrates the second passivation layer 110 and is connected to the first electrode 181, and the second electrode pad 112 penetrates the second passivation layer 110 and is connected to the second electrode 182.

[0051] In the embodiments disclosed herein, the substrate 100 may be any of the following: sapphire substrate, silicon substrate, etc. The material of the substrate is not limited in this disclosure.

[0052] For example, substrate 100 is a sapphire substrate.

[0053] In this embodiment of the disclosure, the first semiconductor layer 101 can be an N-type semiconductor layer, the active layer 102 can be a multi-quantum well layer, and the second semiconductor layer 103 can be a P-type semiconductor layer.

[0054] For example, the first semiconductor layer 101 is an N-type GaN layer, the active layer 102 is an InGaN / GaN layer, and the second semiconductor layer 103 is a P-type GaN layer.

[0055] In another example, the first semiconductor layer 101 can be a P-type semiconductor layer, the active layer 102 can be a multi-quantum well layer, and the second semiconductor layer 103 can be an N-type semiconductor layer.

[0056] In this embodiment of the disclosure, the transparent conductive layer 104 may be an indium tin oxide (ITO) layer.

[0057] In this embodiment of the disclosure, the dielectric layer 105 may be a silicon dioxide layer.

[0058] In this embodiment of the disclosure, the thickness of the dielectric layer 105 is 4000-5000 angstroms, for example 5000 angstroms.

[0059] In this embodiment of the disclosure, the first passivation layer 107 and the second passivation layer 110 can be SiO2 layer, TiO2 layer, Al2O3, or SiN. x Any one or more of the insulating films, where x is greater than 0.

[0060] In the embodiments of this disclosure, the passivation layer formed using the above-described materials has a good passivation effect. When the passivation layer comprises a single film layer, it can be any one or more of the aforementioned film layers; the passivation layer can also comprise multiple film layers, which can be formed using different insulating materials. Providing a passivation layer formed by stacking multiple film layers can further increase the film quality of the passivation layer.

[0061] like Figure 1As shown, the plurality of passivation layer compensation blocks 172 correspond one-to-one with the plurality of first vias 151, and the projections of the plurality of first vias 151 on the first semiconductor layer 101 are located within the projections of the plurality of passivation layer compensation blocks 172 on the first semiconductor layer 101.

[0062] This implementation method ensures the compensation effect of multiple passivation layer compensation blocks 172 and guarantees the flatness of the electrode structure.

[0063] In some examples of this disclosure, the projections of the first via 151 and the passivation layer compensation block 172 onto the first semiconductor layer 101 are both circular. For example, the first via 151 and the passivation layer compensation block 172 are either cylinders or frustums of cones.

[0064] For example, the diameter of the circle corresponding to the passivation layer compensation block 172 is not less than the diameter of the circle corresponding to the first through hole 151.

[0065] With this implementation, the diameter of the circle corresponding to the passivation layer compensation block 172 is equal to or greater than the diameter of the circle corresponding to the first through hole 151, which can make the compensation effect of the passivation layer compensation block 172 better and ensure the flatness of the electrode structure.

[0066] In other examples of this disclosure, the projections of the first via 151 and the passivation layer compensation block 172 onto the first semiconductor layer 101 can be other shapes, such as rectangles. In this case, both the first via 151 and the passivation layer compensation block 172 are cuboids or frustums.

[0067] Figure 2 This is a partial structural schematic diagram of the passivation layer and dielectric layer provided in an embodiment of this disclosure. See also... Figure 2 The projections of the first via 151 and the passivation layer compensation block 172 onto the first semiconductor layer 101 are both circular, and the diameter of the circle corresponding to the passivation layer compensation block 172 is larger than the diameter of the circle corresponding to the first via 151.

[0068] For example, the diameter of the circle corresponding to the passivation layer compensation block 172 is 10-15 μm, and the diameter of the circle corresponding to the first through hole 151 is 4-5 μm.

[0069] For example, the diameter of the circle corresponding to the passivation layer compensation block 172 is 10 μm, and the diameter of the circle corresponding to the first through hole 151 is 5 μm.

[0070] By using the passivation layer compensation block and the first through hole of the above size and shape, the flatness of the electrode structure can be guaranteed, as well as the contact effect between the electrode and the silver mirror below, thus ensuring electrical performance.

[0071] In this embodiment of the present disclosure, the side of the first through hole 151 can be a slope, and the inclination angle of the side of the first through hole 151 is 15 to 30°.

[0072] For example, the inclination angle of the side of the first through hole 151 is 30°, and the first through hole with this shape is easier to manufacture.

[0073] The slope of the sidewall of the first through hole at the above angle is relatively small, resulting in a less uneven electrode surface. The compensation effect of using a passivation layer compensation block is better.

[0074] In this embodiment of the disclosure, the spacing between adjacent passivation layer compensation blocks can be greater than the diameter of the passivation layer compensation block.

[0075] In this embodiment, the first passivation layer 107 further has a third via 113, through which the first electrode 181 is connected to the first semiconductor layer 101.

[0076] In this embodiment, the second passivation layer 110 has a fourth through hole 114 and a fifth through hole 115. The first electrode pad 111 is connected to the first electrode 181 through the fourth through hole 114, and the second electrode pad 112 is connected to the second electrode 182 through the fifth through hole 115.

[0077] In this embodiment of the present disclosure, the first electrode 181 and the second electrode 182 include a Cr layer, an Al layer, a Ti layer, a Ni layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer stacked sequentially.

[0078] In this embodiment of the present disclosure, the first electrode pad 111 and the second electrode pad 112 include Ti layer, Al layer, Ti layer, Al layer, Ti layer, Pt layer and AuSn layer stacked sequentially.

[0079] In one example, when the first semiconductor layer 101 is an N-type semiconductor layer, the first electrode 181 is an N-type electrode and the first electrode pad 111 is an N-type electrode pad; when the second semiconductor layer 103 is a P-type semiconductor layer, the second electrode 182 is a P-type electrode and the second electrode pad 112 is a P-type electrode pad.

[0080] In another example, when the first semiconductor layer 101 is a P-type semiconductor layer, the first electrode 181 is a P-electrode and the first electrode pad 111 is a P-electrode pad; when the second semiconductor layer 103 is an N-type semiconductor layer, the second electrode 182 is an N-electrode and the second electrode pad 112 is an N-electrode pad.

[0081] Figure 3 A method for manufacturing a light-emitting diode (LED) is provided as an embodiment of this disclosure. See also: Figure 3 The method includes the following steps:

[0082] S11. Sequentially fabricate the first semiconductor layer, the active layer, and the second semiconductor layer.

[0083] In this embodiment of the disclosure, the first semiconductor layer can be an N-type semiconductor layer, the active layer can be a multi-quantum well layer, and the second semiconductor layer can be a P-type semiconductor layer.

[0084] For example, the first semiconductor layer is an N-type GaN layer, the active layer is an InGaN / GaN layer, and the second semiconductor layer is a P-type GaN layer.

[0085] S12. Fabricate a transparent conductive layer, wherein the transparent conductive layer is located on the second semiconductor layer.

[0086] S13. Fabricate a dielectric layer, the dielectric layer covering the transparent conductive layer, the dielectric layer having a plurality of first through holes.

[0087] S14. Fabricate a silver reflective layer, wherein the silver reflective layer is located on the dielectric layer and is connected to the transparent conductive layer through the plurality of first vias.

[0088] S15. Fabricate a first passivation layer, which covers the transparent conductive layer and the dielectric layer. The first passivation layer has a second through-hole and a plurality of passivation layer compensation blocks located within the second through-hole. The plurality of passivation layer compensation blocks correspond to the plurality of first through-holes.

[0089] S16. Fabricate an electrode, wherein the electrode is located on the first passivation layer and is connected to the silver reflective layer through the second through-hole.

[0090] In the embodiments of this disclosure, the passivation layer formed using the above-described materials has a good passivation effect. When the passivation layer comprises a single film layer, it can be any one or more of the aforementioned film layers; the passivation layer can also comprise multiple film layers, which can be formed using different insulating materials. Providing a passivation layer formed by stacking multiple film layers can further increase the film quality of the passivation layer.

[0091] Figure 4 A flowchart illustrating another method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 4 The method includes the following steps:

[0092] S21. A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially fabricated on the surface of a substrate, wherein the first semiconductor layer, the active layer, and the second semiconductor layer have a stepped structure.

[0093] In this embodiment of the disclosure, the first semiconductor layer is an N-type GaN layer, the active layer is an InGaN / GaN layer, and the second semiconductor layer is a P-type GaN layer.

[0094] In one example, step S21 includes:

[0095] The first step is to grow the first semiconductor layer.

[0096] The first semiconductor layer is an N-type GaN layer.

[0097] For example, an N-type GaN layer can be grown on a substrate surface using a metal-organic chemical vapor deposition (MOCVD) device.

[0098] In the embodiments disclosed herein, semiconductor layer growth can be achieved using Veeco K465i, C4, or RB MOCVD equipment or AIXTRON metal-organic chemical vapor deposition equipment. High-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas; high-purity NH3 is used as the N source; trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources; trimethylindium (TMIn) is used as the indium source; silane (SiH4) is used as the N-type dopant; trimethylaluminum (TMAl) is used as the aluminum source; and magnesium pyrocene (CP2Mg) is used as the P-type dopant.

[0099] The second step is to grow the active layer.

[0100] The active layer is an InGaN / GaN layer.

[0101] For example, an InGaN / GaN layer is grown on the surface of an N-type GaN layer using an MOCVD device.

[0102] The third step is to grow a second semiconductor layer.

[0103] The second semiconductor layer is a P-type GaN layer.

[0104] For example, a P-type GaN layer is grown on the surface of an InGaN / GaN layer using an MOCVD device.

[0105] The fourth step is to pattern the first semiconductor layer, the active layer, and the second semiconductor layer to form a stepped structure.

[0106] For example, inductively coupled plasma (ICP) etching technology is used to pattern the first semiconductor layer, the active layer, and the second semiconductor layer that are stacked sequentially in the epitaxial structure to form a stepped structure.

[0107] S22. Fabricate a transparent conductive layer, which is located on the second semiconductor layer.

[0108] In one example, step S22 includes:

[0109] A transparent conductive layer is formed on the surface of the second semiconductor layer using magnetron sputtering technology.

[0110] The transparent conductive layer is an ITO layer.

[0111] S23. A dielectric layer, a silver reflective layer, and a protective layer are fabricated sequentially. The dielectric layer covers the transparent conductive layer and has multiple first vias. The silver reflective layer is located on the dielectric layer and is connected to the transparent conductive layer through the multiple first vias. The protective layer covers the silver reflective layer.

[0112] In one example, step S23 includes:

[0113] An insulating thin film covering a transparent conductive layer is formed on the surface of a second semiconductor layer using magnetron sputtering. The insulating thin film is patterned using etching to obtain an insulating layer with multiple first vias. A silver reflective layer is formed on the insulating layer using magnetron sputtering, and the silver reflective layer is connected to the transparent conductive layer through the multiple first vias. A protective layer is formed on the silver reflective layer using magnetron sputtering.

[0114] The dielectric layer can be a silicon dioxide layer. The thickness of the dielectric layer is 4000-5000 angstroms, for example, 5000 angstroms.

[0115] The protective layer may include a combination of various layers selected from Cr, Al, Ti, Ni, Pt, and Au. For example, the protective layer may consist of Cr, Al, Ti, Ni, Pt, and Au layers stacked sequentially.

[0116] S24. Fabricate a first passivation layer, which covers a transparent conductive layer and a dielectric layer. The first passivation layer has a second through-hole and multiple passivation layer compensation blocks located within the second through-hole. The multiple passivation layer compensation blocks correspond to the multiple first through-holes.

[0117] In one example, the first passivation layer can be a SiO2 layer, a TiO2 layer, an Al2O3 layer, or a SiN layer. x Any one or more of the insulating films, where x is greater than 0.

[0118] In one example, step S24 includes: depositing a first passivation layer film; forming a second via, a third via, and a plurality of passivation layer compensation blocks within the second via in the first passivation layer film using a patterning technique to obtain the first passivation layer.

[0119] like Figure 1As shown, the plurality of passivation layer compensation blocks 172 correspond one-to-one with the plurality of first vias 151, and the projections of the plurality of first vias 151 on the first semiconductor layer 101 are located within the projections of the plurality of passivation layer compensation blocks 172 on the first semiconductor layer 101.

[0120] This implementation method ensures the compensation effect of multiple passivation layer compensation blocks 172 and guarantees the flatness of the electrode structure.

[0121] In some examples of this disclosure, the projections of the first via 151 and the passivation layer compensation block 172 onto the first semiconductor layer 101 are both circular. For example, the first via 151 and the passivation layer compensation block 172 are either cylinders or frustums of cones.

[0122] For example, the diameter of the circle corresponding to the passivation layer compensation block 172 is not less than the diameter of the circle corresponding to the first through hole 151.

[0123] With this implementation, the diameter of the circle corresponding to the passivation layer compensation block 172 is equal to or greater than the diameter of the circle corresponding to the first through hole 151, which can make the compensation effect of the passivation layer compensation block 172 better and ensure the flatness of the electrode structure.

[0124] In other examples of this disclosure, the projections of the first via 151 and the passivation layer compensation block 172 onto the first semiconductor layer 101 can be other shapes, such as rectangles. In this case, both the first via 151 and the passivation layer compensation block 172 are cuboids or frustums.

[0125] Figure 2 This is a partial structural schematic diagram of the passivation layer and dielectric layer provided in an embodiment of this disclosure. See also... Figure 2 The projections of the first via 151 and the passivation layer compensation block 172 onto the first semiconductor layer 101 are both circular, and the diameter of the circle corresponding to the passivation layer compensation block 172 is larger than the diameter of the circle corresponding to the first via 151.

[0126] For example, the diameter of the circle corresponding to the passivation layer compensation block 172 is 10-15 μm, and the diameter of the circle corresponding to the first through hole 151 is 4-5 μm.

[0127] For example, the diameter of the circle corresponding to the passivation layer compensation block 172 is 10 μm, and the diameter of the circle corresponding to the first through hole 151 is 5 μm.

[0128] By using the passivation layer compensation block and the first through hole of the above size and shape, the flatness of the electrode structure can be guaranteed, as well as the contact effect between the electrode and the silver mirror below, thus ensuring electrical performance.

[0129] In this embodiment of the present disclosure, the side of the first through hole 151 can be a slope, and the inclination angle of the side of the first through hole 151 is 15 to 30°.

[0130] For example, the inclination angle of the side of the first through hole 151 is 30°, and the first through hole with this shape is easier to manufacture.

[0131] The slope of the sidewall of the first through hole at the above angle is relatively small, resulting in a less uneven electrode surface. The compensation effect of using a passivation layer compensation block is better.

[0132] In this embodiment of the disclosure, the spacing between adjacent passivation layer compensation blocks can be greater than the diameter of the passivation layer compensation block.

[0133] S25. Fabricate a first electrode and a second electrode. The first electrode is connected to the first semiconductor layer through a third through-hole, and the second electrode is connected to the protective layer through a second through-hole.

[0134] In one example, step S25 includes:

[0135] The first and second electrodes were fabricated using electron beam evaporation and etching techniques.

[0136] In the embodiments of this disclosure, the first electrode and the second electrode include a Cr layer, an Al layer, a Ti layer, a Ni layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer stacked sequentially.

[0137] S26. Fabricate a second passivation layer, which covers the first passivation layer, the first electrode, and the second electrode.

[0138] In one example, the second passivation layer can be a SiO2 layer, a TiO2 layer, an Al2O3 layer, or a SiN layer. x Any one or more of the insulating films, where x is greater than 0.

[0139] In one example, step S26 includes: depositing a second passivation layer film; forming a fourth via and a fifth via on the second passivation layer film using a patterning technique to obtain the second passivation layer.

[0140] S27. Fabricate the first electrode pad and the second electrode pad. The first electrode pad is connected to the first electrode through the fourth through hole, and the second electrode pad is connected to the second electrode through the fifth through hole.

[0141] In one example, step S27 includes:

[0142] The first electrode pad and the second electrode pad are fabricated using electron beam evaporation and etching techniques.

[0143] In this embodiment of the disclosure, the first electrode pad and the second electrode pad include Ti layer, Al layer, Ti layer, Al layer, Ti layer, Pt layer and AuSn layer stacked sequentially.

[0144] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light emitting diode, characterized by, The light emitting diode comprises: a first semiconductor layer (101), an active layer (102) and a second semiconductor layer (103) stacked in sequence; a transparent conductive layer (104) on the second semiconductor layer (103); a dielectric layer (105) covering the transparent conductive layer (104), the dielectric layer (105) having a plurality of first through holes (151); a silver reflective layer (106) on the dielectric layer (105), the silver reflective layer (106) being connected with the transparent conductive layer (104) through the plurality of first through holes (151); a first passivation layer (107) covering the transparent conductive layer (104) and the dielectric layer (105), the first passivation layer (107) having a second through hole (171) and a plurality of passivation layer compensation blocks (172) in the second through hole (171), the plurality of passivation layer compensation blocks (172) corresponding to the plurality of first through holes (151) one-to-one, and the projections of the plurality of first through holes (151) on the first semiconductor layer (101) being located in the projections of the plurality of passivation layer compensation blocks (172) on the first semiconductor layer (101); an electrode (108) on the first passivation layer (107), and the electrode (108) being connected with the silver reflective layer (106) through the second through hole (171).

2. The light emitting diode of claim 1, wherein, The projections of the first through holes (151) and the passivation layer compensation blocks (172) on the first semiconductor layer (101) are circular, and the diameters of the corresponding circles of the passivation layer compensation blocks (172) are not less than the diameters of the corresponding circles of the first through holes (151).

3. The light emitting diode of claim 2, wherein, The diameters of the corresponding circles of the passivation layer compensation blocks (172) are 10-15 µm, and the diameters of the corresponding circles of the first through holes (151) are 4-5 µm.

4. The light emitting diode according to any one of claims 1 to 3, wherein, The side edges of the first through holes (151) are inclined surfaces, and the inclination angles of the side edges of the first through holes (151) are 15-30°.

5. A method of fabricating a light emitting diode, comprising: The method comprises: sequentially preparing a first semiconductor layer, an active layer and a second semiconductor layer; preparing a transparent conductive layer on the second semiconductor layer; preparing a dielectric layer covering the transparent conductive layer, the dielectric layer having a plurality of first through holes; preparing a silver reflective layer on the dielectric layer, the silver reflective layer being connected with the transparent conductive layer through the plurality of first through holes; preparing a first passivation layer covering the transparent conductive layer and the dielectric layer, the first passivation layer having a second through hole and a plurality of passivation layer compensation blocks in the second through hole, the plurality of passivation layer compensation blocks corresponding to the plurality of first through holes one-to-one, and the projections of the plurality of first through holes on the first semiconductor layer being located in the projections of the plurality of passivation layer compensation blocks on the first semiconductor layer; An electrode is made on the first passivation layer, and the electrode is connected with the silver reflective layer through the second via hole.

6. The method of claim 5, wherein, The first via hole and the passivation layer compensation block are circular in projection on the first semiconductor layer, and the diameter of the circular corresponding to the passivation layer compensation block is not less than the diameter of the circular corresponding to the first via hole.

7. The method of claim 6, wherein, The diameter of the circular corresponding to the passivation layer compensation block is 10-15 µm, and the diameter of the circular corresponding to the first via hole is 4-5 µm.

8. The method according to any one of claims 5 to 7, characterized in that, The side of the first via hole is a slope, and the inclination angle of the side of the first via hole is 15-30°.

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