A silicon-based thin-film crystal preparation method based on silicon wafer hetero-epitaxy

Abstract

The application discloses a silicon-based thin film crystal preparation method based on silicon wafer hetero-epitaxy, which comprises the following steps: preparing a three-layer structure of a bottom insulator / intermediate layer / top insulator on a silicon substrate; etching the three-layer structure to obtain a groove and expose the bottom silicon substrate, thereby obtaining a vertical selected area epitaxial region; etching the surface of the silicon substrate at the bottom of the groove into a V-shaped groove and hollowing out the intermediate layer of the sidewall of a nano ridge epitaxial region to both sides; vertically and selectively hetero-epitaxially growing a group III-V semiconductor nano ridge in the groove; depositing an insulator cladding layer on the surface of the wafer; opening a window at the edge position of a hollow layer which is several microns away from the sidewall of the above-mentioned group III-V semiconductor nano ridge; and laterally and homogeneously epitaxially growing a group III-V semiconductor thin film in the hollow layer of the wafer. The three-layer structure of the group III-V semiconductor / insulator / silicon prepared by the method realizes low-cost, large-size and low-defect-density silicon-based group III-V semiconductor crystal thin film preparation and can be efficiently optically coupled with a silicon waveguide.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated optoelectronic devices and semiconductor materials, and more particularly, to a silicon-based thin film crystal preparation method based on silicon wafer heteroepitaxy. BACKGROUND

[0002] Optoelectronic chips are integrated through optical interconnection technology, which makes originally discrete optoelectronic devices integrated, constantly improves functionality and integration, and also constantly reduces the power consumption and cost of chips; at present, it has become the core technology of data centers and optical communication networks, and also the enabling technology of cloud computing, Internet of Things, and unmanned driving. Compared with indium phosphide (InP) based optoelectronic integration technology, silicon-based optoelectronic integration technology can greatly reduce production cost and greatly improve chip integration. However, since silicon is an indirect bandgap semiconductor, it cannot be used to prepare high-efficiency on-chip light sources, so silicon-based optoelectronic integrated chips need to integrate direct bandgap III-V semiconductors to realize high-efficiency on-chip lasers.

[0003] On the one hand, most of the industry currently adopts hetero-integration technology based on wafer bonding to realize the on-chip integration of silicon-based III-V lasers. The unique three-layer stack structure of "III-V semiconductor / insulator / silicon" in this way can realize efficient evanescent wave coupling between III-V semiconductor and silicon waveguide, and then can combine the low-loss characteristics of silicon material and the high-gain characteristics of III-V semiconductor. However, wafer bonding needs more expensive III-V substrates as the source of transferred materials, and the size of III-V material wafer is much smaller than that of silicon optical SOI wafer (the largest indium phosphide wafer is 4 inches, while the largest silicon optical silicon wafer reaches 12 inches), so the integration cost of this technology is high, and the integration degree is limited. In addition, the existing electrically pumped laser diodes integrated on silicon through wafer bonding all have PIN structures doped in the vertical direction, and the active region is far away from the silicon waveguide, which leads to the need for large coupling structures (such as tapered couplers), and the vertical device epitaxial layer is thick, which needs thick silicon waveguide to realize evanescent wave coupling, resulting in that the existing bonded lasers cannot be compatible with the industry standard 220nm SOI substrate, and need to use more expensive thick silicon SOI as the substrate. In summary, wafer bonding technology has the problems of high cost and low integration, and restricts its large-scale commercial application.

[0004] On the other hand, large-area heteroepitaxy can prepare large-size III-V semiconductor crystal thin films on silicon and can manufacture high-performance electrically pumped lasers thereon; selective heteroepitaxy is a method for realizing low-dislocation-density III-V semiconductor crystals on silicon, and the "defect-limiting effect" brings about the "defect-free buffer layer" feature, which can realize high-efficiency optical coupling between III-V semiconductors and silicon-based waveguides. However, the two epitaxy techniques have their own technical bottlenecks. Large-area heteroepitaxy has a defect buffer layer of several microns thick, which makes it difficult to realize high-efficiency optical coupling between the epitaxial III-V laser and the silicon waveguide, and thus monolithic integration of silicon-based lasers cannot be realized. The selective heteroepitaxy method usually obtains III-V semiconductor crystals of sub-micron size, and it is difficult to manufacture metal electrodes on small-size crystals, and the manufactured metal electrodes often cause excessive optical absorption loss. In addition, the structure realized by large-area heteroepitaxy and general vertical selective heteroepitaxy is usually a two-layer stack structure of "III-V semiconductor / silicon", and since the refractive index difference between III-V semiconductor and silicon is small, it is difficult to realize high-density optoelectronic integrated devices. Moreover, there are high-density crystal defects at the interface between III-V semiconductor and silicon in this two-layer stack structure, which also adversely affects the optical coupling efficiency of the two.

[0005] In summary, neither the wafer bonding technique nor the silicon-based heteroepitaxy method can simultaneously realize the key characteristics of low-cost, large-size, low-defect-density, and high-efficiency optical coupling with silicon waveguides required for silicon-based light sources, and improving one characteristic often severely affects another characteristic. SUMMARY

[0006] The present application is to overcome the defects of the above-mentioned two heteroepitaxy methods that cannot simultaneously meet the requirements of low-defect-density, high-efficiency optical coupling with silicon waveguides, and large-size thin film crystal structure for optoelectronic integration, and provides a silicon-based thin film crystal preparation method based on silicon wafer heteroepitaxy.

[0007] The primary object of the present application is to solve the above technical problems, and the technical solution of the present application is as follows:

[0008] The present application provides a silicon-based thin film crystal preparation method based on silicon wafer heteroepitaxy, which comprises the following steps:

[0009] S1: using a thin film preparation method to prepare a three-layer structure of bottom insulator / intermediate layer / top insulator on a silicon substrate, and each layer can be several hundred nanometers thick;

[0010] S2: etching the three-layer structure to obtain a trench by using photolithography combined with dry etching process, and exposing the silicon substrate at the bottom of the trench, i.e., obtaining a vertical selective epitaxy region;

[0011] S3: etching the surface of the silicon substrate at the bottom of the trench into a V-shaped groove composed of two silicon {111} crystal faces by using a wet etching process, and hollowing out the middle layer of the sidewall of the epitaxial region of the nanoridge on both sides by using a wet etching or soft dry etching process, so that the hollow layer has a lateral depth of several microns;

[0012] S4: growing a Ⅲ-Ⅴ semiconductor nanoridge in the trench with the hollow layer and the V-shaped groove by vertical selective heteroepitaxy using a Ⅲ-Ⅴ semiconductor epitaxial growth device, wherein the height of the nanoridge is higher than the hollow layer and the top insulator serves as a support;

[0013] S5: depositing an insulator cladding layer on the surface of the wafer by using a thin film preparation method;

[0014] S6: opening a window at the edge of the hollow layer at a distance of several microns from the sidewall of the Ⅲ-Ⅴ semiconductor nanoridge by using photolithography combined with a dry etching process;

[0015] S7: laterally homoepitaxially growing a Ⅲ-Ⅴ semiconductor thin film in the hollow layer of the wafer by using a Ⅲ-Ⅴ semiconductor epitaxial growth device.

[0016] Further, the V-shaped groove composed of two silicon {111} crystal faces at the bottom of the Ⅲ-Ⅴ semiconductor nanoridge epitaxial region can inhibit the formation of reverse domain boundary defects in the epitaxial growth of the Ⅲ-Ⅴ semiconductor.

[0017] Further, the vertically grown Ⅲ-Ⅴ semiconductor nanoridge is a high-quality Ⅲ-Ⅴ semiconductor crystal, the upper layer of which has a dislocation density lower than a preset value or no dislocation, and no antiphase domain lattice defects, so that it can serve as a high-quality seed crystal for the laterally homoepitaxially grown Ⅲ-Ⅴ semiconductor thin film.

[0018] Further, in the three-layer structure of the bottom insulator / middle layer / top insulator, the wet etching or soft dry etching selectivity between the middle layer material and the bottom / top insulator is greater than a preset threshold value, so as to hollow out the middle layer to obtain a structure with a hollow layer.

[0019] Further, the thin film of the top insulator needs to be able to support the hollow layer without deformation.

[0020] Further, the hollow layer provides space for the three-layer stacked structure to meet the lateral epitaxial growth of the Ⅲ-Ⅴ semiconductor thin film.

[0021] Further, the insulator cladding layer is used to isolate the Ⅲ-Ⅴ semiconductor nanoridge from the chemical vapor deposition gas during the horizontal lateral epitaxial growth, so as to prevent the gas from reacting and depositing to grow crystals vertically again.

[0022] Further, the gas of the chemical vapor deposition method in step S7 enters the hollow layer from the window, contacts the nanoridge sidewall, and laterally epitaxially grows a crystal thin film from the nanoridge sidewall.

[0023] Further, the metal organic chemical vapor deposition group III-V semiconductor epitaxial growth equipment is used in both step S4 and step S7.

[0024] The second aspect of the present application provides a silicon-based thin film crystal preparation system based on silicon wafer heteroepitaxy, which adopts the silicon-based thin film crystal preparation method based on silicon wafer heteroepitaxy.

[0025] Compared with the prior art, the beneficial effects of the technical scheme of the present application are:

[0026] The present application uses a three-layer structure of bottom insulator / intermediate layer / top insulator to construct an epitaxial frame, and realizes a III-V semiconductor / insulator / silicon three-layer stack structure through low-cost epitaxy. The three-layer stack structure of the present application is consistent with the III-V semiconductor / silicon dioxide / silicon three-layer stack structure currently used in the silicon light industry, which can ensure efficient evanescent wave coupling between the III-V laser and the silicon waveguide. Moreover, the present application has a lateral epitaxial direction, and a PIN laser diode doped in the horizontal direction can be subsequently regrown. The laser active region can have a very thin longitudinal thickness. In the process of preparing a waveguide coupling structure using an SOI substrate, the present application is compatible with a 220nm top silicon standard SOI with lower cost, and the size of the coupling structure can be correspondingly reduced. Therefore, the present application can greatly reduce the process cost of silicon-based III-V semiconductor integration and significantly improve the integration level.

[0027] The present application fully utilizes the defect limiting effect of selective area heteroepitaxy by combining vertical selective area heteroepitaxy with lateral homoepitaxy. First, the deep-width ratio trench obtained by etching the three-layer insulator layer makes the III-V semiconductor obtained through vertical selective area heteroepitaxy have extremely low dislocation density or even no dislocation. In addition, the two silicon {111} crystal planes constituting the V-shaped groove at the bottom of the trench make the nanoridge have no crystal defects such as antiphase domain and reverse domain boundaries. At the same time, since the second step of lateral homoepitaxy theoretically does not produce defects, and the extremely high depth-width ratio of the hollow layer in the horizontal direction can further limit the propagation of dislocations in the growth direction, the III-V semiconductor thin film obtained through the present application has very low defect density.

[0028] Since lateral homoepitaxial growth does not require a low-temperature nucleation layer, this invention allows for the setting of chemical vapor deposition (CVD) conditions that provide a large diffusion length for gas molecules within the CVD system. This enables the gas to penetrate into a hollow layer with a horizontal depth of tens of micrometers, thereby growing a large-area III-V semiconductor thin film. This film can then be used as a substrate for regrowth and fabrication of various III-V semiconductor optoelectronic devices. Furthermore, by utilizing efficient evanescent wave coupling, a low-cost, large-area optoelectronic material platform can be provided for the subsequent monolithic integration of various III-V active devices and silicon-based passive devices. Attached Figure Description

[0029] Figure 1 This is a flowchart illustrating a method for preparing silicon-based thin film crystals based on heteroepitaxial growth of silicon wafers, provided as an embodiment of this application.

[0030] Figure 2 This is a schematic diagram of a three-layer stacked structure of a group III-V semiconductor / silicon nitride / silicon provided in an embodiment of this application.

[0031] Figure 3 This is a schematic diagram illustrating the fabrication process of a three-layer stacked structure of a group III-V semiconductor / silicon nitride / silicon, provided in an embodiment of this application.

[0032] Figure 4 SEM image of InP nanoridges obtained by vertical selected region heteroepitaxialization, provided for an embodiment of this application. Detailed Implementation

[0033] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0034] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0035] Example 1

[0036] like Figure 1 As shown, the first aspect of the present invention provides a method for preparing silicon-based thin film crystals based on silicon wafer heteroepitaxial growth, comprising the following steps:

[0037] S1: A three-layer structure of bottom insulator 2 / intermediate layer 3 / top insulator 4 is prepared on substrate 1 using thin film preparation methods such as chemical vapor deposition. The thickness of each layer can be several hundred nanometers. The substrate can be a silicon wafer with (001) crystal orientation or silicon on insulator (SOI).

[0038] It should be noted that the silicon substrate can be a silicon wafer with a (001) crystal orientation or a silicon-on-insulator (SOI).

[0039] S2: etching the three-layer structure by photolithography combined with a dry etching process to obtain a trench and expose the silicon substrate 1 at the bottom of the trench, i.e., to obtain a vertical selected-area epitaxial region;

[0040] S3: etching the surface of the silicon substrate 1 at the bottom of the trench into a V-shaped groove composed of two silicon {111} crystal planes by a wet etching process, and hollowing out the middle layer 3 of the sidewall of the nanoridge epitaxial region to a depth of several microns by a wet etching or soft dry etching process;

[0041] It should be noted that the V-shaped groove composed of two silicon {111} crystal planes at the bottom of the III-V semiconductor nanoridge epitaxial region can inhibit the formation of reverse domain boundary defects in III-V semiconductor epitaxial growth.

[0042] The vertically selected-area heteroepitaxial growth III-V semiconductor nanoridge is a high-quality III-V semiconductor crystal, and the upper layer of the crystal has a dislocation density lower than a preset value or no dislocation, and no antiphase domain lattice defects, so that it can serve as a high-quality seed crystal for the lateral homoepitaxial growth III-V semiconductor thin film.

[0043] Further, in the three-layer structure of the bottom insulator / middle layer / top insulator, the wet etching or soft dry etching selectivity between the middle layer material and the bottom / top insulator is greater than a preset threshold value, so as to hollow out the middle layer to obtain a structure with a hollow layer.

[0044] Further, the thin film of the top insulator needs to be able to support the hollow layer without deformation.

[0045] Further, the hollow layer provides a space for the three-layer stacked structure to meet the lateral epitaxial growth of the III-V semiconductor thin film.

[0046] S4: using a metal organic chemical vapor deposition (MOCVD) or other III-V semiconductor epitaxial growth equipment to vertically selected-area heteroepitaxially grow a III-V semiconductor nanoridge 5 in the trench with a hollow layer and a V-shaped groove, the height of the nanoridge 5 needs to be higher than the hollow layer, and the top insulator 4 is supported;

[0047] S5: depositing an insulator cladding layer 6 on the wafer surface by a thin film preparation method;

[0048] Further, the insulator coating layer is used to isolate the III-V semiconductor nanoridges from the chemical vapor deposition gas during the horizontal lateral epitaxial growth process, preventing the gas from reacting and depositing at the nanoridges to re-vertically grow crystals.

[0049] S6: A window is opened at the edge of the hollow layer at a distance of several microns from the sidewall of the III-V semiconductor nanoridges 5 using photolithography combined with dry etching process;

[0050] S7: The III-V semiconductor thin film 7 is laterally homo-epitaxially grown in the hollow layer of the wafer using a III-V semiconductor epitaxial growth device.

[0051] In step S7, the gas of the chemical vapor deposition method enters the hollow layer from the window, contacts the nanoridge sidewall, and laterally homo-epitaxially grows a crystal thin film from the nanoridge sidewall.

[0052] The second aspect of the present application provides a silicon-based thin film crystal preparation system based on silicon wafer hetero-epitaxy.

[0053] Figure 2 A structure of a III-V semiconductor / silicon nitride / silicon three-layer stack structure is shown.

[0054] Example 2

[0055] This example takes the preparation of a "indium phosphide / silicon nitride / silicon" three-layer stack structure as an example, and combines Figure 3 (a) to (g) to explain in detail the method for manufacturing a "indium phosphide / silicon nitride / silicon" three-layer stack structure. The substrate 1 is a (001) crystal-oriented silicon wafer, the bottom insulator 2 is silicon nitride, the intermediate layer 3 is silicon dioxide, the top insulator 4 is silicon nitride, the III-V semiconductor nanoridge 5 obtained by vertical selective hetero-epitaxy is indium phosphide, the insulator coating layer 6 is silicon dioxide, and the III-V semiconductor thin film 7 obtained by lateral homo-epitaxy is indium phosphide. The specific steps are as follows:

[0056] (1) A "silicon nitride / silicon dioxide / silicon nitride" three-layer structure is grown on a cleaned (001) crystal-oriented silicon substrate 1, wherein the bottom silicon nitride 2 and the top silicon nitride 4 are grown by a low-pressure chemical vapor deposition system (LPCVD) at 700°C, and the intermediate layer of silicon dioxide 3 is grown by an inductively coupled plasma chemical vapor deposition system (ICPCVD) at 300°C, and the thickness of the three layers is about 200 nm, as shown in Figure 3 (a);

[0057] (2) Position the vertical epitaxial region of InP nanoridges by an electron beam lithography system (EBL), the nanoridge epitaxial region width is 450 nm, length is 2 mm; then etch the "silicon nitride / silicon dioxide / silicon nitride" three-layer structure by a reactive ion beam etching system (RIE), the etching gas combination is CHF3 and O2, etch to the surface of the silicon substrate 1, and remove the photoresist, as shown in Figure 3 (b) ;

[0058] (3) Use 45% potassium hydroxide (KOH) solution at 70°C to etch a V-shaped groove at the bottom of the trench by using its anisotropic wet etching on the silicon substrate 1, and then use 6:1 BOE (buffered oxide etching solution) stock solution to hollow out the middle layer of silicon dioxide 3 on both sides of the trench sidewall by about 10 μm, to obtain a hollow layer for horizontal lateral epitaxy, the obtained structure is as shown in Figure 3 (c) ;

[0059] (4) As shown in Figure 3 (d), use a metal organic chemical vapor deposition system (MOCVD) to epitaxially grow InP nanoridges 5 by a "vertical selective heteroepitaxy" method, Figure 4 (a) and (b) are SEM (scanning electron microscope) images of the InP nanoridges 5 grown by this step in this embodiment;

[0060] (5) Use an inductively coupled plasma chemical vapor deposition system (ICPCVD) to grow a silicon dioxide coating layer 6 on the surface by about 30 nm, as shown in Figure 3 (e) ;

[0061] (6) Position a window at the edge of the hollow layer by a few microns from the InP nanoridges 5 by a maskless lithography machine, the window width is about 5 μm, and then etch the silicon dioxide coating layer 6 and the top layer of silicon nitride 4 at the window by a reactive ion beam etching system (RIE), as shown in Figure 3 (f) ;

[0062] (7) Use a metal organic chemical vapor deposition system (MOCVD) to grow an InP thin film 7 in the hollow layer by a "lateral homoepitaxy" method, as shown in Figure 3 (g).

[0063] Example 3

[0064] This embodiment takes the preparation of a "InP / silicon dioxide / silicon" three-layer stack structure as an example, and the specific preparation process is as follows Figure 3(a) to (g) shown, wherein the substrate 1 is a (001) crystal direction silicon wafer, the bottom insulator 2 is silicon dioxide, the middle layer 3 is polysilicon, the top insulator 4 is silicon nitride, the III-V semiconductor nanoridge 5 obtained by vertical selective heteroepitaxy is indium phosphide, the insulator coating layer 6 is silicon dioxide, and the III-V semiconductor thin film 7 obtained by lateral horizontal homoepitaxy is indium phosphide. The specific steps are as follows:

[0065] (1) A "silicon nitride / polysilicon / silicon dioxide" three-layer structure is grown on a cleaned (001) crystal direction silicon substrate 1, the bottom silicon dioxide 2 and the middle layer polysilicon 3 are grown by an inductively coupled plasma chemical vapor deposition system (ICPCVD) at 300°C, and the top silicon nitride 4 is grown by a low-pressure chemical vapor deposition system (LPCVD) at 700°C, and the thickness of the three layers is about 200 nm, as shown in Figure 3 (a);

[0066] (2) The vertical epitaxial area of the indium phosphide nanoridge is positioned by an electron beam exposure system (EBL), the nanoridge epitaxial area has a width of 450 nm and a length of 2 mm; then the "silicon nitride / polysilicon / silicon dioxide" three-layer structure is etched by a reactive ion beam etching system (RIE), the etching gas combination is CHF3 and O2, 60 nm of silicon dioxide is etched and the photoresist is removed, as shown in Figure 3 (b);

[0067] (3) The residual silicon dioxide at the bottom of the trench is etched using a 30% potassium hydroxide (KOH) solution at 80°C, and then the V-shaped groove is etched at the bottom of the trench by utilizing the anisotropic wet etching of the silicon substrate 1 and the isotropic wet etching of the middle layer amorphous silicon 3, and a hollow layer with a horizontal direction depth of 10 μm is obtained at the same time, and the obtained structure is as shown in Figure 3 (c);

[0068] (4) The indium phosphide nanoridge 5 is epitaxied by a metal organic chemical vapor deposition system (MOCVD) through "vertical selective heteroepitaxy", as shown in Figure 3 (d);

[0069] (5) A silicon dioxide coating layer 6 with a thickness of about 30 nm is grown on the surface by an inductively coupled plasma chemical vapor deposition system (ICPCVD), as shown in Figure 3 (e);

[0070] (6) A window is positioned at the edge of the hollow layer about several microns away from the indium phosphide nanoridge 5 by a maskless lithography machine, and the window has a width of about 5 μm, and then the silicon dioxide coating layer 6 and the top silicon nitride 4 at the window are etched by a reactive ion beam etching system (RIE), as shown in Figure 3 (f);

[0071] (7) Using a metal organic chemical vapor deposition system (MOCVD) to grow an indium phosphide film 7 in the hollow layer by "lateral homoepitaxy", as shown in Figure 3 (g).

[0072] The same or similar reference numerals in the drawings denote the same or similar components;

[0073] The terms describing the positional relationship in the drawings are only used for illustrative description, and should not be understood as a limitation to the present patent;

[0074] Obviously, the above embodiments of the present application are merely exemplary for clearly illustrating the present application, and are not intended to limit the implementation manners of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and also impossible to enumerate all the implementation manners. Any modification, equivalent replacement and improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the claims of the present application.

Claims

1. A method for preparing a silicon-based thin-film crystal based on silicon wafer hetero-epitaxy, characterized in that, The method comprises the following steps: S1: preparing a three-layer structure of bottom insulator / intermediate layer / top insulator on a silicon substrate by a thin film preparation method; S2: etching the three-layer structure by photolithography combined with a dry etching process to obtain a trench and expose the silicon substrate at the bottom of the trench, i.e. to obtain a vertical selected area epitaxial region; S3: etching the surface of the silicon substrate at the bottom of the trench into a V-shaped groove composed of two silicon {111} crystal faces by a wet etching process, and hollowing out the intermediate layer on the sidewall of the trench region to the two sides by a wet etching or soft dry etching process to obtain a structure with a hollow layer; S4: vertically selected area heteroepitaxially growing a group III-V semiconductor nanoridge in the trench with the hollow layer and V-shaped groove by a group III-V semiconductor epitaxial growth device, the height of the nanoridge being higher than the hollow layer and supporting the top insulator; S5: depositing an insulator cladding layer on the surface of the wafer by a thin film preparation method; S6: opening a window at the edge of the hollow layer at a distance of several microns from the sidewall of the group III-V semiconductor nanoridge by photolithography combined with a dry etching process; S7: laterally homoepitaxially growing a group III-V semiconductor thin film in the hollow layer of the wafer by a group III-V semiconductor epitaxial growth device.

2. The method according to claim 1, wherein the method is characterized by, The V-shaped groove composed of two silicon {111} crystal faces at the bottom of the group III-V semiconductor nanoridge epitaxial region can inhibit the formation of reverse domain boundary defects in the group III-V semiconductor epitaxial growth.

3. The method of claim 1, wherein the method further comprises: The vertically selected area heteroepitaxially grown group III-V semiconductor nanoridge is a high-quality group III-V semiconductor crystal, the upper layer of which has a dislocation density lower than a preset value or no dislocation and no antiphase domain lattice defects, so that it can serve as a high-quality seed crystal for the laterally homoepitaxially grown group III-V semiconductor thin film.

4. The method of claim 1, wherein the method further comprises: In the three-layer structure of bottom insulator / intermediate layer / top insulator, the wet etching or soft dry etching selectivity between the intermediate layer material and the bottom / top insulator is greater than a preset threshold value, so as to hollow out the intermediate layer to obtain a structure with a hollow layer.

5. The method of claim 1, wherein the method further comprises: The thin film of the top insulator needs to be able to support the hollow layer without deformation.

6. The method of claim 1, wherein the method further comprises: The hollow layer provides space for the lateral epitaxial growth of the group III-V semiconductor thin film for the three-layer stacked structure.

7. The method of claim 1, wherein the method further comprises: The insulator cladding layer is used to isolate the group III-V semiconductor nanoridge from the chemical vapor deposition gas during the horizontal lateral epitaxial growth, preventing the gas from reacting and depositing at the nanoridge to grow crystals vertically again.

8. The method of claim 1, wherein the method further comprises: In step S7, the gas of the chemical vapor deposition method enters the hollow layer from the window, contacts the sidewall of the nanoridge, and laterally homoepitaxially grows a crystal thin film from the sidewall of the nanoridge.

9. The method of claim 1, wherein the method further comprises: The group III-V semiconductor epitaxial growth device used in steps S4 and S7 is a metal organic chemical vapor deposition device.

10. A silicon-based thin-film crystal preparation system based on silicon wafer hetero-epitaxy, characterized in that, The system adopts the silicon wafer heteroepitaxy-based thin film crystal preparation method of any one of claims 1-9.

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