Slope compensation circuit and control chip

Abstract

The present application discloses a slope compensation circuit and a control chip, which belongs to the field of integrated circuit technology. The slope compensation circuit includes: a slope voltage generating circuit, which is connected to a reference signal and converts the reference signal into a slope voltage signal according to a first conversion coefficient; a voltage-current conversion circuit is electrically connected to the slope voltage generating circuit, and converts the slope voltage signal into a slope current signal according to a second conversion coefficient; an output circuit is electrically connected to the voltage-current conversion circuit, and outputs the slope current signal according to a third conversion coefficient; a modulation circuit can adjustably set the parameters of the components connected to the connected circuit to set the conversion coefficient; a modulation control circuit is electrically connected to the modulation circuit, and responds to a ramp slow-down signal to control the conversion coefficient to gradually decrease. According to the control circuit of the present application, the slope current signal is slowly reduced by adjusting the parameters of the components connected to the circuit, so as to avoid the generation of audio noise due to the sudden change of the slope compensation amount.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and in particular, relates to a slope compensation circuit and a control chip. Background Art

[0002] For switching converters, conversion efficiency is an important performance indicator. Currently, most switching converters on the market achieve higher conversion efficiency by combining multiple working modes.

[0003] In the control technology of multi-mode switching converters, peak current mode control is usually used. However, when the duty cycle is large, the small disturbance current on the inductor will cause subharmonic oscillation of the inductor current, so slope compensation is required to correct the inductor current waveform, thereby improving the stability of the switching converter. For multi-mode switching converters, slope compensation is usually performed on the inductor current only in CCM (continuous conduction) mode, but if the slope compensation is suddenly cancelled when the CCM mode is switched to QR (quasi-resonant flyback) mode, it will cause large audio noise. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a slope compensation circuit and a control chip, which slowly reduces the slope current signal by adjusting the parameters of the components connected to the circuit to avoid audio noise caused by sudden changes in the slope compensation amount.

[0005] In a first aspect, the present application provides a slope compensation circuit, comprising:

[0006] A ramp voltage generating circuit is configured to receive a reference signal and convert the reference signal into a ramp voltage signal according to a first conversion coefficient;

[0007] A voltage-to-current conversion circuit is electrically connected to the output end of the ramp voltage generating circuit and is configured to convert the ramp voltage signal into a ramp current signal according to a second conversion coefficient;

[0008] an output circuit electrically connected to the output terminal of the voltage-to-current conversion circuit and configured to output the ramp current signal according to a third conversion coefficient;

[0009] A modulation circuit, electrically connected to the ramp voltage generating circuit, the voltage-current conversion circuit and / or the output circuit, and configured to adjustably set the parameters of the components connected to the connected circuit to set the conversion coefficient, wherein the component parameters include current value, capacitance value and / or resistance value;

[0010] The modulation control circuit is electrically connected to the modulation circuit and is configured to respond to the ramp slow-down signal and adjust the modulation circuit to control the set conversion coefficient to gradually decrease.

[0011] According to the slope compensation circuit of the present application, the modulation control circuit controls the modulation circuit to adjust the parameters of the components connected to the slope voltage generating circuit, the voltage-current conversion circuit and / or the output circuit, and gradually reduces the conversion coefficient corresponding to each circuit, which can slowly reduce the slope current signal and avoid audio noise caused by sudden changes in the slope compensation amount.

[0012] According to one embodiment of the present application, the modulation circuit includes:

[0013] A plurality of modulation elements, the modulation elements are electrically connected to the ramp voltage generating circuit, the voltage-current conversion circuit or the output circuit, and the number of the modulation elements connected is used to set the conversion coefficient;

[0014] A plurality of switches, each switch being electrically connected to a corresponding modulation element, and the switch being configured to control the modulation element to be connected to or disconnected from the connected circuit;

[0015] The modulation control circuit is configured to control each switch to be closed or opened, and the modulation element includes a resistor, a capacitor or a current mirror.

[0016] According to one embodiment of the present application, the ramp voltage generating circuit includes:

[0017] a first switch, wherein a first end of the first switch is used to access a reference signal, a second end of the first switch is electrically connected to a ground node, and a driving end of the first switch is used to access a first signal, and the first signal is used to drive the first switch to be turned on or off;

[0018] a first capacitor, wherein a first end of the first capacitor is electrically connected to a first end of the first switch circuit, and a second end of the first capacitor is electrically connected to a ground node;

[0019] The modulation element includes a modulation capacitor, the switch includes a transmission gate, the first end of each transmission gate is electrically connected to the first end of the first capacitor, the second end of each transmission gate is electrically connected to the first end of each modulation capacitor in a one-to-one correspondence, the second end of each modulation capacitor is electrically connected to the second end of the first capacitor, and the driving end of each transmission gate is electrically connected to the modulation control circuit.

[0020] According to one embodiment of the present application, a voltage-current conversion circuit includes:

[0021] A buffer, wherein a non-inverting input terminal of the buffer is electrically connected to a first terminal of a first capacitor;

[0022] a second switch, wherein a driving end of the second switch is electrically connected to an output end of the buffer;

[0023] A first resistor, a first end of the first resistor being electrically connected to the negative phase input end of the buffer and the first end of the second switch circuit respectively, and a second end of the first resistor being electrically connected to the ground node;

[0024] The modulation element includes modulation resistors, each modulation resistor is connected in series with the first resistor, the switch includes transmission gates, each transmission gate is connected in parallel with each modulation resistor in a one-to-one correspondence, and the driving end of each transmission gate is electrically connected to the modulation control circuit.

[0025] According to one embodiment of the present application, the output circuit includes:

[0026] a first current mirror, an input end of the first current mirror being electrically connected to the second end of the second switch, and an output end of the first current mirror being configured to provide a ramp current signal;

[0027] The modulation element includes a current replica mirror, each current replica mirror is connected in parallel with the first current mirror, the switch includes a transmission gate, the driving end of each transmission gate is electrically connected to the modulation control circuit, the first end of each transmission gate is connected to the output end of each current replica mirror in a one-to-one correspondence, the second end of the transmission gate is electrically connected to the output node, and the ramp current signal is output through the output node.

[0028] According to one embodiment of the present application, the output circuit includes:

[0029] an output resistor, a first end of the output resistor being electrically connected to an output end of the first current mirror;

[0030] The modulation circuit includes:

[0031] An adjustable resistance unit, the adjustable resistance unit is electrically connected to the second end of the output resistor, and the ramp current signal is output through the adjustable resistance unit;

[0032] Wherein, the modulation control circuit is configured to adjust the working resistance of the adjustable resistance unit.

[0033] According to one embodiment of the present application, the modulation control circuit includes:

[0034] A plurality of cascaded D flip-flops, wherein a clock input terminal of a first-stage D flip-flop is used to access a driving signal, a first data input terminal and a first output terminal of a previous-stage D flip-flop are both electrically connected to a second clock input terminal of a next-stage D flip-flop, and a reset terminal of each D flip-flop is used to access a second signal;

[0035] A decoder having an enable terminal, a plurality of input terminals and a plurality of output terminals, wherein the input terminals of the decoder are respectively connected to the output terminals of the D flip-flops one by one, the enable terminal of the decoder is electrically connected to the reset terminal of each D flip-flop, and the output terminals of the decoder are electrically connected to the modulation circuit to control the set conversion coefficient to gradually decrease;

[0036] The driving signal is used to drive the switching converter to operate, and the second signal is used to drive the decoder to operate when the switching converter operates in a quasi-resonant flyback mode.

[0037] According to one embodiment of the present application, the slope compensation circuit further includes:

[0038] A ramp control circuit is electrically connected to the ramp voltage generating circuit and is configured to receive the driving signal and enable the ramp voltage generating circuit when the duty cycle of the driving signal is greater than the target duty cycle;

[0039] The driving signal is used to drive the switching converter to operate.

[0040] According to one embodiment of the present application, the ramp control circuit includes:

[0041] A first NOT gate, wherein an input terminal of the first NOT gate is used to receive a driving signal;

[0042] A NOR gate, wherein a first input terminal of the NOR gate is electrically connected to an output terminal of the first NOR gate, and a second input terminal of the NOR gate is used to access a third signal, wherein a duty cycle of the third signal is greater than a first threshold value;

[0043] A second NOT gate, an input end of the second NOT gate is electrically connected to an output end of the NOR gate, an output end of the second NOT gate is electrically connected to a driving end of the first switch Q1, and the second NOT gate is configured to generate a first signal.

[0044] In the second aspect, the present application provides a control chip, which includes a control signal circuit and the aforementioned slope compensation circuit. The control signal circuit is electrically connected to the slope compensation circuit and the switching converter, respectively, and is configured to drive the switching converter and output a slope relief signal to the slope compensation circuit when the operating mode of the switching converter is switched from a continuous conduction mode to a quasi-resonant flyback mode.

[0045] According to the control chip of the present application, the slope compensation circuit modulation circuit gradually reduces the conversion coefficient corresponding to each circuit by adjusting the parameters of the components connected to the slope voltage generating circuit, the voltage-to-current conversion circuit and / or the output circuit, so as to slowly reduce the slope current signal and avoid the generation of audio noise due to the sudden change of the slope compensation amount when the working mode of the switching converter is switched from the continuous conduction mode to the quasi-resonant flyback mode.

[0046] According to one embodiment of the present application, the control signal circuit includes:

[0047] A comparator, wherein the positive input terminal of the comparator is used to access the current sampling signal and the ramp current signal respectively, and the negative input terminal of the comparator is used to access the current peak value;

[0048] A logic circuit, the logic circuit having a first input terminal and a second input terminal, the first input terminal of the logic circuit being electrically connected to the output terminal of the comparator;

[0049] A protection circuit, wherein the protection circuit has a first input terminal and a second input terminal, the first input terminal of the protection circuit is electrically connected to the negative phase input terminal of the comparator, and the output terminal of the protection circuit is electrically connected to the second input terminal of the logic circuit;

[0050] A valley bottom detection counting and control circuit, wherein an input end of the valley bottom detection counting and control circuit is electrically connected to a second input end of the protection circuit;

[0051] A continuous conduction mode fixed frequency circuit configured to generate a continuous conduction signal when the switching converter operates in a continuous conduction mode;

[0052] a switching frequency control circuit having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal of the switching frequency control circuit is electrically connected to the output terminal of the valley detection, counting and control circuit, the second input terminal of the switching frequency control circuit is electrically connected to the output terminal of the continuous conduction mode fixed frequency circuit, the first output terminal of the switching frequency control circuit is electrically connected to the enable terminal of the decoder, and the first output terminal of the switching frequency control circuit is configured to generate a second signal;

[0053] An RS trigger, wherein a set terminal of the RS trigger is electrically connected to the second output terminal of the switching frequency control circuit, a reset terminal of the RS trigger is electrically connected to the output terminal of the logic circuit, and an output terminal of the RS trigger is electrically connected to the switching converter;

[0054] The driving circuit has an input terminal electrically connected to an output terminal of the RS trigger, and an output terminal of the driving circuit electrically connected to the switch converter.

[0055] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0057] Figure 1 is a structural block diagram of a slope compensation circuit provided in an embodiment of the present application;

[0058] Figure 2 It is one of the structural schematic diagrams of the slope compensation circuit provided in the embodiment of the present application;

[0059] Figure 3 It is one of the structural schematic diagrams of the ramp control circuit provided in the embodiment of the present application;

[0060] Figure 4 It is one of the partial signal waveform diagrams in the slope compensation circuit provided in the embodiment of the present application;

[0061] Figure 5 It is one of the structural schematic diagrams of the modulation control circuit provided in the embodiment of the present application;

[0062] Figure 6 This is the second structural schematic diagram of the ramp control circuit provided in the embodiment of the present application;

[0063] Figure 7 This is the second of the partial signal waveform diagrams in the slope compensation circuit provided in the embodiment of the present application;

[0064] Figure 8 This is the third structural diagram of the ramp control circuit provided in the embodiment of the present application;

[0065] Fig. 9 is a schematic diagram of the structure of a modulation circuit provided in an embodiment of the present application;

[0066] Fig.10 This is the fourth structural diagram of the ramp control circuit provided in the embodiment of the present application;

[0067] Fig.11 It is a schematic diagram of the structure of the control signal circuit provided in the embodiment of the present application.

[0068] Reference numerals:

[0069] Slope compensation circuit 100, slope voltage generating circuit 110, voltage-current conversion circuit 120, output circuit 130, modulation circuit 140, modulation control circuit 150, current input circuit 200, control signal circuit 300, switching converter 400, logic circuit 500, protection circuit 600, valley detection counting and control circuit 700, continuous conduction mode fixed frequency circuit 800, switching frequency control circuit 900, drive circuit 910, buffer A1, comparator A2, first to second switches Q1-Q2, RS trigger S, first to second NOT gates U1-U2, NOR gate U3, first to third D triggers D1-D3, first to nth current replica mirrors P1-Pn, first to nth transmission gates TG1-TGn, decoder E, first capacitor C0, first resistor R0, first to nth modulation resistors R1-Rn, first to nth modulation capacitors C1-Cn, output resistor Rcs, adjustable resistor Rbst. DETAILED DESCRIPTION

[0070] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0071] In the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "coupled to" or "connected to" another element or an element / circuit is said to be "coupled to" or "connected to" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0072] In the description, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the numerical descriptors used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0073] In addition, descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0074] For switching converters, conversion efficiency is an important performance indicator. Currently, most switching converters on the market achieve higher conversion efficiency by combining multiple working modes.

[0075] In the control technology of multi-mode switching converters, peak current mode control is usually used. However, when the duty cycle is large, the small disturbance current on the inductor will cause subharmonic oscillation of the inductor current, so slope compensation is required to correct the inductor current waveform, thereby improving the stability of the switching converter. For multi-mode switching converters, slope compensation is usually performed on the inductor current only in CCM (continuous conduction) mode, but if the slope compensation is suddenly cancelled when the CCM mode is switched to QR (quasi-resonant flyback) mode, it will cause large audio noise.

[0076] The present application proposes a slope compensation circuit and a control chip, which slowly reduce the slope current signal by adjusting the parameters of components connected to the circuit, thereby avoiding audio noise caused by sudden changes in the slope compensation amount.

[0077] Reference Figure 1 One embodiment of the present application provides a slope compensation circuit, which includes: a slope voltage generating circuit 110, configured to receive a reference signal and convert the reference signal into a slope voltage signal according to a first conversion coefficient; a voltage-current conversion circuit 120, electrically connected to the output end of the slope voltage generating circuit 110, and configured to convert the slope voltage signal into a slope current signal according to a second conversion coefficient; an output circuit 130, electrically connected to the output end of the voltage-current conversion circuit 120, and configured to output the slope current signal according to a third conversion coefficient; a modulation circuit 140, electrically connected to the slope voltage generating circuit 110, the voltage-current conversion circuit 120 and / or the output circuit 130, and configured to adjustably set the parameters of the components connected to the connected circuits to set the conversion coefficient, the component parameters including current value, capacitance value and / or resistance value; a modulation control circuit 150, electrically connected to the modulation circuit 140, and configured to respond to the ramp slow-down signal and adjust the modulation circuit 140 to control the set conversion coefficient to gradually decrease.

[0078] The switching converter 400 includes at least one switch tube. The switching converter 400 mainly controls the flow of current based on the on and off of the switch tube, thereby realizing the conversion of electric energy. The switch tube allows current to pass during the on time, and prevents current from passing during the off time. By adjusting the on time and off time of the switch, i.e., the duty cycle, the output voltage can be controlled.

[0079] The switching converter 400 also includes an inductor and a capacitor. As an energy storage element, the inductor stores energy when the switch tube is turned on and releases energy when the switch tube is turned off, thereby smoothing the flow of current.

[0080] The slope compensation circuit provided in the embodiment of the present application is mainly used to generate a slope compensation signal, which can be a current signal or a voltage signal. When the duty cycle of the switch tube in the switching converter 400 is large, a small disturbance current on the inductor will cause subharmonic oscillation of the inductor current. At this time, superimposing the slope compensation signal can correct the inductor current waveform, thereby improving the stability of the switching converter 400.

[0081] In some embodiments, the slope compensation circuit is electrically connected to the control signal circuit, and when the operating mode of the switching converter is switched from the continuous conduction mode to the quasi-resonant flyback mode, the slope compensation circuit outputs a ramp slow-down signal to the slope compensation circuit.

[0082] The input end of the ramp voltage generating circuit 110 is used to access a reference signal, and the reference signal can be obtained by processing the current signal output by the current source, and the ramp voltage generating circuit 110 can convert the reference signal into a ramp voltage signal. The modulation circuit 140 is electrically connected to the ramp voltage generating circuit 110, and the modulation circuit 140 can adjustably set the capacitance value connected to the ramp voltage generating circuit 110. After receiving the ramp slow retreat signal, the modulation control circuit 150 adjusts the number of capacitors connected to the ramp voltage generating circuit 110 to gradually reduce the first conversion coefficient.

[0083] The voltage-current conversion circuit 120 is electrically connected to the output end of the ramp voltage generating circuit 110, and is mainly used to convert the ramp voltage signal into a ramp current signal. The modulation circuit 140 is electrically connected to the voltage-current conversion circuit 120, and the modulation circuit 140 can adjustably set the resistance value connected to the voltage-current conversion circuit 120. After receiving the ramp slow retreat signal, the modulation control circuit 150 adjusts the number of resistors connected to the voltage-current conversion circuit 120 to gradually reduce the second conversion coefficient.

[0084] The output circuit 130 is electrically connected to the output end of the voltage-current conversion circuit 120, and is mainly used to output the ramp current signal according to the third conversion coefficient. The modulation circuit 140 is electrically connected to the output circuit 130,

[0085] After receiving the ramp slow-down signal, the modulation control circuit 150 can adjust the current value, capacitance value and / or resistance value connected to the ramp voltage generating circuit 110, the voltage-current conversion circuit 120 and / or the output circuit 130 to reduce the first conversion coefficient, the second conversion coefficient or the third conversion coefficient of the corresponding circuit, and gradually reduce the output voltage or output current of the slope compensation signal, thereby slowly reducing the slope compensation amount and avoiding audio noise caused by sudden changes in the slope compensation amount.

[0086] According to the slope compensation circuit of the present application, the modulation control circuit 150 controls the modulation circuit 140 to adjust the parameters of the components connected to the slope voltage generating circuit 110, the voltage-current conversion circuit 120 and / or the output circuit 130, and gradually reduces the conversion coefficient corresponding to each circuit, which can slowly reduce the slope current signal and avoid audio noise caused by sudden changes in the slope compensation amount.

[0087] In some embodiments, the modulation circuit 140 includes: a plurality of modulation elements, the modulation elements are electrically connected to the ramp voltage generating circuit 110, the voltage-current conversion circuit 120 or the output circuit 130, and the number of connected modulation elements is used to set the conversion coefficient; a plurality of switches, each switch is electrically connected to each modulation element, and the switches are configured to control the modulation elements to connect or disconnect from the connected circuit; wherein the modulation control circuit 150 is configured to control each switch to be closed or opened, and the modulation elements include resistors, capacitors or current mirrors.

[0088] Each modulation element is connected to a corresponding switch. When the switch is turned on, the corresponding modulation element is connected to the circuit, and when the switch is turned off, the corresponding modulation element is out of the circuit. Therefore, by controlling each switch to close or open, the number of modulation elements connected to the circuit can be changed, thereby achieving a change in the conversion coefficient.

[0089] As an example, the modulation element connected to the voltage-current conversion circuit 120 is a resistor, and each switch is connected in parallel with the resistor. When the switch is closed, the resistor connected in parallel with it is short-circuited and out of the circuit. When the switch is opened, the resistor connected in parallel with it is connected to the circuit. By controlling the closing or opening of the switch, the resistance value of the connected circuit can be changed, thereby changing the size of the ramp current.

[0090] In some embodiments, the slope compensation circuit also includes: a slope control circuit, which is electrically connected to the slope voltage generating circuit 110 and is configured to receive a drive signal and enable the slope voltage generating circuit 110 when the duty cycle of the drive signal is greater than a target duty cycle; wherein the drive signal is used to drive the switching converter to operate.

[0091] When the duty cycle of the driving signal is greater than the target duty cycle, the on-time of the switch tube in the switching converter 400 is greater than the off-time, and the inductor current in the switching converter 400 increases continuously in each cycle, which may cause device damage.

[0092] The target duty cycle is usually 50%, but considering the actual circuit parameter changes and design margin, the specific value of the target duty cycle is not limited here, and can be selected according to the actual application scenario. For example, the target duty cycle can be 40%. The following is an example of a target duty cycle of 40%.

[0093] When the duty cycle of the driving signal of the ramp control circuit is greater than 40%, the ramp voltage generating circuit 110 is enabled to generate a ramp compensation voltage, which is converted into a ramp current signal after passing through the voltage-current conversion circuit 120 and the output circuit 130 to correct the inductor current waveform, thereby improving the stability of the switching converter 400.

[0094] Reference Figure 3 In some embodiments, the ramp control circuit includes: a first NOT gate U1, an input end of the first NOT gate U1 is used to access the drive signal; an NOR gate U3, a first input end of the NOR gate U3 is electrically connected to the output end of the first NOT gate U1, and a second input end of the NOR gate U3 is used to access a third signal, and a duty cycle of the third signal is greater than a first threshold; a second NOT gate U2, an input end of the second NOT gate U2 is electrically connected to the output end of the NOR gate U3, an output end of the second NOT gate U2 is electrically connected to the drive end of the first switch Q1, and the second NOT gate U2 is configured to generate a first signal.

[0095] Reference Figure 4 , Figure 4 The waveform diagram of the driving signal DRV, the first signal clk_slope and the third signal clk_st is shown. When the driving signal DRV is high and the third signal clk_st is low, the first signal clk_slope is low, and the first signal clk_slope can control the first switch Q1 to close and generate a slope voltage signal.

[0096] If the cycle of the driving signal DRV is Ts, the high level time of the driving signal DRV in one cycle is Ton, the high level time of the third signal clk_st in one cycle is Tduty=0.4Ts, then the low level time of the first signal clk_slope in one cycle is Toff_clk_slope=Ton-Tduty=Ton-0.4Ts.

[0097] Reference Figure 5 In some embodiments, the modulation control circuit 150 includes: a plurality of cascaded D flip-flops and a decoder E. The clock input terminal of the first-stage D flip-flop is used to access the drive signal DRV, the first data input terminal and the first output terminal of the previous-stage D flip-flop are both electrically connected to the second clock input terminal of the next-stage D flip-flop, and the reset terminal of each D flip-flop is used to access the second signal ccm_flag; the decoder E has an enable terminal, multiple input terminals and multiple output terminals, each input terminal of the decoder E is respectively connected to the output terminal of each D flip-flop in a one-to-one correspondence, the enable terminal of the decoder E is electrically connected to the reset terminal of each D flip-flop, and each output terminal of the decoder E is electrically connected to the modulation unit to control the modulation level of the modulation unit; the drive signal DRV is used to drive the switch converter to work, and the second signal ccm_flag is used to drive the decoder E to work when the switch converter works in the quasi-resonant flyback mode.

[0098] This article takes the modulation control circuit 150 including three cascaded D flip-flops and a 3-8 decoder E as an example for explanation.

[0099] The three cascaded D flip-flops are respectively a first D flip-flop D1, a second D flip-flop D2 and a third D flip-flop D3. The first data input terminal of the first D flip-flop D1 is electrically connected to the first output terminal, the second clock input terminal of the second D flip-flop D2 is electrically connected to the first output terminal, the second data input terminal of the second D flip-flop D2 is electrically connected to the second output terminal, the third clock input terminal of the third D flip-flop D3 is electrically connected to the second output terminal, and the third data input terminal of the third D flip-flop D3 is electrically connected to the third output terminal; the first input terminal of the 3-8 decoder E is electrically connected to the first output terminal, the second input terminal of the 3-8 decoder E is electrically connected to the second output terminal, and the third input terminal of the 3-8 decoder E is electrically connected to the third output terminal.

[0100] The reset terminals of the first D flip-flop D1 , the second D flip-flop D2 , and the third D flip-flop D3 and the enable terminal of the 3-8 decoder E are all connected to the second signal ccm_flag.

[0101] It should be noted that the reset ends of the first D flip-flop D1, the second D flip-flop D2 and the third D flip-flop D3 and the enable end of the 3-8 decoder E can be electrically connected to the first inverter, the input end of the first inverter is connected to the second signal ccm_flag, and the output end of the first inverter is electrically connected to the reset ends of the first D flip-flop D1, the second D flip-flop D2 and the third D flip-flop D3 and the enable end of the 3-8 decoder E respectively.

[0102] When the operation mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode, the second signal ccm_flag is a low-level signal, which is converted into a high-level signal after passing through the first inverter to drive the decoder E to operate.

[0103] The clock input of the first-stage D flip-flop is used to access the drive signal DRV. The first D flip-flop D1, the second D flip-flop D2 and the third D flip-flop D3 are cascaded to achieve eight-frequency division, that is, the frequency of the signal q1 output from the first output of the first D flip-flop D1 is 1 / 2 of the frequency of the drive signal DRV, the frequency of the signal q2 output from the second output of the second D flip-flop D2 is 1 / 2 of the frequency of q1, and the frequency of the signal q3 output from the third output of the third D flip-flop D3 is 1 / 2 of the frequency of q2, so that when the working mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode, the signal at the input of the 3-8 decoder E is encoded and outputted as 1, 2, 3...8 at a time.

[0104] It should be noted that the number of cascaded D flip-flops in the control circuit and the type of decoder E are not specifically limited here and can be selected according to the actual application scenario. For example, 4 D flip-flops can be cascaded and a 4-16 decoder E can be used.

[0105] Reference Figure 6In some embodiments, the ramp voltage generating circuit 110 includes: a first switch Q1, a first end of the first switch Q1 is used to access a reference signal, a second end of the first switch is electrically connected to a ground node, a driving end of the first switch Q1 is used to access a first signal, and the first signal is used to drive the first switch to be turned on or off; a first capacitor, a first end of the first capacitor is electrically connected to a first end of the first switch Q1, and a second end of the first capacitor is electrically connected to the ground node; the modulation element includes a modulation capacitor, the switch includes a transmission gate, a first end of each transmission gate is electrically connected to a first end of the first capacitor, a second end of each transmission gate is electrically connected to a first end of each modulation capacitor in a one-to-one correspondence, a second end of each modulation capacitor is electrically connected to a second end of the first capacitor, and a driving end of each transmission gate is electrically connected to a modulation control circuit 150.

[0106] The first switch Q1 can be switched between two working modes: on and off. When the first signal clk_slope drives the first switch Q1 to turn on, the reference signal Ichr charges the first capacitor C0, and the voltage at the first end of the first capacitor C0 gradually rises, thereby generating a slope voltage signal Vslope.

[0107] In some embodiments, the ramp voltage generating circuit 110 is electrically connected to the current input circuit 200, and the current input circuit 200 is mainly used to generate a reference signal. The current input circuit 200 may include a second current mirror. The input end of the second current mirror is electrically connected to the current source, the output end of the second current mirror is electrically connected to the first end of the first switch Q1, and the output end of the second current mirror is configured to output the reference signal.

[0108] As an example, the current provided by the current source is Ib, and the current mirror ratio of the second current mirror is 1:K1, that is, the reference signal Ichr=K1Ib.

[0109] It can be seen from the above embodiments that the expression of the ramp voltage signal is:

[0110]

[0111] Wherein, C0 is the capacitance of the first capacitor C0.

[0112] The first switch Q1 may be an NMOS tube. When the first signal clk_slope is a low level signal, the first switch Q1 is turned on, and the reference signal Ichr charges the first capacitor C0.

[0113] In some embodiments, the modulation unit includes: a plurality of modulation capacitors and a plurality of transmission gates connected in parallel. Each modulation capacitor is connected in parallel with the first capacitor C0; the first end of each transmission gate is electrically connected to the first end of the first capacitor C0, the second end of each transmission gate is electrically connected to the first end of each modulation capacitor in a one-to-one correspondence, and the driving end of each transmission gate is electrically connected to the modulation control circuit 150.

[0114] This article takes the modulation element including 6 modulation capacitors and the switch including 6 transmission gates as an example for explanation. The modulation capacitors are respectively the first modulation capacitor C1, the second modulation capacitor C2, the third modulation capacitor C3, the fourth modulation capacitor C4, the fifth modulation capacitor C5 and the sixth modulation capacitor C6; the transmission gates are respectively the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6.

[0115] It should be noted that the number of modulation capacitors and transmission gates in the control circuit is not specifically limited here and can be selected according to the actual application scenario. For example, the number of modulation capacitors and transmission gates can also be 8, 10, etc.

[0116] The first modulation capacitor C1, the second modulation capacitor C2, the third modulation capacitor C3, the fourth modulation capacitor C4, the fifth modulation capacitor and the sixth modulation capacitor C6 are all connected in parallel with the first capacitor C0. The first ends of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6 are all electrically connected to the first end of the first capacitor C0. The second end of the first transmission gate TG1 is electrically connected to the first end of the first modulation capacitor C1, the first driving end of the first transmission gate TG1 is electrically connected to the first output end of the 3-8 decoder E, and the second driving end of the first transmission gate TG1 is connected to the inversion signal of the output signal of the first output end of the 3-8 decoder E; the second end of the second transmission gate TG2 is electrically connected to the first end of the second modulation capacitor C2, the first driving end of the second transmission gate TG2 is electrically connected to the second output end of the 3-8 decoder E, and the second driving end of the second transmission gate TG2 is connected to the inversion signal of the output signal of the second output end of the 3-8 decoder E; the second end of the third transmission gate TG3 is electrically connected to the first end of the third modulation capacitor C3, the first driving end of the third transmission gate TG3 is electrically connected to the third output end of the 3-8 decoder E, and the second driving end of the third transmission gate TG3 is connected to the inversion signal of the output signal of the third output end of the 3-8 decoder E ; The second end of the fourth transmission gate TG4 is electrically connected to the first end of the fourth modulation capacitor C4, the first driving end of the fourth transmission gate TG4 is electrically connected to the fourth output end of the 3-8 decoder E, and the second driving end of the fourth transmission gate TG4 is connected to the inversion signal of the output signal of the fourth output end of the 3-8 decoder E; the second end of the fifth transmission gate TG5 is electrically connected to the first end of the fifth modulation capacitor, the first driving end of the fifth transmission gate TG5 is electrically connected to the fifth output end of the 3-8 decoder E, and the second driving end of the fifth transmission gate TG5 is connected to the inversion signal of the output signal of the fifth output end of the 3-8 decoder E; the second end of the sixth transmission gate TG6 is electrically connected to the first end of the sixth modulation capacitor C6, the first driving end of the sixth transmission gate TG6 is electrically connected to the sixth output end of the 3-8 decoder E, and the second driving end of the sixth transmission gate TG6 is connected to the inversion signal of the output signal of the sixth output end of the 3-8 decoder E. The second ends of the first modulation capacitor C1 , the second modulation capacitor C2 , the third modulation capacitor C3 , the fourth modulation capacitor C4 , the fifth modulation capacitor and the sixth modulation capacitor C6 are all electrically connected to the second end of the first capacitor C0 .

[0117] In some embodiments, the first modulation capacitor C1 has a capacitance of C1, the second modulation capacitor C2 has a capacitance of C2, the third modulation capacitor C3 has a capacitance of C3, the fourth modulation capacitor C4 has a capacitance of C4, the fifth modulation capacitor has a capacitance of C5, and the sixth modulation capacitor C6 has a capacitance of C6, C1 = C2 = C3 = C4 = C5 = C6 = K5*C0. The value of K5 can be selected according to the actual application scenario, for example, K5 can be 2.

[0118] When the switching converter 400 operates in the continuous conduction mode, the 3-8 decoder E does not work, the signals Y1 to Y6 at its output terminals are all low level, the negated signals at each output terminal are high level, and each transmission gate is in the disconnected state. At this time, each modulation capacitor is open circuit, and the expression of the ramp voltage signal is:

[0119]

[0120] When the working mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode, the signals Y1 to Y6 outputted from the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal and the sixth output terminal of the 3-8 decoder E are sequentially changed to high level, and the corresponding negation signals are sequentially changed to low level, and each transmission gate is sequentially turned on, and the modulation capacitor connected in series with the turned-on transmission gate is connected to the modulation unit until the ramp voltage signal finally outputted is:

[0121]

[0122] The waveforms of the signals changing during the process of the modulation control circuit 150 adjusting the first conversion coefficient of the modulation circuit 140 are further referred to. Figure 7 Therefore, the slope compensation signal can be gradually reduced when the operating mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode.

[0123] Reference Figure 8 In some embodiments, the voltage-current conversion circuit 120 includes: a buffer A1, a second switch Q2 and a first resistor R0, the positive phase input terminal of the buffer is electrically connected to the first end of the first capacitor; the driving end of the second switch Q2 is electrically connected to the output end of the buffer; the first end of the first resistor is electrically connected to the negative phase input terminal of the buffer and the first end of the second switch Q2 respectively, and the second end of the first resistor is electrically connected to the ground node; the modulation element includes modulation resistors, each modulation resistor is connected in series with the first resistor, the switch includes transmission gates, each transmission gate is connected in parallel with each modulation resistor in a one-to-one correspondence, and the driving end of each transmission gate is electrically connected to the modulation control circuit 150.

[0124] The positive input terminal of the buffer A1 is connected to the slope voltage signal Vslope, and the output terminal of the buffer A1 is electrically connected to the driving terminal of the second switch Q2. The buffer A1 can convert the slope voltage signal Vslope into an initial slope current signal Islope0 by controlling the voltage of the driving terminal of the second switch Q2.

[0125] The type of the second switch Q2 can be selected according to the actual application scenario, and is not limited here. For example, the second switch Q2 can be an NMOS tube.

[0126] This article takes the modulation unit including 6 modulation resistors and 6 transmission gates as an example for explanation. The modulation resistors are respectively the first modulation resistor R1, the second modulation resistor R2, the third modulation resistor R3, the fourth modulation resistor R4, the fifth modulation resistor R5 and the sixth modulation resistor R6; the transmission gates are respectively the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6.

[0127] It should be noted that the number of modulation resistors and transmission gates in the control circuit is not specifically limited here and can be selected according to the actual application scenario. For example, the number of modulation resistors and transmission gates can also be 8, 10, etc.

[0128] The first modulation resistor R1, the second modulation resistor R2, the third modulation resistor R3, the fourth modulation resistor R4, the fifth modulation resistor R5 and the sixth modulation resistor R6 are connected in series with the first resistor R0. The first transmission gate TG1 is connected in parallel with the first modulation resistor R1, the first driving end of the first transmission gate TG1 is electrically connected to the first output end of the 3-8 decoder E, and the second driving end of the first transmission gate TG1 is connected to the inverted signal of the output signal of the first output end of the 3-8 decoder E; the second transmission gate TG2 is connected in parallel with the second modulation resistor R2, the first driving end of the second transmission gate TG2 is electrically connected to the second output end of the 3-8 decoder E, and the second driving end of the second transmission gate TG2 is connected to the inverted signal of the output signal of the second output end of the 3-8 decoder E; the third transmission gate TG3 is connected in parallel with the third modulation resistor R3, the first driving end of the third transmission gate TG3 is electrically connected to the third output end of the 3-8 decoder E, and the second driving end of the third transmission gate TG3 is connected to the inverted signal of the output signal of the third output end of the 3-8 decoder E; The fourth transmission gate TG4 is connected in parallel with the fourth modulation resistor R4R3, the first driving end of the fourth transmission gate TG4 is electrically connected to the fourth output end of the 3-8 decoder E, and the second driving end of the fourth transmission gate TG4 is connected to the inversion signal of the output signal of the fourth output end of the 3-8 decoder E; the fifth transmission gate TG5 is connected in parallel with the fifth modulation resistor R5, the first driving end of the fifth transmission gate TG5 is electrically connected to the fifth output end of the 3-8 decoder E, and the second driving end of the fifth transmission gate TG5 is connected to the inversion signal of the output signal of the fifth output end of the 3-8 decoder E; the sixth transmission gate TG6 is connected in parallel with the sixth modulation resistor R6, the first driving end of the sixth transmission gate TG6 is electrically connected to the sixth output end of the 3-8 decoder E, and the second driving end of the sixth transmission gate TG6 is connected to the inversion signal of the output signal of the sixth output end of the 3-8 decoder E.

[0129] In some embodiments, the first modulation resistor R1 has a resistance of R1, the second modulation resistor R2 has a resistance of R2, the third modulation resistor R3 has a resistance of R3, the fourth modulation resistor R4 has a resistance of R4, the fifth modulation resistor R5 has a resistance of R5, and the sixth modulation resistor R6 has a resistance of R6, R1 = R2 = R3 = R4 = R5 = R6 = K4*R0. The value of K4 can be selected according to the actual application scenario, for example, K4 can be 2.

[0130] When the switching converter 400 operates in the continuous conduction mode, the 3-8 decoder E does not work, the signals Y1 to Y6 at its output terminals are all low level, the negated signals at each output terminal are high level, and each transmission gate is in the on state. At this time, each modulation resistor is short-circuited, and the ramp current signal finally output by the ramp signal generating circuit is expressed as:

[0131]

[0132] When the working mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode, the signals Y1 to Y6 outputted from the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal and the sixth output terminal of the 3-8 decoder E are successively changed to high level, and the corresponding negation signals are successively changed to low level, and each transmission gate is successively turned off, and the modulation resistor connected in parallel with the turned-off transmission gate is connected to the modulation unit until the ramp current signal finally outputted is:

[0133]

[0134] The waveforms of the signals changing during the process of the modulation control circuit 150 adjusting the second conversion coefficient of the modulation circuit 140 are further referred to. Figure 7 Therefore, the slope compensation signal can be gradually reduced when the operating mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode.

[0135] Reference Fig. 9 In some embodiments, the output circuit 130 includes a first current mirror, an input end of the first current mirror is electrically connected to the second end of the second switch Q2, and an output end of the first current mirror is configured to provide a ramp current signal; the modulation element includes a current replica mirror, each current replica mirror is connected in parallel with the first current mirror, the switch includes a transmission gate, a driving end of each transmission gate is electrically connected to the modulation control circuit 150, a first end of each transmission gate is connected to an output end of each current replica mirror in a one-to-one correspondence, and a second end of the transmission gate is electrically connected to an output node, and the ramp current signal is output through the output node.

[0136] The input end of the first current mirror is electrically connected to the second end of the second switch Q2, that is, the current input to the input end of the first current mirror is the ramp current signal Islope0. If the current mirror ratio of the first current mirror is K2:1, the expression of the current at the output end of the first current mirror is:

[0137]

[0138] This article takes the modulation unit including 6 current replica mirrors and 6 transmission gates, and the current mirror ratio of each current replica mirror to the first current mirror is 1:K3 as an example for explanation. The current replica mirrors are respectively the first current replica mirror P1, the second current replica mirror P2, the third current replica mirror P3, the fourth current replica mirror P4, the fifth current replica mirror P5 and the sixth current replica mirror P6; the transmission gates are respectively the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6.

[0139] The first end of the first transmission gate TG1 is electrically connected to the output end of the first current copy mirror P1, the first driving end of the first transmission gate TG1 is electrically connected to the first output end of the 3-8 decoder E, and the second driving end of the first transmission gate TG1 is connected to the inversion signal of the output signal of the first output end of the 3-8 decoder E; the first end of the second transmission gate TG2 is electrically connected to the output end of the second current copy mirror P2, the first driving end of the second transmission gate TG2 is electrically connected to the second output end of the 3-8 decoder E, and the second driving end of the second transmission gate TG2 is connected to the inversion signal of the output signal of the second output end of the 3-8 decoder E; the first end of the third transmission gate TG3 is electrically connected to the output end of the third current copy mirror P3, the first driving end of the third transmission gate TG3 is electrically connected to the third output end of the 3-8 decoder E, and the second driving end of the third transmission gate TG3 is connected to the inversion signal of the output signal of the third output end of the 3-8 decoder E; The first end of the fourth transmission gate TG4 is electrically connected to the output end of the fourth current copy mirror P4, the first driving end of the fourth transmission gate TG4 is electrically connected to the fourth output end of the 3-8 decoder E, and the second driving end of the fourth transmission gate TG4 is connected to the inversion signal of the output signal of the fourth output end of the 3-8 decoder E; the first end of the fifth transmission gate TG5 is electrically connected to the output end of the fifth current copy mirror P5, the first driving end of the fifth transmission gate TG5 is electrically connected to the fifth output end of the 3-8 decoder E, and the second driving end of the fifth transmission gate TG5 is connected to the inversion signal of the output signal of the fifth output end of the 3-8 decoder E; the first end of the sixth transmission gate TG6 is electrically connected to the output end of the sixth current copy mirror P6, the first driving end of the sixth transmission gate TG6 is electrically connected to the sixth output end of the 3-8 decoder E, and the second driving end of the sixth transmission gate TG6 is connected to the inversion signal of the output signal of the sixth output end of the 3-8 decoder E.

[0140] The current outputted from the second end of the first transmission gate TG1 is Islope2, the current outputted from the second end of the second transmission gate TG2 is Islope3, the current outputted from the second end of the third transmission gate TG3 is Islope4, the current outputted from the second end of the fourth transmission gate TG4 is Islope5, the current outputted from the second end of the fifth transmission gate TG5 is Islope6, and the current outputted from the second end of the sixth transmission gate TG6 is Islope7. Then, the current Islope2 outputted from the second end of each transmission gate is Islope3=Islope4=Islope5=Islope6=Islope7=K3Islope1.

[0141] When the switching converter 400 operates in the continuous conduction mode, the 3-8 decoder E does not work, the signals Y1 to Y6 at its output terminals are all low level, the negated signals at each output terminal are high level, and each transmission gate is in the on state. At this time, the ramp current signal finally output by the ramp signal generating circuit is expressed as:

[0142]

[0143] When the working mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode, the signals Y1 to Y6 outputted from the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal and the sixth output terminal of the 3-8 decoder E are successively changed to high level, and the corresponding negation signals are successively changed to low level, and each transmission gate is successively turned off, and the branch where the turned-off transmission gate is located no longer outputs current, until the ramp current signal finally outputted is:

[0144]

[0145] Reference Figure 7 , Figure 7 The waveforms of the signals changing during the modulation control circuit 150 adjusting the third conversion coefficient of the modulation circuit 140 are shown, so that the slope compensation signal can be gradually reduced when the working mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode.

[0146] It should be noted that the number of current replica mirrors and transmission gates in the control circuit is not specifically limited here and can be selected according to the actual application scenario. For example, the number of current replica mirrors and transmission gates can also be 8, 10, etc.

[0147] It can be seen from the above expression that the magnitude of the ramp current is positively correlated with the duty cycle of the driving signal DRV of the switching converter 400 , which can effectively solve the system over-compensation problem and ensure the transient response capability and loop stability of the system.

[0148] Reference Fig.10In some embodiments, the output circuit 130 includes an output resistor Rcs, a first end of the output resistor Rcs is electrically connected to the output end of the first current mirror; the modulation circuit 140 includes: an adjustable resistance unit Rbst, the adjustable resistance unit Rbst is electrically connected to the second end of the output resistor Rcs, and the ramp current signal is output through the adjustable resistance unit Rbst; wherein the modulation control circuit 150 is configured to adjust the working resistance of the adjustable resistance unit Rbst.

[0149] The first end of the adjustable resistance unit Rbst is electrically connected to the second end of the output resistor Rcs, the second end of the adjustable resistance unit Rbst outputs a ramp current signal, the adjustment end of the adjustable resistance unit Rbst is electrically connected to the output end of the 3-8 decoder E, and the maximum operating resistance value of the adjustable resistance unit Rbst is Rbst.

[0150] The slope current expression connected to the output circuit 130 is:

[0151]

[0152] When the switching converter 400 operates in the continuous conduction mode, the adjustable resistor Rbst is fully connected to the slope compensation signal generating circuit. At this time, the slope compensation signal generating circuit outputs a voltage:

[0153]

[0154] When the working mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode, the signals Y1 to Y6 outputted from the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal and the sixth output terminal of the 3-8 decoder E are successively changed to high level, and the corresponding negation signals are successively changed to low level, and the resistance value of the adjustable resistor Rbst connected to the modulation unit is gradually reduced until it is completely short-circuited, and the ramp current signal finally outputted is:

[0155]

[0156] The waveforms of the signals changing during the process of the modulation control circuit 150 adjusting the fourth conversion coefficient of the modulation circuit 140 are further referred to. Figure 7 Therefore, the slope compensation signal can be gradually reduced when the operating mode of the switching converter 400 is switched from the continuous conduction mode to the quasi-resonant flyback mode.

[0157] One embodiment of the present application proposes a control chip, which includes a control signal circuit and the aforementioned slope compensation circuit. The control signal circuit is electrically connected to the slope compensation circuit and the switching converter, respectively, and is configured to drive the switching converter and output a slope relief signal to the slope compensation circuit when the operating mode of the switching converter is switched from a continuous conduction mode to a quasi-resonant flyback mode.

[0158] The control signal circuit is mainly used to apply a driving signal to the switching converter to drive the switching converter to turn on or off. When the working mode of the switching converter is switched from the continuous conduction mode to the quasi-resonant flyback mode, the control signal circuit outputs a ramp-down signal to the slope compensation circuit, that is, the aforementioned low-level ccm_flag, and the modulation control circuit 150 responds to the ramp-down signal and adjusts the modulation circuit 140 to control the set conversion coefficient to gradually decrease.

[0159] According to the control chip of the present application, the modulation circuit 140 is adjusted to control the modulation circuit 140 by adjusting the parameters of the components connected to the ramp voltage generating circuit 110, the voltage-current conversion circuit 120 and / or the output circuit 130, and gradually reducing the conversion coefficient corresponding to each circuit, so as to slowly reduce the ramp current signal and avoid the audio noise generated by the sudden change of the slope compensation amount when the working mode of the switching converter is switched from the continuous conduction mode to the quasi-resonant flyback mode.

[0160] Reference Fig.11In some embodiments, the control signal circuit 300 includes: a comparator A2, a logic circuit 500, a protection circuit 600, a valley detection counting and control circuit 700, a continuous conduction mode fixed frequency circuit 800, a switching frequency control circuit 900, an RS trigger S and a driving circuit 910. The positive input terminal of the comparator A2 is used to access the current sampling signal and the slope compensation signal respectively, and the negative input terminal of the comparator A2 is used to access the current peak value; the logic circuit 500 has a first input terminal and a second input terminal, and the first input terminal of the logic circuit 500 is electrically connected to the output terminal of the comparator A2; the protection circuit 600 has a first input terminal and a second input terminal, and the first input terminal of the protection circuit 600 is electrically connected to the negative input terminal of the comparator A2, and the output terminal of the protection circuit 600 is electrically connected to the second input terminal of the logic circuit 500; the input terminal of the valley detection counting and control circuit 700 is electrically connected to the second input terminal of the protection circuit 600; the continuous conduction mode fixed frequency circuit 800 is configured to generate a continuous conduction signal when the switching converter 400 operates in the continuous conduction mode; the switching frequency control circuit 900 has a first input terminal and a second input terminal. an input terminal, a second input terminal, a first output terminal and a second output terminal, the first input terminal of the switching frequency control circuit 900 is electrically connected to the output terminal of the valley detection, counting and control circuit, the second input terminal of the switching frequency control circuit 900 is electrically connected to the output terminal of the continuous conduction mode fixed frequency circuit 800, the first output terminal of the switching frequency control circuit 900 is electrically connected to the enable terminal of the decoder E, and the first output terminal of the switching frequency control circuit 900 is configured to generate a second signal ccm_flag; the set terminal of the RS trigger S is electrically connected to the second output terminal of the switching frequency control circuit 900, the reset terminal of the RS trigger S is electrically connected to the output terminal of the logic circuit 500, the output terminal of the RS trigger S is electrically connected to the input terminal of the drive circuit 910, and the output terminal of the drive circuit 910 is electrically connected to the switching converter 400.

[0161] Comparator A2 may be a PWM comparator A2. The non-inverting input terminal of comparator A2 is connected to the voltage sampling signal of the peak current after slope compensation. Comparator A2 compares the voltage sampling signal of the peak current after slope compensation with the load feedback voltage. When the positive input terminal of the PWM comparator is greater than the negative input terminal, DRV is controlled to be turned off. After the protection signal of the protection circuit and the signal output by comparator A2 are logically operated by the logic circuit 500, the logic circuit 500 transmits the signal driving the switch converter 400 to be turned off to the reset terminal of the RS trigger S.

[0162] The valley detection counting and control circuit 700 is used to generate a signal for driving the switching converter 400 to turn on when the switching converter 400 operates in the quasi-resonant flyback mode.

[0163] The continuous conduction mode fixed frequency circuit 800 is used to generate a signal for driving the switching converter 400 to conduct when the switching converter 400 operates in the continuous conduction mode. The switching frequency control circuit 900 transmits the signal for driving the switching converter 400 to conduct to the set terminal of the RS flip-flop S.

[0164] The RS trigger S transmits a signal to drive the switch converter 400 to turn on or off to the drive signal DRV according to the output signal. The drive circuit 910 is used to strengthen the drive signal DRV to accurately control the switch converter 400 to turn on or off.

[0165] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A slope compensation circuit, characterized in that: include: A ramp voltage generating circuit is configured to receive a reference signal and convert the reference signal into a ramp voltage signal according to a first conversion coefficient; a voltage-to-current conversion circuit, electrically connected to the output end of the ramp voltage generating circuit and configured to convert the ramp voltage signal into a ramp current signal according to a second conversion coefficient; an output circuit, electrically connected to an output terminal of the voltage-current conversion circuit and configured to output the ramp current signal according to a third conversion coefficient; a modulation circuit, electrically connected to the ramp voltage generating circuit, the voltage-current conversion circuit and / or the output circuit, and configured to adjustably set parameters of components connected to the connected circuits to set conversion coefficients, wherein the component parameters include current values, capacitance values ​​and / or resistance values; The modulation control circuit is electrically connected to the modulation circuit and is configured to respond to the ramp slow-down signal, adjust the modulation circuit to control the set conversion coefficient to gradually decrease, and gradually reduce the output voltage or output current of the slope compensation signal, thereby slowly reducing the slope compensation amount.

2. The slope compensation circuit according to claim 1, characterized in that: The modulation circuit comprises: A plurality of modulation elements, wherein the modulation elements are electrically connected to the ramp voltage generating circuit, the voltage-current conversion circuit or the output circuit, and the number of the modulation elements connected is used to set the conversion coefficient; A plurality of switches, each of the switches being electrically connected to a corresponding modulation element, and each of the switches being configured to control the modulation element to be connected to or disconnected from a connected circuit; The modulation control circuit is configured to control each of the switches to be closed or opened, and the modulation element includes a resistor, a capacitor or a current mirror.

3. The slope compensation circuit according to claim 2, characterized in that: The ramp voltage generating circuit comprises: a first switch, wherein a first end of the first switch is used to access the reference signal, a second end of the first switch is electrically connected to a ground node, and a driving end of the first switch is used to access a first signal, and the first signal is used to drive the first switch to be turned on or off; a first capacitor, wherein a first end of the first capacitor is electrically connected to a first end of the first switch, and a second end of the first capacitor is electrically connected to the ground node; The modulation element includes a modulation capacitor, and the switch includes a transmission gate. The first end of each of the transmission gates is electrically connected to the first end of the first capacitor, the second end of each of the transmission gates is electrically connected to the first end of each of the modulation capacitors in a one-to-one correspondence, the second end of each of the modulation capacitors is electrically connected to the second end of the first capacitor, and the driving end of each of the transmission gates is electrically connected to the modulation control circuit.

4. The slope compensation circuit according to claim 3, characterized in that: The voltage-current conversion circuit comprises: a buffer, wherein a non-inverting input terminal of the buffer is electrically connected to a first end of the first capacitor; a second switch, wherein a driving end of the second switch is electrically connected to an output end of the buffer; a first resistor, wherein a first end of the first resistor is electrically connected to a negative phase input end of the buffer and a first end of the second switch circuit respectively, and a second end of the first resistor is electrically connected to a ground node; The modulation element includes a modulation resistor, each of which is connected in series with the first resistor. The switch includes a transmission gate, each of which is connected in parallel with each of the modulation resistors in a one-to-one correspondence. The driving end of each of the transmission gates is electrically connected to the modulation control circuit.

5. The slope compensation circuit according to claim 4, characterized in that: The output circuit comprises: a first current mirror, wherein an input terminal of the first current mirror is electrically connected to the second terminal of the second switch, and an output terminal of the first current mirror is configured to provide the ramp current signal; The modulation element includes a current replica mirror, each of which is connected in parallel with the first current mirror. The switch includes a transmission gate, a driving end of each transmission gate is electrically connected to the modulation control circuit, a first end of each transmission gate is connected to an output end of each current replica mirror in a one-to-one correspondence, and a second end of each transmission gate is electrically connected to an output node. The ramp current signal is output via the output node.

6. The slope compensation circuit according to claim 5, characterized in that: The output circuit comprises: an output resistor, a first end of the output resistor being electrically connected to an output end of the first current mirror; The modulation circuit comprises: An adjustable resistance unit, the adjustable resistance unit is electrically connected to the second end of the output resistor, and the ramp current signal is output via the adjustable resistance unit; Wherein, the modulation control circuit is configured to adjust the working resistance of the adjustable resistance unit.

7. The slope compensation circuit according to any one of claims 1 to 6, characterized in that: The modulation control circuit comprises: A plurality of cascaded D flip-flops, wherein the clock input terminal of the first stage D flip-flop is used to access the driving signal, the first data input terminal and the first output terminal of the previous stage D flip-flop are electrically connected to the second clock input terminal of the next stage D flip-flop, and the reset terminal of each of the D flip-flops is used to access the second signal; A decoder having an enable terminal, a plurality of input terminals and a plurality of output terminals, wherein the input terminals of the decoder are respectively connected to the output terminals of the D flip-flops one by one, the enable terminal of the decoder is electrically connected to the reset terminal of each D flip-flop, and the output terminals of the decoder are electrically connected to the modulation circuit to control the set conversion coefficient to gradually decrease; The driving signal is used to drive the switching converter to operate, and the second signal is used to drive the decoder to operate when the switching converter operates in a quasi-resonant flyback mode.

8. The slope compensation circuit according to any one of claims 1 to 6, characterized in that: The slope compensation circuit also includes: a ramp control circuit electrically connected to the ramp voltage generating circuit and configured to receive a driving signal and enable the ramp voltage generating circuit when a duty cycle of the driving signal is greater than a target duty cycle; The driving signal is used to drive the switching converter to operate.

9. The slope compensation circuit according to claim 8, characterized in that: The ramp control circuit comprises: A first NOT gate, wherein an input end of the first NOT gate is used to receive a driving signal; A NOR gate, wherein a first input terminal of the NOR gate is electrically connected to an output terminal of the first NOR gate, and a second input terminal of the NOR gate is used to access a third signal, wherein a duty cycle of the third signal is greater than a first threshold; A second NOT gate, wherein the input end of the second NOT gate is electrically connected to the output end of the NOR gate, the output end of the second NOT gate is electrically connected to the driving end of the first switch, and the second NOT gate is configured to generate a first signal.

10. A control chip, characterized in that: It comprises a control signal circuit and a slope compensation circuit according to any one of claims 1 to 9, wherein the control signal circuit is electrically connected to the slope compensation circuit and the switching converter, respectively, and is configured to drive the switching converter, and output a slope relief signal to the slope compensation circuit when the operating mode of the switching converter is switched from a continuous conduction mode to a quasi-resonant flyback mode.

11. The control chip according to claim 10, characterized in that: The control signal circuit comprises: A comparator, wherein the positive input terminal of the comparator is used to access the current sampling signal and the ramp current signal respectively, and the negative input terminal of the comparator is used to access the current peak value; a logic circuit, the logic circuit having a first input terminal and a second input terminal, the first input terminal of the logic circuit being electrically connected to the output terminal of the comparator; A protection circuit, wherein the protection circuit has a first input terminal and a second input terminal, the first input terminal of the protection circuit is electrically connected to the negative phase input terminal of the comparator, and the output terminal of the protection circuit is electrically connected to the second input terminal of the logic circuit; A valley detection counting and control circuit, wherein an input end of the valley detection counting and control circuit is electrically connected to a second input end of the protection circuit; A continuous conduction mode fixed frequency circuit, configured to generate a continuous conduction signal when the switching converter operates in a continuous conduction mode; a switching frequency control circuit, having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal of the switching frequency control circuit is electrically connected to the output terminal of the valley detection, counting and control circuit, the second input terminal of the switching frequency control circuit is electrically connected to the output terminal of the continuous conduction mode fixed frequency circuit, the first output terminal of the switching frequency control circuit is electrically connected to the enable terminal of the decoder, and the first output terminal of the switching frequency control circuit is configured to generate a second signal; An RS trigger, wherein a set terminal of the RS trigger is electrically connected to the second output terminal of the switching frequency control circuit, a reset terminal of the RS trigger is electrically connected to the output terminal of the logic circuit, and an output terminal of the RS trigger is electrically connected to the switching converter; A drive circuit, wherein an input end of the drive circuit is electrically connected to an output end of the RS trigger, and an output end of the drive circuit is electrically connected to the switching converter.

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