A parallel bus data transmission system, method and storage medium

Abstract

The present invention provides a parallel bus data transmission system, method and storage medium, belonging to the technical field of data transmission, the system comprises: a data receiving end and a data transmitting end; the data receiving end generates a first state code through a state coding module, and sends the first state code to the data transmitting end through a heartbeat link; the data transmitting end controls a digital code generator to generate a first training code pattern corresponding to the first state code through a control register according to the received first state code, and sends the first training code pattern, a reference clock signal and N-channel data signals to the data receiving end; the data receiving end generates N-channel virtual clock signals through a clock distribution module based on the reference clock signal, and performs clock alignment processing to align the center of the N-channel virtual clock signal with the center of the N-channel data signal, and through the parallel bus data transmission system, the problem of clock skew and data skew in the parallel bus data transmission process can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a parallel bus data transmission system, method and storage medium. Background Art

[0002] Serial communication is widely used due to its low cost and simple structure. However, with the growing demand for high-speed data transmission, the bandwidth problem of serial communication has become increasingly prominent. To overcome this limitation, people have developed parallel communication technology, which uses a parallel transmission mechanism to send data simultaneously on multiple channels, significantly improving the data transmission rate.

[0003] Although parallel communication technology has advantages in increasing the rate, it also encounters a number of technical challenges including signal synchronization in the process of moving to higher rates. In particular, the difference in signal propagation time on different channels will cause clock and data skew, which poses a potential threat to the accuracy of data transmission and the reliability of the system. Summary of the invention

[0004] In view of the above problems, embodiments of the present application provide a parallel bus data transmission system, method and storage medium to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect of an embodiment of the present application, a parallel bus data transmission system is provided, comprising: a data receiving end and a data sending end;

[0006] The data receiving end generates a first state code through a state coding module, and sends the first state code to the data sending end through a heartbeat link;

[0007] The data transmitting end controls the digital code generator to generate a first training code pattern corresponding to the first state code through a control register according to the received first state code, and sends the first training code pattern, a reference clock signal and N data signals to the data receiving end;

[0008] Based on the reference clock signal, the data receiving end generates N virtual clock signals through a clock distribution module, and performs clock alignment processing to align the Nth virtual clock signal with the center of the Nth data signal, where the value range of N is an integer from 1 to N.

[0009] Furthermore, the data receiving end further comprises: a verification module and a delay module;

[0010] The verification module is used to calculate the bit error rate according to the first training code pattern and the first code pattern output by the data receiving end; wherein the first code pattern is obtained by the data receiving end sampling the N-channel data signals received based on the N-channel virtual clock signals;

[0011] The delay module is used to perform delay debugging on the N virtual clock signals respectively when the bit error rate is higher than the preset bit error rate, until the bit error rate is lower than the preset bit error rate.

[0012] Furthermore, the delay debugging of the N virtual clock signals respectively includes:

[0013] The N channels of virtual clock signals are debugged by increasing delay or reducing delay, so that the N channels of virtual clock signals after delay adjustment are aligned with the centers of the N channels of data signal sampling.

[0014] Further, after aligning the center of the N-th virtual clock signal with the N-th data signal, the data receiving end generates a second state code through the state coding module, and sends the second state code to the data sending end through the heartbeat link;

[0015] The data transmitting end controls the digital code generator to generate a second training code pattern corresponding to the second state code by controlling the register according to the received second state code, and sends the second training code pattern to the data receiving end;

[0016] The data receiving end calculates the delay error between the N-th virtual clock signal and the reference clock signal, determines whether there is data misalignment in the N-th data signal based on the delay error, performs synchronization compensation through the buffer of the data receiving end based on the data misalignment of the N-way data signal, and generates and outputs a second code type after the N-way data signal is transmitted.

[0017] Further, the determining whether there is data misalignment in the Nth data signal according to the delay error includes:

[0018] If the delay error is greater than or equal to half a clock cycle, it is determined whether there is data misalignment in the Nth data signal.

[0019] Further, according to the data misalignment of the N data signals, synchronous compensation is performed through the buffer of the data receiving end, and after the N data signals are all transmitted, a second code pattern is generated and output, including:

[0020] When receiving the data signals of each channel without data misalignment, storing the data signals of each channel without data misalignment into the buffer;

[0021] When receiving the data signals of each channel with data misalignment, combining the data signals of each channel with data misalignment with the data signals of each channel without data misalignment in the buffer to generate the second code pattern;

[0022] At the clock transition edge at which the data signal transmission is completed and the data misalignment occurs and the delay error is the largest, the second code type is output.

[0023] Further, when receiving the data signals with data misalignment, before merging the data signals with data misalignment with the data signals without data misalignment in the buffer to generate the second code pattern, the method further includes:

[0024] Determine whether there is a target data signal in each data signal with data misalignment; wherein the target data signal is a data signal with a misalignment of one clock cycle;

[0025] If it exists, the target data signal is delayed by one clock cycle, and the target data signal after the delay is stored in the buffer as a data signal without data misalignment.

[0026] Further, when receiving the data signals of each channel with data misalignment, merging the data signals of each channel with data misalignment with the data of each channel without data misalignment in the buffer to generate the second code pattern, including:

[0027] Obtaining the delay error corresponding to each data signal with data misalignment;

[0028] Based on the delay error, adjusting each data signal with data misalignment to be aligned with each data signal without data misalignment in clock cycle, and obtaining the aligned data signals with data misalignment;

[0029] The aligned data signals of each channel with data misalignment are combined with the data signals of each channel without data misalignment to generate the second code type.

[0030] Furthermore, before outputting the second code pattern at the clock transition edge at which the data signal transmission of a channel with the largest delay error and data misalignment is completed, the method further includes:

[0031] Compare the delay errors corresponding to the data signals of each channel, and mark the data signal with the largest delay error;

[0032] The outputting the second code type comprises:

[0033] The second code type is output according to the clock transition edge at which the transmission of a data signal is marked to be completed.

[0034] Further, the generating of N virtual clock signals through the clock distribution module and performing clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal includes:

[0035] Based on the N virtual clock signals, the delay error between the N data signals is controlled to be less than half a clock signal period.

[0036] Furthermore, the parallel bus data transmission system includes parallel buses, and the lengths of the parallel buses are equal or unequal.

[0037] In a second aspect of the embodiment of the present application, a parallel bus data transmission method is provided, which is applied to a data receiving end of the parallel bus data transmission system described in the first aspect of the embodiment of the present application, comprising:

[0038] Generate a first state code by a state coding module, and send the first state code to a data transmitting end through a heartbeat link;

[0039] Receive the data transmitting end, and control the digital code generator to generate a first training code pattern, a reference clock signal and N data signals corresponding to the first state code through a control register;

[0040] Based on the reference clock signal, N virtual clock signals are generated by a clock distribution module, and clock alignment processing is performed to align the center of the Nth virtual clock signal with the Nth data signal; wherein the value range of N is an integer from 1 to N.

[0041] Furthermore, it also includes:

[0042] Calculate the bit error rate based on the first training code pattern and the first code pattern output by the data receiving end; wherein the first code pattern is obtained by the data receiving end sampling the N data signals received based on the N virtual clock signals;

[0043] When the bit error rate is higher than a preset bit error rate, delay debugging is performed on the N virtual clock signals respectively until the bit error rate is lower than the preset bit error rate.

[0044] Further, after generating N virtual clock signals through a clock distribution module based on the reference clock signal and performing clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal, the method further includes:

[0045] Generate a second state code by the state coding module, and send the second state code to the data sending end through the heartbeat link;

[0046] Receiving a second training code pattern sent by the data transmitting end;

[0047] Obtaining a delay error between the Nth virtual clock signal and the reference clock signal, and determining whether there is a data misalignment in the Nth data signal based on the delay error;

[0048] In the case where the data misalignment exists, synchronization compensation is performed based on the data misalignment of the N data signals, and after the N data signals are all transmitted, a second code type is generated and output.

[0049] In a third aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the parallel bus data transmission method described in the second aspect of the embodiments of the present application are implemented.

[0050] The parallel bus data transmission system provided by this embodiment includes: a data receiving end and a data sending end; first, the data receiving end generates a first state code through a state coding module, and sends the first state code to the data sending end through a heartbeat link; then the data sending end controls the digital code generator to generate a first training code corresponding to the first state code through a control register according to the received first state code, and sends the first training code, a reference clock signal and N data signals to the data receiving end; finally, the data receiving end generates N virtual clock signals through a clock distribution module based on the reference clock signal, and performs clock alignment processing to align the Nth virtual clock signal with the center of the Nth data signal, wherein the value range of N is an integer from 1 to N.

[0051] The data receiving end generates a first state code through the state coding module, and sends the first state code to the data sending end through the heartbeat link, informing the data sending end that link training is required. Then the data sending end controls the digital code generator to generate a first training code pattern corresponding to the first state code through the control register according to the first state code, that is, the data sending end cooperates with the data receiving end to complete the training of the entire link, ensuring that the data sending end and the receiving end are synchronized before data transmission, so as to reduce errors and optimize link performance.

[0052] After the link training is completed, the data receiving end generates N virtual clock signals based on the reference clock signal through the clock distribution module, and performs clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal, solve the clock skew and data skew corresponding to each data signal, and ensure the stable and reliable transmission of each data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0054] Figure 1 It is a schematic diagram of a high-speed parallel digital-to-analog converter interface provided by the related art;

[0055] Figure 2 is a schematic diagram of a parallel bus data transmission system provided in an embodiment of the present application;

[0056] Figure 3 is a schematic diagram of calculating a delay error provided in an embodiment of the present application;

[0057] Figure 4 is a schematic diagram of data and clock before clock alignment processing provided by an embodiment of the present application;

[0058] Figure 5 It corresponds to Figure 4 A schematic diagram of data and clock after clock alignment is provided;

[0059] Figure 6 It is a schematic diagram of a parallel bus clock skew, data skew and equal length provided by the related art;

[0060] Figure 7 This is a flowchart of automatic alignment of a virtual synchronous clock provided by an embodiment of the present application;

[0061] Figure 8 It is a schematic diagram of a virtual synchronous clock matching data transmission provided by an embodiment of the present application;

[0062] Fig. 9 It is a schematic diagram of data delay judgment of unequal-length parallel buses provided in an embodiment of the present application;

[0063] Fig.10 It is a flow chart of data delay determination of unequal-length parallel buses provided in an embodiment of the present application;

[0064] Fig.11 is a schematic diagram of data misalignment provided in an embodiment of the present application;

[0065] Fig.12 This is a flow chart of data delay and misalignment adjustment provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully conveyed to those skilled in the art.

[0067] In high-speed data transmission systems, clock skew and data skew are two major issues that affect data synchronization and accuracy. Clock skew occurs in parallel data transmission. Due to the different propagation delays of signals on different channels, the arrival time of the clock signal at the receiving end is inconsistent. This will make the clock edge of data sampling inaccurate, increasing the risk of data sampling errors or losses. Data skew occurs in multi-channel data transmission. Due to differences in physical length, electrical characteristics, or signal propagation speed, the time at which the data signal arrives at the receiver is inconsistent, making it difficult for the receiving end to accurately sample all data at the correct clock edge, thereby increasing the risk of data errors.

[0068] As data transmission rates increase, the above skew problem becomes more significant. High-speed parallel buses face more challenges in PCB routing and signal transmission, such as crosstalk, power supply noise, and ground bounce, which seriously affect the stability and performance of the system. In order to reduce the impact of skew, the PCB layout needs to be strictly designed to ensure that the signal lines are of equal length, line width, and spacing, which not only increases the difficulty of design, but also increases the cost. Although the parallel bus improves transmission efficiency through multiple signal lines, at high speeds, the skew introduced by a single clock and data line may cause bit errors, limiting the bandwidth improvement of the parallel bus.

[0069] In the related art, field programmable gate arrays usually interact with digital-to-analog converters or analog-to-digital converters through high-speed parallel interfaces. This interaction is to achieve efficient data transmission and processing, especially in applications that require fast response and high precision, such as signal processing, communication systems, test and measurement equipment, etc. DDR (Double Data Rate, double data rate synchronous dynamic random access memory) memory is a dynamic random access memory that achieves a higher data transmission rate than traditional single data rate memory by transmitting data simultaneously on the rising and falling edges of each clock cycle.

[0070] This double data rate technology is the origin of the name of DDR memory and is also the key to its high-speed operation. The parallel interface design of DDR memory allows multiple digital signals to be read and written simultaneously, greatly improving the data processing speed. With the development of technology, from DDR1 to DDR5, each generation of DDR memory has increased the frequency and bandwidth while also increasing the number of pins on the memory module to maintain high-speed transmission of parallel data. For example, the maximum memory transfer speed of DDR5 can reach 6.4Gbps, which is more than twice the maximum memory transfer speed under the DDR4 standard.

[0071] Parallel data transmission can process more data at the same time in the memory field, thereby increasing the overall data transmission rate. Although serial data transmission is more common in some cases due to its lower hardware complexity and cost, in the memory field, parallel interfaces are widely adopted due to their high-speed characteristics.

[0072] In general, DDR memory uses its high-speed parallel interface to perform two data transmissions in each clock cycle. This design enables DDR memory to achieve high data transmission rates while maintaining low latency, meeting the requirements for memory performance.

[0073] Reference Figure 1 , Figure 1 It is a schematic diagram of a high-speed parallel digital-to-analog converter interface provided by the related technology. In the application scenario of 1, Figure 1 The high-speed parallel port interacts with the programmable gate array through 16 low-voltage differential signal transmissions, which requires equal-length signal processing, but is difficult for PCB layout and wiring; secondly, the reference clock frequency cannot be too large, otherwise clock skew will cause bit errors, and the larger the data bus bandwidth, the more difficult it is to adjust the reference clock and each bus.

[0074] In view of this, the present embodiment provides a parallel bus data transmission system, which dynamically monitors the status of the data receiving end through a heartbeat link and accurately trains the parallel bus based on the monitoring results, effectively solving the problems of clock skew and data skew, while adapting to the data synchronization requirements under conditions of unequal line lengths, and improving the transmission stability and reliability of the system.

[0075] Reference Figure 2 , Figure 2 is a schematic diagram of a parallel bus data transmission system provided in an embodiment of the present application; Figure 2 It can be seen that the parallel bus data transmission system includes: a data receiving end and a data sending end;

[0076] First, the data receiving end generates a first state code through a state coding module, and sends the first state code to the data sending end through a heartbeat link; then the data sending end controls the digital code generator to generate a first training code corresponding to the first state code through a control register according to the received first state code, and sends the first training code, a reference clock signal and N data signals to the data receiving end; finally, the data receiving end generates N virtual clock signals through a clock distribution module based on the reference clock signal, and performs clock alignment processing to align the Nth virtual clock signal with the center of the Nth data signal, wherein the value range of N is an integer from 1 to N.

[0077] In this embodiment, from Figure 2 It can be seen that a heartbeat link is set between the data receiving end and the data sending end. The heartbeat link detects the state of the data receiving end to determine whether the data receiving end can operate and respond normally. Secondly, the heartbeat link can carry state coding. The state coding module is a module responsible for generating state coding. The state coding generated by the state coding module can represent the current working state of the data receiving end and the real-time state of the data receiving end during the link training process, such as synchronization state, buffer state, error detection state, etc.

[0078] Therefore, the data receiving end can generate the first state code through the state coding module, and send the first state code to the data sending end through the heartbeat link. The first state code triggers the data sending end to start link training to ensure the synchronization of the link before data transmission. The first state code can be the initial state information of the data receiving end.

[0079] Then, the data sending end determines the initial state or specific requirements of the data receiving end according to the received first state code, and controls the digital code generator to generate a first training code pattern corresponding to the first state code through the control register. The first training code pattern is used to cooperate with the data receiving end to complete link training, ensuring that before data transmission, the data receiving end and the data sending end can be accurately aligned in timing and phase, thereby optimizing the synchronization and accuracy of data transmission.

[0080] The first training code type, the reference clock signal and N data signals are then sent to the data receiving end, so that the data receiving end can generate a clock synchronized with the data sending end based on the reference clock signal. Since the data sending module sends N data signals to the data receiving end, in a parallel bus data transmission system, multiple data signals need to be operated synchronously. The data receiving end generates N virtual clock signals based on the reference clock signal through the clock distribution module. The virtual clock signal is used to ensure that each data signal can be accurately synchronized and sampled.

[0081] Then, the Nth virtual clock signal is aligned with the center of the Nth data signal to ensure that each data signal is sampled at the correct time, thereby reducing or compensating for the clock skew and data skew caused by the difference in signal propagation delay, thereby improving the synchronization and accuracy of data transmission. Since the value range of N is an integer from 1 to N, for example, by aligning the center of the 1st virtual clock signal with the 1st data signal, the clock skew and data skew caused by the difference in propagation delay of the 1st data signal can be solved.

[0082] The parallel bus data transmission system provided by this embodiment realizes real-time monitoring of the state of the data receiving end by setting a heartbeat link, and triggers the link training of the data sending end by using the first state code generated by the state coding module, thereby ensuring the precise alignment of the timing and phase before data transmission. The data sending end further optimizes the data synchronization and accuracy by combining the reference clock signal and N-channel data signals with the first training code pattern generated by the first state code. The data receiving end generates N-channel virtual clock signals based on the received reference clock signal, realizes the independent synchronization of multiple data signals, effectively reduces clock skew and data skew, and improves the stability and transmission efficiency of the parallel bus data transmission system.

[0083] In a specific embodiment, the data receiving end further includes: a verification module and a delay module;

[0084] The verification module is used to calculate the bit error rate based on the first training code type and the first code type output by the data receiving end; wherein the first code type is obtained by the data receiving end sampling the N data signals received based on the N virtual clock signals; the delay module is used to, when the bit error rate is higher than the preset bit error rate, respectively perform delay debugging on the N virtual clock signals until the bit error rate is lower than the preset bit error rate.

[0085] In this embodiment, refer to Figure 2 The data receiving end also includes a check module and a delay module. The check module is used to calculate the bit error rate based on the first training code type and the first code type. The first code type is obtained by the data receiving end by sampling the received N-channel data signals based on the N-channel virtual clock signals. If the first code type is consistent with the first training code type, it indicates that no error occurs during the data transmission process, that is, the bit error rate is zero. If there is a difference between the first code type and the first training code type, the check module will calculate the bit error rate through these differences. The method for calculating the bit error rate is usually to count the ratio of the number of error bits to the total number of bits in a certain number of bits or data blocks. For example, if 1000 bits are sent and 10 bits are erroneous, the bit error rate is 1%.

[0086] The delay module is used to perform delay debugging on N virtual clock signals respectively when the bit error rate is higher than the preset bit error rate, until the bit error rate is lower than the preset bit error rate.

[0087] Therefore, the verification module is responsible for determining the bit error rate. Once the bit error rate is detected to exceed the preset threshold, the delay module will be triggered to intervene. The delay module performs accurate delay debugging on each virtual clock signal corresponding to the first code type that is different from the first training code type. After the debugging is completed, the verification module will recalculate the bit error rate and adjust iteratively until the bit error rate drops below the preset bit error rate, which helps to reduce data skew and clock skew and ensure the accuracy and reliability of data transmission. The preset bit error rate in this embodiment is not limited and can be set according to the actual situation of the system.

[0088] The clock skew is solved by the delay module. The accuracy of the sampling time can be improved by aligning the center of the Nth virtual clock signal with the Nth data signal, thereby improving the accuracy of data sampling and reducing the bit errors caused by clock deviation, thereby reducing the bit error rate in the entire data transmission process.

[0089] In a specific embodiment, the delay debugging of the N virtual clock signals respectively includes: increasing the delay debugging or reducing the delay debugging of the N virtual clock signals so that the N virtual clock signals after delay adjustment are aligned with the center of the N data signal sampling.

[0090] In this embodiment, the arrival time of the clock signal on different channels may be inconsistent due to factors such as physical line length differences, signal propagation speed differences, or internal device delays in the parallel data transmission system, so targeted delay debugging can be performed on the N-channel virtual clock signals with synchronization deviations. If the virtual clock signal arrives early, the delay can be reduced; if the virtual clock signal arrives late, the delay can be increased. This debugging ensures that the adjusted N-channel virtual clock signals can be accurately aligned with the center of the N-channel data signal sampling.

[0091] In a specific embodiment, after aligning the center of the Nth virtual clock signal with the Nth data signal, the data receiving end generates a second state code through the state coding module, and sends the second state code to the data sending end through the heartbeat link; the data sending end controls the digital code generator to generate a second training code corresponding to the second state code by controlling the register according to the received second state code, and sends the second training code to the data receiving end; the data receiving end calculates the delay error between the Nth virtual clock signal and the reference clock signal, determines whether there is data misalignment in the Nth data signal according to the delay error, performs synchronization compensation through the buffer of the data receiving end according to the data misalignment of the N data signals, and generates and outputs a second code after the N data signals are all transmitted.

[0092] In this embodiment, the data receiving end aligns the center of the Nth virtual clock signal with the Nth data signal, that is, the problem of clock skew is solved. Therefore, it is also necessary to generate a second state code through the state coding module, and send the second state code to the data sending end through the heartbeat link. The data sending end controls the digital code generator to generate a second training code corresponding to the second state code through the control register according to the received second state code, and sends the second training code to the data receiving end. The data receiving end calculates the delay error between the Nth virtual clock signal and the reference clock signal, and determines whether there is data misalignment in the Nth data signal. If there is data misalignment, there is a problem of data skew. At this time, it is necessary to perform synchronization compensation through the buffer of the data receiving end. After the N-way data signal is transmitted, the second code is generated and output to solve the problem of data skew.

[0093] In a specific embodiment, determining whether the Nth data signal has data misalignment based on the delay error includes: if the delay error is greater than or equal to half a clock cycle, determining whether the Nth data signal has data misalignment.

[0094] In this embodiment, since the Nth virtual clock signal is aligned with the center of the Nth data signal, if the delay error is greater than or equal to half a clock cycle, this may mean that there is a large deviation between the arrival time of the data signal and the clock synchronization of the receiving end. Since the N virtual clock signals have been delayed and debugged separately before, the bit error rate has been reduced below the preset bit error rate. It is possible to determine whether there is data misalignment in the Nth data signal.

[0095] For example, refer to Figure 3 , Figure 3 is a schematic diagram of calculating a delay error provided by an embodiment of the present application, from Figure 3It can be seen that after the Nth virtual clock signal is automatically aligned with the Nth data signal, the sampling edge of the Nth virtual clock signal is in the center of the data. The reason why it can be automatically aligned is that the delay error is obtained based on the reference clock signal. All the 1st virtual clock signal to the Nth virtual clock signal are delayed with the reference clock signal, that is, the delay error between the 1st data signal to the Nth data signal and the reference clock signal. If the delay error is greater than or equal to half the reference clock signal cycle, there will be data misalignment. Therefore, if the delay error is greater than or equal to half the clock cycle, it is determined whether there is data misalignment in the Nth data signal.

[0096] In a specific embodiment, according to the data misalignment of the N data signals, synchronous compensation is performed through the buffer of the data receiving end, and after the N data signals are all transmitted, a second code pattern is generated and output, including the following steps:

[0097] When receiving data signals without data misalignment, the data signals without data misalignment are stored in the buffer; when receiving data signals with data misalignment, the data signals with data misalignment are merged with the data signals without data misalignment in the buffer to generate the second code type; at the clock transition edge when the transmission of the data signal with data misalignment with the largest delay error is completed, the second code type is output.

[0098] In this embodiment, each data signal may have a time difference when arriving at the data receiving end due to various reasons (such as signal propagation path, device processing speed, etc.), which may cause data misalignment. The buffer can temporarily store data and allow the data receiving end to make synchronization adjustments based on the actual arrival time of each data signal. Therefore, when receiving each data signal without data misalignment, each data signal without data misalignment is stored in the buffer for waiting.

[0099] When receiving data signals with data misalignment, the data signals with data misalignment are combined with data signals without data misalignment in the buffer to correct the data signals with data misalignment and generate a correct data sequence, namely, a second code type.

[0100] The second code pattern is output after the data signal with the largest delay error and data misalignment is transmitted to ensure that all data signals with data misalignment have reached the buffer and are processed correctly, thereby avoiding incomplete or erroneous data due to premature output.

[0101] Therefore, the second code type is output at the clock transition edge when the data signal transmission of the channel with the largest delay error and data misalignment is completed.

[0102] In a specific embodiment, when receiving data signals with data misalignment, the data signals with data misalignment are merged with the data signals without data misalignment in the buffer to generate the second code type, and it also includes: determining whether there is a target data signal in the data signals with data misalignment; wherein the target data signal is a data signal that is misaligned by one clock cycle; if so, delaying the target data signal by one clock cycle, and storing the target data signal after the delay as a data signal without data misalignment in the buffer.

[0103] In a specific embodiment, in a specific embodiment of data transmission, each data signal must be accurately synchronized with the clock of the data receiving end so as to be sampled at the correct clock edge. If the data signal is misaligned by one clock cycle, it will not be accurately sampled at the predetermined clock edge, resulting in a data misalignment problem. This misalignment means that the actual arrival time of the data signal does not match the expected sampling time, and a clock synchronization error occurs. Therefore, it is necessary to determine whether there is a target data signal in each data signal with data misalignment, and to extend the sampling time of the target data signal by one clock cycle to compensate for its misalignment. After the extension process is completed, the target data signal is stored in the buffer as a data signal without data misalignment to ensure that it is consistent in time with each data signal in the buffer.

[0104] In a specific embodiment, when receiving data signals with data misalignment, merging the data signals with data misalignment with data signals without data misalignment in the buffer to generate the second code pattern may include the following steps:

[0105] First, the delay error corresponding to each data signal with data misalignment is obtained; then, based on the delay error, the data signals with data misalignment are adjusted to be aligned with the data signals without data misalignment in the clock cycle, and the aligned data signals with data misalignment are obtained; then, the aligned data signals with data misalignment are merged with the data signals without data misalignment to generate the second code type.

[0106] In this embodiment, the delay error corresponding to each data signal with data misalignment is obtained, and then, based on the delay error, the data signals with data misalignment are adjusted to be aligned with the data signals without data misalignment in the clock cycle, and then the aligned data signals with data misalignment are obtained, and the aligned data signals with data misalignment are merged with the data signals without data misalignment to generate a second code type.

[0107] In a specific embodiment, before outputting the second code type at the clock transition edge at which the data signal with the largest delay error and data misalignment is transmitted, the following steps are also included: comparing the delay errors corresponding to each data signal, and marking the data signal with the largest delay error; outputting the second code type includes: outputting the second code type according to the clock transition edge at which the marked data signal is transmitted.

[0108] In this embodiment, after first comparing the delay errors of the data signals, the data signal with the largest delay error is marked, which can minimize the incomplete data sampling caused by the excessive delay error and the second data code type. The clock transition edge at which the marked data signal transmission is completed is used as the timing for outputting the second code type, which can ensure that the output is performed after all data signals have been received and synchronized, avoiding the problem of data inconsistency caused by premature output.

[0109] In a specific embodiment, N virtual clock signals are generated by a clock distribution module, and clock alignment processing is performed to align the center of the Nth virtual clock signal with the Nth data signal, including: based on the N virtual clock signals, controlling the delay error between the N data signals to be less than half a clock signal period.

[0110] In this embodiment, based on N virtual clock signals, the delay error between the N data signals is controlled to be less than half a clock signal cycle, which can ensure that the data signals do not overlap within half a clock signal cycle, avoid data conflicts at the sampling points, and ensure that the data signals can be accurately sampled at the correct clock edge, thereby reducing misalignment and conflicts, thereby reducing the bit error rate and improving the data signal integrity.

[0111] For example, refer to Figure 4 , Figure 4 is a schematic diagram of data and clock before clock alignment processing provided by an embodiment of the present application;

[0112] from Figure 4 It can be seen that the Nth virtual clock signal is not aligned with the Nth data signal at the beginning as shown below. It can be seen that during sampling, the sampling edge of the Nth virtual clock signal is in the transition window area of ​​the Nth data signal. At this time, the signal of the Nth data signal is abnormal.

[0113] Below Figure 3 Perform clock alignment, refer to Figure 5 , Figure 5 It corresponds to Figure 4 The schematic diagram of data and clock after clock alignment is provided. Figure 5It can be seen that the Nth virtual clock signal is delayed accordingly, that is, Figure 5 Shifting the Nth virtual clock signal to the left, we can see that the sampling is normal when it is at the center of the vertical line. If we continue to shift to the left, the sampling bit errors will increase. As the delay parameters of the Nth virtual clock signal are adjusted, the bit error rate will meet the following characteristics: high at both ends and low in the middle. According to this characteristic, Figure 2 The verification module continuously adjusts the delay parameters to find the sampling center point, thus completing the virtual synchronous clock automatic alignment technology.

[0114] Due to different virtual clocks, the 1st virtual clock signal to the Nth virtual clock signal may have delays across clock cycles, that is, some clocks need to be delayed backwards and some clocks need to be adjusted forward. Although multiple groups of clocks ensure alignment with various data signals, delays are generated between each data signal. If the data delay between each data signal cannot be synchronized, the overall sampling is also problematic. The delay of each data signal can be controlled to be within half a clock signal cycle.

[0115] In a specific embodiment, the parallel bus data transmission system includes parallel buses, and the lengths of the parallel buses are equal or unequal.

[0116] In this embodiment, no matter whether the lengths of the parallel buses are equal or not, the parallel bus data transmission system provided by this embodiment can be used to solve the problems of data skew and clock skew in the parallel bus data transmission process.

[0117] By way of example, this embodiment will provide a complete description of the unequal length parallel bus data transmission system through a specific embodiment:

[0118] For data validity, data sampling is usually performed at the edge of the clock. However, as the parallel interface bit width increases, the design of equal-length routing, and the clock frequency increase, it becomes increasingly difficult to create parallel buses with high bit width, high frequency, and high difficulty. The problem lies in: the jitter of the signal edge or the rise time cannot meet the sufficient sampling window; the high bit width parallel bus cannot achieve true "equal length"

[0119] Reference Figure 6 , Figure 6 This is a schematic diagram of parallel bus clock skew, data skew and equal length provided by the relevant technology. Figure 6 As can be seen from the figure, data and clock are not a beautiful transition edge, but a set of thick lines (i.e. Figure 6The vertical line in the figure is caused by the jitter of the transition edge and the limited edge climbing ability. In addition, the 1st to Nth data signals cannot be synchronized when transmitting the same signal. This is because the equal length design becomes more difficult as the row interface bit width increases. All of the above problems have led to a problem. The sampling error problem occurs when the sampling window consistency cannot be guaranteed during sampling.

[0120] Reference Figure 7 , Figure 7 This is a flowchart of a virtual synchronous clock automatic alignment provided by an embodiment of the present application, combined with Figure 2 ,from Figure 7 It can be seen that after the initial power-on, link training is performed, and then the receiving end status coding output, the sending end control synchronization code pattern output, clock alignment processing, and the receiving end status coding output are completed. After that, the link training is returned to inform that the link training is completed. Figure 7 The receiving end is Figure 2 The data receiving end in is Figure 2 The data sending end in the Figure 2 ,right Figure 7 The specific process is described as follows:

[0121] First, when the power is turned on for the first time, link training is performed. Assume that the first state code output by the state coding module of the data receiving end to the data sending end is 0001...0001...000 continuous code. At this time, the data sending end will control the digital code generator to generate a first training code corresponding to the first state code through the control register. The first training code is 0101...0101...0101 continuous N-channel clock synchronization code. Then, based on the N-channel virtual clock signal, the first code is obtained by sampling the received N-channel data signal, and the first training code is compared with the first code. The virtual clock is automatically synchronized and aligned, and the second state code is output to the data sending end to complete the initialization configuration, that is, the link training is completed.

[0122] Figure 7 The clock alignment process in Figure 2 The clock distribution module in the clock distribution module generates N virtual clock signals according to the reference clock signal, and performs clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal, referring to Figure 8 , Figure 8 is a schematic diagram of a virtual synchronous clock matching data transmission provided by an embodiment of the present application, from Figure 8 It can be seen that the Nth virtual clock signal is aligned with the center of the Nth data signal.

[0123] In addition, when the parallel buses are of unequal length, refer to Fig. 9 , Fig. 9Schematic diagram of a data delay judgment of unequal length parallel buses provided in an embodiment of the present application, from Fig. 9 It can be seen that there is no problem with the sampling point of the data, but when the 1st data signal to the Nth data signal are combined, there is a problem with the first code pattern due to the reference clock delay error. Therefore, it is necessary to make a delay judgment after the clock alignment.

[0124] Reference Fig.10 , Fig.10 is a flowchart of the delay judgment of unequal-length parallel bus data provided by the embodiment of the present application, from Fig.10 It can be seen that after the clock is aligned, the delay judgment is made in sequence, the receiving end status coding output, the sending end controls the synchronization code output, the receiving end records the code start clock time, compares the delay size, and the parallel port data buffer combination, and then returns to the delay judgment. Fig.10 The receiving end is Figure 2 The data receiving end in is Figure 2 The data sending end in the Figure 2 ,right Fig.10 The specific process is as follows: the data receiving end sends the second state code through the heartbeat link. Assuming that the second state code is 0011…0011…0011, the data sending end is informed that a delay judgment needs to be made. The data sending end controls the delay code type 8bit11111010 to be output on each data port, measures the delay time of all data buses, compares the delay size, and then, at the end of the transmission, the parallel data buffer is combined. For example, when all data ports receive 100 data signals, the clock delay of the last code type of each data signal is compared. The parallel port data is buffered and combined according to the delay size to eliminate the problem of data misalignment.

[0125] Reference Fig.11 , Fig.11 is a schematic diagram of data misalignment provided in an embodiment of the present application, from Fig.11 It can be seen that the 1st data signal and the Nth data signal transmit the same 8-bit data. The 1st data signal is transmitted earlier than the Nth data signal. If the delay problem is not considered, data misalignment will occur. For example, there is data misalignment between bit6 of the Nth data signal and bit7 of the 1st data signal, that is, data skew. After the 1st data signal to the Nth data signal complete a group of data transmission, the port data that has been transmitted first will be stored in the cache for retention. After all port data are transmitted, they will be output uniformly. For example, the 1st data signal is transmitted in the 7th cycle of the reference clock signal. The data of the 1st data signal is first put into the cache, and the data of the Nth data signal is transmitted in the 8th cycle of the reference clock signal. At this time, the cached data of the 1st data signal and the Nth data signal are officially received at the same time as the 8th cycle of the reference clock signal.

[0126] Reference Fig.12 , Fig.12 1 is a flow chart of data delay and misalignment adjustment provided by an embodiment of the present application. Fig.12 It can be seen that first, the minimum data transmission port delay is used to determine whether the data is misaligned. If so, it is determined whether the data misalignment differs by 1 clock cycle. If so, the number of clock cycles of the port data misalignment is obtained, and then the port analysis is completed, and the minimum data transmission port delay is left. If not, the delay minus 1 clock cycle is used to determine whether the data is misaligned again.

[0127] If there is no misalignment in the data, the data is counted into the cache. After all ports are combed, the relevant adjustment clock cycles are recorded, and the first transmission is counted into the cache. After the last clock transition edge of the port with the largest delay completes the transmission, the output and combination of all data ports are completed. It should be noted in this embodiment that the larger the bit width and the greater the delay, the higher the requirements for the cache size and data adjustment time. If the bit width is 8bit and the reference clock signal size is 100Mhz, the maximum delay size shall not exceed 10ns. The cache size is 16bit, and the adjustment time shall not exceed 5ns.

[0128] The embodiment of the present application further provides a parallel bus data transmission method, which is applied to a data receiving end of the parallel bus data transmission system described in the first aspect of the embodiment of the present application, comprising:

[0129] Generate a first state code by a state coding module, and send the first state code to a data transmitting end through a heartbeat link;

[0130] Receive the data transmitting end, and control the digital code generator to generate a first training code pattern, a reference clock signal and N data signals corresponding to the first state code through a control register;

[0131] Based on the reference clock signal, N virtual clock signals are generated by a clock distribution module, and clock alignment processing is performed to align the center of the Nth virtual clock signal with the Nth data signal; wherein the value range of N is an integer from 1 to N.

[0132] In this embodiment, it also includes:

[0133] Calculate the bit error rate based on the first training code pattern and the first code pattern output by the data receiving end; wherein the first code pattern is obtained by the data receiving end sampling the N data signals received based on the N virtual clock signals;

[0134] When the bit error rate is higher than a preset bit error rate, delay debugging is performed on the N virtual clock signals respectively until the bit error rate is lower than the preset bit error rate.

[0135] In this embodiment, after generating N virtual clock signals through a clock distribution module based on the reference clock signal and performing clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal, the method further includes:

[0136] Generate a second state code by the state coding module, and send the second state code to the data sending end through the heartbeat link;

[0137] Receiving a second training code pattern sent by the data transmitting end;

[0138] Obtaining a delay error between the Nth virtual clock signal and the reference clock signal, and determining whether there is a data misalignment in the Nth data signal based on the delay error;

[0139] In the case where the data misalignment exists, synchronization compensation is performed based on the data misalignment of the N data signals, and after the N data signals are all transmitted, a second code type is generated and output.

[0140] Through the parallel bus data transmission method provided in this embodiment, the data receiving end can be controlled to generate a first state code through the state coding module, and the first state code can be sent to the data sending end through the heartbeat link to inform the data sending end that link training is required. Then, the data sending end controls the digital code generator to generate a first training code pattern corresponding to the first state code through the control register according to the first state code, that is, the data sending end cooperates with the data receiving end to complete the training of the entire link, ensuring that the data sending end and the receiving end are synchronized before data transmission, so as to reduce errors and optimize link performance.

[0141] After the link training is completed, the data receiving end generates N virtual clock signals based on the reference clock signal through the clock distribution module, and performs clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal, solve the clock skew and data skew corresponding to each data signal, and ensure the stable and reliable transmission of each data signal.

[0142] The embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the parallel bus data transmission method as described in the embodiment of the present application are implemented.

[0143] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0144] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods and devices according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0145] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0147] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0148] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0149] The above is a detailed introduction to a parallel bus data transmission system, method and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A parallel bus data transmission system, characterized in that: include: Data receiving end and data sending end; The data receiving end generates a first state code through a state coding module, and sends the first state code to the data sending end through a heartbeat link; The data transmitting end controls the digital code generator to generate a first training code pattern corresponding to the first state code through a control register according to the received first state code, and sends the first training code pattern, a reference clock signal and N data signals to the data receiving end; wherein the first state code is used to represent the real-time state of the data receiving end, and the first training code is used to cooperate with the data receiving end to complete link training; The data receiving end generates N virtual clock signals through a clock distribution module based on the reference clock signal, and performs clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal, wherein the value range of N is an integer from 1 to N; The data receiving end also includes: a verification module and a delay module; The verification module is used to calculate the bit error rate according to the first training code pattern and the first code pattern output by the data receiving end; wherein the first code pattern is obtained by the data receiving end sampling the N-channel data signals received based on the N-channel virtual clock signals; The delay module is used to respectively perform delay debugging on the N virtual clock signals when the bit error rate is higher than the preset bit error rate until the bit error rate is lower than the preset bit error rate; wherein, respectively performing delay debugging on the N virtual clock signals includes: The N channels of virtual clock signals are debugged by increasing delay or reducing delay, so that the N channels of virtual clock signals after delay adjustment are aligned with the centers of the N channels of data signal sampling.

2. The parallel bus data transmission system according to claim 1, characterized in that: After aligning the center of the Nth virtual clock signal with the Nth data signal, the data receiving end generates a second state code through the state coding module, and sends the second state code to the data sending end through the heartbeat link; The data transmitting end controls the digital code generator to generate a second training code pattern corresponding to the second state code by controlling the register according to the received second state code, and sends the second training code pattern to the data receiving end; The data receiving end calculates the delay error between the N-th virtual clock signal and the reference clock signal, determines whether there is data misalignment in the N-th data signal based on the delay error, performs synchronization compensation through the buffer of the data receiving end based on the data misalignment of the N-way data signal, and generates and outputs a second code type after the N-way data signal is transmitted.

3. The parallel bus data transmission system according to claim 2, characterized in that: The determining, according to the delay error, whether the Nth data signal has data misalignment includes: If the delay error is greater than or equal to half a clock cycle, it is determined whether there is data misalignment in the Nth data signal.

4. The parallel bus data transmission system according to claim 2, characterized in that: The method of performing synchronization compensation by a buffer at the data receiving end according to the data misalignment of the N data signals, and generating and outputting a second code type after the N data signals are all transmitted, comprises: When receiving the data signals of each channel without data misalignment, storing the data signals of each channel without data misalignment into the buffer; When receiving the data signals of each channel with data misalignment, combining the data signals of each channel with data misalignment with the data signals of each channel without data misalignment in the buffer to generate the second code pattern; At the clock transition edge at which the data signal transmission is completed and the data misalignment occurs and the delay error is the largest, the second code type is output.

5. The parallel bus data transmission system according to claim 3, characterized in that: When receiving the data signals with data misalignment, before combining the data signals with data misalignment with the data signals without data misalignment in the buffer to generate the second code pattern, the method further includes: Determine whether there is a target data signal in each data signal with data misalignment; wherein the target data signal is a data signal with a misalignment of one clock cycle; If it exists, the target data signal is delayed by one clock cycle, and the target data signal after the delay is stored in the buffer as a data signal without data misalignment.

6. The parallel bus data transmission system according to claim 2, characterized in that: When receiving data signals of various channels with data misalignment, merging the data signals of various channels with data misalignment with data signals of various channels without data misalignment in the buffer to generate the second code pattern, including: Obtaining the delay error corresponding to each data signal with data misalignment; Based on the delay error, adjusting each data signal with data misalignment to be aligned with each data signal without data misalignment in clock cycle, and obtaining the aligned data signals with data misalignment; The aligned data signals of each channel with data misalignment are combined with the data signals of each channel without data misalignment to generate the second code type.

7. The parallel bus data transmission system according to claim 2, characterized in that: At the clock transition edge when the data signal transmission of a channel with the largest delay error and data misalignment is completed, before outputting the second code pattern, the method further includes: Compare the delay errors corresponding to the data signals, and mark the data signal with the largest delay error; The outputting the second code type comprises: The second code type is output according to the clock transition edge at which the transmission of a data signal is marked to be completed.

8. The parallel bus data transmission system according to claim 2, characterized in that: The method of generating N virtual clock signals through a clock distribution module and performing clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal includes: Based on the N virtual clock signals, the delay error between the N data signals is controlled to be less than half a clock signal period.

9. The parallel bus data transmission system according to claim 1, characterized in that: The parallel bus data transmission system comprises parallel buses, and the lengths of the parallel buses are equal or unequal.

10. A parallel bus data transmission method, characterized in that: A data receiving end used in a parallel bus data transmission system according to any one of claims 1 to 9, comprising: Generate a first state code by a state coding module, and send the first state code to a data transmitting end through a heartbeat link; Receive the data transmitting end, and control the digital code generator to generate a first training code pattern, a reference clock signal, and N data signals corresponding to the first state code through a control register; wherein the first state code is used to represent the real-time state of the data receiving end, and the first training code is used to cooperate with the data receiving end to complete link training; Based on the reference clock signal, N virtual clock signals are generated by a clock distribution module, and clock alignment processing is performed to align the center of the Nth virtual clock signal with the Nth data signal; wherein the value range of N is an integer from 1 to N.

11. The parallel bus data transmission method according to claim 10, characterized in that: Also includes: Calculate the bit error rate based on the first training code pattern and the first code pattern output by the data receiving end; wherein the first code pattern is obtained by the data receiving end sampling the N data signals received based on the N virtual clock signals; When the bit error rate is higher than a preset bit error rate, delay debugging is performed on the N virtual clock signals respectively until the bit error rate is lower than the preset bit error rate; The data receiving end also includes: a verification module and a delay module; The verification module is used to calculate the bit error rate according to the first training code pattern and the first code pattern output by the data receiving end; wherein the first code pattern is obtained by the data receiving end sampling the N-channel data signals received based on the N-channel virtual clock signals; The delay module is used to respectively perform delay debugging on the N virtual clock signals when the bit error rate is higher than the preset bit error rate until the bit error rate is lower than the preset bit error rate; wherein, respectively performing delay debugging on the N virtual clock signals includes: The N channels of virtual clock signals are debugged by increasing delay or reducing delay, so that the N channels of virtual clock signals after delay adjustment are aligned with the centers of the N channels of data signal sampling.

12. The parallel bus data transmission method according to claim 10, characterized in that: After generating N virtual clock signals based on the reference clock signal through a clock distribution module and performing clock alignment processing to align the center of the Nth virtual clock signal with the Nth data signal, the method further includes: Generate a second state code by the state coding module, and send the second state code to the data sending end through the heartbeat link; Receiving a second training code pattern sent by the data transmitting end; Obtaining a delay error between the Nth virtual clock signal and the reference clock signal, and determining whether there is a data misalignment in the Nth data signal based on the delay error; In the case where the data misalignment exists, synchronization compensation is performed based on the data misalignment of the N data signals, and after the N data signals are all transmitted, a second code type is generated and output.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the parallel bus data transmission method according to any one of claims 10 to 12 are implemented.

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