Transmitting and receiving device, transmission method and system based on Ethernet interface

Abstract

The present application discloses an interface, which includes a general function unit and one or more special function units, wherein: the general function unit includes one or more general function modules; the special function unit includes one or more specific function modules.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 202110049548.5 filed on January 14, 2021, and invention name “Interface, electronic device and communication system”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to an interface, an electronic device and a communication system. Background Art

[0003] In the current evolution of Ethernet interfaces, new interface rates need to be compatible with the previous electrical and optical interfaces of various rates. However, the Ethernet interface logic layer solution has a low utilization rate for the performance of the transmission medium. Summary of the invention

[0004] The embodiments of the present application provide an interface, an electronic device, and a communication system. The technical solution of the embodiments of the present application can make full use of the performance of the optical module. In the first aspect, an interface includes a functional part 1 and a functional part 2, wherein the functional part 1 is used to implement processing related to the media access control MAC rate, and the functional part 2 is used to implement processing unrelated to the MAC rate.

[0005] In some embodiments, the interface is an Ethernet interface.

[0006] In some embodiments, the functional portion one includes a media independent interface.

[0007] In some embodiments, the functional part 1 includes a MAC module, a coordination sublayer RS ​​module, and a coding and rate adaptation module in a physical coding sublayer PCS.

[0008] In some embodiments, the functional part two includes one or more functional units, wherein the one or more functional units include a first functional unit, and the first functional unit includes a transcoding module, a scrambling module, an alignment mark insertion module, a forward error correction FEC module, a physical medium access sublayer PMA module, and a physical medium associated PMD module.

[0009] In some embodiments, the functional part two includes a PMA / PMD module and one or more functional units, wherein the one or more functional units include a second functional unit, the second functional unit includes a transcoding module, a scrambling module, an alignment mark insertion module, and a forward error correction FEC module, and the second functional unit is coupled to the PMA / PMD module.

[0010] In some embodiments, the functional part two includes a cascaded first-level functional unit and a second-level functional unit, the first-level functional unit includes one or more first-level sub-functional units, wherein at least one first-level sub-unit in the first-level functional unit includes a transcoding module, a scrambling module, an alignment mark insertion module, a forward error correction FEC module and a PMA module; the second-level functional unit includes one or more second-level sub-units, wherein at least one second-level sub-unit in the second-level functional unit includes a PCS / FEC / PMA module and a PMD module.

[0011] In some embodiments, the data of the FEC outputs of the plurality of functional units two are interleaved at the PMA layer.

[0012] In some embodiments, the FEC module included in at least one first-level subunit in the first-level functional unit is used to perform Reed-Solomon RS (544, 514) FEC encoding and / or decoding, and the FEC module included in at least one second-level subunit in the second-level functional unit is used to perform BCH FEC encoding and / or decoding, Reed-Solomon forward error correction RSFEC encoding and / or decoding, polar FEC encoding and / or decoding, low-density parity check forward error correction LDPC FEC encoding and / or decoding, concatenated forward error correction cFEC encoding and / or decoding, open forward error correction OFEC encoding and / or decoding or turbo product code forward error correction TPC FEC encoding and / or decoding. Optionally, the FEC module included in the first-level subunit is an outband FEC module.

[0013] In some embodiments, the interface comprises an optical digital signal processor oDSP.

[0014] In some embodiments, the FEC module is a cascade FEC module, and the second-level functional unit further includes an inner code encoding module for performing cascade code inner code encoding on data entering the second-level functional unit. Optionally, the second-level functional unit further includes a decoding module for decoding the inner code of the cascade FEC code of the data entering the second-level functional unit.

[0015] In some embodiments, the functional part 1 includes a MAC module, a coordination sublayer RS ​​module, and a coding and rate adaptation module and a transcoding module in a physical coding sublayer PCS.

[0016] In some embodiments, the functional part two includes one or more functional units, the one or more functional units include a third functional unit, and the third functional unit includes an scrambling module, an alignment mark insertion module, a forward error correction FEC module and a physical medium access sublayer PMA / physical medium association PMD module.

[0017] In some embodiments, the functional part two includes one or more functional units, wherein the one or more functional units include a fourth functional unit, and the fourth functional unit includes a transcoding module, a scrambling module, an alignment mark insertion module, a forward error correction FEC module, a physical medium access sublayer PMA module, and a physical medium associated PMD module.

[0018] In some embodiments, the functional part 1 includes a MAC module, a coordination sublayer RS ​​module, and a coding and rate adaptation module, a transcoding module, and a scrambling module in a physical coding sublayer PCS.

[0019] In some embodiments, the functional part two includes one or more functional units, the one or more functional units include a fifth functional unit, and the fifth functional unit includes an alignment mark insertion module, a forward error correction FEC module, and a physical medium access sublayer PMA / physical medium association PMD module.

[0020] In some embodiments, the interface is an Ethernet interface with a rate of 800 Gb / s or 1.6 Tb / s.

[0021] In some embodiments, the transcoding module is a 64B / 66B to 256B / 257B transcoder compliant with IEEE 802.3-2018.

[0022] In some embodiments, the functional part two includes 1, 2, 3, 4, 5, 8 or 16 functional units.

[0023] In some embodiments, the functional part 2 is coupled to the functional part 1 via a data block distribution module.

[0024] On the other hand, an electronic device includes the interface described in any one of the above embodiments.

[0025] On the other hand, a communication system includes a sending side device and a receiving side device, and the sending side device and / or the receiving side device are the electronic devices mentioned above.

[0026] In some embodiments, an interface includes a general function unit and one or more special function units, wherein: the general function unit includes one or more general function modules; the special function unit includes one or more specific function modules.

[0027] In some embodiments, the interface is an Ethernet interface.

[0028] In some embodiments, the general functional unit includes a functional module closely related to a media access control MAC rate.

[0029] In some embodiments, the special function unit includes a rate-dependent functional part.

[0030] In some embodiments, the general purpose functional unit comprises a media independent interface.

[0031] In some embodiments, the general functional unit includes a medium access control MAC unit, a coordination sublayer RS ​​unit, and a coding and rate adaptation module in a PCS layer.

[0032] In some embodiments, the special function unit includes a transcoding unit, a scrambling unit, an alignment unit, a forward error correction FEC encoding / decoding unit, and a physical medium access sublayer PMA / physical medium association PMD unit.

[0033] In some embodiments, the special function unit includes multiple sub-function units and a PMA / PMD unit, each sub-function unit includes a transcoding sub-unit, a scrambling sub-unit, an alignment processing sub-unit and a FEC sub-unit, and the multiple sub-function units are coupled to the PMA / PMD unit.

[0034] In some embodiments, the special function unit includes a first level and a second level, the first level includes one or more first-level sub-units, each first-level sub-unit includes a transcoding sub-unit, a scrambling sub-unit, an alignment sub-unit, an FEC sub-unit and a PMA sub-unit; the second level includes one or more second-level sub-units, each second-level sub-unit includes a PCS / FEC / PMA sub-unit and a PMD sub-unit.

[0035] In some embodiments, data of FEC outputs of multiple special function units are interleaved at the PMA layer.

[0036] In some embodiments, the first level FEC is used to perform RS (544, 514) FEC encoding, and the second level FEC is used to perform BCH FEC encoding, polar FEC encoding, LDPC FEC encoding, CFEC encoding, OFEC encoding or TPC FEC encoding.

[0037] In some embodiments, the interface comprises an optical digital signal processor oDSP.

[0038] In some embodiments, the FEC is a cascaded FEC, and the second stage further includes an inner code decoding unit for decoding the cascaded code inner code of the data entering the second stage (the decoding is mainly an error correction function, and the overhead caused by the inner code encoding is removed after the decoding is completed).

[0039] In some embodiments, the PCS / FEC / PMA in the second stage is PCS / CFEC / OFEC / PMA.

[0040] In some embodiments, the general functional unit includes a coding and rate adaptation module in the MAC, RS, and PCS layers, and a transcoding module.

[0041] In some embodiments, the special function units include scrambling, AM, FEC and PMA / PMD.

[0042] In some embodiments, the special function unit includes a plurality of sub-function units, each of which includes a scrambling sub-unit, an alignment sub-unit, a FEC sub-unit, a PMA sub-unit and a PMD sub-unit.

[0043] In some embodiments, the general functional unit includes a MAC unit, an RS unit, a coding and rate adaptation module in a PCS layer, a transcoding module, and a scrambling module.

[0044] In some embodiments, the special function units include an alignment unit, a FEC unit, and a PMA / PMD unit.

[0045] In some embodiments, the FEC subunit is an 800Gb / s Ethernet interface.

[0046] In some embodiments, the transcoding complies with the 64B / 66B to 256B / 257B transcoder of IEEE 802.3-2018.

[0047] In some embodiments, the interface includes 1, 2, 4, 5, 8 or 16 special function units.

[0048] In some embodiments, the general function unit is coupled to the special function unit via a data block distribution module.

[0049] On the other hand, an electronic device includes the interface described in any one of the above embodiments.

[0050] On the other hand, a network system includes a sending side device and a receiving side device, and the sending side device and / or the receiving side device are the electronic devices mentioned above.

[0051] On the other hand, a computer-readable storage medium is characterized in that it includes a computer-readable program or instruction, which, when executed, enables a device to perform the function of the interface described in any one of the above embodiments.

[0052] On the other hand, a computer program product includes a computer-readable program or instructions, which, when executed, enables a device to perform the functions of the interface described in any one of the above embodiments.

[0053] On the other hand, a transmission method includes the functional steps of the interface described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a schematic diagram of interface composition and communication;

[0055] Figure 2A and Figure 2B It is another interface composition and communication diagram;

[0056] Figure 3 is a schematic diagram of an interface architecture of an embodiment;

[0057] Figure 4A is a schematic diagram of an interface architecture of another embodiment;

[0058] Figure 4B is a schematic diagram of an interface architecture of another embodiment;

[0059] Figure 4C Yes Figure 4A A schematic diagram of a communication system having an interface;

[0060] Figure 4D Yes Figure 4B A schematic diagram of a communication system having an interface;

[0061] Figure 4E Yes Figure 4A A schematic diagram of a communication system of a transmitting side device interface of IEEE 802.3 standard interface and a receiving side device of IEEE 802.3 standard interface;

[0062] Figure 4F Yes Figure 4B A schematic diagram of a communication system of a transmitting side device interface of IEEE 802.3 standard interface and a receiving side device of IEEE 802.3 standard interface;

[0063] Figure 5A is a schematic diagram of an interface architecture of yet another embodiment;

[0064] Figure 5B Yes Figure 5A A schematic diagram of a communication system having an interface;

[0065] Fig. 6A is a schematic diagram of an interface architecture of yet another embodiment;

[0066] Figure 6B Yes Fig. 6A A schematic diagram of a communication system having an interface;

[0067] Figure 6C is a schematic diagram of an interface architecture of yet another embodiment;

[0068] Fig.6D Yes Figure 6CA schematic diagram of a communication system having an interface;

[0069] Fig. 7A is a schematic diagram of an interface architecture of yet another embodiment;

[0070] Figure 7B Yes Fig. 7A A schematic diagram of a communication system having an interface;

[0071] Figure 8 is a schematic diagram of the interface architecture of the first embodiment;

[0072] Fig. 9 is a schematic diagram of the interface architecture of the second embodiment;

[0073] Fig.10 is a schematic diagram of the interface architecture of Embodiment 3;

[0074] Fig.11 is a schematic diagram of the interface architecture of Embodiment 4;

[0075] Fig. 12A is a schematic diagram of the interface architecture of Embodiment 5;

[0076] Fig. 12B It includes corresponding Figure 4A A schematic diagram of a communication system of a receiving side device interface of IEEE 802.3 standard interface and a sending side device of IEEE 802.3 standard interface;

[0077] Fig. 12C It includes corresponding Figure 4B A schematic diagram of another communication system of a receiving side device interface of IEEE 802.3 standard interface and a sending side device of IEEE 802.3 standard interface;

[0078] Fig.12D It includes corresponding Figure 5A A schematic diagram of another communication system of a receiving side device interface of IEEE 802.3 standard interface and a sending side device of IEEE 802.3 standard interface;

[0079] Fig.12E It includes corresponding Fig. 6A A schematic diagram of another communication system of a receiving side device interface of IEEE 802.3 standard interface and a sending side device of IEEE 802.3 standard interface;

[0080] Fig.12F It includes corresponding Figure 6C A schematic diagram of another communication system of a receiving side device interface of IEEE 802.3 standard interface and a sending side device of IEEE 802.3 standard interface;

[0081] Figure 12G It includes corresponding Fig. 7A A schematic diagram of another communication system of a receiving side device interface of IEEE 802.3 standard interface and a sending side device of IEEE 802.3 standard interface;

[0082] Fig.13 is a schematic diagram of the device structure of an embodiment;

[0083] Fig.14 The present invention is a schematic diagram of the device structure of an embodiment. DETAILED DESCRIPTION

[0084] In this embodiment, "functional part one" is also called "general functional part" or "general functional unit", "functional part two" is also called "special functional part", "functional unit two" is also called "special functional part", and multiple functional units in "functional part two" are also called "special functional units". For example, "functional part two" includes n functional units: the 1st functional unit, the 2nd functional unit...the nth functional unit, the ith functional unit is also called the ith special functional unit, i is a positive integer, n is a positive integer greater than 1, 1≤i≤n.

[0085] In this application, the media independent interface (full name in English: media independent interface) is called MII at 10Mb / s and 100Mb / s, GMII at 1000Mb / s, and XGMI at 10Gb / s. The xMII in the present application may include RMII (reduced MII), serial MII (serial MII, SMII), serial synchronous MII (serial sync MII, SSMII), source synchronous SMII (source synchronous SMII, S3MII), Gigabit MII (Gigabit MII, GMII), RGMII (Reduced GMII), serial GMII (serial GMII, SGMII), 10 bit interface (ten bit interface, TBI), RTBI (Reduced TBI), 10 Gigabit MII (10Gigabit MII, XGMII), 25 Gigabit MII (25GigabitMII), 40 Gigabit MII, 50 Gigabit MII, 100 Gigabit MII (100Gb / s MII, CGMII), 200 Gigabit MII (200Gb / s MII, 200GMII), 400 Gigabit MII (400Gb / s MII, 400GMII), 800 Gigabit MII, 1.6 Terabit MII and other Ethernet interfaces.

[0086] The 200GbE / 400GbE rate standard realizes a new generation of Ethernet rate standards based on the single-channel electrical interface 50G four-level pulse amplitude modulation (PAM4) technology. In the research of the next-generation Ethernet 800G / 1.6TE standard, as the single-channel electrical interface rate increases to 100G PAM4 or 200G (using N-level pulse amplitude modulation PAM-N, N = 4, 6 or 8), the next-generation rate may support the electrical interface rate and may need to be compatible with the old 50G electrical interface per channel. The optical interface rate has the possibility of multiple evolution routes such as 50Gbps / 100Gbps / 200Gbps / 400Gbps / 800Gbps per wavelength.

[0087] There are many Ethernet interface logic layer solutions at present. There are some common features and obvious differences between the interface logic layers of different rates. These differences make it difficult to share hardware resources between different rates, or to bind multiple low-rate Ethernet interfaces to a high-rate interface module for intercommunication. For example, on the 200GbE / 400GbE interface, Figure 1 The logical layer architecture. Figure 1 In the IEEE 802.11 protocol, the device interface includes the medium access control (MAC) layer, the coordination sublayer (RS), the physical coding sublayer (PCS), the forward error correction (FEC), the physical medium attachment sublayer (PMA), and the physical medium dependent (PMD) layer. The data of the sending side device is sent from the PMD to the PMD of the receiving side device after processing, and reaches the MAC layer after being processed by multiple submodules. The PCS sublayer is used to implement functions such as 64B / 66B encoding and decoding, transcoding, scrambling, alignment marker (AM) insertion, and FEC encoding and decoding; the PMA sublayer is used to implement functions such as clock recovery, carrier detection, and PAM4 modulation / demodulation; the PMD sublayer is used to perform parallel-to-serial / serial-to-parallel conversion on the received data and modulate the digital signal to the line for transmission. Among them, in the FEC sublayer of the PCS layer, the introduction of new interleaved FEC (such as Reed-Solomon RS (544,514) FEC) makes its logical layer very different from the 100GbE solution, and the workload of redevelopment is large. For example, the logical layer defined by 400G-ZR adopts Figure 2A and 2BIn this logical layer architecture, an optical module that supports 400G-ZR (80km) cannot support a 2x200GbE interface because the host-side interface is fixed at 400GAUI (attachment unit interface, AUI).

[0088] The inventors have found that the changes in the logical layer caused by the Ethernet rate crossing generations are mainly in the PCS function. Above PCS, the data output by RS has great similarity. If the similar part is distinguished from the dissimilar part, and the dissimilar part is modularized in a direction parallel to the data flow direction, greater resource reuse can be achieved, development costs can be saved, and economic advantages can be generated. According to the embodiments of the present application, the current Ethernet architecture is divided into two parts according to the functional parts related to a specific rate and the functional parts related to the sub-rate corresponding to a specific PMD: functional part one and functional part two. Reference Figure 3 Functional part one is a general functional part, and functional part one includes functional modules closely related to the MAC rate, such as an RS module, a module that needs to be rate adapted, etc.; in some embodiments, functional part one also includes an xMII interface that is directly related to the rate. Functional part two includes functional parts that are independent of the rate, such as functional part two includes one or more functional units: single function 1, functional unit 2, ... functional unit n. Functional part two may include PCS / PMA layer functions that are processed based on data streams. PMD is related to the medium and can be used as part of functional part two according to the specific implementation, or PMD can be considered to be independent of the protocol and PMD can be used as a functional component independent of functional part one and functional part two.

[0089] The reference standards for selecting the demarcation point of the two functional parts here may include one or more of the following: (1) select as low as possible so that after the rate crosses generations, there are as many common functional parts as possible to save costs; (2) simplify the design of data distribution between the two functional modules as much as possible so that the data block distribution has smaller units; (3) make the units in the second functional part have complete functionality as much as possible, including necessary verification functions to ensure reliability; (4) consider the difficulty of specific implementation and the control of chip resources, and make comprehensive considerations to achieve the optimal design. For (4), in some scenarios, such as ultra-high-speed connection scenarios, the traditional parallelized media-independent interface is not suitable as a connection function interface.

[0090] like Figure 4AAs shown, in one embodiment, the interface includes a functional part 1, a functional part 2, and a data block distribution module located between the functional part 1 and the functional part 2. The functional part 1 includes a MAC module, an RS module, and an encoding and rate matching module in the PCS layer. The functional part 2 includes one or more functional units, each of which includes a transcoding module, a scrambling module, an alignment mark insertion module, a FEC module, a PMA / PMD module, and other functional sub-modules.

[0091] For example, assuming that each functional unit in the functional part 2 can process a MAC data stream corresponding to a rate of 200Gbps, then for a MAC module with a rate of 800GbE (full name in English: 800Gigabit Ethernet), the functional part 2 may include 4 functional units, each of which can process a MAC data stream corresponding to a rate of 200Gbps; the 4 functional units may be integrated or separately arranged. For a MAC module with a rate of 1Tbps, the functional part 2 may include 5 functional units, each of which can process a MAC data stream corresponding to a rate of 200Gbps, and the 5 functional units may be integrated or separately arranged. For a MAC module with a rate of 1.6Tbps, the functional part 2 may include 8 functional units, each of which can process a MAC data stream corresponding to a rate of 200Gbps, and the 8 functional units may be integrated or separately arranged.

[0092] In some embodiments, each functional unit in the functional part two can process MAC data streams corresponding to other rates, such as 5 Gbps, 10 Gbps, 20 Gbps, 25 Gbps, 100 Gbps, 400 Gbps, 800 Gbps, 1 Tbps or 1.6 Tbps.

[0093] In some other embodiments, the functional part 2 includes M functional units, N functional units of the M functional units are in an activated state, and the N functional units are used to transmit data from the current MAC module, and the N functional units include a first functional unit and a second functional unit, and the rate of the corresponding MAC data flow that can be processed by the first functional unit is the same as or different from that of the second functional unit. For example, for a MAC module with a rate of 800GbE, the functional part 2 may include 8 functional units: a, b, c, d, e, f, g, h, wherein the functional units a, b, c, d are activated, and the rate of the corresponding MAC data flow that can be processed by each of the functional units a, b, c, d is 200Gbps; or the functional units d, e, f are in an activated state and the functional units a, b, c, d, g, h are in an unactivated state, and the rates of the corresponding MAC data flows that can be processed by the functional units d, e, f are 200Gbps, 200Gbps, and 400Gbps, respectively. Wherein M and N are positive integers and M≥N≥1.

[0094] From top to bottom, the data after encoding (such as 64B / 66B or 256B / 257B encoding) and rate adaptation is the first suitable demarcation point, because the data distributed here is in data blocks, and the data blocks have their own synchronization headers (syncheader), unlike the xMII interface, which is synchronized by data plus clock transmission; in addition, the transmission rate of the data block after rate adaptation is a fixed value, which can be distributed regularly. After polling distribution, it can ensure that the processing rate of each activated functional unit in the functional part 2 is consistent, so there is no need to perform any rate adaptation work in the functional part 2. It should be noted that rate adaptation in the Ethernet interface requires the identification of the data stream format, the need to find the message boundary, and add or delete idle code blocks in the MAC frame gap (IFG, inter frame gap, also known as IPG-inter packet gap) to adjust the rate. Moving the rate adaptation function to the functional part 1 distinguishes the part related to the MAC rate from the part that is not related to the MAC rate but only related to the medium rate.

[0095] Figure 4A Since PMA / PMD does not identify any protocol or data format, PMA / PMD can exist across functional parts. Figure 4BAs shown. For example, the functional units in the functional part 2 that are in an activated state and are used to process the data stream from the current MAC module, such as N functional units among the M functional units, share a PMA / PMD module. In some embodiments, it is also possible that some of the N functional units share the first PMA / PMD module and some share the second PMA / PMD module; or some of the N functional units share the first PMA / PMD module, and each of the other functional units uses a separate shared first PMA / PMD module.

[0096] In some embodiments, Figure 4A or Figure 4B The functional part one and the functional part two can be integrated into the same chip.

[0097] Take the interface of the sending side device as Figure 4B For example, refer to Figure 4D , the communication system includes a sending side device and a receiving side device.

[0098] The message received by the sending side device interface enters the functional part 1 of the sending side device interface.

[0099] In this embodiment, the functional part 1 of the transmission side device interface includes a MAC module, an RS module and an encoding and rate matching module. The message enters the data block distribution module after being processed by the MAC module, the RS module and the encoding and rate matching module. Specifically, the data frame obtained after the MAC module is processed is converted by the RS module into data of corresponding bit width (the width changes with the rate), and sent to the encoding and rate matching module for processing through the medium independent interface MII. The encoding and rate matching module generates a 64B / 66B block after processing the data sent from the MII.

[0100] In one embodiment, the input data of the PCS layer with a transmission rate of 100G is parallel data in the 100G Ethernet medium independent interface (CGMII) format of the coordination sublayer RS. The 400G Ethernet (400GbE in English) interface converts the input data into the corresponding CDGMII format. The specific data format of the CDGMII interface is described as follows: The digital bit width of the CDGMII interface is (64+8+2). The format of the CDGMII interface is 64-bit data information bits plus 8-bit control information indication bits, and two clocks corresponding to sending and receiving, where the 8-bit control information bit indicates whether the 64-bit 8 bytes of data represent data or control information. The CDGMII data format is transmitted to the 64B / 66B encoding module for encoding.

[0101] After receiving the data blocks processed by the coding and rate matching module, the data block distribution module of the sending side device distributes the data blocks to N functional units in the functional part 2 of the sending side device.

[0102] In this embodiment, each of the N functional units includes one or more PCS lanes. In some embodiments, each of one or more of the N functional units includes one or more PCS lanes.

[0103] In this embodiment, the data block distribution module distributes the 64B / 66B blocks generated after processing by the coding and rate matching module to the N functional units. In some embodiments, the data block distribution module distributes the 64B / 66B blocks to the N functional units one by one in a round robin manner, for example, the data block distribution module distributes the first received 64B / 66B block to the first of the N functional units, distributes the second received 64B / 66B block to the second of the N functional units, ..., distributes the Nth received 64B / 66B block to the Nth of the N special functional units.

[0104] In this embodiment, each of the N functional units includes a transcoding module, a scrambling module, an AM module, an FEC encoding module, and a PMA / PMD module. The transcoding module, the scrambling module, the AM module, and the FEC encoding module in each functional unit respectively perform corresponding processing on the data blocks entering the functional unit. For example, the i-th functional unit among the N functional units sequentially performs transcoding, scrambling, AM insertion, and FEC encoding processing on the data received from the data distribution module, and the processed data is sent to the receiving side device via the PMA / PMD and the medium (for example, the backplane or the optical fiber). For example, the block after the data stream is 64B / 66B encoded is transcoded, and the specific formats of the data transcoded by the transcoding module are 256B / 257B, 512B / 513B, 256B / 258B, 512B / 514B, etc. This application does not limit the specific transcoding method.

[0105] Specifically, the scrambling module scrambles the data stream after transcoding. In some embodiments, the scrambling can be performed in whole or in part according to a certain granularity. A unified overall data stream can be used for self-synchronizing scrambling (also known as multiplicative scramble), or synchronous scrambling (also known as additive scramble) corresponding to the FEC granularity, or self-synchronizing or synchronous scrambling with the PCS channel (English name lane) as the granularity, and in the case of synchronous scrambling, the initialization values ​​of the scrambling and descrambling modules can be configured to ensure the performance of the entire system.

[0106] After the alignment mark insertion module inserts the alignment mark AM into the scrambled data stream, the data enters the FEC encoding module for FEC encoding. In some embodiments, the FEC module processes the received data stream, which can be based on one or more encoding methods of Reed Solomon RS (544, 514) FEC, Bose-Chaudhuri-Hocquenghem (English: Bose-Chaudhuri-Hocquenghem, referred to as: BCH) FEC, polar FEC, LDPC FEC, CFEC FEC, OFEC FEC, or TPC FEC. The data processed by the FEC encoding module arrives at the transmission medium via the PMA module and the PMD module in turn. The PMA module and the PMD module can be integrated in a functional module or set independently. The PMA module can convert the received data into serial and parallel and send it to the PMD module, and the PMD module converts the received signal to the corresponding transmission medium.

[0107] like Figure 4D In one embodiment, the architecture of the receiving device interface is similar to Figure 4A The interface structure shown in FIG. 1 corresponds to the interface structure shown in FIG. 1 , and the N-channel data processed by the functional part 2 of the sending side device enters the functional part 2 of the receiving side device interface through the medium, and the N functional units of the functional part 2 of the receiving side device interface correspond to the N functional units of the functional part 2 of the sending side device interface one by one. The N functional units of the functional part 2 of the receiving side device interface respectively receive the data sent by the N functional units of the functional part 2. Each of the N functional units of the functional part 2 includes a reverse transcoding module, a descrambling module, an alignment mark removal (AM removal) module, a FEC decoding module, and an alignment (Alignment lock) module. For example, the i-th functional unit of the N functional units sequentially performs alignment mark alignment, FEC decoding, alignment mark removal, descrambling, and reverse transcoding on the data received from the PMA / PMD module, and the processed N-channel data enters the data block distribution module of the receiving side device interface. The data block distribution module of the receiving side device interface sends the N-channel data to the functional part 1 of the receiving side device interface. The functional part 1 of the receiving side device interface includes a MAC module, an RS module, and a decoding and rate matching module. The decoding and rate matching module of the receiving side device interface decodes the N-channel data distributed by the data block distribution module, performs rate matching, and then sends it to the RS module, which arrives at the MAC module of the receiving side device interface after processing. Optionally, the decoding and rate matching module of the receiving side device interface performs rate matching on the N-channel data and then arrives at the RS module of the receiving side device interface via xMII.

[0108] refer to Figure 4CThe communication system includes a sending side device and a receiving side device. The architecture of the sending side device interface is as follows: Figure 4A , the architecture of the receiving device interface corresponds to Figure 4A The interface architecture of the sending side device interface processes the data and sends it to the receiving side device interface, and the receiving side device interface processes the received data. Figure 4D The sending side device interface and the receiving side device interface in the communication system are similar and will not be described in detail here.

[0109] refer to Figure 4E A communication system includes a sending side device and a receiving side device, wherein the sending side device includes Figure 4A The interface shown in the figure is a standard Ethernet interface of IEEE 802.3. The processing process of the sending device interface to send data is the same as that of the receiving device. Figure 4C The operation of the sending side device interface in is similar and will not be repeated here. After the sending side device interface processes the data, the N-channel data processed by the functional part 2 of the sending side device enters the receiving side device interface through the medium. The receiving side device interface is an Ethernet interface of IEEE 802.3, including a MAC module, an RS module, a decoding and rate matching module, a data block distribution module, a reverse transcoding module, a descrambling module, an alignment mark deletion module, an FEC decoding module and a PMA / PMD module. After the receiving side device interface receives the data stream sent by the sending side device through the medium, it is processed by PMD / PMA, alignment mark alignment, FEC decoding, alignment mark deletion, descrambling, and reverse transcoding in sequence before arriving at the data block distribution module. The data block distribution module processes the received data stream and then processes it in sequence through decoding and rate matching, RS processing before arriving at the MAC module, and the MAC module generates an Ethernet frame after processing.

[0110] refer to Figure 4F A communication system includes a sending side device and a receiving side device, wherein the sending side device includes Figure 4B The interface shown in the figure is a standard Ethernet interface of IEEE 802.3. The processing process of the sending side device interface to send data is the same as Figure 4D The operation of the sending device interface in is similar to that in the example above, so I will not repeat it here. The receiving device processes the received data in the same way as Figure 4E The processing process of the receiving side device interface in is similar and will not be repeated here.

[0111] like Figure 5AAs shown, in one embodiment, the Ethernet interface includes a functional part 1, a functional part 2 and a data block distribution module located between the functional part 1 and the functional part 2, the functional part 1 includes a MAC module, a Reconciliation module and an Encode and Rate Matching module, and the functional part 2 includes multiple functional units, for example, each functional unit includes multiple PCS functions. A Data block distribution module is included between the functional part 1 and the functional part 2. The Data block distribution module accesses the multiple functional units of the functional part 2. The multiple functional units of the functional part 2 are output via PMA / PMD. In some embodiments, the multiple functional units of the functional part 2 can access a common PMA / PMD.

[0112] refer to Figure 5B A communication system includes a sending side device and a receiving side device, wherein the sending side device includes Figure 5A The receiving device includes the corresponding Figure 5A The interface shown is the interface. Figure 5A The processing methods of each module in the functional part of the interface shown are similar to Figure 4A The functional part in is similar and will not be repeated here. Figure 5A The functional part 2 includes m PCS functions, where m is an integer greater than or equal to 1. Each PCS function includes a transcoding module, a scrambling module, an alignment mark insertion module, and a FEC encoding module. The processing methods of these modules are the same as Figure 4A The data block distribution module distributes the data blocks from the Encode and Rate Matching module to m PCS functions. After the m PCS functions perform the corresponding processing, they send the data of the m PCS functions to a PMA module. The data processed by the PMA module is distributed to one or more PMD modules, and then sent to the transmission medium after being processed by the PMD module. Figure 5AIn the scheme, only the transcoding module, scrambling module, alignment mark insertion module and FEC encoding module are separately set in the functional part 2, and a single PMA module is used to process the data output by the m PCS functions, so that the data can be processed more flexibly. The m-channel data processed by the functional part 2 of the sending side device enters the functional part 2 of the receiving side device through the medium. The functional part 2 of the receiving side device includes m PCS functions and PMA and PMD shared by the m PCS functions. The m-channel data processed by the functional part 2 of the sending side device enters the functional part 2 through the medium, and enters the m PCS functions of the receiving side device respectively after being processed by the PMD and PMA of the receiving side device. The m PCS functions of the functional part 2 of the receiving side device correspond one-to-one to the m-channel functional units of the functional part 2 of the sending side device, and each functional unit includes a reverse transcoding module, a descrambling module, an alignment mark deletion module, an FEC decoding module, and an alignment (alignment lock) module. The m PCS functions of the functional part 2 of the receiving side device respectively receive the data sent by the m PCS functions of the functional part 2 of the sending side device. For example, the i-th PCS function among the m PCS functions performs PCS processing on the data received from the PMA. The data output by the m PCS functions of the functional part 2 of the receiving side device is processed by the Datablock distribution module and then enters the functional part 1 of the receiving side device. The functional part 1 of the receiving side device sequentially performs decoding and rate matching, Reconciliation, and MAC module processing on the data from the Data block distribution module to obtain an Ethernet frame.

[0113] In some embodiments, Fig. 6A and 6B As shown, the data distribution position in the interface can be different. The data obtained after transcoding is used as the data distribution point, and the data is distributed according to the granularity after transcoding (for example, 257-bit). Functional part 2 processes according to the 257-bit data stream. Fig. 6AIn the embodiment, the interface includes a functional part 1, a functional part 2, and a data block distribution module located between the functional part 1 and the functional part 2. The functional part 1 includes a MAC module, an RS module, an encoding and rate matching module in a PCS layer, and a transcoding module. The functional part 2 includes a plurality of functional units, each of which includes a scrambling module, an alignment mark insertion module, a FEC encoding module, and a PMA / PMD module. The functional part 1 is coupled and communicated with the functional part 2 via the data block distribution module. Fig. 6A The Ethernet interface structure can be used for sending side devices. Fig. 6A The functions and features of the various functional modules in the MAC module, RS module, coding and rate matching module, transcoding module, data block distribution module, scrambling module, FEC module, PMA module, and PMD module Figure 4A The functions of the corresponding modules in are similar and will not be repeated here. Fig. 6A In the embodiment, the functional part 1 includes a MAC module, an RS module and a transcoding module. For the sending side device, after the sending side device receives the message, the message enters the functional part 1 of the sending side device, and the MAC module of the functional part 1 processes it to form a data frame, and the data frame is converted into data of corresponding bit width by the RS module, and then sent to the coding and rate matching module, and the coding and rate matching module processes the received data to generate a 64B / 66B block. The 64B / 66B block is forwarded to the transcoding module, and the transcoding module transcodes the received data block, for example, the block after the data stream is 64B / 66B encoded is transcoded, and the specific format of the data transcoded by the transcoding module includes 256B / 257B, 512B / 513B, 256B / 258B, 512B / 514B, etc. This application does not limit the specific transcoding method.

[0114] The data block distribution module distributes the transcoded data stream to the m functional units included in the functional part 2, each of which includes a scrambling module, an alignment mark insertion module, an FEC encoding module, a PMA module and a PMD module. The functions and operations of the scrambling module, the alignment mark insertion module, the FEC encoding module, the PMA module and the PMD module are the same as those of Figure 4A The functions of the corresponding functional modules are similar and will not be described here. The data block distribution module distributes the transcoded data stream to the m functional units included in the functional part 2, specifically including: the data block distribution module distributes the transcoded data stream to the m functional units included in the functional part 2 in a round-robin mode.

[0115] In some embodiments, Fig. 6A In the functional part 2, each of the m functional units includes a scrambling module, an alignment module and an FEC encoding module. The FEC encoding module in the m functional units sends the data processed by FEC to one or more PMA modules, which are processed by the one or more PMA modules and sent to one or more PMD modules for processing. The one or more PMD modules send the processed data to the receiving side device via a transmission medium.

[0116] like Figure 6B A communication system includes a sending side device and a receiving side device, wherein the sending side device includes Fig. 6A The receiving device includes an interface Fig. 6A The interface corresponding to the interface shown. The receiving side device interface includes a functional part one, a functional part two, and a data block distribution module located between the functional part one and the functional part two. The functional part one includes a MAC module, an RS module, a decoding and rate matching module in the PCS layer, and a transcoding module. The functional part two includes multiple functional units, each of which includes a descrambling module, an alignment mark removal module, an FEC decoding module, an alignment lock module, and a PMA / PMD module. The functional part one is coupled and communicated with the functional part two via the data block distribution module. Figure 6B The functions and features of the various functional modules of the receiving side device interface in the MAC module, RS module, decoding and rate matching module, reverse transcoding module, data block distribution module, descrambling module, alignment mark removal (AM Removal) module, FEC decoding module, alignment (alignment lock) module, PMA module, and PMD module Figure 4C The functions of the corresponding modules in are similar and will not be repeated here.

[0117] In some embodiments, Fig. 6A The functional part one and the functional part two can be integrated into the same chip.

[0118] refer to Figure 6CIn another interface structure, data can be distributed with scramble as the boundary, and the data can have multiple distribution granularities, such as 1-bit, 10-bit, etc. The interface includes a functional part one, a functional part two, and a data block distribution module located between the functional part one and the functional part two. The functional part one is coupled and communicates with the functional part two via the data block distribution. The functional part one includes a MAC module, an RS module, an encoding and rate matching module in the PCS layer, a transcoding module, and a scrambling module. The functional part two includes an AM insertion module, an FEC encoding module, and a PMA / PMD module. The functional part two includes m-way functional units, each of which includes an alignment mark insertion module, an FEC module, and a PMA / PMD module.

[0119] like Fig.6D A communication system includes a sending side device and a receiving side device, wherein the sending side device includes Figure 6C The receiving device includes an interface Figure 6C The interface corresponding to the interface shown. The receiving side device interface includes a functional part one, a functional part two, and a data block distribution module located between the functional part one and the functional part two. The functional part one includes a MAC module, an RS module, a decoding and rate matching module in the PCS layer, a reverse transcoding module, and a descrambling module. The functional part two includes multiple functional units, each of which includes an alignment mark removal (AM Removal) module, a FEC decoding module, an alignment (alignment lock) module, and a PMA / PMD module. The functional part one is coupled and communicated with the functional part two via the data block distribution module. Fig.6D The functions and features of the various functional modules of the receiving side device, including MAC module, RS module, decoding and rate matching module, reverse transcoding module, data block distribution module, descrambling module, alignment mark removal (AM Removal) module, FEC decoding module, alignment module, PMA module, and PMD module Figure 4CThe functions of the corresponding modules in are similar and will not be repeated here. In the sending side device, the MAC module processes the received message to obtain a data frame and forwards the data frame to the RS module. The RS module converts the received data frame into data of corresponding bit width and sends the converted data to the coding and rate matching module. The coding and rate matching module generates a 64B / 66B block after processing the data. The transcoding module receives the data block processed by the coding and rate matching module and transcodes the data block. The specific format of the data transcoded by the transcoding module includes 256B / 257B, 512B / 513B, 256B / 258B, 512B / 514B and other transcoding methods. This application does not limit the specific transcoding method. The data stream after transcoding processing by the transcoding module is scrambled at the scrambling module and then sent to the data block distribution module. The data block distribution module distributes the received data stream to the m-way functional units of the functional part 2 of the sending side device, where m is an integer greater than or equal to 1. The alignment mark insertion (AM Insertion) module of each of the m-way functional units adds the alignment mark AM to the received data stream and sends it to the FEC encoding module. The FEC encoding module performs FEC encoding on the received data stream and sends it to the PMA module. The data stream passes through the PMA module and the PMD module and is sent to the transmission medium. The alignment mark insertion module in the sending side device processes the data stream by inserting the alignment mark, which is called AM insertion. The data block distribution module distributes the received data stream to the m-way functional units of the functional part 2 of the sending side device, specifically including: the data block distribution module performs round-robin distribution on the scrambled data stream according to a certain granularity (such as 1-bit, 2-bit, 8-bit, 10-bit, etc.), and distributes the received data stream to the m-way functional units of the functional part 2 of the sending side device.

[0120] The receiving device receives the data via the transmission medium. Figure 6CThe data stream sent by the sending side device of the interface shown. The m-channel data sent by the sending side device enter the m-channel functional units of the functional part 2 of the receiving side device respectively. For each of the m-channel functional units of the receiving side device, the PMD module converts the received data that conforms to the transmission format of the transmission medium into data that conforms to the format of the receiving side device, and sends the data to the PMA module. The PMA module performs parallel-to-serial conversion on the received data and sends it to the alignment (alignment lock) module. The aligned data enters the FEC decoding module. After the FEC decoding module performs FEC decoding on the data, it deletes the alignment flag and then sends it to the data block distribution module. The data block distribution module sends the received m-channel data to the descrambling module of the functional part 1 of the interface of the receiving side device. The descrambling module performs descrambling processing on the received data and then sends it to the transcoding module. The transcoding module performs reverse transcoding processing on the received data, such as transcoding data in formats such as 256B / 257B, 512B / 513B, 256B / 258B, 512B / 514B into 64B / 66B code blocks. The reverse transcoding module sends the generated 64B / 66B code blocks to the decoding and rate matching module. The decoding and rate matching module processes the 64B / 66B blocks to obtain data of corresponding bit widths, and sends the data of corresponding bit widths to the RS module. The RS module processes the data of corresponding bit widths to obtain data frames, and sends the data frames to the MAC module for processing. The MAC module processes the data frames to obtain the message sent by the sending side device. The process of removing the alignment mark in the received data stream by the alignment mark removal (AM Removal) module of the receiving side device is also called AM removal, the processing of the data of corresponding bit width by the RS module of the receiving side device is called Reconciliation, and the process of FEC decoding of the data stream by the FEC decoding module of the receiving side device is called FECdecode.

[0121] In some embodiments, the sending side device includes Fig. 6AOr the interface shown in 6C, the receiving side device includes a standard interface of IEEE802.3. The m-channel data processed by the sending side device enters the receiving side device through the medium. The PMA of the interface of the receiving side device converts the received m-channel data into data, and the data is sent to the alignment mark deletion module after the serial-to-parallel / parallel-to-serial conversion of the PMA module. The aligned data enters the FEC decoding module, and the FEC decoding module performs FEC decoding on the received data and sends it to the descramble module. The descramble module descrambles the received data and sends it to the transcoding module. The transcoding module transcodes the received data. The specific formats of the data transcoded by the transcoding module are 256B / 257B, 512B / 513B, 256B / 258B, 512B / 514B, etc. This application does not limit the specific transcoding method. The reverse transcoded blocks are processed by the data block distribution module, the decoding and rate matching module, and the RS module in turn and arrive at the MAC module. In some embodiments, the RS module and the decoding and rate matching module are connected via MII.

[0122] In some embodiments, Figures 6A to 6D In the m-way functional units of the functional part 2, each functional unit may not include a PMA module and a PMD module, and the m-way functional units share one PMA module and one PMD module.

[0123] In some embodiments, the functional part 2 of the interface of each embodiment of the present application may be extended to include two or even multiple levels of functional parts 2, for example Fig. 7A The transmission distance is increased by implementing FEC cascading through the two-level functional part 2. Functional part 1 includes the encoding and rate matching functional units in the MAC, RS, and PCS layers. Functional part 2 includes two levels. The first level includes multiple first-level functional units, and each first-level functional unit includes a transcoding module, a scrambling module, an alignment mark insertion module, an FEC encoding module, and a PMA module. The second level includes multiple second-level functional units, and the second-level functional units correspond one-to-one to the first-level functional units. The second-level functional units include PCS / FEC / PMA modules and PMD modules. Functional part 1 is coupled and communicated with functional part 2 via the data block distribution module.

[0124] Fig. 7AThe interface shown includes a functional part 1, a functional part 2 and a data block distribution module. The functional part 2 includes m first-level functional units and m second-level functional units, and the m second-level functional units correspond to the m first-level functional units one by one. The functional part 1 includes a MAC module, an RS module and a coding and rate matching module. Each first-level functional unit includes a transcoding module, a scrambling module, an alignment module, an FEC coding module and a PMA module, and each second-level functional unit includes a PCS module, an FEC module, and a PMA / PMD module.

[0125] like Figure 7B As shown, a communication system includes a sending side device and a receiving side device, and the sending side device includes Fig. 7A The receiving device includes the corresponding Fig. 7AThe interface of the interface. In the sending side device, the MAC module processes the received message stream to obtain a data frame, and forwards the data frame to the RS module. The RS module converts the received data frame into data of corresponding bit width, and sends the converted data to the coding and rate matching module. The coding and rate matching module generates data blocks after processing the data, such as 64B / 66B blocks, and sends the data blocks to the data block distribution module. The data block distribution module receives the data blocks processed by the coding and rate matching module, and distributes the data blocks to the m-way first-level functional units of the functional part two of the sending side device, where m is a positive integer greater than or equal to 1. The method by which the data block distribution module distributes the data blocks to the m-way first-level functional units of the functional part two, and the functions of each module in each first-level functional unit, are similar to those in the aforementioned embodiment and will not be repeated here. The m-way data processed by the sending side device enters the receiving side device through the medium. The second-level functional unit, the first-level functional unit, the data block distribution module, the decoding and rate matching module, the RS module, and the MAC module of the interface of the receiving side device process the received m-channel data in sequence to obtain an Ethernet frame. Specifically, the m-channel data processed by the sending side device arrives at the m-channel second-level functional units corresponding to the interface of the sending side device in the second-level functional unit through the medium, and the PMD module and the PCS / FEC / PMA module in each channel of the functional unit convert the received data into data, which enters each channel of the first-level functional unit corresponding to the first-level functional unit in the first-level functional unit, and the PMA module in each channel of the first-level functional unit performs serial-to-parallel / parallel-to-serial conversion on the received data and sends it to the FEC decoding module, and the FEC decoding module performs FEC decoding on the received data, and the FEC-decoded data is processed by the alignment mark removal (AM removal) module, the descramble module, and the transcoding module in sequence and arrives at the data block distribution module. Among them, the alignment mark deletion module deletes the alignment mark in the data, the descramble module descrambles the data with the alignment mark removed, and the descrambled data reaches the reverse transcoding module, and the reverse transcoding module performs reverse transcoding processing on the received data. The specific formats of the data transcoded by the transcoding module are 256B / 257B, 512B / 513B, 256B / 258B, 512B / 514B, etc. This application does not limit the specific transcoding method. The transcoded blocks are processed by the data block distribution module, the decoding and rate matching module, and the RS module in turn and arrive at the MAC module. In some embodiments, the RS module is connected to the decoding and rate matching module through MII.

[0126] exist Figure 3- In Figure 7, in each group of functional units in the functional part 2, each block diagram only represents the function, and does not represent the number of circuits and modules that perform the function. For example, the FEC function may include multiple FEC encoders / decoders, and the FEC-encoded data is not necessarily output in a single channel, but is output through multiple virtual channels (or PCS lanes).

[0127] The technical solution of the embodiment of the present application is described in detail below based on a specific MAC rate.

[0128] Embodiment 1: Functional part 2 includes a set of functional units, supporting 800Gb / s MAC rate

[0129] Figure 8 The figure is a possible schematic diagram of the 800GE interface structure. The interface includes a functional part one, a functional part two, and a data block distribution module located between the functional part one and the functional part two. The functional part one includes a MAC module, an RS module, an Encode and Rate Matching module, and the functional part two includes a transcoding module, a scrambling module, an alignment module, an FEC encoding module, a PMA module, and a PMD module. The FEC encoding module is used to implement FEC encoding of the data stream. The output is a 66-bit data block encoded in 64B / 66B. These data blocks will enter the functional part two through the data block distribution in the original order, and gradually perform the various processing steps in the functional part two. The functional part two includes one or more groups of functional units, each group of functional units includes a transcoding module, a scrambling module, an AM insertion module, an 800G FEC module, a PMA module, and a PMD module. The transcoder here can be the same 64B / 66B to 256B / 257B transcoder as in IEEE 802.3-2018, AM insertion can be similar to the AM insertion method of 200GE / 400GE interface, FEC coding can use Reed-Solomon RS-FEC for multi-code block coding and interleaving, and the encoded data is distributed to multiple PCS lanes according to the FEC symbol (10-bit symbol) interleaving, and then adapted to multiple PMDs through the PMA layer bit mux.

[0130] In some embodiments, the functional part 2 may include multiple functional units, each of which includes a transcoding module, a scrambling module, an alignment mark insertion module, an FEC encoding module, a PMA module and a PMD module. The specific implementation method can refer to the above embodiments. Figure 8 The interface shown can be used for a sending-side device, and its method for processing data can refer to the aforementioned embodiment.

[0131] Embodiment 2: Functional part 2 includes two groups of functional units, using the technology of embodiment 1 to implement 1.6TbE interface

[0132] exist Figure 8 Based on the interface architecture shown, Fig. 9 As shown, support for 1.6Tb / s Ethernet MAC can be achieved by implementing two groups of functional units in functional part two. The MAC, RS, Encode and Rate Matching modules are located in functional part one, and their functions are similar to those of embodiment one, except that the rate is doubled. The data block distribution module polls and distributes the encoded 66-bit data blocks to the two groups of functional units in functional part two, so the operating rate and operating mode of each group of functional units are the same as those in embodiment one. Among them, the PMA layer can perform simple bit level operations across functional units and bitmux the two parts of data to facilitate support for multiple PMDs.

[0133] Example 3: FEC cascade is realized by two-stage cascading of functional parts

[0134] Fig.10In the example, the functional part 1 includes MAC, RS, Encode and Rate Matching functions, and the output is a 66-bit data block encoded in 64B / 66B. These data blocks will enter the functional part 2 through data block distribution in the original order, and gradually perform various processing steps in the functional part 2. The functional part 2 includes the first level and the second level, and the functional units in the two levels are different. For example, the first level in the "functional part 2" includes multiple groups of functional units, each group of functional units includes transcoding, scrambling, alignment mark insertion, FEC encoding, PMA and other functional sub-modules. The data processed by the first level enters the second level. "Functional part 2 cascade" means that in the second level, the second level FEC encoding operation can be performed on the output data stream of the previous level. The second level includes functional units corresponding to the first level one by one, and each functional unit includes PCS / FEC / PMA, PMD. The role of the two-level functional part 2 is to process the data transmitted by its previous level, without the need to perceive the protocol of the MAC data in the functional part 1. A typical scenario of this embodiment may be a scenario where the host ASIC is externally connected to an optical digital signal processor (oDSP). Among them, the second-level functional part 2 may not terminate the FEC of the previous level, but directly perform the encoding of the second-level FEC. For example, the first-level FEC is RS (544, 514) FEC encoding, and the second level may be BCH encoding (Bose–Chaudhuri–Hocquenghem codes) FEC, polar FEC, low density parity check (low density parity check, LDPC) FEC, concatenated FEC (concatenated FEC, cFEC), open FEC (Open FEC, OFEC), Turbo product code (TPC) FEC, source coding FEC (source coding FEC, SCFEC) and the like. One or more.

[0135] Example 4: FEC cascade is realized by two-stage cascading of functional parts

[0136] like Fig.11 As shown, similar to the third embodiment, in some scenarios, stronger FEC protection may be required between the two functional parts, such as Fig.11As shown, the upper layer functional part 2 already includes cascade FEC, using RS+BCH cascade, and in the cascade functional part 2, due to data overhead restrictions and SerDes rate restrictions, it may be necessary to remove the inner code of the cascade FEC before handing it over to the stronger FEC frame encapsulation in the oDSP. At this time, the cascade functional part 2 does not need to operate on the data stream corresponding to the MAC rate of the functional part 1, but only processes the data stream corresponding to the rate of one functional unit in the upper layer functional part 2.

[0137] According to the technical solution of the present application, through the multi-channel parallel operation of the functional part 2, one functional unit can be copied into multiple channels and spliced ​​at any rate, thereby finally reusing the functional unit investment and greatly reducing the Ethernet interface cost.

[0138] In some embodiments, the Ethernet interface is divided into two layers of functional parts from a logical layer architecture: functional part one that processes based on the total data transmission rate of a specific interface rate, and functional part two that processes based on a subset of the specific interface rate (part of the total data transmission rate). Functional part two includes at least one functional unit. In some embodiments, functional part two includes two or more functional units.

[0139] In some embodiments, the functional part 1 completes data processing based on the specific data transmission rate, including the MAC and RS sublayers of the current Ethernet standard, and the 64 / 66B Encode / Decode sublayer subordinate to the PCS sublayer. The functional part 1 may further include transcoding, scrambling and descrambling, or the complete specific full-bandwidth PCS / FEC / PMA sublayer based on different embodiments.

[0140] In some embodiments, functional part one distributes data in a rotation according to a set rule or order using the functional units subordinate to functional part two, and the data is distributed as data blocks in a message format that does not reflect the specific interface rate. The data block granularity can be bit, 64 / 66B, transcoded 256 / 257B, and other different transcoded data formats, FECSymbol, etc., or a combination of these.

[0141] In some embodiments, each functional unit of the functional part 2 performs PCS / FEC / PMA layer processing required for further data transmission on the data block from the functional part 1, but these processes no longer need to understand the panoramic information of the specific interface rate of the functional part 1. In layman's terms, each functional unit only considers the information of the data received by itself to re-interleave and combine to form a data block and performs further PCS / FEC / PMA layer processing based on this. This combination process does not require the perception of the total data transmission rate of the functional part 1 to reflect the content information for processing, and no longer needs to recover or perceive the specific information of the Ethernet data frame of the functional part 1 (such as Idle, Preamble / SFD, etc.) before it can be performed. Further, different functional units can optionally only re-combine or interleave bit-level data at the PMA level, and there is no need to interact between multiple functional units based on the perception of multi-bit combined information.

[0142] In some embodiments, each functional unit in functional part two works independently, and there is no need to restore part or all of the functions of functional part one for the specific interface rate. For example, functional part two no longer performs unified addition, deletion and adjustment of Idle in functional part one, or no longer performs AM identification in functional part one or restores the corresponding data after re-alignment.

[0143] In some embodiments, each functional unit of functional part two corresponds to the PMD physical layer of its own functional unit, so that theoretically any number of multiple functional units can be combined to form a physical layer solution that matches the requirements of the specific rate Ethernet interface, thereby realizing a rate-independent Ethernet architecture.

[0144] In some embodiments, the interface of the embodiments of the present application is an independent chip or a functional module deployed on other devices.

[0145] In some embodiments, the interface of the embodiments of the present application is located on a network device or a workstation or a storage device or a server.

[0146] In some embodiments, a workstation may be a host, a terminal, a server, a virtual machine, or other types of devices. A network device may be a switch, a router, or other devices used to forward messages in a communication network, and network devices in the same communication network may be the same network devices or different network devices. For example, all network devices in the same communication network are routers, or some network devices are routers and other network devices are switches.

[0147] For this application Figures 1 to 11In non-breakout scenarios, the alignment marker insertion process needs to be coordinated between multiple functional units (for example, inserted according to bit spacing or code block spacing). Only in this way can the receiving side perform data block recovery operations according to the distribution order of the distribution unit on the sending side.

[0148] Example 5 Breakout scenario

[0149] The breakout scenario is to separate a large-capacity port through a physical channel to support multiple relatively low-speed ports or interfaces. For example, a switch supports a 400GbE port for breakout, and can support 4 100GbE ports, or 8 50GbE ports, etc. through a breakout cable or a fanout cable or a module. In this application, since functional part 2 naturally supports multi-channel parallelism, it has an inherent advantage in supporting breakout scenarios. For example, if functional part 1 already has a 1.6TbE MAC, and functional part 2 has 8 functional units, each supporting 200Gb / s data processing capability, the architecture can achieve a 2x800GbE breakout with very little modification, such as Fig. 12A At this time, the functional part 1 is divided into two 800GbE functional units from a 1.6TbE functional unit, each unit is a standard 800GbEMAC; the 8 functional units of the functional part 2 remain unchanged, and only the final data aggregation method is modified from the original one output to two outputs, each of which is a standard 800GbE physical port.

[0150] In the breakout scenario, each unit carries its own Ethernet data stream, and the alignment mark insertion process is implemented adaptively. There is no need for coordinated insertion between multiple functional units. The data block recovery operation can be performed on the receiving side according to the distribution order of the distribution unit on the sending side.

[0151] refer to Fig. 12B In some embodiments, a communication system includes a receiving side device and a plurality of sending side devices, wherein the interface of the sending side device is a standard Ethernet interface of IEEE 802.3, and the receiving side device includes corresponding Figure 4A The interface shown in FIG. 1 is similar to the interface shown in FIG. 1 , but also includes an alignment lock module between the PMA module and the FEC module, and Figure 4A Replace the scramble module in with the Descramble module. Figure 4AThe alignment mark insertion (AM Insertion) module in the IEEE 802.3 is replaced with the alignment mark removal (AM Removal) module. The interface of the sending side device processes the data to be sent according to the processing method of the IEEE 802.3 Ethernet interface and sends it to the receiving side device through the medium. The interface of the receiving side device receives data from the sending side device. In the breakout scenario, the interface of the receiving side device distributes the data from multiple sending side device interfaces to one or more functional units in the receiving side device interface corresponding to the rate of the sending side device interface. For example, four IEEE 802.3 standard Ethernet interfaces with a rate of 200Gbps are sent to Figure 4A The interface shown sends data, Figure 4A The interface shown receives the 4-way data at a rate of 200Gbps, corresponds the 4-way data at a rate of 200Gbps to the 4 functional units of its own functional part two with a rate of 200Gbps respectively, performs processing by the functional part two, and then performs processing by the functional part one to obtain the data sent by the 4 sending side devices.

[0152] refer to Fig. 12C A communication system includes a receiving side device and a plurality of sending side devices, wherein the interface of the sending side device is a standard Ethernet interface of IEEE 802.3, and the receiving side device includes corresponding Figure 4B The interface shown in FIG. 1 is similar to the interface shown in FIG. 1 , but also includes an alignment lock module between the PMA module and the FEC module, and Figure 4B Replace the scramble module in with the Descramble module. Figure 4B The AM Insertion module in the IO is replaced by the AM Removal module. The processing of the data to be sent by the sending device interface is the same as Fig. 12B The operation of the sending side device interface in is similar and will not be repeated here.

[0153] refer to Fig.12D A communication system includes a receiving side device and a plurality of sending side devices, wherein the interface of the sending side device is a standard Ethernet interface of IEEE 802.3, and the receiving side device includes corresponding Figure 5A The interface shown in FIG. 1 is similar to the interface shown in FIG. 1 , but also includes an alignment lock module between the PMA module and the FEC module, and Figure 5A Replace the scramble module in with the Descramble module. Figure 5A The AM Insertion module in the IO is replaced by the AM Removal module. The processing of the data to be sent by the sending device interface is the same as Fig. 12BThe operation of the sending side device interface in is similar and will not be repeated here.

[0154] refer to Fig.12E A communication system includes a receiving side device and a plurality of sending side devices, wherein the interface of the sending side device is a standard Ethernet interface of IEEE 802.3, and the receiving side device includes corresponding Fig. 6A The interface shown in FIG. 1 is similar to the interface shown in FIG. 1 , but also includes an alignment lock module between the PMA module and the FEC module, and Fig. 6A Replace the scramble module in with the Descramble module. Fig. 6A The AM Insertion module in the IO is replaced by the AM Removal module. The processing of the data to be sent by the sending device interface is the same as Fig. 12B The operation of the sending side device interface in is similar and will not be repeated here.

[0155] refer to Fig.12F A communication system includes a receiving side device and a plurality of sending side devices, wherein the interface of the sending side device is a standard Ethernet interface of IEEE 802.3, and the receiving side device includes corresponding Figure 6C The interface shown in FIG. 1 is similar to the interface shown in FIG. 1 , but also includes an alignment lock module between the PMA module and the FEC module, and Figure 6C Replace the scramble module in with the Descramble module. Figure 6C The AM Insertion module in the IO is replaced by the AM Removal module. The processing of the data to be sent by the sending device interface is the same as Fig. 12B The operation of the sending side device interface in is similar and will not be repeated here.

[0156] refer to Figure 12G A communication system includes a receiving side device and a plurality of sending side devices, wherein the interface of the sending side device is a standard Ethernet interface of IEEE 802.3, and the receiving side device includes corresponding Fig. 7A The interface shown in FIG. 1 is similar to the interface shown in FIG. 1 , but also includes an alignment lock module between the PMA module and the FEC module, and Fig. 7A Replace the scramble module in with the Descramble module. Fig. 7A The AM Insertion module in the IO is replaced by the AM Removal module. The processing of the data to be sent by the sending device interface is the same as Fig. 12B The operation of the sending side device interface in is similar and will not be repeated here.

[0157] For the functional units in the functional part 2 of the receiving side device interface in the embodiment of the present application, if there is only a single PCS Lane, only alignment lock is required. If there are multiple PCS Lanes, lane deskew is required between the lanes after alignment lock.

[0158] In some embodiments, for the functional units in the functional part two of the receiving side device interface, the FEC decode module can be shared, that is, multiple or all functional units in the functional part two share the same FEC decode module, and the same FEC decode module performs FEC decoding of data from other modules of multiple or all functional units.

[0159] See also Fig.13 , Fig.13 The schematic diagram of the structure of an apparatus 2100 of an exemplary embodiment of the present application is shown. The apparatus 2100 is, for example, a switch, a router, etc., and the apparatus 2100 can be implemented by a bus architecture.

[0160] like Fig.13 As shown, the device 2100 includes: a main control board 2110 and an interface board 2130, wherein the interface board 2130 includes the above Figure 3-1 Any of the interfaces shown in 2.

[0161] The main control board is also called a main processing unit (MPU) or a route processor card. The main control board 2110 is used to control and manage various components in the device 2100, including route calculation, device management, device maintenance, and protocol processing functions. The main control board 2110 includes: a central processing unit 2111 and a memory 2112.

[0162] The interface board 2130 is also called a line processing unit (LPU), a line card or a service board. The interface board 2130 is used to provide various service interfaces and realize the forwarding of data packets. The service interface includes but is not limited to an Ethernet interface, a POS (Packet over SONET / SDH) interface, etc., and the Ethernet interface is, for example, a Flexible Ethernet Client (FlexE Client). The interface board 2130 includes: a central processing unit 2131, a network processor 2132, a forwarding table entry memory 2134 and a physical interface card (physical interface card, PIC) 2133.

[0163] The central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110 .

[0164] The network processor 2132 is used to implement the forwarding processing of the message. The network processor 2132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward the received message based on the forwarding table stored in the forwarding table entry memory 2134. If the destination address of the message is the address of the device 2100, the message is sent to the CPU (such as the central processor 2131) for processing; if the destination address of the message is not the address of the device 2100, the next hop and the output interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the output interface corresponding to the destination address. Among them, the processing of the uplink message may include: processing of the message input interface, forwarding table search; the processing of the downlink message may include: forwarding table search, etc. In some embodiments, the central processor can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board.

[0165] The physical interface card 2133 is used to implement the physical layer docking function, whereby the original traffic enters the interface board 2130, and the processed message is sent out from the physical interface card 2133. The physical interface card 2133, also called a daughter card, can be installed on the interface board 2130, and is responsible for converting the photoelectric signal into a message and forwarding the message to the network processor 2132 for processing after checking the legitimacy of the message. In some embodiments, the central processor 2131 can also perform the functions of the network processor 2132, such as implementing software forwarding based on a general-purpose CPU, so that the network processor 2132 is not required in the physical interface card 2133.

[0166] Optionally, the device 2100 includes a plurality of interface boards, for example, the device 2100 further includes an interface board 2140, and the interface board 2140 includes: a central processing unit 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143. The functions and implementations of the components in the interface board 2140 are the same or similar to those of the interface board 2130, and are not described in detail herein. The interface board includes one or more interfaces described in the above embodiments.

[0167] Optionally, the device 2100 further includes a switching fabric board 2120. The switching fabric board 2120 may also be referred to as a switch fabric unit (SFU). When the device has multiple interface boards, the switching fabric board 2120 is used to complete data exchange between the interface boards. For example, the interface board 2130 and the interface board 2140 may communicate through the switching fabric board 2120.

[0168] The main control board 2110 is coupled to the interface board. For example, the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane through the system bus to achieve intercommunication. In a possible implementation, an inter-process communication (IPC) channel is established between the main control board 2110 and the interface board 2130 and the interface board 2140, and the main control board 2110 and the interface board 2130 and the interface board 2140 communicate through the IPC channel.

[0169] Logically, the device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processor 2111. The forwarding plane includes various components for performing forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs functions such as a router, generating a forwarding table, processing signaling and protocol messages, and configuring and maintaining the status of the device. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the network processor 2132 forwards the message received by the physical interface card 2133 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.

[0170] It is worth noting that there may be one or more main control boards, and when there are multiple boards, they may include a primary main control board and a backup main control board. There may be one or more interface boards, and the more interface boards provided, the stronger the data processing capability of the device. There may also be one or more physical interface cards on the interface board. There may be no switching network board, or there may be one or more switching network boards, and when there are multiple switching network boards, they can jointly realize load sharing and redundant backup. Under a centralized forwarding architecture, the device may not need a switching network board, and the interface board is responsible for the processing function of the business data of the entire system. Under a distributed forwarding architecture, the device may have at least one switching network board, and the switching network board is used to realize data exchange between multiple interface boards, providing large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of the device with a distributed architecture are greater than those of the device with a centralized architecture. Optionally, the device may have only one board, that is, no switching board, and the functions of the interface board and the main control board are integrated on the board. In this case, the central processor on the interface board and the central processor on the main control board can be combined into one central processor on the board to perform the functions of the two. This type of device has low data exchange and processing capabilities (for example, low-end switches or routers). The specific architecture to be adopted depends on the specific networking deployment scenario, and no limitation is made here.

[0171] It should be understood that the above processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the advanced RISC machines (ARM) architecture.

[0172] Further, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0173] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct memory bus random access memory (DR RAM).

[0174] See also Fig.14 , Fig.14 A schematic structural diagram of an apparatus 4000 provided in an exemplary embodiment of the present application is shown. Fig.14 The device 4000 shown is used to perform the above Figure 3-1 2. The device 4000 is, for example, a switch, a router, a controller, etc., and may also be a server, a storage device, a network device, etc. The device 4000 may be implemented by a bus architecture.

[0175] like Fig.14 As shown, the apparatus 4000 includes at least one processor 4001 and at least one communication interface 4004. In some embodiments, the processor 4001 is coupled to the memory 4003.

[0176] Processor 4001 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing units (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, processor 4001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present invention. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0177] Optionally, the device 4000 further includes a bus. The bus is used to transmit information between the components of the device 4000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.14 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0178] The memory 4003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 4003 is, for example, independent and connected to the processor 4001 via a bus. The memory 4003 can also be integrated with the processor 4001.

[0179] The communication interface 4004 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN) or a wireless local area network (WLAN), etc. The communication interface 4004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 4004 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 4004 can be used for the device 4000 to communicate with other devices.

[0180] In a specific implementation, as an embodiment, the processor 4001 may include one or more CPUs, such as Fig.14 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0181] In a specific implementation, as an embodiment, the apparatus 4000 may include multiple processors, such as Fig.14 4001 and processor 4005 shown in . Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0182] In a specific implementation, as an embodiment, the device 4000 may also include an output device and an input device. The output device communicates with the processor 4001 and can display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 4001 and can receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0183] In some embodiments, the memory 4003 is used to store the program code 4010 for executing the solution of the present application, and the processor 4001 can execute the program code 4010 stored in the memory 4003. That is, the apparatus 4000 can implement the program code 4010 in the processor 4001 and the memory 4003. Figure 3-1 2. The program code 4010 may include one or more software modules. Optionally, the processor 4001 itself may also store program codes or instructions for executing the solution of the present application.

[0184] In some embodiments, the communication interface 4004 is used to perform the above Figure 3-1 The operations involved in any of the interface functions shown in 2.

[0185] The embodiment of the present application also provides a computer-readable storage medium, wherein at least one instruction is stored in the storage medium, and the instruction is loaded and executed by the processor to implement the following Figure 3-1 The functions of any of the interfaces shown in 2.

[0186] The present application provides a computer program (product), which, when executed by a computer, can cause a processor or computer to execute Figure 3-1 The functions of any of the interfaces shown in 2.

[0187] The embodiment of the present application provides a chip, including a processor, for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes Figure 3-1 The functions of any of the interfaces shown in 2.

[0188] The embodiment of the present application provides another chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to Figure 3-1 The functions of any of the interfaces shown in 2.

[0189] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Drive), etc.

[0190] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation methods of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the scope of protection of the present application.

[0191] Those of ordinary skill in the art will appreciate that, in conjunction with the various method steps and modules described in the embodiments disclosed herein, they can be implemented in software, hardware, firmware, or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0192] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0193] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target. Generally speaking, a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure. In various embodiments, the function of the program module can be merged or divided between the described program modules. The machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.

[0194] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by a computer or other programmable data processing device, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer or completely on a remote computer or server.

[0195] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like.

[0196] Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0197] A machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0198] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0199] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0200] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0201] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0202] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0203] In the present application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various described examples, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image. Both the first image and the second image may be images, and in some cases, may be separate and different images.

[0204] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0205] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0206] It should be understood that the terms used in the description of the various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0207] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0208] It should also be understood that the terms "if" and "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrases "if it is determined that ..." or "if [a stated condition or event] is detected" may be interpreted to mean "upon determining that ..." or "in response to determining that ..." or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0209] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0210] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0211] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A sending device, characterized in that: It includes a coding and rate matching module, a data block distribution module, a first group of modules, a second group of modules and a physical medium attachment PMA layer, wherein: The encoding and rate matching module is coupled to the data block distribution module, and the data block distribution module is coupled to the first group of modules and the second group of modules; The first group of modules is coupled to the PMA layer, and the second group of modules is coupled to the PMA layer, wherein the PMA layer is used to implement bit multiplexing across the first group of modules and the second group of modules; Wherein, the first group of modules includes a first transcoding module, a first scrambling module, a first alignment mark insertion module and a first forward error correction FEC encoding module; and The second group of modules includes a second transcoding module, a second scrambling module, a second alignment mark insertion module and a second FEC encoding module.

2. The sending device according to claim 1, characterized in that The transmitting device includes a physical coding sublayer PCS, which is used to interleave first data based on FEC symbols to obtain first symbol interleaved data, and to interleave second data based on FEC symbols to obtain second symbol interleaved data. The first data is output by the first FEC encoding module, and the second data is output by the second FEC encoding module.

3. The sending device according to claim 2, characterized in that The PMA layer is used to implement bit multiplexing across the first group of modules and the second group of modules, including: The PMA layer performs bit multiplexing on the first symbol interleaved data and the second symbol interleaved data across the first group of modules and the second group of modules.

4. The transmitting device according to claim 1, characterized in that The first FEC encoding module is a first-level FEC encoding module in the cascaded FEC encoding modules.

5. The sending device according to claim 4, characterized in that The first-level FEC encoding module is used to perform Reed-Solomon RS forward error correction.

6. The sending device according to any one of claims 1 to 5, characterized in that: The sending device further comprises a coordination sublayer RS ​​module, and the RS module is coupled to the coding and rate matching module via a medium independent interface MII.

7. The transmitting device according to claim 1, characterized in that The data block distribution module is used to distribute data to the first group of modules and the second group of modules at a granularity of 66 bits.

8. The sending device according to any one of claims 1 to 5, characterized in that: The sum of the rates of the first group of modules and the second group of modules matches the medium access control MAC rate of the coding and rate matching module.

9. The transmitting device according to claim 8, characterized in that The MAC rate is 800 Gb / s, the rate of the first group of modules is 400 Gb / s, and the rate of the second group of modules is 400 Gb / s.

10. The sending device according to any one of claims 1 to 5, characterized in that: The rate of the first FEC encoding module is 400 Gb / s, and the rate of the second FEC encoding module is 400 Gb / s.

11. The sending device according to any one of claims 1 to 5, characterized in that: The first transcoding module is used to perform transcoding from 64B / 66B to 256B / 257B, and the second transcoding module is used to perform transcoding from 64B / 66B to 256B / 257B.

12. A receiving device, characterized in that: include: A decoding and rate matching module, a data block distribution module, a first group module, a second group module and a physical medium attachment PMA layer; The decoding and rate matching module is coupled to the data block distribution module, and the data block distribution module is coupled to the first group of modules and the second group of modules; The first group of modules is coupled to the PMA layer, and the second group of modules is coupled to the PMA layer, wherein the PMA layer is used to implement bit demultiplexing across the first group of modules and the second group of modules; Wherein, the first group of modules includes a first reverse transcoding module, a first descrambling module, a first alignment mark removal module and a first forward error correction FEC decoding module; and The second group of modules includes a second reverse transcoding module, a second descrambling module, a second alignment mark removal module and a second FEC decoding module.

13. The receiving device according to claim 12, characterized in that The first FEC decoding module is a first-level FEC decoding module in the cascaded FEC decoding modules.

14. The receiving device according to claim 12, characterized in that The receiving device further comprises a coordination sublayer RS ​​module, and the RS module is coupled to the decoding and rate matching module via a medium independent interface MII.

15. The receiving device according to any one of claims 12 to 14, characterized in that: The sum of the rates of the first group of modules and the second group of modules matches the MAC rate of the decoding and rate matching module.

16. The receiving device according to claim 15, characterized in that The MAC rate is 800 Gb / s, the rate of the first group of modules is 400 Gb / s, and the rate of the second group of modules is 400 Gb / s.

17. The receiving device according to any one of claims 12 to 14, characterized in that: The rate of the first FEC encoding module is 400 Gb / s, and the rate of the second FEC encoding module is 400 Gb / s.

18. The receiving device according to any one of claims 12 to 14, characterized in that: The first reverse transcoding module is used to perform reverse transcoding from 256B / 257B to 64B / 66B, and the second reverse transcoding module is used to perform reverse transcoding from 256B / 257B to 64B / 66B.

19. A transmission method, characterized in that: include: Encoding and rate matching the first data to obtain second data; The first group of modules transcodes the first part of the second data to obtain first transcoded data; The first group of modules scrambles the first transcoded data to obtain first scrambled data; The first group of modules inserts a first alignment flag into the first scrambled data to obtain first alignment data; The first group of modules encodes the first aligned data according to a forward error correction FEC code to obtain first processed data; The second group of modules transcodes the second part of the second data to obtain second transcoded data; The second group of modules scrambles the second transcoded data to obtain second scrambled data; The second group of modules inserts a second alignment flag into the second scrambled data to obtain second aligned data; The second group of modules encodes the second aligned data according to the FEC code to obtain second processed data; The first processed data and the second processed data are bit-multiplexed across the first group of modules and the second group of modules at a physical medium attachment (PMA) layer.

20. The method according to claim 19, characterized in that in, The first group of modules encodes the first aligned data according to a forward error correction FEC code to obtain the first processed data, specifically including: The first group of modules encodes the first aligned data according to the FEC code to obtain first encoded data; The first group of modules performs FEC symbol-based interleaving on the first coded data in a physical coding sublayer PCS to obtain the first processed data; The second group of modules encodes the second aligned data according to the FEC code to obtain the second processed data, specifically including: The second group of modules encodes the second aligned data according to the FEC code to obtain second encoded data; The second group of modules performs FEC symbol-based interleaving on the second encoded data at the PCS to obtain the second processed data.

21. The method according to claim 19, characterized in that The first FEC encoding process is a first-level FEC encoding process in a cascaded FEC encoding process.

22. The method according to claim 21, characterized in that The first-level FEC encoding process is used to perform Reed-Solomon (RS) forward error correction.

23. The method according to any one of claims 19 to 22, characterized in that The sum of the rates of the first group of modules and the second group of modules matches the MAC rate of the first data.

24. The method according to claim 23, characterized in that The MAC rate is 800 Gb / s, the rate of the first group of modules is 400 Gb / s, and the rate of the second group of modules is 400 Gb / s.

25. The method according to any one of claims 19 to 22, characterized in that The transcoding is used to perform 64B / 66B to 256B / 257B transcoding.

26. A transmission method, characterized in that: include: Performing bit demultiplexing across the first group of modules and the second group of modules on the third data at the physical medium attachment (PMA) layer to obtain first processed data and second processed data, wherein the third data is data from the physical medium association (PMD) layer; The first group of modules decodes the first processed data according to a forward error correction (FEC) code to obtain first decoded data; The first group of modules deletes a first alignment flag in the first decoded data to obtain first alignment deleted data; The first group of modules descrambles the first alignment-deleted data to obtain first descrambled data; The first group of modules performs reverse transcoding on the first descrambled data to obtain a first part of second data; The second group of modules decodes the second processed data according to the FEC code to obtain second decoded data; The second group of modules deletes the second alignment flag in the second decoded data to obtain second alignment deleted data; The second group of modules descrambles the second alignment-deleted data to obtain second descrambled data; The second group of modules reversely transcodes the second descrambled data to obtain a second part of the second data; The first part and the second part of the second data are decoded and rate matched to obtain first data.

27. The method according to claim 26, characterized in that in, The first group of modules decodes the first processed data according to the FEC code to obtain the first decoded data, specifically including: The first group of modules performs FEC symbol-based deinterleaving on the first processed data in a physical coding sublayer PCS to obtain first de-symbolized interleaved data; The first group of modules decodes the first de-symbolized interleaved data according to a forward error correction (FEC) code to obtain the first decoded data; The second group of modules decodes the second processed data according to the FEC code to obtain the second decoded data, specifically including: The second group of modules performs FEC symbol-based deinterleaving on the second processed data at the PCS to obtain second de-symbolized interleaved data; The second group of modules decodes the second de-symbolized interleaved data according to the FEC code to obtain the second decoded data.

28. The method according to claim 26, characterized in that The FEC decoding process is a first-level FEC decoding process in a cascaded FEC decoding process.

29. The method according to any one of claims 26 to 28, characterized in that: The sum of the rates of the first group of modules and the second group of modules matches the MAC rate of the first data.

30. The method according to claim 29, characterized in that The MAC rate is 800 Gb / s, the rate of the first group of modules is 400 Gb / s, and the rate of the second group of modules is 400 Gb / s.

31. The method according to any one of claims 26 to 28, characterized in that: The reverse transcoding is used to perform reverse transcoding from 256B / 257B to 64B / 66B.

32. A communication system, characterized in that: It comprises a sending device as described in any one of claims 1-11 and a receiving device as described in any one of claims 12-18.

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