No external capacitor LDO power supply architecture

Abstract

The present invention discloses a no-chip-capacitor LDO power supply architecture, comprising: a no-chip-capacitor LDO, whose input is connected to a power supply voltage, whose ground is connected to a power ground, and whose output is connected to a regulating unit; a regulating unit, whose control end is connected to an inverting unit output; an inverting unit, whose input is connected to a comparator output; a comparator, whose non-inverting input is connected to a first voltage, and whose inverting input is connected to a second voltage; the first voltage is determined according to the no-chip-capacitor LDO output voltage, and the second voltage is determined according to the power supply voltage. Compared with the prior art, the present invention can drive multiple digital IOs to flip at a frequency of 100M to realize data transmission function, and the timing and voltage amplitude meet the indicators. The present invention achieves low power consumption (less than 40μA) and low cost (no off-chip capacitor) and meets the use requirements of high-speed applications (can drive >100M data transmission). The circuit structure of the present invention is also scalable and can be expanded to multiple other platforms in the future.

Description

Technical Field

[0001] The present invention relates to the field of electronic engineering, and in particular to an LDO power supply architecture without an external capacitor. Background Art

[0002] GPIO (General Purpose Input / Output) is short for general-purpose input / output (GPIO), which enables external communication and data transmission. It facilitates data transmission in various application scenarios and is a commonly used peripheral module in MCUs. The output portion of an I / O port includes output driver circuits with different drive levels or response speeds. In practice, users can select different drive levels based on different usage scenarios. The stronger the drive capability, the greater the power consumption and noise, and the greater the susceptibility to distortion. In some scenarios, it is necessary to use it in conjunction with an LDO (low dropout regulator). An LDO converts an external power supply into a stable voltage with a certain load capacity to supply the module. When used with an I / O port, the LDO can provide a stable, low-noise power supply for the I / O port and also provide mid-bias for the I / O driver circuit to ensure stable switching.

[0003] When high-speed driving is required, LDO is often required to have good transient response capabilities. Existing circuits often use external off-chip capacitors to cope with the changes in high-speed transient current, achieve stable voltage output, and ensure the normal function of the interface circuit. Taking the scenario where LDO provides power for IO as an example, the existing LDO power supply architecture is as follows: Figure 1 As shown in the figure, the LDO output VOUT terminal needs to be connected to a 1μF capacitor outside the chip to drive multiple digital IOs to achieve high-speed signal transmission. When multiple IOs are synchronously flipped at a high speed (hundreds of Mbps), a large current will be generated, affecting the stability of the LDO output voltage. At this time, the presence of a 1μF capacitor can meet the high-speed requirements and smooth the periodic fluctuations of the output voltage. Figure 1 shown.

[0004] Existing external capacitors require an additional chip package pin for soldering the capacitor during packaging or adding peripheral application circuitry to provide this capacitance. These use cases increase chip costs (e.g., chip area and packaging costs), introduce additional ESD risks, and hinder integration into SoCs (System on Chip). To facilitate system integration and reduce costs, capless LDO designs are becoming increasingly popular. However, the lack of external capacitors also makes LDOs disadvantageous in high-speed applications. To ensure stable voltage output, high loop bandwidth is required to ensure transient response. This high loop bandwidth consumes significant power, and low power consumption is a key requirement for electronic devices. Furthermore, when using an LDO to provide mid-bias, the LDO output voltage can easily be pushed up, and existing LDO architectures lack the output voltage regulation capability to handle this situation. Therefore, power architectures with low power consumption, fast response, low cost, and bidirectional output regulation are highly competitive.

[0005] Therefore, there is an urgent need for an LDO power supply architecture that does not require large power consumption (less than 40μA) and has fast response capability and no external capacitors. Summary of the Invention

[0006] The Summary of the Invention introduces a series of simplified concepts, which are simplifications of existing technologies in the field and are further described in detail in the Detailed Description of the Invention. The Summary of the Invention is not intended to define the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] The technical problem to be solved by the present invention is to provide a LDO power supply architecture without external capacitors that does not require large power consumption (less than 40μA) and has a fast response capability.

[0008] To solve the above technical problems, the present invention provides an LDO power supply architecture without external capacitors, comprising:

[0009] An LDO without external capacitors, wherein the input terminal is connected to the power supply voltage, the ground terminal is connected to the power ground, and the output terminal is connected to the regulating unit; the specific structure of the LDO without external capacitors is not limited and any one of the existing technologies can be used;

[0010] A regulating unit, a control terminal of which is connected to the output terminal of the inverting unit;

[0011] an inverting unit, an input end of which is connected to an output end of the comparator;

[0012] a comparator, wherein a non-inverting input terminal thereof is connected to a first voltage, and an inverting input terminal thereof is connected to a second voltage;

[0013] The first voltage is determined according to the output voltage of the LDO without an external capacitor, and the second voltage is determined according to the power supply voltage.

[0014] Preferably, the LDO power supply architecture without external capacitors is further improved, and the regulating unit includes:

[0015] An NMOS, a drain of which is connected to the output terminal of the LDO without an off-chip capacitor, a source of which is connected to the ground, and a gate of which is connected to the output terminal of the inverting unit;

[0016] And / or, a PMOS, whose source is connected to the power supply voltage, whose drain is connected to the output end of the LDO without an off-chip capacitor, and whose gate is connected to the output end of the inverting unit.

[0017] Preferably, the LDO power supply architecture without external capacitors is further improved, and the inverting unit includes: a first inverter and a second inverter connected in series.

[0018] Preferably, the LDO power supply architecture without external capacitors is further improved, wherein when the output voltage of the LDO without external capacitors overshoots, the first voltage is a*VOUT1, and the second voltage is b*VCCIO, where VOUT1 is the output voltage when the output voltage of the LDO without external capacitors overshoots, and VCCIO is the power supply voltage;

[0019] When the LDO output voltage undershoots without external capacitors, the first voltage is c*VOUT2, and the second voltage is d*VCCIO, where VOUT2 is the output voltage when the LDO output voltage undershoots without external capacitors, and VCCIO is the power supply voltage;

[0020] Wherein, VOUT1 is the output voltage of the LDO when the output voltage overshoots without external capacitors, VOUT2 is the output voltage of the LDO when the output voltage undershoots without external capacitors, VCCIO is the power supply voltage, and a, b, c, and d are specified coefficients.

[0021] Preferably, the above-mentioned LDO power supply architecture without external capacitors is further improved, and the first voltage and the second voltage are obtained by dividing the output voltage of the LDO without external capacitors, for example, by using voltage-dividing resistors and voltage-dividing capacitors.

[0022] Preferably, the LDO power supply architecture without external capacitors is further improved, and the positive and negative inputs of the comparator can be exchanged, and only the corresponding logic numbers need to be changed.

[0023] refer to Figure 2 and Figure 3As shown in the figure, the present invention consists of a capless LDO, a comparator, an inverter unit, and an adjustment unit. The specific structure of the capless LDO is not limited. The comparator monitors the output voltage, and the output result of the comparator controls the pull-down / pull-up transistor through inverter logic to adjust the output voltage, so that the LDO output remains within a suitable voltage range.

[0024] In actual high-speed applications, there may be situations where current is drawn from or injected into the LDO output node (this situation exists when the LDO supplies power to the IO or provides mid-bias for the driving circuit of the IO). When current is injected into the output voltage node, the common LDO loop has no adjustment ability, and the output voltage will be boosted. Without other adjustment mechanisms, it is easy to cause the circuit function to fail. Figure 2 The comparator, inverter, and pull-down NMOS realize the loop adjustment function. The voltage division of the output voltage VOUT1 (a*VOUT1) is compared with the voltage division of the main power supply voltage VCCIO (b*VCCIO). When VOUT1 > VCCIO*b / a, the comparator output is high, and the NMOS transistor is turned on through the inverter logic output to pull down the output voltage VOUT1. When VOUT1 is lower than VCCIO*b / a again, the comparator stops pulling down.

[0025] When current is drawn from the output node, the loop of the general LDO has a certain adjustment ability, but the low-power LDO in high-speed applications cannot effectively adjust the output, and the output voltage will be quickly pulled down. Figure 3 The comparison unit, inverter unit, and pull-up PMOS are used to realize the loop adjustment in this case. The voltage division of the output voltage VOUT2 (c*VOUT2) is compared with the voltage division of the main power supply voltage VCCIO (d*VCCIO). When VOUT2 < VCCIO*d / c, the comparator output is low, and the PMOS transistor is turned on through the inverter logic output to pull up the output voltage VOUT2. When VOUT2 is higher than VCCIO*d / c again, the comparator stops pulling up.

[0026] Take the example of using the LDO to provide Mid-bias to control the gate of the MOS transistor in the driver circuit of the IO: As Figure 4 shown, the VOUT of the LDO controls the gate of the driver module in the digital IO as an intermediate potential. VOUT, together with the PGATE and NGATE signals, controls the pull-up and pull-down of the MOS transistor, so that the PAD follows the Input to output high (amplitude reaches the VCCIO voltage) and low (amplitude is the ground voltage), realizing data transmission. When the VOUT voltage is too high or too low, the VOH and VOL output by the PAD will be affected, and even cause incorrect output.

[0027] In I / O design, driver module circuits often use large W / L dimensions for MOS transistors to achieve a certain level of drive capability. When the input and output flip, the VOUT terminal sinks and draws current to the LDO output through the parasitic capacitance between the MOS transistor gate and other terminals, causing the LDO's VOUT to increase or decrease. The larger the driver transistor size, the greater the rise and fall of the LDO's VOUT. In high-speed usage scenarios, where input and output change rapidly, without a suitable regulation mechanism, the PAD output may not be able to keep up with the input.

[0028] When the existing capless LDO is used with digital IO, the input is 100M square wave, the PAD output and LDO VOUT waveform are as follows Figure 5 As shown in the figure, since the LDO has no ability to regulate the input current, the LDO's VOUT gradually increases, causing the PAD output amplitude to become lower and lower, unable to follow the INPUT, resulting in an output error.

[0029] Based on the existing capless LDO, a comparator, an inverter and a pull-down tube are introduced to form the circuit proposed by the present invention. Figure 2 The power supply architecture shown in the figure is used to drive the output of digital IO. Figure 6 As shown in the figure, with a 100 MHz square wave input, the output follows the input with amplitude and timing performance that meet requirements, achieving 100 MHz data transmission. Table 1 shows the specific values ​​of the output waveform quality. This demonstrates that this power supply architecture achieves the requirements of driving high-speed data transmission (>100 MHz) without external capacitors, low power consumption, and no need for external capacitors.

[0030] The present invention proposes a low-power power supply architecture with fast response capability and no external capacitor (such as Figure 2 and Figure 3 The circuit (shown in Figure 1) has been applied in the design of advanced process platforms such as the 28nm high-k metal gate process (HK). Virtuoso simulation verification shows that this power supply architecture can drive multiple digital IOs to flip at a frequency of 100 MHz, realizing data transmission, and the timing and voltage amplitude meet the specifications. This circuit achieves low power consumption (less than 40μA) and low cost (no external capacitors) and meets the requirements of high-speed applications (capable of driving data transmission >100M). The circuit structure of the present invention is also scalable and can be expanded to multiple other platforms in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings herein are intended to illustrate the general characteristics of methods, structures, and / or materials used in certain exemplary embodiments of the present invention, supplementing the descriptions in the specification. However, the drawings herein are schematic diagrams not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment. The drawings herein should not be interpreted as defining or limiting the range of values ​​or properties encompassed by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0032] Figure 1 This is a schematic diagram of the structure of an off-chip capacitor type LDO power supply in the prior art.

[0033] Figure 2 This is a schematic diagram of the structure of the present invention Figure 1 .

[0034] Figure 3 This is a schematic diagram of the structure of the present invention Figure 2 .

[0035] Figure 4 It is a schematic diagram of the application of the present invention.

[0036] Figure 5 This is a simulation diagram of the existing technology Figure 1 .

[0037] Figure 6 This is a simulation diagram of the present invention Figure 2 . DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art will fully understand the other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can be applied based on different perspectives and various modifications or changes can be made without departing from the overall design concept of the invention. It should be noted that the following embodiments and features therein can be combined with each other unless there is a conflict. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be construed as being limited to the specific embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Throughout the drawings, the same reference numerals represent the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0039] First embodiment;

[0040] refer to Figure 2 As shown, the present invention provides a LDO power supply architecture without external capacitors, including:

[0041] An LDO without an external capacitor has an input terminal connected to a power supply voltage, a ground terminal connected to a power ground, and an output terminal connected to a regulating unit;

[0042] The regulating unit has a control terminal connected to the output terminal of the inverting unit, which is an NMOS, the drain of the NMOS is connected to the output terminal of the LDO without an off-chip capacitor, the source of the NMOS is connected to the ground, and the gate of the NMOS is connected to the output terminal of the inverting unit;

[0043] An inverting unit, whose input end is connected to the output end of the comparator, and which is two inverters connected in series;

[0044] a comparator, wherein a non-inverting input terminal thereof is connected to a first voltage, and an inverting input terminal thereof is connected to a second voltage;

[0045] When the LDO output voltage overshoots without external capacitors, the first voltage is a*VOUT1, and the second voltage is b*VCCIO, where VOUT1 is the output voltage when the LDO output voltage overshoots without external capacitors, VCCIO is the power supply voltage, and a and b are specified coefficients.

[0046] The first voltage and the second voltage are obtained by dividing the output voltage of the LDO without an external capacitor, for example, by dividing the voltage through a voltage dividing resistor and a voltage dividing capacitor.

[0047] Among them, the positive and negative inputs of the comparator can be swapped by simply changing the corresponding logic numbers.

[0048] In addition, it should be understood that, although the terms "first", "second", etc. may be used herein to describe different elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of exemplary embodiments of the present invention, the first element, component, region, layer or part discussed below may also be referred to as the second element, component, region, layer or part.

[0049] Second embodiment;

[0050] refer to Figure 3 As shown, the present invention provides a LDO power supply architecture without external capacitors, including:

[0051] An LDO without an external capacitor has an input terminal connected to a power supply voltage, a ground terminal connected to a power ground, and an output terminal connected to a regulating unit;

[0052] The regulating unit has a control terminal connected to the output terminal of the inverting unit, which is a PMOS, a PMOS source connected to the power supply voltage, a PMOS drain connected to the output terminal of the LDO without an off-chip capacitor, and a PMOS gate connected to the output terminal of the inverting unit;

[0053] An inverting unit, whose input end is connected to the output end of the comparator, and which is two inverters connected in series;

[0054] a comparator, wherein a non-inverting input terminal thereof is connected to a first voltage, and an inverting input terminal thereof is connected to a second voltage;

[0055] When the LDO output voltage undershoots without external capacitors, the first voltage is c*VOUT2, and the second voltage is d*VCCIO, where VOUT2 is the output voltage when the LDO output voltage undershoots without external capacitors, VCCIO is the power supply voltage, and c and d are specified coefficients.

[0056] The first voltage and the second voltage are obtained by dividing the output voltage of the LDO without an external capacitor, for example, by dividing the voltage through a voltage dividing resistor and a voltage dividing capacitor.

[0057] Among them, the positive and negative inputs of the comparator can be swapped by simply changing the corresponding logic numbers.

[0058] It should be noted that the first embodiment and the second embodiment can be used in combination or separately.

[0059] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, rather than being interpreted in an idealized or overly formal sense.

[0060] The present invention has been described in detail above by way of specific embodiments and examples, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered within the scope of protection of the present invention.

Claims

1. A LDO power supply architecture without external capacitors, characterized in that: include: An LDO without an external capacitor has an input terminal connected to a power supply voltage, a ground terminal connected to a power ground, and an output terminal connected to a regulating unit; A regulating unit, a control terminal of which is connected to the output terminal of the inverting unit; an inverting unit, an input end of which is connected to an output end of the comparator; a comparator, wherein a non-inverting input terminal thereof is connected to a first voltage, and an inverting input terminal thereof is connected to a second voltage; The first voltage is determined according to the output voltage of the LDO without an external capacitor, and the second voltage is determined according to the power supply voltage.

2. The LDO power supply architecture without external capacitors according to claim 1, wherein: The regulating unit includes: An NMOS, a drain of which is connected to the output terminal of the LDO without an off-chip capacitor, a source of which is connected to the ground, and a gate of which is connected to the output terminal of the inverting unit; And / or, a PMOS, whose source is connected to the power supply voltage, whose drain is connected to the output end of the LDO without an off-chip capacitor, and whose gate is connected to the output end of the inverting unit.

3. The LDO power supply architecture without external capacitors according to claim 1, wherein: The inverting unit includes a first inverter and a second inverter connected in series.

4. The capacitor-free LDO power supply architecture according to claim 1, wherein: When the LDO output voltage overshoots without external capacitors, the first voltage is a*VOUT1, and the second voltage is b*VCCIO, where VOUT1 is the output voltage when the LDO output voltage overshoots without external capacitors, and VCCIO is the power supply voltage; When the LDO output voltage undershoots without external capacitors, the first voltage is c*VOUT2, and the second voltage is d*VCCIO, where VOUT2 is the output voltage when the LDO output voltage undershoots without external capacitors, and VCCIO is the power supply voltage; Wherein, VOUT1 is the output voltage of the LDO when the output voltage overshoots without external capacitors, VOUT2 is the output voltage of the LDO when the output voltage undershoots without external capacitors, VCCIO is the power supply voltage, and a, b, c, and d are specified coefficients.

5. The capacitor-free LDO power supply architecture according to any one of claims 1 to 4, wherein: The first voltage and the second voltage are obtained by dividing the output voltage of the LDO without an external capacitor.

6. The capacitor-free LDO power supply architecture according to any one of claims 1 to 4, wherein: The comparator's positive and negative inputs can be swapped.

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