Instruction extension method, system, device and medium for DSP fixed-point calculation

Abstract

The present application provides an instruction extension method, system, device and medium for DSP fixed-point calculation. It utilizes the scalability of RISC‑V and expands the frequently used Q fixed-point multiplication and MAC calculation in DSP scenarios into a solidified hardware circuit based on its R‑type instruction format, so as to integrate multiple basic instructions into one instruction, reduce the pressure of the pipeline and the delay of instruction execution, etc., improve the efficiency of program operation, and the integrated instruction obtains at least double the performance improvement of the original instruction combination. In addition, the present application also extends the instruction set so that the 64-bit intermediate result can be directly saved after the multiplication of 32-bit numbers, and performs logical right shift operations in the Q fixed-point format, retaining more low-bit data and improving calculation accuracy. Furthermore, since the maximum multiplication of the same two 32-bit numbers will not exceed 64 bits, and the extended instruction set in the present application expands the intermediate result register to 64 bits, it improves the adaptation range during application calculation and can effectively prevent overflow problems during multiplication.

Description

Technical Field

[0001] The present application relates to the technical field of instruction extension, and in particular to an instruction extension method, system, device and medium applied to DSP fixed-point calculation. Background Art

[0002] The instruction set architecture (ISA) is the soul of the processor, consisting of a set of instructions corresponding to the smallest operation units such as addition, subtraction, multiplication, division, data reading and writing. RISC-V is an open source reduced instruction set (RISC-V) that adheres to the design philosophy of simplicity. The instruction design is simple, which makes the hardware implementation overhead small, power consumption and cost low when designing chips.

[0003] The basic instruction set RV32I corresponding to RISC-V has only more than 40 instructions. At the same time, modular instruction set subsets are designed for different application scenarios: RVM / A / F / D / C / V, etc., to achieve extensions such as atomic operations, integer multiplication and division, single / double-precision floating points, compressed instructions, vectors, etc. Users can decide whether to use these extensions according to their needs. For example, adding integer multiplication and division, atomic operations, and single-precision floating points on the basis of RV32I can be expanded to RV32IMAF, from low-power embedded to high-performance floating-point computing processors.

[0004] The RISC-V standard instruction set RV32G represents RV32IMAFD, which is a full-featured instruction set suitable for most general fields. At the same time, RISC-V also retains the possibility of user-defined extended instruction sets, which can customize and extend instructions for special fields, greatly enhancing the vitality of RISC-V and enabling better performance in niche areas.

[0005] In the fixed-point calculation in the DSP field, MAC calculations and fixed-point multiplication calculations in formats such as Q31 or Q15 need to be frequently performed. Among them, there is no MAC function in the native fixed-point calculation instructions of RISC-V, and the compiler needs to divide it into multiple instructions according to the calculation function. At the same time, when facing Q fixed-point multiplication operations, after the multiplication is completed, logical shifts need to be performed according to the Q fixed point, which is decomposed into the basic instructions of RISC-V. A Q calculation operation will also be decomposed into at least 2 instructions, and data needs to be frequently transferred in the middle, which affects the calculation efficiency. At the same time, it also faces the problems of precision loss and easy overflow. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an instruction extension method, system, device and medium for DSP fixed-point calculation, which is used to solve the technical problems of precision loss and easy overflow in the existing DSP fixed-point calculation.

[0007] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an instruction extension method for DSP fixed-point calculation, comprising: determining high-frequency operation instructions in DSP fixed-point calculation; extracting a basic instruction format matching the instruction format from the RISC-V instruction set according to the calculation scenario requirements of the high-frequency operation instructions; and performing instruction extension on each coding segment of the basic instruction format to integrate the operation instructions corresponding to several calculation scenario requirements into corresponding extended instructions; performing hardware circuit logic encoding on each of the extended instructions to generate the calculation function required by each of the extended instructions; and adding a macro definition of the extended instruction in the compiler according to each of the extended instructions and its hardware logic circuit, so that the extended instruction is decoded and the corresponding hardware circuit is called to perform DSP fixed-point calculation.

[0008] In some embodiments of the first aspect of the present application, the basic instruction format extracted from the RISC-V instruction set includes an R-type instruction format.

[0009] In some embodiments of the first aspect of the present application, performing instruction extension on each encoding segment of the basic instruction format includes: performing instruction extension on the encoding type, register encoding segment, and operation type encoding segment in the R-type instruction format, respectively.

[0010] In some embodiments of the first aspect of the present application, the method of performing instruction extension on the register encoding segment in the R-type instruction format includes: setting the storage number of the encoding segment rs1 of the R-type instruction format to the address pointing to the first input register; setting the storage number of the encoding segment rs2 of the R-type instruction format to the address pointing to the second input register; setting the storage number of the encoding segment rd of the R-type instruction format to the address pointing to the output register; wherein the first input register and the second input register are multiplication input registers for Q fixed-point calculation and MAC calculation; and the output register is a register for storing Q fixed-point calculation results and MAC calculation results.

[0011] In some embodiments of the first aspect of the present application, instruction extension is performed on the operation type encoding segment funct7 in the R-type instruction format, and the instruction extension method includes: in Q fixed-point calculation, the highest 2 bits of the 7 bits of the operation type encoding segment funct7 are set to 0x3 to represent the Q fixed-point calculation program, and the remaining 5 bits are set to immediate values; in MAC calculation, the 7 bits of the operation type encoding segment funct7 are set to 0x20 to represent the MAC calculation program.

[0012] In some embodiments of the first aspect of the present application, the operation type encoding segment funct3 in the R-type instruction format is instruction-extended so that various sub-functions of Q fixed-point calculations can be set accordingly by performing different encoding definitions on the operation type encoding segment funct3.

[0013] In some embodiments of the first aspect of the present application, in Q fixed-point calculation: the funct3[2:0] encoding of the operation type encoding segment funct3 is defined as 0x0 to point to the mulsri operation instruction; the mulsri operation instruction is used to indicate the operation of performing a logical right shift after multiplying to obtain a 64-bit result and retaining the lower 32 bits; the funct3[2:0] encoding of the operation type encoding segment funct3 is defined as 0x1 to point to the srl64li operation instruction; the srl64li operation instruction is used to indicate the operation of performing a logical right shift after merging into a 64-bit result and retaining the lower 32 bits.

[0014] In some embodiments of the first aspect of the present application, the operation type encoding segment funct3 in the R-type instruction format is instruction-extended so as to set various sub-functions of MAC calculation accordingly by performing different encoding definitions on the operation type encoding segment funct3.

[0015] In some embodiments of the first aspect of the present application, in MAC calculation: the funct3[2:0] encoding of the operation type coding segment funct3 is defined as 0x0 to point to the dmac operation instruction; the dmac operation instruction is used to indicate the operation of adding after multiplication and saving 64 bits; the funct3[2:0] encoding of the operation type coding segment funct3 is defined as 0x1 to point to the mah operation instruction; the mah operation instruction is used to indicate the operation of adding after multiplication and saving the high 32 bits; the funct3[2:0] encoding of the operation type coding segment funct3 is defined as 0x2 to point to the mal operation instruction; the mal operation instruction is used to indicate the operation of adding after multiplication and saving the low 32 bits.

[0016] In some embodiments of the first aspect of the present application, the high-frequency operation instructions include Q fixed-point calculation operation instructions and MAC calculation operation instructions.

[0017] In some embodiments of the first aspect of the present application, the extended instruction is encoded in hardware circuit logic based on the Verilog hardware programming language.

[0018] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an instruction extension system for DSP fixed-point calculation, including: an extended instruction generation module, which is used to determine high-frequency operation instructions in DSP fixed-point calculation, and according to the calculation scenario requirements of the high-frequency operation instructions, perform instruction extension on each coding segment of the R-type instruction format in the RISC-V instruction set, so as to integrate the operation instructions corresponding to several calculation scenario requirements into corresponding extended instructions; a hardware circuit logic encoding module, which is used to perform hardware circuit logic encoding on each of the extended instructions to generate the calculation function required by each of the extended instructions; a macro definition module, which is used to add macro definitions of the extended instructions in the compiler according to each of the extended instructions and their hardware logic circuits, so that the extended instructions can be decoded and then call the corresponding hardware circuit to perform DSP fixed-point calculations.

[0019] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the instruction extension method applied to DSP fixed-point calculation is implemented.

[0020] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer device, including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the instruction extension method applied to DSP fixed-point calculation.

[0021] As described above, the instruction extension method, system, device and medium applied to DSP fixed-point calculation of the present application have the following beneficial effects:

[0022] (1) Taking advantage of the scalability of RISC-V, the Q fixed-point multiplication and MAC calculations frequently used in DSP scenarios are expanded into fixed hardware circuits based on its R-type instruction format, so as to integrate multiple basic instructions into one instruction, reduce the pressure on the pipeline and the delay of instruction execution, and improve the program running efficiency. The integrated instructions achieve at least twice the performance improvement compared with the original instruction combination.

[0023] (2) By extending the instruction set, the 64-bit intermediate result can be directly saved after 32-bit numbers are multiplied, and the logical right shift operation can be performed in the Q fixed-point format, which retains more low-bit data and improves the calculation accuracy.

[0024] (3) Since the maximum multiplication of two 32-bit numbers will not exceed 64 bits, and the extended instruction set in the present invention expands the intermediate result register to 64 bits, it can prevent overflow problems during multiplication, improve the adaptability range during application calculation, and prevent overflow problems from occurring. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a flow chart of an instruction extension method applied to DSP fixed-point calculation in one embodiment of the present application.

[0026] Figure 2 Shown is a schematic diagram of the structure of each basic instruction in the RISC-V instruction set in one embodiment of the present application.

[0027] Figure 3 Shown is a schematic diagram of the expanded instruction calling format in one embodiment of the present application.

[0028] Figure 4 Shown is a structural schematic diagram of an instruction extension system applied to DSP fixed-point calculation in one embodiment of the present application.

[0029] Figure 5 Shown is a schematic diagram of the structure of a computer device in one embodiment of the present application. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0031] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It should be understood that other embodiments may also be used, and mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents.

[0032] In this application, unless otherwise expressly specified and limited, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0033] To solve the problems in the above-mentioned background technology, the present invention provides an instruction extension method, system, terminal and medium for DSP fixed-point calculation. Aiming at the defects of frequent MAC calculation and Q fixed-point multiplication calculation in RISC-V in the field of DSP application, a series of extended instruction sets and extension methods are provided, which improve the calculation efficiency, reduce the execution time of instructions, and solve the problems of precision loss and overflow.

[0034] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution in the embodiments of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0035] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0036] (1) DSP fixed-point calculation: Fixed-point numbers are usually used for numerical calculations in fixed-point DSP chips, and their operands are generally represented by integers. The maximum representation range of an integer depends on the word length given by the DSP chip, which is generally 16 bits or 32 bits. The longer the word length, the larger the range of numbers that can be represented and the higher the precision. Take 16-bit word length as an example: the numbers of DSP chips are represented in 2's complement form, and each 16-bit number uses a sign bit to indicate the positive or negative value. 0 indicates a positive value, 1 indicates a negative value, and the remaining 15 bits indicate the magnitude of the value. For DSP chips, the numbers involved in numerical calculations are 16-bit integers. If decimals are processed, it is necessary to determine which position of the decimal point is located in the 16 bits (also called number calibration); by setting the decimal point in different positions in the 16-bit number, decimals of different sizes and different precisions can be represented.

[0037] (2) Q format: A binary fixed-point format. Compared with floating-point numbers, the Q format specifies the corresponding number of decimal places and integer places. On platforms without floating-point operations, floating-point data can be processed faster and applied in programs that require constant resolution.

[0038] (3) RISC-V: An open source instruction set architecture (ISA) based on the principles of the Reduced Instruction Set Computing (RISC). The RISC-V instruction set is suitable for modern computer devices (such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems).

[0039] (4)mulsri (multiplication shift right immediate): logically shift right several bits immediately after multiplication.

[0040] (5) srl64li (shift right logical 64logical immediate): combines the 64 bits and then shifts them right logically by a certain number of bits.

[0041] The embodiment of the present invention provides an instruction extension method applied to DSP fixed-point calculation, a system for the instruction extension method applied to DSP fixed-point calculation, a storage medium storing an executable program for implementing the instruction extension method applied to DSP fixed-point calculation, and a corresponding computer device. As for the implementation of the instruction extension method applied to DSP fixed-point calculation, the embodiment of the present invention will explain an exemplary implementation scenario of the instruction extension applied to DSP fixed-point calculation.

[0042] like Figure 1 FIG. 1 is a flow chart showing a method for extending instructions for fixed-point calculation of a DSP in an embodiment of the present invention. The method for extending instructions for fixed-point calculation of a DSP in this embodiment mainly includes the following steps:

[0043] Step S1: Determine high-frequency operation instructions in DSP fixed-point calculations.

[0044] In an embodiment of the present invention, from the perspective of efficiency improvement, high-frequency operation instructions in the calculation process (i.e., basic calculation instructions corresponding to the core algorithms used frequently) are screened, and multiple instruction sets such as Q fixed-point calculations and MAC calculations that need to be expanded are sorted out to improve the computing efficiency and accuracy in proprietary fields.

[0045] In some examples, an absolute threshold method may be used to determine whether an operation instruction is frequently used. Specifically, the absolute threshold method refers to setting a comparison threshold (for example, 1000 times), and an operation instruction whose usage frequency exceeds the comparison threshold may be identified as a high-frequency operation instruction, otherwise it is identified as a non-high-frequency operation instruction.

[0046] In some examples, a relative comparison method may also be used to determine whether an operation instruction is frequently used. Specifically, the relative comparison method refers to counting the frequency of use of each operation instruction within a time window. If the frequency of use of a certain operation instruction far exceeds that of other operation instructions (for example, its frequency of use is N times that of other operation instructions, and N can be flexibly set), then the operation instruction can be identified as a high-frequency operation instruction, otherwise it is identified as a non-high-frequency operation instruction.

[0047] Step S2: extracting a basic instruction format that matches the instruction format from the RISC-V instruction set according to the computing scenario requirements of the high-frequency operation instructions; and performing instruction expansion on each encoding segment of the basic instruction format to integrate the operation instructions corresponding to several computing scenario requirements into corresponding extended instructions.

[0048] It should be understood that the RISC-V instruction set is an open source instruction set architecture based on a reduced instruction set. The RISC-V instruction set can be divided into the RV32I instruction set, the RV32E instruction set, the RV64I instruction set and the RV128I instruction set. The RV32I instruction set is a basic integer instruction set, including integer calculation instructions, LOAD / STORE and control instructions; RV32I has a 32-bit addressing space and 32 32-bit registers. The instructions of the RV32E instruction set are the same as those of the RV32I, but the number of registers becomes 16 for embedded environments. The RV64I instruction set is an integer instruction with a 64-bit addressing space and 32 64-bit registers. The RV128I instruction set is an integer instruction with a 128-bit addressing space and 32 128-bit registers.

[0049] The present invention relates to the RV32I instruction set, which provides six basic instruction formats, namely R-type instruction format, I-type instruction, S-type instruction, B-type instruction, U-type instruction, and J-type instruction. The length of each basic instruction format is 32 bits. The structure of each instruction format is as follows: Figure 2 shown.

[0050] In R-type instructions, it refers to the encoding structure of opcode+rd+funct3+rs1+rs2+funct7. In 32 bits, [6:0] is opcode, indicating a type of encoding; [11:7] is the register encoding segment, the storage number is the address of the target register rd; [14:12] is the operation type encoding segment, the storage number is the funct3 opcode; [19:15] is the register encoding segment, the storage number is the address of the source register rs1; [24:20] is the register encoding segment, the storage number is the address of the source register rs2; [31:25] is the operation type encoding segment, the storage number is the funct7 opcode.

[0051] I-type instruction refers to the encoding structure of opcode+rd+funct3+rs1+imm. In 32 bits, [6:0] is opcode, indicating a type of encoding; [11:7] is the register encoding segment, the storage number is the address of the target register rd; [14:12] is the operation type encoding segment, the storage number is the funct3 opcode; [19:15] is the register encoding segment, the storage number is the address of the source register rs1; [31:20] is the immediate encoding segment, the storage number is the immediate number.

[0052] S-type instruction refers to the encoding structure of opcode+imm+funct3+rs1+rs2+imm. In 32 bits, [6:0] is opcode, indicating a type of encoding; [11:7] is the register encoding segment, the storage number is the address of the target register rd; [14:12] is the operation type encoding segment, the storage number is the funct3 opcode; [19:15] is the register encoding segment, the storage number is the address of the source register rs1; [24:20] is the register encoding segment, the storage number is the address of the source register rs2; [31:25] is the immediate encoding segment, the storage number is the immediate number.

[0053] B-type instructions refer to the encoding structure of opcode+imm+imm+funct3+rs1+rs2+imm+imm. In 32 bits, [6:0] is opcode, indicating a type of encoding; [11:7] is the immediate encoding segment, the stored number is the immediate number; [14:12] is the operation type encoding segment, the stored number is the funct3 opcode; [19:15] is the register encoding segment, the stored number is the address of the source register rs1; [24:20] is the register encoding segment, the stored number is the address of the source register rs2; [30:25] is the immediate encoding segment, the stored number is the immediate number;

[31] is the immediate encoding segment, the stored number is the immediate number.

[0054] U-type instruction refers to the encoding structure of opcode+rd+imm. In 32 bits, [6:0] is opcode, which indicates a type of encoding; [11:7] is the register encoding segment, and the storage number is the address of the target register rd; [31:12] is the immediate encoding segment, and the storage number is the immediate number.

[0055] J-type instructions refer to the encoding structure of opcode+rd+imm+imm+imm+imm. In 32 bits, [6:0] is opcode, indicating a type of encoding; [11:7] is the register encoding segment, the storage number is the address of the target register rd; [19:12] is the immediate encoding segment, the storage number is the immediate number;

[20] is the immediate encoding segment, the storage number is the immediate number; [24:21] is the immediate encoding segment, the storage number is the immediate number; [31:25] is the immediate encoding segment, the storage number is the immediate number.

[0056] It should be understood that the computing scenario requirements of the high-frequency operation instructions mainly refer to the operation instructions used in Q fixed-point calculation and MAC calculation. For example, the computing scenario requirements of Q fixed-point calculation include at least multiplication operation instructions, logical shift operation instructions, merge operation instructions, etc.; the computing scenario requirements of MAC calculation include at least multiplication operation instructions, addition operation instructions, etc. Integrating the operation instructions corresponding to several computing scenario requirements into corresponding extended instructions mainly refers to integrating at least two operation instructions into corresponding extended instructions, for example, the multiplication operation instruction and the logical right shift operation instruction in Q fixed-point calculation are integrated into mulsri; mulsri is the integrated extended instruction, which means the operation of performing a logical right shift after the multiplication calculation.

[0057] In view of this, the embodiment of the present invention preferably uses the R-type instruction format as the basic instruction format extracted from the RISC-V instruction set, because: the embodiment of the present invention mainly involves operations in the DSP field, that is, instruction extensions for Q fixed-point multiplication calculations and MAC calculations. From the perspective of application requirements and algorithms, both Q fixed-point multiplication calculations and MAC calculations have 2 input registers and 1 result output register, and the R-type instruction format contains exactly three registers (source register rs1, source register rs2, and target register rd). Therefore, the source register rs1 and source register rs2 in the R-type instruction format can be used as the two input registers required for calculation, and the target register rd in the R-type instruction format can be used as the output register required for calculation.

[0058] In the embodiment of the present invention, performing instruction extension on each encoding segment of the basic instruction format includes: performing instruction extension on the encoding type, register encoding segment, and operation type encoding segment in the R-type instruction format. The structure of the R-type instruction format is as follows: Figure 2 As shown, it includes instruction type encoding (opcode), register encoding segments (rs1, rs2, rd), operation type encoding segments (funct7, funct3), etc. Therefore, it is necessary to perform instruction extension on the above encoding segments respectively. The specific extension method and process are as follows:

[0059] (1) Coding type;

[0060] Q fixed-point calculation and MAC calculation both involve multiplication operations, and the RV-M extended opcode can be used, and the opcodes of the two types of extended instruction sets can be set to 0110011.

[0061] (2) Register encoding segment;

[0062] In an embodiment of the present invention, the method of performing instruction extension on the register encoding segment in the R-type instruction format includes: setting the storage number of the encoding segment rs1 of the R-type instruction format to the address pointing to the first input register; setting the storage number of the encoding segment rs2 of the R-type instruction format to the address pointing to the second input register; setting the storage number of the encoding segment rd of the R-type instruction format to the address pointing to the output register; wherein the first input register and the second input register are multiplication input registers for Q fixed-point calculation and MAC calculation; and the output register is a register for storing Q fixed-point calculation results and MAC calculation results.

[0063] (3) Operation type encoding segment funct7;

[0064] In an embodiment of the present invention, the method of performing instruction extension on the operation type coding segment funct7 in the R-type instruction format includes: in Q fixed-point calculation, setting the highest 2 bits of the 7 bits of the operation type coding segment funct7 to 0x3 to represent the Q fixed-point calculation program, and setting the remaining 5 bits to an immediate number; in MAC calculation, setting the 7 bits of the operation type coding segment funct7 to 0x20 to represent the MAC calculation program.

[0065] Specifically, in the Q fixed-point calculation extension, the input support of registers rs1, rs2, rd and immediate number imm is involved. In the R-type instruction format: rs1 occupies [15:19] of 32 bits, a total of 5 bits; rs2 occupies [20:24] of 32 bits, a total of 5 bits; rd occupies [7:11] of [0:31], a total of 5 bits; immediate number imm occupies [25:29] of 32 bits, a total of 5 bits, which in the Q fixed-point multiplication instruction represents the operation of logical shift immediately after the multiplication operation.

[0066] Therefore, in the Q fixed-point calculation, the highest 2 bits are set to 0x3 (funct7[6:5]=0x3) to represent the Q fixed-point calculation procedure, and the remaining 5 bits are set to the immediate value (funct7[4:0]=imm[4:0]). In the MAC calculation, the 7 bits of the funct7 encoding segment are set to 0x20 (funct7[6:0]=0x20) to represent the MAC calculation procedure.

[0067] (4) Operation type encoding segment funct3;

[0068] In the embodiment of the present invention, instruction extension is performed on the operation type coding segment funct3 in the R-type instruction format, so that various sub-functions of Q fixed-point calculation are correspondingly set by performing different coding definitions on the operation type coding segment funct3.

[0069] Furthermore, in the Q fixed-point calculation, the funct3[2:0] encoding of the operation type encoding segment funct3 is defined as 0x0 to point to the mulsri operation instruction; the mulsri operation instruction is used to indicate the operation of performing a logical right shift after multiplying to obtain a 64-bit result and retaining the lower 32 bits; the funct3[2:0] encoding of the operation type encoding segment funct3 is defined as 0x1 to point to the srl64li operation instruction; the srl64li operation instruction is used to indicate the operation of performing a logical right shift after merging into a 64-bit result and retaining the lower 32 bits.

[0070] Specifically, in Q fixed-point calculations, according to various requirements in actual application scenarios, there are mulsri operations (Q fixed-point multiplication, multiplication followed by logical right shift) and direct 64-bit logical right shift operations. To distinguish between various sub-functions, the code defines that when funct3[2:0] is 0x0, it points to the mulsri instruction, and when funct3[2:0] is 0x1, it points to the srl64li instruction.

[0071] For ease of understanding, the following examples are given for the mulsri instruction and srl64li instruction involved in Q fixed-point calculation:

[0072] mulsri,rs1,rs2,rd,imm;

[0073] rd=(rs1*rs2)>>imm, save the lower 32 bits of the result;

[0074] This mulsri instruction means multiplying the storage number in register rs1 and the storage number in register rs2, shifting the immediate number right by imm bits, and loading the final result into register rd.

[0075] srl64li,rs1,rs2,rd,imm;

[0076] rd={rs1,rs2}>>imm, save the lower 32 bits of the result;

[0077] This srl64li instruction means to merge the 32-bit storage number in register rs1 and the 32-bit storage number in register rs2 into a 64-bit value, shift the immediate value right by imm bits after merging, and load the final result into register rd.

[0078] In the embodiment of the present invention, the operation type coding segment funct3 in the R-type instruction format is extended, so that various sub-functions of MAC calculation are correspondingly set by performing different coding definitions on the operation type coding segment funct3.

[0079] Furthermore, in the MAC calculation, the funct3[2:0] encoding of the operation type coding segment funct3 is defined as 0x0 to point to the dmac operation instruction; the dmac operation instruction is used to indicate the operation of adding after multiplication and saving 64 bits; the funct3[2:0] encoding of the operation type coding segment funct3 is defined as 0x1 to point to the mah operation instruction; the mah operation instruction is used to indicate the operation of adding after multiplication and saving the high 32 bits; the funct3[2:0] encoding of the operation type coding segment funct3 is defined as 0x2 to point to the mal operation instruction; the mal operation instruction is used to indicate the operation of adding after multiplication and saving the low 32 bits.

[0080] For ease of understanding, the following examples are given for the dmac instruction, mah instruction, and mal instruction involved in MAC calculation:

[0081] dmac,rs1,rs2,rd;

[0082] rd=rs1*rs2+rd, save the 64-bit result;

[0083] This dmac instruction means multiplying the storage number in register rs1 by the storage number in register rs2, adding the multiplication result to the storage number in register rd as the new storage number in memory rd, and saving the 64-bit result of the new storage number.

[0084] mah,rs1,rs2,rd;

[0085] rd=rs1*rs2+rd, save the high 32 bits result;

[0086] Among them, this extended instruction means multiplying the storage number of register rs1 by the storage number of register rs2, adding the multiplication result to the storage number in register rd as the new storage number of memory rd, and saving the high 32 bits of the new storage number.

[0087] mal,rs1,rs2,rd;

[0088] rd=rs1*rs2+rd, save the lower 32 bits of the result.

[0089] Among them, this extended instruction means multiplying the storage number of register rs1 by the storage number of register rs2, adding the multiplication result to the storage number in register rd as the new storage number of memory rd, and saving the lower 32 bits of the new storage number.

[0090] It is worth noting that, although the low 32-bit result is retained in the end, the embodiment of the present invention can directly save the 64-bit intermediate result through the extended instruction set, and perform the logical right shift operation in the Q fixed-point format, so that more low-bit data can be retained, and the calculation accuracy is improved. At the same time, since the multiplication of the same two 32-bit numbers will not exceed 64 bits at most, and the extended instruction set in the present invention expands the intermediate result register to 64 bits, it can prevent the overflow problem during multiplication, improve the adaptation range during application calculation, and prevent the overflow problem from occurring.

[0091] Step S3: Perform hardware circuit logic encoding on each of the extended instructions to generate the calculation function required by each of the extended instructions.

[0092] Specifically, after the encoding is completed, the hardware circuit needs to be implemented. The operations implemented in the present invention are relatively basic multiplication and addition operations, and do not involve relatively complex algorithms. Verilog encoding can be used to implement hardware circuit logic to complete the calculation functions required in all extended instruction sets. Q fixed-point calculation or MAC calculation is performed through the operands provided by the system, and the calculation results are stored in the result register.

[0093] It should be noted that Verilog generally refers to Verilog HDL, which is a hardware description language that describes the structure and behavior of digital system hardware in text form. It can be used to represent logic circuit diagrams, logic expressions, and the logical functions performed by digital logic systems.

[0094] Step S4: According to each of the extended instructions and the hardware logic circuits thereof, a macro definition of the extended instruction is added in the compiler, so that after the extended instruction is decoded, the corresponding circuit is called to perform DSP fixed-point operation.

[0095] Specifically, the instructions extended by the embodiment of the present invention and their corresponding codes are as follows: Figure 3 As shown, the extended instruction calling format is as follows:

[0096] The Q fixed-point multiplication followed by a right shift operation is as follows:

[0097] mulsri,rs1,rs2,rd,imm;

[0098] rd=(rs1*rs2)>>imm, save the lower 32 bits of the result;

[0099] srl64li,rs1,rs2,rd,imm;

[0100] rd={rs1,rs2}>>imm, save the lower 32 bits of the result;

[0101] The 64-bit MAC operation is as follows:

[0102] dmac,rs1,rs2,rd;

[0103] rd=rs1*rs2+rd, save the 64-bit result;

[0104] mah,rs1,rs2,rd;

[0105] rd=rs1*rs2+rd, save the high 32 bits result;

[0106] mal,rs1,rs2,rd;

[0107] rd=rs1*rs2+rd, save the lower 32 bits of the result.

[0108] according to Figure 3 The extended instruction set encoding in the compiler is added with the macro definition of the extended instruction set, and the opcode table is updated. In the application process, after the decoding module parses the extended instruction set, it points to the extended instruction through code segments such as opcode, funct7, and funct3, and passes the source register rs1, source register rs2, immediate operand imm and other contents to the extended target circuit for Q fixed-point multiplication calculation and MAC calculation, and finally outputs the result to the target register rd.

[0109] In the above, a detailed explanation is given on an instruction extension method for DSP fixed-point calculation provided by the present invention. In the following, a further explanation is given on an instruction extension system for DSP fixed-point calculation provided by the present invention.

[0110] like Figure 4400 is a block diagram of an instruction extension system for DSP fixed-point calculation according to an embodiment of the present invention. The instruction extension system 400 for DSP fixed-point calculation includes an extension instruction generation module 401, a hardware circuit logic encoding module 402 and a macro definition module 403.

[0111] The extended instruction generation module 401 is used to determine high-frequency operation instructions in DSP fixed-point calculations, and extract a basic instruction format that matches the instruction format from the RISC-V instruction set according to the computing scenario requirements of the high-frequency operation instructions; and perform instruction expansion on each encoding segment of the basic instruction format to integrate the operation instructions corresponding to several computing scenario requirements into corresponding extended instructions.

[0112] The hardware circuit logic encoding module 402 is used to perform hardware circuit logic encoding on each of the extended instructions to generate the computing function required by each of the extended instructions.

[0113] The macro definition module 403 is used to add macro definitions of extended instructions in the compiler according to the extended instructions and their hardware logic circuits, so that the extended instructions can be decoded and the corresponding hardware circuits can be called to perform DSP fixed-point operations.

[0114] It should be noted that: the instruction extension system for DSP fixed-point calculation provided in the above embodiment is only illustrated by the division of the above program modules when performing instruction extension for DSP fixed-point calculation. In actual application, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above. In addition, the instruction extension device for DSP fixed-point calculation provided in the above embodiment and the instruction extension method embodiment for DSP fixed-point calculation belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0115] like Figure 5 As shown, a schematic diagram of the structure of a computer device in an embodiment of the present invention is shown. The computer device 500 can be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The computer device 500 includes: at least one processor 501, a memory 502, at least one network interface 504 and a user interface 506. The various components in the device are coupled together through a bus system 505. It can be understood that the bus system 505 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 505 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 3 In the specification, various buses are labeled as bus systems.

[0116] The user interface 506 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0117] It is understood that the memory 502 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0118] The memory 502 in the embodiment of the present invention is used to store various types of data to support the operation of the instruction extension terminal 500 applied to DSP fixed-point calculation. Examples of these data include: any executable program used to operate on the instruction extension terminal 500 applied to DSP fixed-point calculation, such as an operating system 5021 and an application 5022; the operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 5022 can include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The instruction extension method applied to DSP fixed-point calculation provided by the embodiment of the present invention can be included in the application 5022.

[0119] The method disclosed in the above embodiment of the present invention can be applied to the processor 501, or implemented by the processor 501. The processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 501 or the instruction in the form of software. The above processor 501 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 501 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 501 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0120] In an exemplary embodiment, the instruction extension terminal 500 applied to DSP fixed-point calculation can be used by one or more application-specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the above method.

[0121] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0122] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0123] In summary, the present application provides an instruction extension method, device, terminal and medium for DSP fixed-point calculation. The present invention utilizes the scalability of RISC-V, and based on its R-type instruction format, expands the frequently used Q fixed-point multiplication and MAC calculation in the DSP scene into a solidified hardware circuit, so as to integrate multiple basic instructions into one instruction, reduce the pressure of the pipeline and the delay of instruction execution, etc., improve the program running efficiency, and the integrated instruction obtains at least one times the performance improvement of the original instruction combination; by extending the instruction set, the 64-bit intermediate result can be directly saved after the 32-bit number is multiplied, and the logical right shift operation is performed in the Q fixed-point format, which retains more low-bit data and improves the calculation accuracy; because the same two 32-bit numbers multiplied will not exceed 64 bits at most, and the extended instruction set in the present invention expands the intermediate result register to 64 bits, which can prevent the overflow problem during multiplication, improve the adaptation range during application calculation, and prevent the overflow problem from occurring. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0124] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An instruction extension method for DSP fixed-point calculation, characterized in that: include: Determine the high-frequency operation instructions in DSP fixed-point calculations; According to the computing scenario requirements of the high-frequency operation instructions, a basic instruction format matching the instruction format is extracted from the RISC-V instruction set; and each encoding segment of the basic instruction format is extended to integrate the operation instructions corresponding to the computing scenario requirements into corresponding extended instructions; The basic instruction format extracted from the RISC-V instruction set includes an R-type instruction format; performing instruction extension on each encoding segment of the basic instruction format includes: performing instruction extension on an encoding type, a register encoding segment, and an operation type encoding segment in the R-type instruction format; The operation type coding segment funct3 in the R-type instruction format is extended to set various sub-functions of Q fixed-point calculations by defining different codes for the operation type coding segment funct3; the Q format is a binary fixed-point number format, and the Q format specifies the corresponding number of decimal places and integer places; In the Q fixed-point calculation: The funct3[2:0] code of the operation type code segment funct3 is defined as 0x0 to point to the mulsri operation instruction; the mulsri operation instruction is used to indicate the operation of performing a logical right shift after the multiplication obtains a 64-bit result and retaining the lower 32 bits; The funct3[2:0] code of the operation type code segment funct3 is defined as 0x1 to point to the srl64li operation instruction; the srl64li operation instruction is used to indicate the operation of performing a logical right shift after merging into a 64-bit result and retaining the lower 32 bits; Performing hardware circuit logic encoding on each of the extended instructions to generate a computing function required by each of the extended instructions; According to the extended instructions and their hardware logic circuits, macro definitions of the extended instructions are added in the compiler so that the corresponding hardware circuits are called to perform DSP fixed-point operations after the extended instructions are decoded.

2. The instruction extension method for DSP fixed-point calculation according to claim 1, characterized in that: The methods for extending the register encoding segment in the R-type instruction format include: Set the storage number of the encoding segment rs1 of the R-type instruction format to point to the address of the first input register; Set the storage number of the encoding segment rs2 of the R-type instruction format to point to the address of the second input register; Set the storage number of the encoding segment rd of the R-type instruction format to point to the address of the output register; The first input register and the second input register serve as multiplication input registers for Q fixed-point calculation and MAC calculation; and the output register serves as a register for storing the Q fixed-point calculation result and the MAC calculation result.

3. The instruction extension method for DSP fixed-point calculation according to claim 1, characterized in that: The operation type encoding segment funct7 in the R-type instruction format is extended by instructions. The instruction extension methods include: In Q fixed-point calculation, the highest 2 bits of the 7 bits of the operation type encoding segment funct7 are set to 0x3 to indicate the Q fixed-point calculation program, and the remaining 5 bits are set to an immediate value; In the MAC calculation, bit 7 of the operation type encoding segment funct7 is set to 0x20 to indicate the MAC calculation procedure.

4. The instruction extension method for DSP fixed-point calculation according to claim 1, characterized in that: The operation type coding segment funct3 in the R-type instruction format is extended, so that various sub-functions of MAC calculation are correspondingly set by performing different coding definitions on the operation type coding segment funct3.

5. The instruction extension method for DSP fixed-point calculation according to claim 4, characterized in that: In MAC calculation: The funct3[2:0] encoding of the operation type encoding segment funct3 is defined as 0x0 to point to the dmac operation instruction; the dmac operation instruction is used to indicate the operation of adding after multiplication and saving 64 bits; The funct3[2:0] encoding of the operation type encoding segment funct3 is defined as 0x1 to point to the mah operation instruction; the mah operation instruction is used to indicate the operation of adding after multiplication and saving the high 32 bits; The funct3[2:0] encoding of the operation type encoding segment funct3 is defined as 0x2 to point to the mal operation instruction; the mal operation instruction is used to indicate the operation of performing addition after multiplication and saving the lower 32 bits.

6. The instruction extension method for DSP fixed-point calculation according to claim 1, characterized in that: The high-frequency operation instructions include Q fixed-point calculation operation instructions and MAC calculation operation instructions.

7. The instruction extension method for DSP fixed-point calculation according to claim 1, characterized in that: The extended instructions are encoded with hardware circuit logic based on the Verilog hardware programming language.

8. An instruction extension system for DSP fixed-point calculation, characterized in that: include: The extended instruction generation module is used to determine high-frequency operation instructions in DSP fixed-point calculations, and according to the calculation scenario requirements of the high-frequency operation instructions, perform instruction extension on each coding segment of the R-type instruction format in the RISC-V instruction set, so as to integrate the operation instructions corresponding to several calculation scenario requirements into corresponding extended instructions; the basic instruction format extracted from the RISC-V instruction set includes the R-type instruction format; the instruction extension on each coding segment of the basic instruction format includes: performing instruction extension on the coding type, register coding segment, and operation type coding segment in the R-type instruction format; The operation type coding segment funct3 in the R-type instruction format is extended to set various sub-functions of Q fixed-point calculations by defining different codes for the operation type coding segment funct3; the Q format is a binary fixed-point number format, and the Q format specifies the corresponding number of decimal places and integer places; In the Q fixed-point calculation: The funct3[2:0] code of the operation type code segment funct3 is defined as 0x0 to point to the mulsri operation instruction; the mulsri operation instruction is used to indicate the operation of performing a logical right shift after the multiplication obtains a 64-bit result and retaining the lower 32 bits; The funct3[2:0] code of the operation type code segment funct3 is defined as 0x1 to point to the srl64li operation instruction; the srl64li operation instruction is used to indicate the operation of performing a logical right shift after merging into a 64-bit result and retaining the lower 32 bits; A hardware circuit logic encoding module, used for performing hardware circuit logic encoding on each of the extended instructions to generate a computing function required by each of the extended instructions; The macro definition module is used to add the macro definition of the extended instruction in the compiler according to each of the extended instructions and the hardware logic circuit, so that the extended instruction can be decoded and the corresponding hardware circuit can be called to perform DSP fixed-point operation.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the instruction extension method for DSP fixed-point calculation according to any one of claims 1 to 7 is implemented.

10. A computer device, characterized in that: include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory, so that the device executes the instruction extension method applied to DSP fixed-point calculation according to any one of claims 1 to 7.

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