An output method, device and equipment of a superconducting quantum computer and a storage medium

Abstract

The application discloses an output method and device of a superconducting quantum computer, equipment and a storage medium, and relates to the technical field of computers, which comprises the following steps: integrating quantum bits required for completing a target quantum algorithm to obtain integrated bits; obtaining the minimum value in the decoherence time of each quantum bit, and slicing a quantum circuit according to the minimum value; reading the quantum state of the integrated bits at the first slice to obtain a target quantum state, and converting the quantum state into a classical state to obtain read-after bits after reading, and initializing the read-after bits; using a preset quantum state preparation circuit to re-prepare the initialized bits to obtain prepared bits, and applying the prepared bits to the next slice connected with the first slice to obtain the quantum state output of the quantum circuit. The application can reduce the influence of the decoherence effect on the implementation of the quantum algorithm, improve the circuit depth of the quantum algorithm that can be applied by the quantum computer, and improve the fidelity of the output result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and particularly relates to an output method and device of a superconducting quantum computer, equipment and a storage medium. BACKGROUND

[0002] Quantum computing is one of the most popular new computing methods at present and has been applied in multiple application fields. Compared with a classical bit of classical computing, a quantum bit of quantum computing can be in a |0> state, a |1> state, or a superposition state composed of |0> and |1>, and the existence of the superposition state gives quantum computing the ability to process data in parallel. For an n-bit quantum bit, an operation can be equivalent to a calculation in a space with a maximum dimension of 2n, so quantum computing has the ability of parallel computing, thereby improving the efficiency of quantum computing. n

[0003] However, in the process of quantum computing, reading a quantum bit in a superposition state will cause the quantum superposition state to collapse onto one of the computational basis vectors, thereby causing the destruction of the quantum superposition state, and the quantum bit will be affected by decoherence effects (such as energy dissipation and environmental noise interference), thereby causing the fidelity of the output result of quantum computing to decrease. In addition, decoherence effects also limit the number of logical gate operations that can be performed on the quantum bit, thereby limiting the complexity of the quantum algorithm that can be run by the quantum computer.

[0004] At present, all schemes for suppressing the decoherence effect of a quantum bit are to improve the decoherence time of the quantum bit from the aspects of chip structure and chip material. However, each quantum bit has a decoherence time, and all quantum logic gates required in the process of implementing a quantum algorithm need to be completed within the decoherence time. However, quantum computing is still in its early stages of development, and the decoherence time of the quantum bit still cannot meet the needs of actual quantum algorithm implementation. For example, the time required for a double-qubit controlled non-gate (Control-Not gate, CNOT gate), which is the most commonly used in quantum algorithm implementation, is about 100 nanoseconds, so without considering the buffer time required between quantum logic gate operations, only the limitation of the decoherence time determines that the maximum number of CNOT gate operations in one algorithm run is about several thousand times. Obviously, this cannot meet the needs of using a quantum computer (such as a superconducting quantum computer) to solve actual problems that are difficult to handle by classical computing. SUMMARY

[0005] ​Therefore, the purpose of the present application is to provide an output method, device and equipment of a superconducting quantum computer and a storage medium, which can improve the number of quantum logic gate operations that can be implemented by a quantum computer, reduce the influence of decoherence effect on quantum algorithm implementation, improve the circuit depth of quantum algorithms that can be applied by a quantum computer, and improve the fidelity and computing power of the output results of a quantum computer. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses an output method of a superconducting quantum computer, comprising:

[0007] determining the quantum bits required to complete a target quantum algorithm, and integrating a plurality of quantum bits to obtain integrated bits;

[0008] respectively calculating the decoherence time of each quantum bit in the integrated bits, obtaining the minimum value of each decoherence time, and slicing the quantum circuit corresponding to the target quantum algorithm according to the minimum value to obtain a plurality of circuit slices;

[0009] reading the quantum state of the integrated bits at the first slice in the circuit slice to obtain a target quantum state, and converting the quantum state of the integrated bits into a classical state after reading to obtain read-after bits;

[0010] performing an initialization operation on the read-after bits to obtain initialized bits;

[0011] re-preparing the initialized bits using a preset quantum state preparation circuit to convert the quantum state of the initialized bits into the same quantum state as the target quantum state to obtain prepared bits, and applying the prepared bits to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit.

[0012] Optionally, the method further comprises:

[0013] respectively calculating the decoherence time of each quantum bit in the integrated bits, and creating an array based on each decoherence time to obtain a time array;

[0014] obtaining the minimum value of each decoherence time from the time array.

[0015] Optionally, the method further comprises:

[0016] respectively measuring the relaxation time and the dephasing time of each quantum bit in the integrated bits to obtain the target relaxation time and the target dephasing time corresponding to each quantum bit.

[0017] calculating a decoherence time of the quantum bit corresponding to the target relaxation time and the target dephasing time.

[0018] Optionally, the decoherence time is calculated according to the following formula:

[0019]

[0020] wherein T1 represents the target relaxation time of the quantum bit, T2 represents the target dephasing time of the quantum bit, and T2 represents the decoherence time of the quantum bit.

[0021] Optionally, the method for measuring the relaxation time and the dephasing time of each quantum bit in the integrated bit respectively to obtain the target relaxation time and the target dephasing time corresponding to each quantum bit comprises:

[0022] using a Pauli X gate and measuring each quantum bit multiple times according to a plurality of preset time intervals, and recording the time for the probability of the measurement result being in the |1> state to decrease from 1 to 1 / e to obtain the target relaxation time corresponding to the quantum bit;

[0023] using a first X / 2 gate and a second X / 2 gate and measuring the quantum bit multiple times according to the plurality of time intervals, recording the time variation curve of the probability of the measurement result being in the |1> state, and then using a fitting calculation formula to fit the time variation curve to obtain the target dephasing time corresponding to the quantum bit; wherein the frequency of the first X / 2 gate and the second X / 2 gate is the same, and the microwave frequency corresponding to the first X / 2 gate and the second X / 2 gate is different from the bit frequency of the quantum bit by a preset threshold;

[0024] wherein the fitting calculation formula is:

[0025]

[0026] wherein P(|1>) represents the probability of the measurement result being in the |1> state, and t represents time.

[0027] Optionally, the running time of the first segment of the slice is less than or equal to the minimum value, and the running time of the next segment of the slice is less than or equal to the difference between the minimum value and the running time of the preset quantum state preparation circuit.

[0028] Optionally, the initialization operation on the read-after bit to obtain an initialized-after bit comprises:

[0029] using a thermal relaxation method to initialize the read-after bit to obtain an initialized-after bit.

[0030] In a second aspect, the present application discloses a machine learning model operation optimization device, comprising:

[0031] A determination module is configured to determine quantum bits required to complete a target quantum algorithm.

[0032] An integration module is configured to integrate a plurality of quantum bits to obtain integrated bits.

[0033] A calculation module is configured to calculate decoherence times of each quantum bit in the integrated bits respectively, and obtain a minimum value in each decoherence time.

[0034] A circuit division module is configured to slice quantum circuits corresponding to the target quantum algorithm according to the minimum value to obtain a plurality of circuit slices.

[0035] A quantum state reading module is configured to read quantum states of the integrated bits at a first slice in the circuit slices to obtain a target quantum state.

[0036] A quantum state transformation module is configured to transform the quantum states of the integrated bits into classical states after reading to obtain read bits.

[0037] An initialization module is configured to perform an initialization operation on the read bits to obtain initialized bits.

[0038] A re-preparation module is configured to re-prepare the initialized bits by using a preset quantum state preparation circuit to transform quantum states of the initialized bits into quantum states identical to the target quantum state to obtain prepared bits, and apply the prepared bits to a next slice connected to the first slice to obtain quantum state output of the quantum circuit.

[0039] In a third aspect, the present application discloses an electronic device, comprising a processor and a memory; wherein the processor implements the output method of the superconducting quantum computer as described above when executing the computer program stored in the memory.

[0040] In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to implement the output method of the superconducting quantum computer as described above.

[0041] It can be seen that the present application first determines the quantum bits required to complete the target quantum algorithm, integrates the plurality of quantum bits to obtain integrated bits, then calculates the decoherence time of each quantum bit in the integrated bits respectively, obtains the minimum value in each decoherence time, and slices the quantum circuit corresponding to the target quantum algorithm according to the minimum value to obtain a plurality of circuit slices. Further, the quantum state of the integrated bits is read at the first slice in the circuit slice to obtain a target quantum state, and the quantum state of the integrated bits is converted into a classical state after reading to obtain a read-after bit. Then, the read-after bit is initialized to obtain an initialized bit, and the initialized bit is re-prepared by using a preset quantum state preparation circuit to convert the quantum state of the initialized bit into the same quantum state as the target quantum state, thereby obtaining a prepared bit. The prepared bit is applied to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit. It can be seen that the present application uses the minimum decoherence time to slice the entire quantum circuit, reads the quantum bits at each circuit slice, collapses the quantum state into a classical state after reading, re-prepares the quantum state according to the reading result by using the pre-created quantum state preparation circuit, and applies the quantum bits to the next slice. The above steps are repeated until the algorithm application is completed. By collapsing the quantum state into a classical state, the decoherence time of the quantum bits can be recalculated, thereby increasing the number of quantum logic gate operations that can be implemented by the superconducting quantum computer, reducing the influence of decoherence effect on quantum algorithm implementation, improving the circuit depth of the quantum algorithm that can be applied by the superconducting quantum computer, and further improving the fidelity and computing power of the output result of the superconducting quantum computer. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0043] Figure 1 Flow chart of the output method of the superconducting quantum computer disclosed by the present application;

[0044] Figure 2 Flow chart of the output method of the superconducting quantum computer disclosed by the present application;

[0045] Figure 3 Flow chart of the output method of the superconducting quantum computer disclosed by the present application;

[0046] Figure 4A machine learning model operation optimization device structure schematic diagram disclosed by the present application;

[0047] Figure 5 An electronic device structure diagram disclosed by the present application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0049] The embodiments of the present application disclose an output method of a superconducting quantum computer, referring to Figure 1 The method comprises the following steps:

[0050] Step S11: determining quantum bits required to complete a target quantum algorithm, and integrating a plurality of the quantum bits to obtain integrated bits.

[0051] In the embodiment, first, a target quantum algorithm to be implemented by the current superconducting quantum computer is determined, then all quantum bits required to complete the target quantum algorithm are determined, and all the quantum bits are integrated to obtain integrated bits q[1:n]. Wherein, n is the number of all quantum bits required to complete the quantum algorithm.

[0052] Step S12: respectively calculating decoherence times of each quantum bit in the integrated bits, obtaining a minimum value in each decoherence time, and slicing a quantum circuit corresponding to the target quantum algorithm according to the minimum value to obtain a plurality of circuit slices.

[0053] In the embodiment, after the plurality of quantum bits are integrated to obtain the integrated bits, further, the decoherence times of each quantum bit in the integrated bits are calculated, then a minimum value τ, i.e. the minimum decoherence time, is determined from the plurality of calculated decoherence times, and the quantum circuit corresponding to the target quantum algorithm is sliced according to the minimum decoherence time, thereby obtaining a plurality of circuit slices with the length of the minimum value. For example, when the quantum circuit corresponding to the target quantum algorithm is U, the quantum circuit U is sliced, thereby obtaining the sliced circuit U=U1U2U3...U g .

[0054] In the embodiment, the calculating the decoherence time of each of the quantum bits in the integrated bit respectively can include: measuring the relaxation time and the dephasing time of each of the quantum bits in the integrated bit respectively to obtain the target relaxation time and the target dephasing time corresponding to each of the quantum bits; and calculating the decoherence time of the corresponding quantum bit based on the target relaxation time and the target dephasing time. That is, the relaxation time and the dephasing time of each of the quantum bits in the integrated bit are measured respectively, and then the decoherence time of the corresponding quantum bit is calculated based on the measured relaxation time and the dephasing time.

[0055] Specifically, the formula for calculating the decoherence time is:

[0056]

[0057] wherein T1 represents the target relaxation time corresponding to the quantum bit, T2 represents the decoherence time of each of the quantum bits.

[0058] In a specific embodiment, the measuring the relaxation time and the dephasing time of each of the quantum bits in the integrated bit respectively to obtain the target relaxation time and the target dephasing time corresponding to each of the quantum bits can include: measuring each of the quantum bits multiple times using a Pauli X gate and according to a plurality of preset time intervals, and recording the time for the probability of the measurement result being in the |1> state to decrease from 1 to 1 / e to obtain the target relaxation time corresponding to the quantum bit; measuring each of the quantum bits multiple times using a first X / 2 gate and a second X / 2 gate and according to the plurality of time intervals, recording the time variation curve of the probability of the measurement result being in the |1> state, and fitting the time variation curve using a fitting calculation formula to obtain the target dephasing time corresponding to the quantum bit; wherein the first X / 2 gate and the second X / 2 gate have the same frequency, and the microwave frequency corresponding to the first X / 2 gate and the second X / 2 gate differs from the bit frequency of the quantum bit by a preset threshold.

[0059] wherein the fitting calculation formula is:

[0060]

[0061] wherein P(|1>) represents the probability of the measurement result being in the |1> state, and t represents time.

[0062] In this embodiment, a Pauli-X gate (equivalent to a logical NOT gate) can be applied to each quantum bit in the integrated bit, at which time the quantum bit will change from the |0> state to the |1> state without other operations, and the state of the quantum bit will decay from the |1> state to the |0> state with energy dissipation. In order to measure the relaxation time of the quantum bit, the above process can be repeated M times, and the number m of times of obtaining the |1> state is recorded, and then the probability m / M of obtaining the measurement result as the |1> state is obtained. It should be noted that the time interval between the Pauli-X gate operation and the measurement is increased during the measurement process. It can be understood that as the time interval increases, the probability of obtaining the measurement result as the |1> state will be lower and lower. The probability of obtaining the measurement result as the |1> state decreases from 1 to 1 / e (where e is the natural constant) in the time interval, which is the relaxation time T1 of the quantum bit.

[0063] Further, the dephasing time of each quantum bit is calculated. Specifically, two X / 2 gates with the same frequency can be applied to the quantum bit successively, which are the first X / 2 gate and the second X / 2 gate. The microwave frequency corresponding to the two X / 2 gates differs from the bit frequency of the corresponding quantum bit by a preset threshold d. The quantum bit can be measured immediately after the second X / 2 gate is applied. The above process is repeated F times, and the number f of times of obtaining the |1> state is recorded. The probability f / F of obtaining the measurement result as the |1> state can be obtained. During the measurement process, the time interval between the two X / 2 gates is increased. As the time interval increases, the change in the probability of obtaining the measurement result as the |1> state can be recorded, thereby obtaining a curve of the probability of obtaining the measurement result as the |1> state with respect to the time interval. The time variation curve is obtained. Then, the fitting calculation formula is used to fit the above time variation curve to obtain the dephasing time of the corresponding quantum bit wherein the fitting calculation formula is:

[0064]

[0065] In the formula, P(|1>) represents the probability of obtaining the measurement result as the |1> state, and t represents the time.

[0066] Through the calculation of the relaxation time T1 and the dephasing time of the quantum bit, the decoherence time T2 of the quantum bit can be further calculated by the following formula:

[0067]

[0068] Step S13: reading the quantum state of the integrated bit at the first segment slice in the line slice to obtain a target quantum state, and converting the quantum state of the integrated bit into a classical state after reading to obtain a read-after bit.

[0069] In this embodiment, after the quantum circuit corresponding to the target quantum algorithm is sliced according to the minimum value, the integrated bits q[1:n] in the initial state are subjected to U1, and the quantum state of the integrated bits q[1:n] in the initial state is read at the first slice U1 in the above-mentioned slicing, so that the target quantum state after U1 is obtained , and the quantum state of the integrated bits is converted into a classical state after reading, so that the read bits are obtained. It should be noted that the running time of the first slice U1 is less than or equal to the above-mentioned minimum value τ, so that the reading operation in step S13 is effective. Since the quantum state of the n integrated bits is converted into a classical state after reading, the decoherence time of the quantum bits is recalculated at this time, thereby increasing the number of quantum logic gate operations that can be implemented by the superconducting quantum computer, reducing the limitation of the decoherence effect on the application of quantum algorithms to the quantum computer, and further improving the circuit depth of the quantum algorithm that can be applied to the superconducting quantum computer, i.e., the total number of quantum gate operations in the quantum circuit.

[0070] Step S14: performing an initialization operation on the read bits to obtain initialized bits.

[0071] In this embodiment, after the quantum state of the integrated bits is converted into a classical state to obtain read bits, an initialization operation is performed on the read bits to obtain initialized bits.

[0072] In a specific embodiment, the initialization operation on the read bits to obtain initialized bits can specifically include: performing an initialization operation on the read bits by using a thermal relaxation method to obtain initialized bits. That is, the n read bits can be initialized by using a thermal relaxation method, so that the n read bits are reset to the initial state

[0073] In another specific embodiment, the initialization operation on the read bits to obtain initialized bits can specifically include: performing an initialization operation on the read bits by using a feedback reset method to obtain initialized bits. That is, the n read bits can be initialized by using a feedback reset method, so that the n read bits are reset to the initial state

[0074] Step S15: re-preparing the initialized bit by using a preset quantum state preparation circuit to change the quantum state of the initialized bit to the same quantum state as the target quantum state, to obtain a prepared bit, and applying the prepared bit to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit.

[0075] In this embodiment, as shown in FIG. 2, after the initialization operation on the read bit, the quantum state of the read bit is Then, the initialized bit can be re-prepared by using a preset quantum state preparation circuit, so as to change the quantum state of the initialized bit to the same quantum state as the target quantum state, that is, the n-bit initialized bit is re-prepared back to the quantum state by using the quantum state preparation circuit, to obtain a prepared bit, and then applying the prepared bit to the next slice (i.e., U2) connected to the first slice (i.e., U1), and repeating the re-preparation operation in steps S13 to S15, and after applying U2, the quantum state is obtained. Then, continue to apply subsequent slices (i.e., U2, U3... U g ), and repeat the re-preparation operation in steps S13 to S15, until the last slice U g is applied, and finally the quantum state output of the quantum circuit is obtained. Figure 2 wherein the horizontal line represents a quantum circuit, the diagonal line represents a multi-bit quantum bit, U represents a quantum algorithm circuit slice, M represents measurement, the double line represents bit initialization and transfer of read results, and O represents a preset quantum state preparation circuit.

[0076] It should be noted that the preset quantum state preparation circuit is related to the number of bits of the initialized bit, and the depth of the preset quantum state preparation circuit is less than that of the quantum algorithm implementation circuit (i.e., the quantum circuit), so that the n-bit initialized bit can be re-prepared back to the quantum state , and then the next slice U2 is applied, wherein the running time t2 of the next slice U2 is less than or equal to the difference between the minimum value and the running time t p of the preset quantum state preparation circuit, that is, t2≤τ-t p .

[0077] It can be seen that, in the embodiment of the application, the quantum bits required to complete the target quantum algorithm are first determined, and a plurality of the quantum bits are integrated to obtain integrated bits, then the decoherence time of each quantum bit in the integrated bits is calculated respectively, the minimum value in each decoherence time is obtained, and the quantum circuit corresponding to the target quantum algorithm is sliced according to the minimum value to obtain a plurality of circuit slices. Further, the quantum state of the integrated bits is read at the first slice in the circuit slice to obtain a target quantum state, and the quantum state of the integrated bits is converted into a classical state after reading to obtain read-after bits. Then, the read-after bits are initialized to obtain initialized-after bits, and the initialized-after bits are re-prepared by using a preset quantum state preparation circuit to convert the quantum state of the initialized-after bits into the same quantum state as the target quantum state to obtain prepared-after bits. The prepared-after bits are applied to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit. It can be seen that, in the embodiment of the application, the minimum decoherence time is used to slice the entire quantum circuit, and the quantum bits are read at each circuit slice. After reading, the quantum state is collapsed into a classical state, and then the quantum state is re-prepared according to the reading result by using the pre-created quantum state preparation circuit, and the quantum bits are applied to the next slice. The above steps are repeated until the algorithm application ends. By collapsing the quantum state into a classical state, the decoherence time of the quantum bits can be recalculated, thereby increasing the number of quantum logic gate operations that can be implemented by the superconducting quantum computer, reducing the influence of the decoherence effect on the implementation of the quantum algorithm, improving the circuit depth of the quantum algorithm that can be applied by the superconducting quantum computer, and further improving the fidelity of the output result and the computing power of the superconducting quantum computer.

[0078] The embodiment of the application discloses a specific output method of a superconducting quantum computer, as shown in Figure 3 The method comprises the following steps.

[0079] Step S21: determining quantum bits required to complete a target quantum algorithm, and integrating a plurality of the quantum bits to obtain integrated bits.

[0080] Step S22: calculating the decoherence time of each quantum bit in the integrated bits respectively, and creating an array based on each decoherence time to obtain a time array.

[0081] In the embodiment, after the plurality of quantum bits are integrated, the decoherence time of each quantum bit in the integrated bits q[1:n] can be calculated respectively, and then an array, i.e., the time array, is created based on all the decoherence times.

[0082] Step S23: obtaining the minimum value from the time array, and slicing the quantum circuit corresponding to the target quantum algorithm according to the minimum value to obtain a plurality of circuit slices.

[0083] In this embodiment, an array is created based on the decoherence times to obtain a time array Then, the minimum value of all decoherence times is obtained from the time array Then, the minimum value of all decoherence times is obtained from the time array

[0084] Step S24: reading the quantum state of the integrated bits at the first slice in the circuit slice to obtain a target quantum state, and converting the quantum state of the integrated bits into a classical state after reading to obtain read bits.

[0085] Step S25: initializing the read bits to obtain initialized bits.

[0086] Step S26: re-preparing the initialized bits using a preset quantum state preparation circuit to convert the quantum state of the initialized bits into the same quantum state as the target quantum state to obtain prepared bits, and applying the prepared bits to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit.

[0087] The more specific processing procedures of the above steps S21, S24, S25 and S26 can refer to the corresponding contents disclosed in the foregoing embodiments, and will not be described here again.

[0088] It can be seen that the embodiment of the application first determines the quantum bits required to complete the target quantum algorithm, integrates a plurality of the quantum bits to obtain integrated bits, then calculates the decoherence time of each quantum bit in the integrated bits respectively, creates an array based on each decoherence time to obtain a time array, obtains the minimum value in each decoherence time from the time array, slices the quantum circuit corresponding to the target quantum algorithm according to the minimum value to obtain a plurality of circuit slices, reads the quantum state of the integrated bits at the first slice in the circuit slices to obtain a target quantum state, and converts the quantum state of the integrated bits into a classical state after reading to obtain read-after bits, performs an initialization operation on the read-after bits to obtain initialized bits, and finally re-prepares the initialized bits using a preset quantum state preparation circuit to convert the quantum state of the initialized bits into the same quantum state as the target quantum state to obtain prepared bits, and applies the prepared bits to the next slice connected to the first slice, thereby obtaining the quantum state output of the quantum circuit. It can be seen that the minimum decoherence time is obtained from the created decoherence time array, and the entire quantum circuit is sliced using the minimum decoherence time, then the quantum bits are read at each circuit slice, and the quantum state is collapsed into a classical state after reading, the quantum state is re-prepared according to the reading result using the pre-created quantum state preparation circuit, and the quantum bits are applied to the next slice, and the above steps are repeated until the algorithm application ends. By collapsing the quantum state into a classical state, the decoherence time of the quantum bits can be recalculated, thereby reducing the adverse effects of the decoherence effect on the depth of the implemented quantum circuit, and improving the number of quantum logic gate operations that can be implemented by the quantum computer and the fidelity of the output result of the quantum computer, while meeting the actual quantum circuit implementation requirements.

[0089] Correspondingly, the embodiment of the application also discloses a machine learning model operation optimization device, as shown in Figure 4 The device comprises:

[0090] A determination module 11 is configured to determine quantum bits required to complete a target quantum algorithm.

[0091] An integration module 12 is configured to integrate a plurality of the quantum bits to obtain integrated bits.

[0092] A calculation module 13 is configured to calculate the decoherence time of each quantum bit in the integrated bits respectively, and obtain the minimum value in each decoherence time.

[0093] A circuit division module 14 is configured to slice the quantum circuit corresponding to the target quantum algorithm according to the minimum value to obtain a plurality of circuit slices.

[0094] a quantum state reading module 15, configured to read the quantum state of the integrated bit at a first segment of the circuit segment to obtain a target quantum state;

[0095] a quantum state transforming module 16, configured to transform the quantum state of the integrated bit into a classical state after reading to obtain a read bit;

[0096] an initialization module 17, configured to perform an initialization operation on the read bit to obtain an initialized bit;

[0097] a re-preparation module 18, configured to re-prepare the initialized bit by using a preset quantum state preparation circuit to transform the quantum state of the initialized bit into a quantum state same as the target quantum state to obtain a prepared bit, and apply the prepared bit to a next segment connected to the first segment to obtain a quantum state output of the quantum circuit.

[0098] Specific working procedures of the above modules can refer to the corresponding content disclosed in the foregoing embodiments, and will not be described here in detail.

[0099] It can be seen that in the embodiments of the present application, the number of quantum bits required to complete the target quantum algorithm is first determined, and the plurality of quantum bits are integrated to obtain integrated bits, then the decoherence time of each quantum bit in the integrated bits is calculated respectively, and the minimum value of each decoherence time is obtained, and then the quantum circuit corresponding to the target quantum algorithm is sliced according to the minimum value to obtain a plurality of circuit slices. Further, the quantum state of the integrated bits is read at the first slice in the circuit slice to obtain a target quantum state, and the quantum state of the integrated bits is converted into a classical state after reading to obtain read bits, and then the read bits are initialized to obtain initialized bits, and finally the initialized bits are re-prepared using a preset quantum state preparation circuit to convert the quantum state of the initialized bits into the same quantum state as the target quantum state, to obtain prepared bits, and the prepared bits are applied to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit. It can be seen that the embodiments of the present application slice the entire quantum circuit using the minimum decoherence time, read the quantum bits at each circuit slice, collapse the quantum state into a classical state after reading, and then re-prepare the quantum state according to the reading result using the pre-created quantum state preparation circuit, and apply the quantum bits to the next slice. Repeat the above steps until the algorithm application is completed. By collapsing the quantum state into a classical state, the decoherence time of the quantum bits can be recalculated, thereby increasing the number of quantum logic gate operations that can be implemented by the superconducting quantum computer, reducing the influence of decoherence effect on quantum algorithm implementation, improving the circuit depth of the quantum algorithm that can be applied by the superconducting quantum computer, and further improving the fidelity of the output result of the superconducting quantum computer and the computing power.

[0100] In some embodiments, the computing module 13 can specifically include:

[0101] a first calculation unit, configured to calculate the decoherence time of each quantum bit in the integrated bits respectively;

[0102] an array creation unit, configured to create an array based on each decoherence time to obtain a time array;

[0103] a minimum value acquisition unit, configured to acquire the minimum value of each decoherence time from the time array.

[0104] In some embodiments, the computing module 13 can specifically include:

[0105] a first measurement unit, configured to measure the relaxation time and the dephasing time of each quantum bit in the integrated bits respectively to obtain the target relaxation time and the target dephasing time corresponding to each quantum bit;

[0106] A second calculation unit is configured to calculate a decoherence time of the quantum bit based on the target relaxation time and the target dephasing time.

[0107] In some embodiments, the decoherence time is calculated according to the following formula:

[0108]

[0109] wherein T1 represents the target relaxation time of the quantum bit, T2 represents the decoherence time of the quantum bit.

[0110] In some embodiments, the first measurement unit can specifically include:

[0111] A second measurement unit is configured to perform multiple measurements on each quantum bit according to a plurality of preset time intervals by using a Pauli X gate, and record a time at which a probability of a measurement result being in a state |1> decreases from 1 to 1 / e, to obtain a target relaxation time of the quantum bit.

[0112] A third measurement unit is configured to perform multiple measurements on the quantum bit according to the plurality of time intervals by using a first X / 2 gate and a second X / 2 gate, and record a time variation curve of a probability of a measurement result being in a state |1>, and then perform fitting calculation on the time variation curve by using a fitting calculation formula to obtain a target dephasing time of the quantum bit, wherein the first X / 2 gate and the second X / 2 gate have the same frequency, and a microwave frequency corresponding to the first X / 2 gate and the second X / 2 gate is different from a bit frequency of the quantum bit by a preset threshold.

[0113] The fitting calculation formula is as follows:

[0114]

[0115] wherein P(|1>) represents the probability of the measurement result being in the state |1>, and t represents time.

[0116] In some embodiments, the running time of the first segment of the slice is less than or equal to the minimum value, and the running time of the next segment of the slice is less than or equal to a difference between the minimum value and the running time of the preset quantum state preparation circuit.

[0117] In some embodiments, the initialization module 17 can specifically include:

[0118] An initialization unit is configured to perform an initialization operation on the read bit by using a thermal relaxation method to obtain an initialized bit.

[0119] Further, the embodiment of the present application further discloses an electronic device, Figure 5 is an electronic device 20 structural diagram shown according to an exemplary embodiment, the contents in the figure cannot be considered as any limitation on the scope of use of the present application.

[0120] Figure 5 An electronic device 20 structural diagram provided by the embodiment of the present application. The electronic device 20, specifically can include: at least one processor 21, at least one memory 22, power supply 23, communication interface 24, input output interface 25 and communication bus 26. Wherein, the memory 22 is used for storing computer programs, the computer programs are loaded and executed by the processor 21, to realize the related steps in the output method of the superconducting quantum computer disclosed in any preceding embodiment. In addition, the electronic device 20 in the embodiment specifically can be electronic computer.

[0121] In the embodiment, the power supply 23 is used for providing working voltage for each hardware device on the electronic device 20; the communication interface 24 can create data transmission channel between the electronic device 20 and the external device, and the communication protocol followed by the communication interface 24 is any communication protocol applicable to the technical solution of the present application, which is not limited specifically herein; the input output interface 25 is used for obtaining external input data or outputting data to the outside world, and the specific interface type can be selected according to the specific application needs, which is not limited specifically herein.

[0122] In addition, the memory 22 as the carrier of resource storage can be read-only memory, random access memory, disk or optical disk, etc., and the resources stored thereon can include operating system 221, computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0123] Wherein, the operating system 221 is used for managing and controlling each hardware device on the electronic device 20 and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. The computer program 222 can further include computer programs capable of completing other specific work in addition to the computer programs capable of completing the output method of the superconducting quantum computer executed by the electronic device 20 disclosed in any preceding embodiment.

[0124] Further, the present application further discloses a computer readable storage medium for storing computer programs; wherein the computer programs are executed by the processor to realize the output method of the superconducting quantum computer disclosed above. The specific steps of the method can refer to the corresponding contents disclosed in the preceding embodiments, which will not be repeated here.

[0125] Further, the embodiment of the present application also discloses a computer program product comprising computer programs / instructions, which, when executed by a processor, implement the steps of the output method of the superconducting quantum computer as disclosed above.

[0126] The various embodiments are described in the present specification in progressive order, each embodiment highlighting a difference from the other embodiments. The same or similar parts between the various embodiments are referred to each other for clear understanding.

[0127] Those skilled in the art will further appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, various components have been described above generally in terms of their functionality, without reference to the specific manner in which such functionality is achieved. Those skilled in the art will appreciate that the described functionality can be achieved with any one of a variety of hardware and / or software configurations, and that the disclosed embodiments are not limited to any particular hardware or software configuration.

[0128] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0129] Finally, it needs to be pointed out that, in the present specification, the relationship terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or sequence between the entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0130] The output method of the superconducting quantum computer, the device, the equipment and the storage medium are introduced in detail. The principle and implementation of the application are described by applying specific examples. The above example is only used to help understand the method and its core idea. At the same time, for those skilled in the art, according to the idea of the application, the specific implementation and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the application.

Claims

1. A method for outputting data from a superconducting quantum computer, characterized in that, include: The number of qubits required to complete the target quantum algorithm is determined, and multiple qubits are integrated to obtain integrated bits; The decoherence time of each of the qubits in the integrated bits is calculated respectively, and the minimum value of each decoherence time is obtained. Then, the quantum circuit corresponding to the target quantum algorithm is sliced ​​according to the minimum value to obtain multiple circuit slices. The quantum state of the integrated bit is read at the first slice in the line slice to obtain the target quantum state, and the quantum state of the integrated bit is transformed into a classical state after reading to obtain the read bit; The read bits are initialized to obtain initialized bits; The initialized bit is re-prepared using a preset quantum state preparation circuit to transform the quantum state of the initialized bit into the same quantum state as the target quantum state, thus obtaining the prepared bit. The prepared bit is then applied to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit.

2. The output method of the superconducting quantum computer according to claim 1, characterized in that, The step of calculating the decoherence time of each of the qubits in the integrated qubit set and obtaining the minimum value among the decoherence times includes: The decoherence time of each of the qubits in the integrated bits is calculated respectively, and an array is created based on each of the decoherence times to obtain a time array; Obtain the minimum value among the decoherence times from the time array.

3. The output method of the superconducting quantum computer according to claim 1, characterized in that, The calculation of the decoherence time of each of the qubits in the integrated qubits includes: The relaxation time and dephase time of each of the qubits in the integrated bit are measured respectively to obtain the target relaxation time and target dephase time of each qubit; The decoherence time of the corresponding qubit is calculated based on the target relaxation time and the target dephase time.

4. The output method of the superconducting quantum computer according to claim 3, characterized in that, The formula for calculating the decoherence time is: Where T1 represents the target relaxation time corresponding to the qubit. T1 represents the target dephase time corresponding to the qubit, and T2 represents the decoherence time of the qubit.

5. The output method of the superconducting quantum computer according to claim 4, characterized in that, The step of measuring the relaxation time and dephase time of each qubit in the integrated qubit to obtain the target relaxation time and target dephase time for each qubit includes: Using the Pauli X gate, each of the qubits is measured multiple times at preset time intervals, and the time when the probability of the |1> state decreases from 1 to 1 / e is recorded to obtain the target relaxation time corresponding to the qubit. The qubit is measured multiple times sequentially using a first X / 2 gate and a second X / 2 gate at multiple time intervals, and the time-varying curve of the probability of the measurement result being the |1> state is recorded. Then, the time-varying curve is fitted using a fitting calculation formula to obtain the target de-phase time corresponding to the qubit. Wherein, the first X / 2 gate and the second X / 2 gate have the same frequency, and the microwave frequency corresponding to the first X / 2 gate and the second X / 2 gate differs from the bit frequency of the qubit by a preset threshold. The fitting calculation formula is as follows: Where P(|1>) represents the probability that the measurement result is in the |1> state, and t represents time.

6. The output method of the superconducting quantum computer according to claim 1, characterized in that, The running time of the first slice is less than or equal to the minimum value, and the running time of the next slice is less than or equal to the difference between the minimum value and the running time of the preset quantum state preparation circuit.

7. The output method of the superconducting quantum computer according to claim 1, characterized in that, The initialization operation on the read bits to obtain initialized bits includes: The read bits are initialized using thermal relaxation to obtain initialized bits.

8. An output device for a superconducting quantum computer, characterized in that, include: The determination module is used to determine the qubits required to complete the target quantum algorithm; An integration module is used to integrate multiple qubits to obtain integrated qubits; The calculation module is used to calculate the decoherence time of each of the qubits in the integrated bits respectively, and to obtain the minimum value among the decoherence times; The circuit segmentation module is used to slice the quantum circuit corresponding to the target quantum algorithm according to the minimum value, so as to obtain multiple circuit slices; A quantum state reading module is used to read the quantum state of the integrated bit at the first slice in the line slice to obtain the target quantum state; A quantum state transition module is used to convert the quantum state of the integrated bit into a classical state after reading, so as to obtain the read bit; An initialization module is used to initialize the read bits to obtain initialized bits; The re-preparation module is used to re-prepare the initialized bit using a preset quantum state preparation circuit, so as to transform the quantum state of the initialized bit into the same quantum state as the target quantum state, to obtain the prepared bit, and to apply the prepared bit to the next slice connected to the first slice to obtain the quantum state output of the quantum circuit.

9. An electronic device, characterized in that, It includes a processor and a memory; wherein, when the processor executes a computer program stored in the memory, it implements the output method of the superconducting quantum computer as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used for storing computer programs; wherein, when the computer programs are executed by a processor, they implement the output method of the superconducting quantum computer as described in any one of claims 1 to 7.

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