Driving circuit and display device

Abstract

The present application provides a driving circuit and a display device, wherein the driving circuit is used to drive a display panel, and the display panel includes a plurality of pixel units, and the driving circuit includes a timing control module and a level conversion module. The timing control module is used to monitor whether the display panel is turned off, and output a trigger signal when it is determined that the display panel is turned off; the level conversion module is electrically connected to the timing control module and the display panel, and the level conversion module outputs a full-on function signal in response to the trigger signal output by the timing control module, and the full-on function signal is used to control the plurality of pixel units in the display panel to discharge charge. The driving circuit provided in the present application can ensure that the timing of the timing control module and the level conversion module remain consistent when the power is turned off, and can improve the problem of afterimage when the power is turned off.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a display device. Background Art

[0002] Currently, Gate Driven on Array (GOA) technology has become a key development direction for panel manufacturers due to its significant advantages over Gate Chip On Film (Gate COF) technology in terms of cost and functionality.

[0003] The signal received by GOA comes from TCON (Timing Controller). When working, TCON sends T_S signal (including STV, CPV and other signals) to Level shift (level converter, LS), and then Level shift sends S_G signal (including boosted STV and CK and other signals) to GOA circuit. Among them, Level shift has XON function, that is, when the logic operating voltage VDD received at shutdown drops to uvlo (F), it outputs a full-on function signal, so that GOA pulls all outputs to VGH, and then drops them to 0. Its purpose is to pull all GOA circuits to VGH at the moment of shutdown, and all scan line outputs are high-level. All TFTs in the control plane are turned on, so that the charge in the capacitor in the pixel is quickly released to avoid shutdown ghosting. However, the effect of eliminating shutdown ghosting using this method is poor. Summary of the Invention

[0004] In view of this, the main purpose of this application is to propose a driving circuit and a display device, aiming to solve the problem that the existing display devices are poor in eliminating shutdown ghosting.

[0005] To achieve the above objectives, a first aspect of the present application provides a driving circuit for driving a display panel, wherein the display panel includes a plurality of pixel units, and the driving circuit includes a timing control module and a level conversion module. The timing control module is configured to monitor whether the display panel is powered off and output a trigger signal when the display panel is determined to be powered off; the level conversion module is electrically connected to the timing control module and the display panel, and in response to the trigger signal output by the timing control module, the level conversion module outputs a full-on function signal, wherein the full-on function signal is configured to control the plurality of pixel units in the display panel to discharge charge.

[0006] The driving circuit provided in the present application outputs a trigger signal to the level conversion module through the timing control module when it detects that the display panel is turned off, triggering the level conversion module to output a full-on function signal to control the multiple pixel units in the display panel to discharge charges. Compared with the method in which the level conversion module turns on the XON function according to the VDD dropping to uvlo (F), it can ensure that the timing of the timing control module and the level conversion module are consistent when shutting down, which can improve the shutdown ghosting problem.

[0007] In some embodiments, the timing control module is used to receive an operating voltage, monitor whether the display panel is turned off according to changes in the operating voltage, and determine that the display panel is turned off when the operating voltage drops below a preset voltage, and output the trigger signal.

[0008] In some embodiments, the timing control module includes a first voltage terminal, a timing controller, and a trigger signal output circuit. The first voltage terminal is used to receive the operating voltage; the timing controller is electrically connected to the first voltage terminal and is used to monitor whether the display panel is shut down based on changes in the operating voltage received by the first voltage terminal, and to determine that the display panel is shut down when the operating voltage drops below a preset voltage threshold and output a control signal; the trigger signal output circuit is electrically connected to both the timing controller and the level conversion module, and outputs the trigger signal to the level conversion module in response to the control signal output by the timing controller.

[0009] In some embodiments, the trigger signal output circuit includes a first switch tube, which includes a first connection end, a second connection end, and a control end. The first connection end of the first switch tube is electrically connected to the first voltage end, the second connection end of the first switch tube is electrically connected to the level conversion module, and the control end of the first switch tube is electrically connected to the timing controller; the first switch tube is turned on in response to the control signal output by the timing controller, and outputs the operating voltage to the level conversion module through the second connection end; wherein, the trigger signal is the operating voltage received by the first voltage end.

[0010] In some embodiments, the level conversion module includes a low-voltage control unit, which includes a second voltage terminal and a second switching transistor. The second voltage terminal is configured to receive a high-level voltage. The second switching transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the second switching transistor is electrically connected to the second voltage terminal, and the second connection terminal of the second switching transistor is electrically connected to the display panel. The second switching transistor is turned on based on a trigger signal output by the timing control module and outputs the high-level voltage to the display panel via the second connection terminal. The fully-on function signal is the high-level voltage received by the second voltage terminal.

[0011] In some embodiments, the level conversion module further includes a third switch tube, a first resistor and a second resistor, the third switch tube includes a first connection end, a second connection end and a control end, the first connection end of the third switch tube is grounded, and the control end of the third switch tube is electrically connected to the timing control module; the first resistor is electrically connected between the control end of the second switch tube and the second voltage end; the second resistor is electrically connected between the control end of the second switch tube and the second connection end of the third switch tube; the third switch tube is turned on in response to the trigger signal output by the timing control module, so that the control end of the second switch tube is grounded through the second resistor and the third switch tube, thereby turning on the second switch tube.

[0012] In some embodiments, the threshold voltage of the third switch tube is lower than the preset voltage; the third switch tube is turned on when the voltage at the control end is higher than the threshold voltage, and is turned off when the voltage at the control end is lower than the threshold voltage.

[0013] In some embodiments, the level conversion module also includes a clock signal output unit, which is electrically connected between the low-voltage control unit and the display panel; the clock signal output circuit responds to the full-on function signal output by the low-voltage control unit, and outputs a clock signal with a constant voltage value of the high-level voltage to the display panel to control the multiple pixel units in the display panel to discharge charges.

[0014] In some embodiments, the timing controller is configured to output a gate timing signal to the level conversion module when the display panel is in a power-on state, and stop outputting the gate timing signal when it is determined that the display panel is powered off.

[0015] A second aspect of the present application further provides a display device, comprising a display panel and the driving circuit described in the first aspect, wherein the driving circuit is electrically connected to the display panel.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the circuit structure of a pixel unit provided in an embodiment of the present application;

[0019] Figure 3 A first driving signal timing diagram of the display device provided in an embodiment of the present application;

[0020] Figure 4 A second driving signal timing diagram of the display device provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the circuit structure of the timing control module provided in an embodiment of the present application;

[0022] Figure 6 This is a schematic diagram of the circuit structure of the level conversion module provided in an embodiment of the present application. The following are the descriptions of the reference numerals:

[0023] Display device 1

[0024] Display panel 200

[0025] Driving circuit 100

[0026] Gate driver 211

[0027] Source driver 212

[0028] Pixel unit P

[0029] Scan line 201

[0030] Data line 202

[0031] Timing control module 10

[0032] Level conversion module 20

[0033] First voltage terminal V1

[0034] Timing controller 11

[0035] Trigger signal output circuit 12

[0036] The first switch N1

[0037] Low voltage control unit 21

[0038] The second voltage terminal V2

[0039] The second switch tube QB

[0040] The third switch tube QA

[0041] First resistor R1

[0042] The second resistor R2

[0043] The third resistor R3

[0044] Clock signal output unit 22

[0045] First transistor T1

[0046] The second transistor T2

[0047] The third transistor T3

[0048] Fourth transistor T4

[0049] The fifth transistor T5

[0050] Sixth transistor T6

[0051] Seventh transistor T7

[0052] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] In addition, the terms "first", "second", etc. in the description of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] It should be noted that, in the absence of conflict, the features in the embodiments of this application can be combined with each other.

[0056] See also Figure 1 , Figure 1 Schematic diagram of the structure of a display device provided in an embodiment of the present application. The display device 1 includes a driving circuit 100 and a display panel 200.

[0057] The display panel 200 includes a display area and a non-display area. The display area is provided with a plurality of data lines (Source lines) 202, a plurality of scan lines (Gate lines) 201, and a plurality of pixel units P arranged in a grid pattern. The plurality of data lines 202 extend along the column direction and are spaced apart along the row direction. The plurality of scan lines 201 extend along the row direction and are spaced apart along the column direction. The plurality of pixel units P are respectively provided at the intersections of the plurality of scan lines 201 and the plurality of data lines 202.

[0058] The non-display area is provided with a gate driver (Gate on Array, GOA) 211 and a source driver (SourceIC) 212 . The gate driver 211 is electrically connected to the plurality of scan lines 201 , and the source driver 212 is electrically connected to the plurality of data lines 202 .

[0059] The driving circuit 100 includes a timing control module 10 , a level conversion module 20 and a power management IC (PMIC).

[0060] The power management integrated circuit is configured to output a gate level signal and provide the gate level signal to the gate driver 211. The gate level voltage includes a high level voltage (VGH) and a low level voltage (VGL). In addition, the power management integrated circuit can also provide an operating voltage to the timing control module 10, the level conversion module 20, and the source driver 212, and provide a gamma signal to the source driver 212. The source driver 212 adjusts the brightness of the displayed image based on the received gamma signal.

[0061] The timing control module 10 is configured to receive image signals representing image information from an external signal source and, based on the image signals, provide a plurality of voltage signals to drive the source driver 212 and the gate driver 211. The voltage signals are then transmitted by the source driver 212 and the gate driver 211 to the plurality of pixel units P, thereby driving the display panel 200 to perform display. Specifically, the timing control module 10 is configured to provide a data timing signal (Data) to the source driver 212, so that the source driver 212 outputs a corresponding data signal Vdata to each column of pixel units P via the plurality of data lines 202 based on the data timing signal. The timing control module 10 is further configured to provide a T_S signal to the level conversion module 20, such as a gate timing signal (CPV, Clock for Pixel Voltage), a vertical synchronization start signal (STV), etc., so that the level conversion module 20 outputs an S_G signal to the gate driver 211 based on the T_S signal, such as a clock signal CK1 to a clock signal CKn, a boosted vertical synchronization start signal STV, etc., thereby enabling the gate driver 211 to output a corresponding scan signal Scan to each row of pixel units P through the multiple scan lines 201 based on the S_G signal, so as to scan each row of pixel units P.

[0062] See also Figure 2 , Figure 2 A schematic diagram of the circuit structure of a pixel unit provided in an embodiment of the present application. Taking the display device 1 as an organic light-emitting display device as an example, the pixel unit P includes first to seventh transistors T1 to T7, a storage capacitor C, and a light-emitting element OLED. The first transistor T1 is used to control whether the light-emitting element OLED is illuminated. Under normal circumstances, the current flowing through the light-emitting element OLED device must flow through the first transistor T1. The second transistor T2 is used to control the magnitude of the current flowing through the light-emitting element OLED device. The third transistor T3 is used to discharge the storage capacitor C to initialize the potential of the negative electrode of the storage capacitor C to Vint. The fourth transistor T4 is used to compensate for the threshold voltage Vth of the second transistor T2. The fifth transistor T5 is used to control when ELVDD supplies power to the light-emitting element OLED. The sixth transistor T6 is used to control when the data signal Vdata charges the storage capacitor C. The seventh transistor T7 is used to initialize the anode of the light-emitting element OLED device. Vint is the initialization voltage, Vdata is the data voltage, ELVDD is the high potential that provides current to the light-emitting element OLED, and ELVSS is the low potential that provides the current direction to the light-emitting element OLED.

[0063] See also Figure 3 , Figure 3The first driving signal timing diagram of the display device provided in the embodiment of the present application, wherein the rising edge of the gate timing signal CPV1 determines the rising edge of the clock signal CK1 to the clock signal CKn, and the falling edge of the gate timing signal CPV2 determines the falling edge of the clock signal CK1 to the clock signal CKn. When the display panel 200 is turned off, the level conversion module 20 has an XON function. When the operating voltage VDD received by the level conversion module 20 drops to uvlo (F), it outputs a full-on function signal to control all signals to be pulled up to VGH and then reduced to 0V. Its purpose is to allow the gate driver 211 to scan all pixel units P at the moment of shutdown, and control the third transistor T3 in all pixel units P to turn on, so that the charge on the storage capacitor C is quickly released to avoid the shutdown ghosting problem.

[0064] However, after research, it was found that, when shutting down, the time when the timing control module 10 stops working is related to its own RC circuit, while the time when the level conversion module 20 stops working is determined by the working voltage VDD. Therefore, when the time when the timing control module 10 stops working is inconsistent with the time when the level conversion module 20 stops working, the timing control module 10 and the level conversion module 20 will be out of sync, resulting in the shutdown ghosting problem. Specifically, Figure 3 As shown, the timing control module 10 has stopped sending CPV1 to CPV2 at the time T_try, and the operating voltage VDD drops to uvlo (F) at the time T_act. That is, during the period from the time T_try to the time T_act, the timing control module 10 has stopped working. However, the level conversion module 20 is still working and cannot receive the gate timing signals CPV1 to CPV2, thereby failing to trigger the falling edge of the clock signals CK1 to CKn, which will cause some clock signals CK1 (for example, Figure 3 CK3) in the T_try moment to the T_act moment is always kept at a high level, which will cause some scan lines 201 in the display panel 200 to be unable to be turned on together according to the XON function, resulting in a shutdown ghosting problem.

[0065] In view of this, the present application proposes a driving circuit 100 for driving a display panel 200 . The display panel 200 includes a plurality of pixel units P. The driving circuit 100 includes a timing control module 10 and a level conversion module 20 .

[0066] The timing control module 10 is used to monitor whether the display panel 200 is turned off, and output a trigger signal when it is determined that the display panel 200 is turned off.

[0067] The level conversion module 20 is electrically connected to the timing control module 10 and the display panel 200. The level conversion module 20 outputs a full-on function signal in response to a trigger signal output by the timing control module 10. The full-on function signal is used to control the multiple pixel units P in the display panel 200 to discharge charge.

[0068] The driving circuit 100 provided in the present application outputs a trigger signal to the level conversion module 20 through the timing control module 10 when monitoring that the display panel 200 is turned off, triggering the level conversion module 20 to output a full-on function signal to control the multiple pixel units P in the display panel 200 to discharge charge. Compared with the method in which the level conversion module 20 turns on the XON function according to the drop of VDD to uvlo (F), it can ensure that the timing of the timing control module 10 and the level conversion module 20 are consistent when shutting down, which can improve the shutdown ghosting problem.

[0069] In some embodiments, the timing control module 10 is used to receive the operating voltage V_H, and monitor whether the display panel 200 is turned off according to the change of the operating voltage V_H, and determine that the display panel 200 is turned off when the operating voltage V_H drops below a preset voltage, and output the trigger signal.

[0070] For example, the operating voltage V_H is 3.3 V. The preset voltage can be set as required. In other embodiments, the timing control module 10 can further determine whether the display panel 200 is shut down based on the rate of decrease of the operating voltage V_H, and determine that the display panel 200 is shut down when the rate of decrease of the operating voltage V_H is greater than a preset rate. This is not limited here.

[0071] Further, see Figure 4 , Figure 4 The second driving signal timing diagram of the display device provided in the embodiment of the present application. The timing controller 11 is used to output the gate timing signal to the level conversion module 20 when the display panel 200 is in the power-on state, and to output the gate timing signal to the level conversion module 20 when it is determined that the display panel 200 is powered off (for example Figure 4 At the T_true moment in the figure, the gate timing signal is stopped from being output, and the trigger signal is output to the level conversion module 20, thereby triggering the level conversion module 20 to turn on the XON function and output the full-on function signal.

[0072] See also Figure 5 , Figure 5 Schematic diagram of the circuit structure of the timing control module provided in an embodiment of the present application. In some embodiments, the timing control module 10 includes a first voltage terminal V1, a timing controller 11 and a trigger signal output circuit 12.

[0073] The first voltage terminal V1 is used to receive the operating voltage V_H.

[0074] The timing controller 11 is electrically connected to the first voltage terminal V1 and is configured to monitor whether the display panel 200 is powered off based on changes in the operating voltage V_H received by the first voltage terminal V1. The timing controller 11 is further configured to determine that the display panel 200 is powered off when the operating voltage V_H drops below a preset voltage threshold and output a control signal.

[0075] The trigger signal output circuit 12 is electrically connected to the timing controller 11 and the level conversion module 20 . The trigger signal output circuit 12 outputs the trigger signal to the level conversion module 20 in response to the control signal output by the timing controller 11 .

[0076] Furthermore, the trigger signal output circuit 12 includes a first switch tube N1, which includes a first connection end, a second connection end, and a control end. The first connection end of the first switch tube N1 is electrically connected to the first voltage end V1, the second connection end of the first switch tube N1 is electrically connected to the level conversion module 20, and the control end of the first switch tube N1 is electrically connected to the timing controller 11.

[0077] The first switch N1 is turned on in response to the control signal output by the timing controller 11, and outputs the operating voltage V_H to the level conversion module 20 through the second connection terminal. The trigger signal is the operating voltage V_H received by the first voltage terminal.

[0078] Exemplarily, the voltage of the trigger signal is between 1.8V and 3.3V.

[0079] Furthermore, the trigger signal output circuit 12 further includes a third resistor R3 , and the third resistor R3 is electrically connected between the second connection terminal of the first switch tube N1 and the ground.

[0080] The first switch N1 is a low-level conductive switch, and the control signal is a low-level signal. During operation, upon determining that the display panel 200 is in the power-on state, the timing control module 10 outputs a high-level signal to the control terminal of the first switch N1, thereby turning off the first switch N1. The second connection terminal of the first switch N1 is grounded via the third resistor R3 and is at ground potential, i.e., the trigger signal is not output.

[0081] For example, the first switch N1 includes at least one of a MOSFET (metal-oxide-semiconductor field-effect transistor), an IGBT (insulated gate bipolar transistor), a silicon carbide switch device, a thyristor switch device, and a gallium arsenide switch device. Figure 5 As shown, the first switch tube N1 is a PMOS.

[0082] In other embodiments, the timing controller 11 may directly output the trigger signal without setting the trigger signal output circuit 12. In this case, the timing controller 11 outputs a high-level signal (i.e., the trigger signal) to the level conversion module 20 when determining that the display panel 200 is turned off, and outputs a low-level signal to the level conversion module 20 when determining that the display panel 200 is in the power-on state, which is equivalent to not outputting the trigger signal.

[0083] See also Figure 6 , Figure 6 Schematic diagram of the circuit structure of the level conversion module provided in an embodiment of the present application. The level conversion module 20 includes a low voltage control unit 21, wherein the low voltage control unit 21 includes a second voltage terminal V2 and a second switch tube QB.

[0084] The second voltage terminal V2 is used to receive a high-level voltage VGH.

[0085] The second switch transistor QB includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the second switch transistor QB is electrically connected to the second voltage terminal V2, and the second connection terminal of the second switch transistor QB is electrically connected to the display panel 200. The second switch transistor QB is turned on based on the trigger signal output by the timing control module 10 and outputs the high-level voltage VGH to the display panel 200 through the second connection terminal. The full-on function signal is the high-level voltage VGH received by the second voltage terminal.

[0086] Exemplarily, the high-level voltage VGH has a voltage value of 30V.

[0087] Furthermore, the level conversion module 20 further includes a clock signal output unit 22, which is electrically connected between the low-voltage control unit 21 and the display panel 200. In response to the full-on function signal output by the low-voltage control unit 21, the clock signal output circuit outputs clock signals CK1 to CKn with a constant voltage value of the high-level voltage VGH to the display panel 200, so as to control the multiple pixel units P in the display panel 200 to discharge charge.

[0088] Furthermore, the level conversion module 20 further includes a third switch tube QA, a first resistor R1 and a second resistor R2.

[0089] The third switch tube QA includes a first connection end, a second connection end, and a control end. The first connection end of the third switch tube QA is grounded, and the control end of the third switch tube QA is electrically connected to the timing controller 11 .

[0090] The first resistor R1 is electrically connected between the control terminal of the second switch tube QB and the second voltage terminal V2.

[0091] The second resistor R2 is electrically connected between the control terminal of the second switch tube QB and the second connection terminal of the third switch tube QA.

[0092] The third switch tube QA is turned on in response to the trigger signal output by the timing controller 11 , so that the control terminal of the second switch tube QB is grounded through the second resistor R2 and the third switch tube, thereby turning on the second switch tube QB.

[0093] The second switch transistor QB is a switch transistor that conducts at a high level, and the third switch transistor QA is a switch transistor that conducts at a low level. The threshold voltage of the third switch transistor QA is lower than the preset voltage. The third switch transistor QA is turned on when the voltage at the control terminal is higher than the threshold voltage, and is turned off when the voltage at the control terminal is lower than the threshold voltage.

[0094] For example, the second switch tube QB and the third switch tube QA include at least one of MOSFET, IGBT, silicon carbide switch device, thyristor switch device, and gallium arsenide switch device. Figure 6 As shown, the second switch tube QB is a PMOS and the third switch tube QA is an NMOS.

[0095] During operation, when the display panel 200 is powered on, the third switch QA does not receive the trigger signal and is turned off, thereby electrically connecting the control terminal of the second switch QB to the second voltage terminal V2 via the first resistor R1. Since the control terminal of the second switch QB is at a high level, the second switch QB is turned off, and the clock signal output unit 22 normally outputs the clock signals CK1 to CKn based on the gate timing signal. When the display panel 200 is powered off, the third switch QA receives the trigger signal and is turned on, thereby causing the voltage at the control terminal of the second switch QB to be the voltage obtained by dividing the high-level voltage VGH by the first resistor R1 and the second resistor R2. Since the control terminal of the second switch QB is at a low level, the second switch QB is turned on and outputs the full-on function signal to the clock signal output unit 22, causing the clock signal output unit 22 to output clock signals CK1 to CKn with a constant voltage value of the high-level voltage VGH, thereby controlling the multiple pixel units P in the display panel 200 to discharge charge.

[0096] In this way, by providing the third switch tube QA, the low voltage trigger signal output by the timing control module 10 can be used to control the second switch tube QB to output the high level voltage VGH, thereby further saving energy consumption.

[0097] Please refer again Figure 1 Based on the same inventive concept, the present application also provides a display device 1, which includes a display panel 200 and a driving circuit 100 described in any one of the above embodiments, and the driving circuit 100 is electrically connected to the display panel 200.

[0098] Among them, the display device 1 can be a liquid crystal display device (Liquid Crystal Display, LCD), an organic light emitting display device (Organic Light Emitting Diode, OLED), a quantum dot light emitting display device (Quantum Dot Light Emitting Display, QLED) and a micro light emitting display device (Mini / Micro Light Emitting Display, MLED) or an active-matrix organic light emitting diode (Active-Matrix Organic Light Emitting Diode, AMOLED) display device.

[0099] The display device 1 provided in the present application outputs a trigger signal to the level conversion module 20 through the timing control module 10 when monitoring that the display panel 200 is turned off, triggering the level conversion module 20 to output a full-on function signal to control the multiple pixel units P in the display panel 200 to discharge charge. Compared with the method in which the level conversion module 20 turns on the XON function according to the drop of VDD to uvlo (F), it can ensure that the timing of the timing control module 10 and the level conversion module 20 are consistent when shutting down, which can improve the shutdown ghosting problem.

[0100] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A driving circuit for driving a display panel, wherein the display panel comprises a plurality of pixel units, characterized in that: The driving circuit includes: a timing control module, configured to monitor whether the display panel is powered off, and output a trigger signal when determining that the display panel is powered off; and a level conversion module, electrically connected to the timing control module and the display panel, the level conversion module outputting a full-on function signal in response to a trigger signal output by the timing control module, the full-on function signal being used to control the plurality of pixel units in the display panel to discharge charge; The timing control module is configured to receive an operating voltage, determine whether the display panel is turned off based on a rate of decrease of the operating voltage, and determine that the display panel is turned off when the rate of decrease of the operating voltage is greater than a preset rate; The level conversion module includes a low voltage control unit, and the low voltage control unit includes: A second voltage terminal, configured to receive a high level voltage; and a second switching transistor, comprising a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal of the second switching transistor is electrically connected to the second voltage terminal, and the second connection terminal of the second switching transistor is electrically connected to the display panel; the second switching transistor is turned on based on the trigger signal output by the timing control module, and outputs the high-level voltage to the display panel through the second connection terminal; wherein the full-on function signal is the high-level voltage received by the second voltage terminal; The level conversion module further includes: a third switch tube, the third switch tube comprising a first connection end, a second connection end, and a control end, the first connection end of the third switch tube being grounded, and the control end of the third switch tube being electrically connected to the timing control module; a first resistor, electrically connected between the control terminal of the second switch tube and the second voltage terminal; and a second resistor, electrically connected between the control terminal of the second switch tube and the second connection terminal of the third switch tube; The third switch tube is turned on in response to the trigger signal output by the timing control module, so that the control terminal of the second switch tube is grounded through the second resistor and the third switch tube, thereby turning on the second switch tube; The threshold voltage of the third switch tube is lower than a preset voltage; the third switch tube is turned on when the voltage at the control terminal is higher than the threshold voltage, and is turned off when the voltage at the control terminal is lower than the threshold voltage; The level conversion module also includes a clock signal output unit, which is electrically connected between the low-voltage control unit and the display panel; the clock signal output circuit responds to the full-on function signal output by the low-voltage control unit, and outputs a clock signal with a constant voltage value of the high-level voltage to the display panel to control the multiple pixel units in the display panel to discharge charge.

2. The driving circuit according to claim 1, wherein: The timing control module is used to receive the operating voltage, monitor whether the display panel is turned off according to the change of the operating voltage, and determine that the display panel is turned off when the operating voltage drops below a preset voltage, and output the trigger signal.

3. The driving circuit according to claim 2, wherein: The timing control module includes: A first voltage terminal, configured to receive the operating voltage; a timing controller electrically connected to the first voltage terminal, configured to monitor whether the display panel is turned off according to changes in the operating voltage received by the first voltage terminal, and to determine that the display panel is turned off when the operating voltage drops below a preset voltage threshold, and to output a control signal; and The trigger signal output circuit is electrically connected to the timing controller and the level conversion module. The trigger signal output circuit outputs the trigger signal to the level conversion module in response to the control signal output by the timing controller.

4. The driving circuit according to claim 3, wherein: The trigger signal output circuit includes a first switching tube, which includes a first connection end, a second connection end, and a control end. The first connection end of the first switching tube is electrically connected to the first voltage end, the second connection end of the first switching tube is electrically connected to the level conversion module, and the control end of the first switching tube is electrically connected to the timing controller. The first switching tube is turned on in response to a control signal output by the timing controller and outputs the operating voltage to the level conversion module through the second connection end. The trigger signal is the operating voltage received by the first voltage end.

5. The driving circuit according to claim 3, wherein: The timing controller is configured to output a gate timing signal to the level conversion module when the display panel is in a power-on state, and stop outputting the gate timing signal when it is determined that the display panel is powered off.

6. A display device, characterized in that: include: Display panel; as well as The driving circuit according to any one of claims 1 to 5, wherein the driving circuit is electrically connected to the display panel.

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