An integrated circuit device and a manufacturing method thereof

Abstract

The embodiments of the present application disclose an integrated circuit device and a method for manufacturing the same, which relate to the field of semiconductor packaging technology and can effectively improve the heat dissipation capacity of integrated circuits. The integrated circuit device includes: a packaging substrate, an adapter board, a first chip and a heat dissipation cover; wherein the packaging substrate includes a substrate and a first conductive layer and a heat dissipation layer formed on the first side of the substrate; the adapter board is connected to the first side of the packaging substrate, and a rewiring layer and a conductive connector are formed on the adapter board, and the rewiring layer is connected to the first conductive layer on the packaging substrate through the conductive connector; the first chip is connected to the first side of the adapter board and is connected to the rewiring layer on the adapter board; wherein the first side of the adapter board is the side of the adapter board facing away from the packaging substrate; the heat dissipation cover is connected to the first side of the packaging substrate; the adapter board and the first chip are located in the heat dissipation cover; the heat dissipation layer is connected to the heat dissipation cover. The present invention is applicable to semiconductor packaging scenarios.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and particularly relates to an integrated circuit device and a manufacturing method thereof. Background Art

[0002] With the increasing requirements for high performance, small size, and high reliability of integrated circuit devices, the market demand for advanced packaging technology is becoming stronger and stronger. However, the stacking of chips in integrated circuit devices poses a great challenge to heat dissipation. For example, multiple chip modules stacked within an integrated circuit device will cause heat accumulation, greatly increasing the heat flux density per unit area. If effective heat dissipation means are not adopted, it will inevitably affect the reliability of the integrated circuit device.

[0003] In current mainstream integrated circuit devices, the main heat dissipation path is upward, and the heat dissipation ability is poor. Summary of the Invention

[0004] To solve the problem of poor heat dissipation ability of existing integrated circuit devices, this application provides an integrated circuit device with good heat dissipation performance and a manufacturing method thereof.

[0005] In a first aspect, an embodiment of the present invention provides an integrated circuit device, including: a packaging substrate, the packaging substrate includes a substrate and a first conductive layer and a heat dissipation layer formed on a first side of the substrate; an interposer, the interposer is connected to the first side of the packaging substrate, and a redistribution layer and a conductive connection member are formed on the interposer, and the redistribution layer is connected to the first conductive layer on the packaging substrate through the conductive connection member; a first chip, the first chip is connected to the first side of the interposer and is connected to the redistribution layer on the interposer; wherein, the first side of the interposer is the side of the interposer facing away from the packaging substrate; a heat dissipation cover, the heat dissipation cover is connected to the first side of the packaging substrate; the interposer and the first chip are located within the heat dissipation cover; the heat dissipation layer is connected to the heat dissipation cover.

[0006] In a specific implementation, a first thermal conductive layer is provided between the heat dissipation layer and the heat dissipation cover, and the heat dissipation layer is connected to the heat dissipation cover through the first thermal conductive layer; and / or, a first thermal conductive material is provided between the first chip and the heat dissipation cover.

[0007] In a specific implementation, the heat dissipation cover includes a top cover portion and a side wall portion; the side wall portion is located on one side of the top cover portion and is connected to the top cover portion, and the top cover portion and the side wall portion enclose a cavity with an opening at one end; the heat dissipation cover is connected to the packaging substrate through the side wall portion; the first thermal conductive layer is provided between the heat dissipation layer and an end face of the side wall portion.

[0008] In a specific embodiment, a solder mask layer is formed on the first side of the first conductive layer and the heat dissipation layer, wherein the first side of the first conductive layer and the heat dissipation layer is the side of the first conductive layer and the heat dissipation layer facing away from the substrate; the solder mask layer includes a first opening and a second opening; the first opening corresponds to the first conductive layer to expose the first conductive layer, and the second opening corresponds to at least a part of the heat dissipation layer to expose at least a part of the heat dissipation layer.

[0009] In a specific embodiment, the heat dissipation layer and the first conductive layer are on the same layer.

[0010] In a specific embodiment, electrical insulation is provided between the heat dissipation layer and the first conductive layer; wherein, the heat dissipation layer and the first conductive layer are of an integral structure, or the heat dissipation layer and the first conductive layer are of a split structure.

[0011] In a specific embodiment, the heat dissipation layer is provided with heat dissipation fins extending in the direction towards the adapter board, and the heat dissipation fins extend into the space between the package substrate and the adapter board.

[0012] In a specific embodiment, the integrated circuit device further includes a second chip, the second chip is connected to the second side of the adapter board and is connected to the redistribution layer on the adapter board, wherein the second side of the adapter board is the side of the adapter board facing the package substrate; the second chip is adjacent to the heat dissipation layer, and a second thermal conductive material is provided between the second chip and the heat dissipation layer.

[0013] In a specific embodiment, the material of the heat dissipation layer includes copper, aluminum, aluminum alloy, nickel or ceramic.

[0014] In a second aspect, an embodiment of the present invention further provides a method for manufacturing an integrated circuit device, the method for manufacturing the integrated circuit device includes: manufacturing a package assembly; the package assembly includes an adapter board and a first chip connected to the first side of the adapter board, the first chip is connected to the redistribution layer on the adapter board; bonding the package assembly to a package substrate; the package substrate includes a substrate and a first conductive layer and a heat dissipation layer formed on the first side of the substrate; the package assembly is connected to the first conductive layer; wherein, the first side of the adapter board is the side of the adapter board facing away from the package substrate; bonding a heat dissipation cover to the package substrate; the package assembly is located inside the heat dissipation cover, and the heat dissipation layer is connected to the heat dissipation cover.

[0015] In a specific embodiment, the bonding of the heat dissipation cover to the packaging substrate includes: forming a first heat-conducting layer on the heat dissipation layer, and bonding the heat dissipation cover to the packaging substrate through the first heat-conducting layer; and / or forming a first heat-conducting material between the heat dissipation cover and the first chip, and connecting the heat dissipation cover to the first chip through the first heat-conducting material.

[0016] In a specific embodiment, before bonding the packaging component to the packaging substrate, the manufacturing method further includes: manufacturing a packaging substrate; the manufacturing of the packaging substrate includes: forming a first conductive layer and a heat dissipation layer on a first side of a substrate; forming a solder mask layer on a first side of the first conductive layer and the heat dissipation layer; the solder mask layer has a first opening and a second opening, the first opening corresponds to the first conductive layer to expose the first conductive layer, and the second opening corresponds to at least a partial area of the heat dissipation layer to expose at least a partial area of the heat dissipation layer.

[0017] In a specific embodiment, the forming of the first conductive layer and the heat dissipation layer on the first side of the substrate includes: forming the first conductive layer and the heat dissipation layer on the same layer on the first side of the substrate.

[0018] In a specific embodiment, the forming of the first conductive layer and the heat dissipation layer on the same layer on the first side of the substrate includes: forming a first conductive layer and a heat dissipation layer that are electrically insulated from each other on the same layer on the first side of the substrate; wherein, the heat dissipation layer and the first conductive layer are of an integral structure, or the heat dissipation layer and the first conductive layer are of a split structure.

[0019] In a specific embodiment, the manufacturing of the packaging component includes: manufacturing an interposer, on which a redistribution layer and conductive connectors are formed; bonding a first chip to a first side of the interposer and connecting it to the redistribution layer on the interposer; bonding a second chip to a second side of the interposer and connecting it to the redistribution layer on the interposer; wherein, the bonding of the packaging component to the packaging substrate includes: connecting the redistribution layer on the interposer to the first conductive layer on the packaging substrate through the conductive connectors; wherein, the first side of the interposer is the side of the interposer facing away from the packaging substrate, and the second side of the interposer is the side of the interposer facing the packaging substrate; the second chip is located between the interposer and the packaging substrate, and the second chip is adjacent to the heat dissipation layer on the packaging substrate.

[0020] In a specific embodiment, the bonding of the packaging component to the packaging substrate further includes: forming a second heat-conducting material on the heat dissipation layer, and connecting the heat dissipation layer to the second chip through the second heat-conducting material.

[0021] An integrated circuit device and a manufacturing method thereof provided by an embodiment of the present invention include a packaging substrate, an interposer, a first chip, and a heat sink cover. The packaging substrate includes a substrate, a first conductive layer, and a heat dissipation layer formed on a first side of the substrate. The interposer is connected to the first side of the packaging substrate, and a redistribution layer and a conductive connection member are formed on the interposer. The redistribution layer is connected to the first conductive layer on the packaging substrate through the conductive connection member. In addition, the first chip is connected to the first side of the interposer and is connected to the redistribution layer on the interposer. Wherein, the first side of the interposer is the side of the interposer facing away from the packaging substrate. The heat sink cover is connected to the first side of the packaging substrate. And the interposer and the first chip are located inside the heat sink cover. The heat dissipation layer is connected to the heat sink cover. The integrated circuit device absorbs and conducts the heat generated and accumulated between the packaging substrate and the interposer to the heat sink cover through the heat dissipation layer, so as to realize three-dimensional heat dissipation for the space range on both the upper and lower sides of the interposer connecting the chip, and make the integrated circuit device have better heat dissipation performance. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 A schematic diagram of an integrated circuit device provided by an embodiment of the present application;

[0024] Figure 2 A schematic diagram of heat dissipation of an integrated circuit device provided by an embodiment of the present application;

[0025] Figure 3 A schematic diagram of the process flow of a manufacturing method of an integrated circuit device provided by an embodiment of the present application;

[0026] Figure 4a A schematic diagram of assembling the first chip in a manufacturing method of an integrated circuit device provided by an embodiment of the present application;

[0027] Figure 4b A schematic diagram of assembling the second chip in a manufacturing method of an integrated circuit device provided by an embodiment of the present application;

[0028] Figure 4c A schematic diagram of assembling the packaging substrate in a manufacturing method of an integrated circuit device provided by an embodiment of the present application;

[0029] Figure 4d A schematic diagram of assembling the heat sink cover in a manufacturing method of an integrated circuit device provided by an embodiment of the present application.

[0030] Description of main reference numerals:

[0031] 1-integrated circuit device; 10-package substrate; 100-substrate; 101-first conductive layer; 102-heat dissipation layer; L1-first interconnection structure; 20-rewiring layer; 30-first chip; 40-heat dissipation cover; 401-top cover; 402-side surrounding part; 50-first thermal conductive layer; 60-first thermal conductive material; 70-solder resist layer; 80-second chip; 90-second thermal conductive material. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] In view of the problem that the main heat dissipation path of current integrated circuit devices is upward heat dissipation and the heat dissipation capacity is poor, the embodiments of the present invention provide an integrated circuit device with better heat dissipation performance and a manufacturing method thereof.

[0035] First, as Figure 1 As shown, an embodiment of the present invention provides an integrated circuit device 1 , which may include a packaging substrate 10 , a transfer board, a first chip 30 and a heat dissipation cover 40 .

[0036] The packaging substrate 10 includes a substrate 100 and a first conductive layer 101 and a heat dissipation layer 102 formed on a first side of the substrate 100; wherein the substrate 100 may include doped or undoped silicon, or other semiconductor materials such as germanium, etc., and other substrates 100 such as ceramics may also be used.

[0037] In some embodiments, a first interconnect structure L1 (also referred to as an upper interconnect structure) may be formed on the first side surface of the substrate 100. The first interconnect structure L1 may include one or more dielectric layers. The dielectric layer is formed of a dielectric material. The dielectric material may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. Specifically, the dielectric layer may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The first conductive layer 101 and the heat dissipation layer 102 may be formed on the topmost dielectric layer. A conductive layer (such as a wire) may also be formed between the upper and lower adjacent dielectric layers. The conductive layers between the dielectric layers may be connected by conductive vias.

[0038] When forming the first conductive layer 101 on the topmost dielectric layer, a conductive material can be deposited as a metal thin film layer on the topmost dielectric layer through a deposition technique such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) process, and then the first conductive layer 101 is formed on the metal thin film layer by using photolithography and etching techniques. The conductive material can include copper, silver, gold, tungsten, aluminum, or a combination thereof, etc.

[0039] When forming the heat dissipation layer 102 on the topmost dielectric layer, a heat conductive material can be used to form the heat dissipation layer 102 on the topmost dielectric layer by adopting the same or similar process as that for forming the first conductive layer 101. The heat conductive material used for the heat dissipation layer 102 can include copper, aluminum, aluminum alloy, nickel, or ceramic, etc. Among them, the thickness of the heat dissipation layer 102 can be the same as or different from the thickness of the first conductive layer 101. In some embodiments, the thickness of the heat dissipation layer 102 is greater than the thickness of the first conductive layer 101, which can enable the heat dissipation layer 102 to have better heat dissipation and / or heat conduction efficiency; the width of the heat dissipation layer 102 is greater than the width of the first conductive layer 101, which can also enable the heat dissipation layer 102 to have better heat dissipation and / or heat conduction efficiency. The thickness of the above-mentioned heat dissipation layer 102 refers to the dimension of the heat dissipation layer 102 in the direction perpendicular to the first side surface of the packaging substrate 10, and the width of the heat dissipation layer 102 refers to the dimension of the heat dissipation layer 102 in the direction parallel to the first side surface of the packaging substrate 10.

[0040] The interposer is connected to the first side of the packaging substrate 10, and a redistribution layer 20 (Redistribution layer, RDL) and conductive connectors are formed on the interposer. The redistribution layer 20 is connected to the first conductive layer 101 on the packaging substrate 10 through the conductive connectors. Among them, the redistribution layer 20 is used to re - distribute the electrical connections of the integrated circuit device 1. For example, a patterned metal layer can be created on the top of the dielectric layer of the interposer, and this metal layer can re - distribute the input / output (I / O) of the integrated circuit to a new, more spacious position, forming a surface array layout. The new position is usually located at the edge of the chip, so that the chip can be placed in a compact and efficient manner, reducing the overall size of the device. The conductive connectors include suitable metals such as copper, etc., so as to form copper pillars or bumps, etc. The redistribution layer 20 can then be connected to the first conductive layer 101 on the packaging substrate 10 through the conductive connectors, such as electrical connection or communication connection, etc.

[0041] The first chip 30 is connected to the first side of the interposer and is connected to the redistribution layer 20 on the interposer; wherein, the first side of the interposer is the side of the interposer facing away from the package substrate 10. The first chip 30 can be flip-chip mounted on the first side of the interposer. The first chip 30 can also be referred to as the first wafer or the first die, and it can be a logic chip (such as a central processing unit, a graphics processing unit, a system-on-chip, an application processor, a microcontroller, etc.), a memory chip (such as a dynamic random access memory chip, a static random access memory chip, etc.), a power management chip (such as a power management integrated circuit chip), a radio frequency chip, a sensor chip, a microelectromechanical system chip, a signal processing chip (such as a digital signal processing chip), etc.

[0042] The heat sink cover 40 is connected to the first side of the package substrate 10. The interposer and the first chip 30 are located inside the heat sink cover 40; the heat dissipation layer 102 is connected to the heat sink cover 40, wherein the heat dissipation layer 102 can be located within the covering range of the heat sink cover 40 to achieve a compact structural space, or according to specific application scenarios, the heat dissipation layer 102 can also extend beyond the covering range of the heat sink cover to further improve the absorption speed of the heat generated and accumulated between the package substrate 10 and the interposer. A thermal conductive material such as thermal grease can be provided between the top surface of the first chip 30 and the inner side surface of the top of the heat sink cover 40 to quickly conduct the heat generated by the first chip 30 to the heat sink cover 40, and the heat sink cover 40 can be made of a metal material such as aluminum, aluminum alloy, or copper, etc.

[0043] The integrated circuit device 1 provided by the embodiment of the present invention includes a package substrate 10, an interposer, a first chip 30, and a heat sink cover 40. The package substrate 10 includes a substrate 100 and a first conductive layer 101 and a heat dissipation layer 102 formed on the first side of the substrate 100; the interposer is connected to the first side of the package substrate 10, and a redistribution layer 20 and a conductive connection member are formed on the interposer, and the redistribution layer 20 is connected to the first conductive layer 101 on the package substrate 10 through the conductive connection member; in addition, the first chip 30 is connected to the first side of the interposer and is connected to the redistribution layer 20 on the interposer; wherein, the first side of the interposer is the side of the interposer facing away from the package substrate 10; the heat sink cover 40 is connected to the first side of the package substrate 10; and the interposer and the first chip 30 are located inside the heat sink cover 40; the heat dissipation layer 102 is connected to the heat sink cover 40. The device absorbs and conducts the heat generated and accumulated between the package substrate 10 and the interposer through the heat dissipation layer 102 to the heat sink cover 40, so as to realize three-dimensional heat dissipation for the space range on both the upper and lower sides of the interposer connecting the chips, and make the integrated circuit device 1 have good heat dissipation performance.

[0044] The heat dissipation layer 102 and the heat dissipation cover 40 can be directly in contact connection. However, considering that when the heat dissipation layer 102 and the heat dissipation cover 40 are in direct contact connection, the contact connection is not tight enough due to the uneven contact surfaces of the two, resulting in possible gaps between the two, which may lead to heat conduction blockage. Therefore, optionally, in an embodiment of the present invention, a first heat conducting layer 50 is provided between the heat dissipation layer 102 and the heat dissipation cover 40, and the heat dissipation layer 102 is connected to the heat dissipation cover 40 through the first heat conducting layer 50. The first heat conducting layer 50 can be made of materials with high heat conduction efficiency such as thermal grease, so as to fill the gap between the contact parts of the heat dissipation layer 102 and the heat dissipation cover 40 and form a reliable heat transfer path between the two. Similarly, a first heat conducting material 60 such as thermal grease can also be provided between the first chip 30 and the heat dissipation cover 40 to form a reliable heat transfer path between the first chip 30 and the heat dissipation cover 40.

[0045] In order to increase the heat dissipation area of the heat dissipation cover 40 and form a three-dimensional heat dissipation mode for the integrated circuit device 1, optionally, in an embodiment of the present invention, the heat dissipation cover 40 includes a top cover portion 401 and a side enclosure portion 402; the side enclosure portion 402 is located on one side of the top cover portion 401 and is connected to the top cover portion 401, and the top cover portion 401 and the side enclosure portion 402 enclose a cavity with an opening at one end; the heat dissipation cover 40 is connected to the packaging substrate 10 through the side enclosure portion 402; a first heat conducting layer 50 is provided between the heat dissipation layer 102 and the end face of the side enclosure portion 402.

[0046] With this structural design of the heat dissipation cover 40, as Figure 2 shown, a heat dissipation path located in the upper part can be formed between the inner side surface of the top cover portion 401 and the top surface of the first chip 30, and another heat dissipation path located in the lower part can be formed between the side enclosure portion 402 and the heat dissipation layer 102, thus forming a three-dimensional heat dissipation structure. In addition, considering that the heat dissipation cover 40 can have multiple side enclosure portions 402, for example, a cavity structure composed of four side enclosure portions 402 and a top cover portion 401, it can have heat dissipation surfaces formed by the four side enclosure portions 402 and the heat dissipation surface formed by the top cover portion 401. Obviously, the heat dissipation surface of this structure is much larger than the heat dissipation surface formed only by the top cover portion 401 in the traditional structure. Therefore, this structural design of the heat dissipation cover 40 in this embodiment can greatly improve the heat dissipation ability of the integrated circuit device 1. Further, in some embodiments, the shape of the side enclosure portion 402 of the heat dissipation cover 40 can be optimized to be wavy or corrugated to further increase the heat dissipation area and improve the heat dissipation efficiency of the integrated circuit device 1.

[0047] Optionally, in an embodiment of the present invention, a solder mask layer 70 is formed on the first side of the first conductive layer 101 and the heat dissipation layer 102. Here, the first side of the first conductive layer 101 and the heat dissipation layer 102 is the side of the first conductive layer 101 and the heat dissipation layer 102 facing away from the substrate 100. The solder mask layer 70 includes a first opening and a second opening. The first opening corresponds to the first conductive layer 101 to expose the first conductive layer 101, and the second opening corresponds to at least a part of the heat dissipation layer 102 to expose at least a part of the heat dissipation layer 102. The solder mask layer 70 is also called a solder resist layer, which can prevent solder from overflowing when a transfer board or other devices are soldered to the packaging substrate 10, causing a short circuit in the circuit board on the packaging substrate 10, thereby preventing pollution sources from the environment or outside and effectively protecting the circuit on the packaging substrate 10.

[0048] To improve the packaging efficiency, optionally, in an embodiment of the present invention, the heat dissipation layer 102 and the first conductive layer 101 are on the same layer. The heat dissipation layer 102 and the first conductive layer 101 being on the same layer facilitates the formation of the heat dissipation layer 102 and the first conductive layer 101 in one process, improving the production and processing efficiency.

[0049] Optionally, in an embodiment of the present invention, the heat dissipation layer 102 and the first conductive layer 101 are electrically insulated from each other. For example, a predetermined gap may be provided between the heat dissipation layer 102 and the first conductive layer 101 to achieve electrical insulation therebetween to meet specific performance requirements. Among them, the heat dissipation layer 102 and the first conductive layer 101 may be an integral structure to improve the integration degree of the component structure; or, the heat dissipation layer 102 and the first conductive layer 101 are a split structure to achieve a more economical processing cost.

[0050] In some embodiments, the heat dissipation layer 102 may have heat dissipation fins extending in the direction towards the transfer board, and the heat dissipation fins extend into the space between the packaging substrate 10 and the transfer board, thereby further optimizing the heat conduction mode, forming a more direct and efficient heat dissipation path and a more sufficient heat absorption and dissipation area, so as to quickly conduct the heat between the packaging substrate 10 and the transfer board to the part of the heat dissipation layer 102 located on the packaging substrate 10, further improving the heat conduction speed and heat dissipation efficiency.

[0051] To make full use of the limited space between the transfer board and the packaging substrate 10 and improve the integration degree of the entire integrated circuit device 1, optionally, in an embodiment of the present invention, the integrated circuit device 1 further includes a second chip 80. The second chip 80 is connected to the second side of the transfer board and is connected to the redistribution layer 20 on the transfer board. Here, the second side of the transfer board is the side of the transfer board facing the packaging substrate 10. The second chip 80 is adjacent to the heat dissipation layer 102, and a second thermal conductive material 90 is provided between the second chip 80 and the heat dissipation layer 102.

[0052] Among them, there can be multiple redistribution layers 20 on the interposer. According to different performance designs and process methods, the second chip 80 and the first chip 30 can be connected to the same redistribution layer 20 of the interposer, or the second chip 80 and the first chip 30 can be connected to different redistribution layers 20 of the interposer. The second thermal conductive material 90 between the second chip 80 and the heat dissipation layer 102 can also be thermal conductive grease, etc.; among them, the heat dissipation layer 102 can include a heat absorption part and a heat conduction part connected to the heat absorption part. The heat absorption part corresponds to the second chip 80 in the up and down position. The heat conduction part is connected or directly connected to the side wall part 402 of the heat dissipation cover 40 through the first thermal conductive layer 50; the second thermal conductive material 90 is arranged between the second chip 80 and the heat absorption part and is in contact with the second chip 80 and the heat absorption part respectively. In this embodiment, due to the setting of the heat dissipation layer 102, the heat generated by the second chip 80 can be conducted upward for heat dissipation by the heat absorption part and the heat conduction part of the heat dissipation layer 102 by the heat dissipation cover 40, and the heat generated by the second chip 80 can also be conducted downward for heat dissipation through the package substrate 10 and the solder balls, thereby expanding the heat dissipation path and improving the heat dissipation ability of the integrated circuit device 1. The surface shape of the heat absorption part is adapted to the shape of the front surface of the second chip 80, and the surface area of the heat absorption part is greater than or equal to the surface area of the front surface of the second chip 80, so as to quickly and fully absorb the heat generated by the second chip 80; in some embodiments, considering that the package substrate 10 may be more sensitive to temperature rise or it is not convenient to arrange the downward heat conduction dissipation path. For example, due to different circuit designs, some package substrates 10 may have fewer solder balls, or the distribution of the solder balls on the package substrate 10 is uneven. The surface shape of the heat conduction part can be strip-shaped, and the surface area of the heat conduction part is smaller than the surface area of the heat absorption part, so as to occupy less surface area of the package substrate 10 and reduce the possibility of the heat conducted by the heat conduction part diffusing to the package substrate 10, thereby conducting most of the heat generated by the second chip 80 upward for heat dissipation by the heat absorption part and the heat conduction part of the heat dissipation layer 102 by the heat dissipation cover 40 and reducing the downward heat conduction dissipation pressure of the package substrate 10.

[0053] In some embodiments, to further make full use of the space between the interposer and the packaging substrate 10 and further improve the integration degree of the entire integrated circuit device 1, a plurality of second chips 80 may be disposed between the interposer and the packaging substrate 10. The plurality of second chips 80 may be linearly arranged on the interposer along a preset direction or arranged circumferentially along the interposer. Among them, the plurality of second chips 80 may be completely identical chips, or may be chips with different functions or structures. The heat dissipation layer 102 may be provided with corresponding heat absorption portions at corresponding positions of each second chip 80. A second heat conductive material 90 may also be provided between each second chip 80 and the corresponding heat absorption portion. After the heat absorption portions corresponding to each second chip 80 absorb the heat at their respective positions, they are jointly conducted to the heat dissipation cover 40 through the heat conduction portion. In this way, the heat absorption efficiency can be enhanced, and the surface area of the packaging substrate 10 occupied can be minimized as much as possible. In the case where the packaging substrate 10 is sensitive to temperature rise or it is not convenient to arrange a downward heat conduction and dissipation path, the possibility of the heat conducted by the heat conduction portion diffusing to the packaging substrate 10 can be reduced. In other embodiments, the heat absorption portions corresponding to each second chip 80 may also conduct the heat absorbed by each of them to the heat dissipation cover 40 through different heat conduction portions respectively. That is to say, each second chip 80 may be provided with an independent heat sink respectively.

[0054] Optionally, in an embodiment of the present invention, the material of the heat dissipation layer 102 includes copper, aluminum, aluminum alloy, nickel, or ceramic, etc.

[0055] In a second aspect, an embodiment of the present invention further provides a manufacturing method of an integrated circuit device 1, which can effectively improve the heat dissipation ability of the integrated circuit.

[0056] As Figure 3 shown, the manufacturing method of the integrated circuit device 1 provided by the embodiment of the present application may include:

[0057] S11. Fabricate a packaging component; the packaging component includes an interposer and a first chip 30 connected to the first side of the interposer, and the first chip 30 is connected to the redistribution layer 20 on the interposer;

[0058] S12. Bond the packaging component to the packaging substrate 10; the packaging substrate 10 includes a substrate 100 and a first conductive layer 101 and a heat dissipation layer 102 formed on the first side of the substrate 100; the packaging component is connected to the first conductive layer 101; wherein, the first side of the interposer is the side of the interposer facing away from the packaging substrate 10;

[0059] S13. Bond the heat dissipation cover 40 to the packaging substrate 10; the packaging component is located inside the heat dissipation cover 40, and the heat dissipation layer 102 is connected to the heat dissipation cover 40.

[0060] The manufacturing method of the integrated circuit device 1 provided by the embodiments of the present invention includes: manufacturing a packaging component; the packaging component includes an interposer and a first chip 30 connected to the first side of the interposer, and the first chip 30 is connected to the redistribution layer on the interposer; bonding the packaging component to a packaging substrate 10; the packaging substrate 10 includes a substrate 100 and a first conductive layer 101 and a heat dissipation layer 102 formed on the first side of the substrate 100; the packaging component is connected to the first conductive layer 101; wherein, the first side of the interposer is the side of the interposer facing away from the packaging substrate 10; bonding a heat dissipation cover 40 to the packaging substrate 10; the packaging component is located within the heat dissipation cover 40, and the heat dissipation layer 102 is connected to the heat dissipation cover 40. This manufacturing method absorbs the heat generated and accumulated between the packaging substrate 10 and the interposer through the heat dissipation layer 102 and conducts it to the heat dissipation cover 40, thereby realizing three-dimensional heat dissipation for the spatial ranges on both the upper and lower sides of the interposer connecting the chips, and improving the heat dissipation performance of the integrated circuit device 1.

[0061] Optionally, in an embodiment of the present invention, step S13 of bonding the heat dissipation cover 40 to the packaging substrate 10 includes: forming a first thermal conductive layer 50 on the heat dissipation layer 102, and bonding the heat dissipation cover 40 to the packaging substrate 10 through the first thermal conductive layer 50; and / or forming a first thermal conductive material 60 between the heat dissipation cover 40 and the first chip 30, and connecting the heat dissipation cover 40 to the first chip 30 through the first thermal conductive material 60.

[0062] Optionally, in an embodiment of the present invention, before step S12 of bonding the packaging component to the packaging substrate 10, the manufacturing method further includes: manufacturing the packaging substrate 10; manufacturing the packaging substrate 10 includes: forming a first conductive layer 101 and a heat dissipation layer 102 on the first side of the substrate 100; forming a solder mask layer 70 on the first side of the first conductive layer 101 and the heat dissipation layer 102; the solder mask layer 70 has a first opening and a second opening, the first opening corresponds to the first conductive layer 101 to expose the first conductive layer 101, and the second opening corresponds to at least a part of the heat dissipation layer 102 to expose at least a part of the heat dissipation layer 102.

[0063] Optionally, in an embodiment of the present invention, forming the first conductive layer 101 and the heat dissipation layer 102 on the first side of the substrate 100 includes: forming the first conductive layer 101 and the heat dissipation layer 102 on the same layer on the first side of the substrate 100.

[0064] Optionally, in an embodiment of the present invention, forming the first conductive layer 101 and the heat dissipation layer 102 on the same layer on the first side of the substrate 100 includes: forming the first conductive layer 101 and the heat dissipation layer 102 that are electrically insulated from each other on the same layer on the first side of the substrate 100; wherein, the heat dissipation layer 102 and the first conductive layer 101 are of an integral structure, or the heat dissipation layer 102 and the first conductive layer 101 are of a split structure.

[0065] Optionally, in an embodiment of the present invention, the step S11 of fabricating an encapsulation component includes: fabricating an interposer on which a redistribution layer 20 and conductive connectors are formed; bonding a first chip 30 to a first side of the interposer and connecting it to the redistribution layer 20 on the interposer; bonding a second chip 80 to a second side of the interposer and connecting it to the redistribution layer 20 on the interposer; wherein, bonding the encapsulation component to an encapsulation substrate 10 includes: connecting the redistribution layer 20 on the interposer to a first conductive layer 101 on the encapsulation substrate 10 through the conductive connectors; wherein, the first side of the interposer is the side of the interposer facing away from the encapsulation substrate 10, and the second side of the interposer is the side of the interposer facing the encapsulation substrate 10; the second chip 80 is located between the interposer and the encapsulation substrate 10, and the second chip 80 is adjacent to a heat dissipation layer 102 on the encapsulation substrate 10.

[0066] Optionally, in an embodiment of the present invention, the step S12 of bonding the encapsulation component to the encapsulation substrate 10 further includes: forming a second thermal conductive material 90 on the heat dissipation layer 102 and connecting the heat dissipation layer 102 to the second chip 80 through the second thermal conductive material 90.

[0067] In summary, as Figures 4a - 4d shown, the present embodiment gives a schematic assembly diagram of a manufacturing method of an integrated circuit device 1:

[0068] As Figure 4a shown, fabricate an encapsulation component, wherein the encapsulation component includes an interposer and a first chip 30 connected to a first side of the interposer, a redistribution layer 20 is formed on the interposer, and the first chip 30 is connected to the redistribution layer 20 on the interposer.

[0069] As Figure 4b shown, bond the second chip 80 to a second side of the interposer and connect it to the redistribution layer 20 on the interposer, and conductive connectors are also provided on the interposer.

[0070] As Figure 4c shown, connect the interposer to the encapsulation substrate 10, wherein the encapsulation substrate 10 includes a substrate 100 and a first conductive layer 101 and a heat dissipation layer 102 formed on a first side of the substrate 100. Specifically, connect the redistribution layer 20 on the interposer to the first conductive layer 101 on the encapsulation substrate 10 through the conductive connectors; the first side of the interposer is the side of the interposer facing away from the encapsulation substrate 10, and the second side of the interposer is the side of the interposer facing the encapsulation substrate 10; the second chip 80 is located between the interposer and the encapsulation substrate 10, and the second chip 80 is adjacent to the heat dissipation layer 102 on the encapsulation substrate 10.

[0071] As Figure 4dAs shown, a first heat-conducting layer 50 is disposed on the heat-dissipating layer 102, and the heat-dissipating cover 40 is joined to the packaging substrate 10 through the first heat-conducting layer 50, such that the packaging assembly is located within the heat-dissipating cover 40, and the heat-dissipating layer 102 is connected to the heat-dissipating cover 40, thereby manufacturing the integrated circuit device 1 having a three-dimensional heat-dissipating capability.

[0072] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0073] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized.

[0074] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the relevant part of the method embodiment for the related content.

[0075] For the convenience of description, the above device is described by dividing it into various units / modules according to functions. Of course, when implementing the present invention, the functions of each unit / module can be realized in one or more software and / or hardware.

[0076] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any change or replacement that can be easily conceived by a person skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An integrated circuit device, characterized in that, include: A packaging substrate, the packaging substrate comprising a substrate and a first conductive layer and a heat dissipation layer formed on a first side of the substrate; An adapter board, the adapter board is connected to the first side of the packaging substrate, a rewiring layer and a conductive connector are formed on the adapter board, and the rewiring layer is connected to the first conductive layer on the packaging substrate through the conductive connector; a first chip, the first chip being connected to a first side of the adapter board and connected to the redistribution layer on the adapter board; wherein the first side of the adapter board is a side of the adapter board facing away from the package substrate; A heat dissipation cover, the heat dissipation cover is connected to the first side of the packaging substrate; the adapter board and the first chip are located in the heat dissipation cover; the heat dissipation layer is connected to the heat dissipation cover; A first heat-conducting layer is provided between the heat-dissipating layer and the heat-dissipating cover, and the heat-dissipating layer is connected to the heat-dissipating cover through the first heat-conducting layer; a first heat-conducting material is provided between the first chip and the heat-dissipating cover; It also includes a second chip, which is connected to the second side of the adapter board and connected to the redistribution layer on the adapter board, wherein the second side of the adapter board is the side of the adapter board facing the packaging substrate; the second chip is adjacent to the heat dissipation layer, and a second thermal conductive material is provided between the second chip and the heat dissipation layer.

2. The integrated circuit device according to claim 1, wherein, The heat dissipation cover comprises a top cover portion and a side surrounding portion; the side surrounding portion is located at one side of the top cover portion and is connected to the top cover portion, and the top cover portion and the side surrounding portion enclose a cavity having an opening at one end; The heat dissipation cover is connected to the packaging substrate through the side surrounding portion; the first heat conducting layer is arranged between the heat dissipation layer and the end surface of the side surrounding portion.

3. The integrated circuit device according to claim 1, characterized in that, A solder resist layer is formed on a first side of the first conductive layer and the heat dissipation layer, wherein the first side of the first conductive layer and the heat dissipation layer is a side of the first conductive layer and the heat dissipation layer facing away from the substrate; The solder resist layer includes a first window and a second window; the first window corresponds to the first conductive layer to expose the first conductive layer, and the second window corresponds to at least a portion of the heat dissipation layer to expose at least a portion of the heat dissipation layer.

4. The integrated circuit device according to claim 1, wherein, The heat dissipation layer and the first conductive layer are located in the same layer.

5. The integrated circuit device according to claim 4, wherein, The heat dissipation layer is electrically insulated from the first conductive layer; wherein the heat dissipation layer and the first conductive layer are an integrated structure, or the heat dissipation layer and the first conductive layer are a separate structure.

6. The integrated circuit device according to claim 1, wherein The heat dissipation layer is provided with heat dissipation fins extending toward the adapter plate, and the heat dissipation fins extend between the packaging substrate and the adapter plate.

7. The integrated circuit device according to claim 1, characterized in that, The material of the heat dissipation layer includes copper, aluminum, aluminum alloy, nickel or ceramic.

8. A method for manufacturing an integrated circuit device, characterized in that, include: Making packaging components; The package assembly includes an adapter board and a first chip connected to a first side of the adapter board, wherein the first chip is connected to a redistribution layer on the adapter board; Bond the encapsulation component to the encapsulation substrate; the encapsulation substrate includes a substrate and a first conductive layer and a heat dissipation layer formed on a first side of the substrate; the encapsulation component is connected to the first conductive layer; wherein, a first side of the interposer is a side of the interposer facing away from the encapsulation substrate; Bond a heat dissipation cover to the encapsulation substrate; the encapsulation component is located within the heat dissipation cover, and the heat dissipation layer is connected to the heat dissipation cover; The bonding of the heat dissipation cover to the encapsulation substrate includes: forming a first heat conductive layer on the heat dissipation layer, bonding the heat dissipation cover to the encapsulation substrate through the first heat conductive layer; forming a first heat conductive material between the heat dissipation cover and the first chip, and connecting the heat dissipation cover to the first chip through the first heat conductive material; The manufacturing of the encapsulation component includes: manufacturing an interposer, on which a redistribution layer and conductive connection members are formed; bonding a first chip to a first side of the interposer and connecting it to the redistribution layer on the interposer; bonding a second chip to a second side of the interposer and connecting it to the redistribution layer on the interposer; Wherein, the bonding of the encapsulation component to the encapsulation substrate includes: connecting the redistribution layer on the interposer to the first conductive layer on the encapsulation substrate through the conductive connection members; wherein, a first side of the interposer is a side of the interposer facing away from the encapsulation substrate, and a second side of the interposer is a side of the interposer facing the encapsulation substrate; the second chip is located between the interposer and the encapsulation substrate, and the second chip is adjacent to the heat dissipation layer on the encapsulation substrate; forming a second heat conductive material on the heat dissipation layer, and connecting the heat dissipation layer to the second chip through the second heat conductive material.

9. The manufacturing method of the integrated circuit device as claimed in claim 8, wherein, Before bonding the encapsulation component to the encapsulation substrate, the manufacturing method further includes: manufacturing the encapsulation substrate; The manufacturing of the encapsulation substrate includes: Forming a first conductive layer and a heat dissipation layer on a first side of the substrate; Forming a solder mask layer on a first side of the first conductive layer and the heat dissipation layer; the solder mask layer has a first opening and a second opening, the first opening corresponds to the first conductive layer to expose the first conductive layer, and the second opening corresponds to at least a partial area of the heat dissipation layer to expose at least a partial area of the heat dissipation layer.

10. The manufacturing method of the integrated circuit device according to claim 9, characterized in that, The forming of the first conductive layer and the heat dissipation layer on the first side of the substrate includes: Forming the first conductive layer and the heat dissipation layer on the same layer on the first side of the substrate.

11. The method for manufacturing an integrated circuit device according to claim 10, wherein, The forming of the first conductive layer and the heat dissipation layer on the same layer on the first side of the substrate includes: Forming a first conductive layer and a heat dissipation layer that are electrically insulated from each other on the same layer on the first side of the substrate; wherein, the heat dissipation layer and the first conductive layer are of an integral structure, or the heat dissipation layer and the first conductive layer are of a split structure.

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