Multi-region gate single-channel microcavity transistor, optoelectronic full logic gate device, control method and circuit

Abstract

The application discloses a kind of based on multi-region grid single channel microcavity transistor, photoelectric full logic gate device, control method and circuit, the full logic gate device includes the substrate, first bottom gate electrode and second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode, top gate dielectric layer, top gate electrode of stacked arrangement, it further includes first laser and second laser.First bottom gate electrode and second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode constitute NOR logic gate;Second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode, top gate dielectric layer, top gate electrode constitute NAND logic gate;Substrate, channel layer, source electrode and drain electrode and first laser and second laser constitute XOR logic gate;The application can realize linear NAND and NOR and nonlinear XOR three kinds of logic functions in single transistor device, reduce transistor consumption and circuit area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a multi-region gate single-channel microcavity transistor, an optoelectronic full-logic gate device, a control method and a circuit. BACKGROUND

[0002] With the rapid development of integrated circuit technology, integrated circuit products are becoming one of the components of people's daily life. As the basic device unit of integrated circuits, transistors are mostly silicon-based devices, and with the increasing demand for integration, the feature size of silicon-based devices is gradually reduced to near its physical limit. In recent years, two-dimensional materials have attracted widespread attention due to their single-atom layer thickness, high carrier mobility, and excellent electrical and optical properties. Reports on two-dimensional material logic devices are also emerging, which are expected to replace silicon-based devices as the next generation of emerging devices.

[0003] Among them, CMOS digital logic circuits are the largest component of integrated circuit chips, and logic gate modules are the core of digital logic circuits. Basic logic gate modules include NAND, NOR, and XOR, and currently NAND is the most basic logic gate, and all digital circuit modules can be built by NAND. According to the CMOS process standard, theoretically, a NAND requires at least 3 transistors, a NOR requires 3 transistors, and an XOR requires 9 transistors; while in actual circuits, a NAND uses 4 transistors, a NOR uses 4 transistors, and an XOR uses 12 transistors. Complex device unit modules make it difficult to reduce circuit power consumption and transistor consumption while improving chip integration.

[0004] Therefore, there is an urgent need for a logic gate unit module that can significantly reduce transistor consumption. There are reports of a two-dimensional material-based transistor, such as patent application CN114188224A, which discloses a semiconductor device and a method for forming the same, which can implement both NAND and NOR logic gates with a single device, but still cannot implement all linear and nonlinear logic gates of NAND, NOR, and XOR with a single transistor device. SUMMARY

[0005] In view of the technical problems existing in the prior art, the primary object of the present application is to provide a multi-region gate single-channel microcavity transistor, an optoelectronic full-logic gate device, a control method and a circuit, which for the first time realizes the completion of the computing functions of all linear and nonlinear logic gates such as NAND, NOR and XOR using a single microcavity transistor, replaces the complex circuit module originally requiring 20 transistors, and greatly reduces the transistor consumption of the digital logic circuit by 90% under the premise of meeting the voltage signal input and output and ensuring the performance of other circuits. It also provides a new possibility for the preparation of transistors and logic devices using two-dimensional materials.

[0006] The present application at least adopts the following technical solutions:

[0007] In one aspect, the present application provides a multi-region gate single-channel microcavity transistor, comprising a substrate, a bottom gate electrode layer, a bottom gate dielectric layer, a channel layer, a source electrode and a drain electrode, a top gate dielectric layer and a top gate electrode arranged in stack.

[0008] The bottom gate electrode layer is arranged on the substrate, and the bottom gate electrode layer comprises a first bottom gate electrode and a second bottom gate electrode, the first bottom gate electrode comprises a first sub-bottom gate electrode and a second sub-bottom gate electrode, and the second bottom gate electrode is arranged between the first sub-bottom gate electrode and the second sub-bottom gate electrode.

[0009] The bottom gate dielectric layer is arranged on the bottom gate electrode, and the bottom gate dielectric layer forms a first cavity structure between the first sub-bottom gate electrode, the second bottom gate electrode and the substrate, and forms a second cavity structure between the second sub-bottom gate electrode, the second bottom gate electrode and the substrate.

[0010] The channel layer is arranged on the bottom gate dielectric layer, and the source electrode and the drain electrode are arranged on the channel layer.

[0011] The top gate dielectric layer is arranged on the source electrode, the drain electrode and the channel layer.

[0012] The top gate electrode is arranged on the top gate dielectric layer.

[0013] The channel layer is a p-type two-dimensional material, and the p-type two-dimensional material exhibits positive photoconductivity and negative photoconductivity under the irradiation of a laser of a first wavelength at different light powers.

[0014] When the first bottom gate electrode and the second bottom gate electrode are respectively applied with a voltage of -3V and 3V, the current state of the drain current satisfies

[0015] When the top gate electrode and the second bottom gate electrode are respectively applied with a voltage of -3V and 3V, the current state of the drain current satisfies

[0016] When the first cavity structure region and the second cavity structure region and the channel layer region overlapping the first cavity structure region and the second cavity structure region in the vertical direction are irradiated with the laser of the first wavelength and the laser of the second wavelength respectively, the current state of the drain current variation quantity satisfies The second wavelength is different from the first wavelength.

[0017] As a preferred scheme of the present application, the p-type two-dimensional material is 2h-MoTe2 material, and the thickness is 15-50 nm.

[0018] The first wavelength is 254-633 nm, and the second wavelength is 635-1550 nm.

[0019] As a preferred scheme of the present application, the thickness of the bottom gate dielectric layer and the top gate dielectric layer is 15-40 nm, and the material of the bottom gate dielectric layer and the top gate dielectric layer is h-BN material.

[0020] As a preferred scheme of the present application, the thickness of the top gate electrode, the first sub-bottom gate electrode, the second sub-bottom gate electrode and the second bottom gate electrode is 30-100 nm.

[0021] The interval between the first sub-bottom gate electrode and the second sub-bottom gate electrode and the second bottom gate electrode is 0.3-3 μm.

[0022] In a second aspect, the present application further provides a photoelectric full logic gate device based on a multi-region gate single channel microcavity transistor, wherein the multi-region gate single channel microcavity transistor is used as the photoelectric full logic gate device, and the multi-region gate single channel microcavity transistor is a single transistor, which realizes NOR logic gate, NAND logic gate and XOR logic gate by taking current signal as output signal.

[0023] As a preferred scheme of the present application, in the realization of the NOR logic gate, the first bottom gate electrode and the second bottom gate electrode are respectively used as the first input end and the second input end of the NOR logic gate, and the source electrode and the drain electrode are both used as the output end of the NOR logic gate.

[0024] As a preferred scheme of the present application, in the realization of the NAND logic gate, the top gate electrode and the second bottom gate electrode are respectively used as the first input end and the second input end of the NAND logic gate, and the source electrode and the drain electrode are both used as the output end of the NAND logic gate.

[0025] As a preferred scheme of the present application, first laser of a first wavelength and second laser of a second wavelength are further included, the second wavelength is different from the first wavelength, the first laser is used for irradiating the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction, and the second laser is used for irradiating the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction.

[0026] In the implementation of the XOR logic gate, the first laser and the second laser are respectively used as the first input end and the second input end of the XOR logic gate, and the source electrode and the drain electrode are both used as the output end of the XOR logic gate.

[0027] In a third aspect, the present application further provides a control method of a photoelectric full logic gate device based on a multi-region gate single-channel microcavity transistor, which is applied to the photoelectric full logic gate device based on a multi-region gate single-channel microcavity transistor described above, the photoelectric full logic gate device includes a NOR logic gate, a NAND logic gate and an XOR logic gate, and the control method includes controlling the photoelectric full logic gate device to realize the following functions:

[0028] Function 1: setting the NAND logic gate to a high resistance state; inputting a first pulse signal to the top gate electrode, the first pulse signal including a high-level pulse signal or a low-level pulse signal, inputting a second pulse signal to the second bottom gate electrode, the second pulse signal including a high-level pulse signal or a low-level pulse signal; inputting a pre-set calculation voltage to the source electrode and the drain electrode; reading the output current of the source electrode or the drain electrode of the NAND logic gate; determining the output level of the NAND logic gate according to the output current to obtain the result of logic calculation;

[0029] Function 2: setting the NOR logic gate to a high resistance state; inputting a first pulse signal to the first bottom gate electrode, the first pulse signal including a high-level pulse signal or a low-level pulse signal, inputting a second pulse signal to the second bottom gate electrode, the second pulse signal including a high-level pulse signal or a low-level pulse signal; inputting a pre-set calculation voltage to the source electrode and the drain electrode; reading the output current of the source electrode or the drain electrode of the NOR logic gate; determining the output level of the NOR logic gate according to the output current to obtain the result of logic calculation;

[0030] Function 3: set the XOR logic gate to a certain blocking state, the certain blocking state is a gate voltage added to the gate electrode when the current reaches the initial set value under the source-drain bias voltage; the first laser with a wavelength of 254-633nm is irradiated or not irradiated to the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction, and the second laser with a wavelength of 635-1550nm is irradiated or not irradiated to the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction, and the first and second lasers are high level pulse signals or low level pulse signals; a pre-set measurement voltage is input to the source electrode and the drain electrode; the output current change value of the source electrode or the drain electrode of the XOR logic gate device is read; and the output level of the XOR logic gate is determined according to the output current change value, so as to obtain the result of logic calculation.

[0031] In a fourth aspect, the present application further provides a photoelectric full logic gate circuit based on a multi-region gate single-channel microcavity transistor, comprising the photoelectric full logic gate device based on a multi-region gate single-channel microcavity transistor as described above, and the photoelectric full logic gate circuit comprises a NOR logic gate circuit, a NAND logic gate circuit and an XOR logic gate circuit.

[0032] Compared with the prior art, the present application has at least the following beneficial effects:

[0033] In the present application, the second bottom gate electrode is arranged between the first and second sub-bottom gate electrodes, that is, the area of the first bottom gate electrode surrounds the second bottom gate electrode, so that the photoelectric full logic gate device with a three-gate transistor structure of the present application only occupies one gate area in the same plane, thereby greatly reducing the size of the logic gate device.

[0034] In the present application, the cavity structure is introduced between the first and second bottom gate electrodes by setting the bottom gate electrode, which avoids the problem of low or no light transmission of metal materials, successfully introduces the input of optical signals in the device structure, makes the optical signals reflect multiple times in the cavity region, increases the absorption of photon energy by the channel material, induces the channel material to break through the energy limit of the barrier more easily to produce positive and negative photoconductive effects, and reduces the laser energy consumption. The present application develops the photoelectric performance of the transistor by introducing the cavity structure and the photoelectric effect of the channel layer material, so that the NAND, NOR and XOR logic gate functions can be realized on a single transistor without relying on additional inverter circuits.

[0035] The application realizes the computing function of three logic gates of linear logic gate NAND, NOR and nonlinear logic gate XOR using a single transistor device, replaces the complex circuit module originally requiring 20 transistors, greatly reduces the transistor consumption of the digital logic circuit by 90% under the premise of meeting the input and output as voltage signals and ensuring the performance of other circuits.

[0036] The device of the application realizes three logic gate circuits of NAND, NOR and XOR on a single transistor, which is not an inverting circuit, only realizes the conversion of current signals to voltage signals, does not realize the inversion of high and low voltage levels, that is, the device itself can realize NAND, NOR and XOR without relying on additional inverting circuits.

[0037] In addition to the logic calculation of electrical signals, the logic device of the application can also perform hybrid logic calculation of optical signals and electrical signals, and logic calculation between optical signals, further expanding the application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is the optical-electric full logic gate device structure based on the multi-region gate single channel microcavity transistor provided by the application.

[0039] Figure 2 is the optical microscope image of the optical-electric full logic gate device based on the multi-region gate single channel microcavity transistor provided by the application.

[0040] Figure 3 is the preparation flowchart of the optical-electric full logic gate device based on the multi-region gate single channel microcavity transistor provided by the application.

[0041] Figure 4 is the transistor circuit diagram for converting the output current signal into a voltage signal provided by the application.

[0042] Figure 5(a) is the V-t graph of the current conversion after the NAND logic calculation provided by the application, and figure 5(b) is the NAND truth table thereof.

[0043] Figure 6(a) is the V-t graph of the current conversion after the NOR logic calculation provided by the application, and figure 6(b) is the NOR truth table thereof.

[0044] Figure 7(a) is the I-t graph of the XOR logic calculation provided by the application, and figure 7(b) is the XOR truth table thereof.

[0045] Marked in the figure: 101: Si substrate; 102: SiO2 substrate; 103: first bottom gate electrode; 104 second bottom gate electrode; 105: bottom gate dielectric layer; 106: channel layer; 107: source electrode; 108: drain electrode; 109 top gate dielectric layer; 110: top gate electrode; 111: first cavity structure; 112: second cavity structure; 201: multi-region gate single-channel microcavity transistor; 202: current-limiting resistor. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application. The described embodiments are only some of the embodiments of the present application, but not all. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0047] Spatially relative terms such as "beneath", "below", "lower", "on", "above", "upper" and the like, are used herein for explaining the position of one element relative to another element as illustrated in the drawings. These terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0048] In addition, terms such as "first", "second", and the like are used to describe various elements, layers, regions, sections, and the like, and are not intended to be limiting. "Have", "contain", "include", "comprise" and the like are open terms, indicating the presence of the stated elements or features, but not excluding additional elements or features. Unless the context clearly indicates otherwise.

[0049] The prior art patent application with publication number CN114188224A discloses a semiconductor device and a forming method thereof, which can realize multiple gate logic functions such as NAND and NOR logic with a single device. In the prior art, the three-gate transistor mode is used as a NAND and NOR switchable logic gate; the channel material is an ultrathin material, and VDD is set to 2V; the voltage signal is used as the input signal, the first bottom gate electrode voltage is the first input, and the second bottom gate electrode voltage is the second input; the logic "1" of the input end is defined as 2V, and the logic "0" is defined as -0.5V; the top gate electrode voltage is a switch for switching the NAND and NOR functions, and the logic "1" of the switch selection end is defined as 2V, corresponding to NOR, and the logic "0" is defined as 0.75V, corresponding to NAND, that is, the three gates all have input signals when the device is working. The device is connected in series with a resistor, the resistor end is connected to VDD, the device end is connected to ground, and the connection point between the device and the resistor is the output end. The voltage signal is used as the output signal, and when the output voltage is higher than VDD / 2, it is defined as the output logic "1", and when the output voltage is lower than VDD / 2, it is defined as the output logic "0". When the input is (0, 0), (0, 1), (1, 0), and (1, 1), the output voltage state respectively meets the NAND and NOR truth table through the top gate switch. However, it should be noted that this circuit connection is a special inverting circuit, and this circuit can convert the current signal output by the device into a voltage signal, and at the same time, the entire circuit module will invert the output signal, changing the high-level signal to a low-level signal or changing the low-level signal to a high-level signal. If the source-drain current is used as the output signal, the actual function realized by the device itself is only AND and OR logic functions and switching, and it cannot realize NAND and NOR logic functions, so it needs to rely on the inverting circuit to obtain.

[0050] And the circuit module is equivalent to 2 transistors, which need to occupy 2 gate areas on the same plane, and at this time the transistor consumption calculation is:

[0051]

[0052] The present application provides a multi-region gate single-channel microcavity transistor, a photoelectric full logic gate device, a control method and a circuit. As Figure 1-7, the present invention realizes a photoelectric full logic gate device with a three-gate transistor structure that only occupies one gate area in the same plane, thereby greatly reducing the size of the logic gate device. The multi-region gate single-channel microcavity transistor of the present invention introduces a cavity structure through the design of the gate electrode, avoiding the problem of metal materials being opaque or having low light transmittance, successfully introducing the input of optical signals into the device structure, and developing related photoelectric applications using the photoelectric effect of two-dimensional materials. The present invention also realizes the use of a single transistor device to complete the calculation functions of three logic gates: linear logic gate NAND, NOR, and nonlinear logic gate XOR, replacing the complex circuit module that originally required 20 transistors. Under the premise of satisfying the input and output as voltage signals and ensuring other circuit performance, it significantly reduces the transistor consumption of the digital logic circuit by 90%. In addition to the logical calculation of electrical signals, the present invention can also perform mixed logical calculations of optical signals and electrical signals, as well as logical calculations between optical signals, further expanding the application scenarios. The above technical solutions of the present invention will be elaborated in detail below.

[0053] Example 1

[0054] like Figures 1-2 As shown, the present invention provides a multi-region gate single-channel microcavity transistor, which includes: a stacked substrate, a first bottom gate electrode 103 and a second bottom gate electrode 104, a bottom gate dielectric layer 105, a channel layer 106, a source electrode 107 and a drain electrode 108, a top gate dielectric layer 109, and a top gate electrode 110. The first bottom gate electrode 103 is composed of a first sub-bottom gate electrode and a second sub-bottom gate electrode, and the second bottom gate electrode 104 is disposed between the first sub-bottom gate electrode and the second sub-bottom gate electrode.

[0055] In an embodiment of the present invention, the second bottom gate electrode 104 is arranged between the first sub-bottom gate electrode and the second sub-bottom gate electrode, and the area region of the first bottom gate electrode surrounds the second bottom gate electrode; the bottom gate dielectric layer is formed on the first bottom gate electrode and the second bottom gate electrode; the channel layer is formed on the bottom gate dielectric layer; the source electrode and the drain electrode are arranged on the channel layer with intervals; the top gate dielectric layer is formed on the source electrode and the drain electrode; and the top gate electrode is formed on the top gate dielectric layer.

[0056] In the embodiment of the present invention, the gap between the first bottom gate electrode and the second bottom gate electrode, together with the bottom gate dielectric layer and the substrate, constitute the first cavity structure 111 and the second cavity structure 112 .

[0057] As a preferred embodiment of the present invention, the material of the bottom gate dielectric layer and the top gate dielectric layer is h-BN, and the thickness ranges from 15 to 40 nm, preferably 30 nm.

[0058] In the embodiment of the present application, the materials of the top gate electrode, the first and second bottom gate electrodes, the source electrode and the drain electrode are metals, and the metal material is preferably Au. The thickness of the top gate electrode, the first and second bottom gate electrodes ranges from 30 to 100 nm, and is preferably 50 nm.

[0059] As a preferred scheme of the present application, the metal material of the top gate electrode, the first and second bottom gate electrodes, and the source and drain electrodes can be replaced by other non-metal materials with high light transmittance and metallic properties, such as Gr, etc., thereby further improving the input range and input efficiency of the optical signal.

[0060] As a preferred scheme of the present application, the interval between the first and second sub-bottom gate electrodes and the second bottom gate electrode ranges from 0.3 to 3 um, and is preferably 3 um. The interval between the first and second bottom gate electrodes determines the formation quality of the cavity structure, and too large or too small interval cannot achieve the cavity quality of the present application. The design of the cavity structure enables the laser irradiated to the transistor structure of the present application to be reflected on the substrate multiple times through the channel layer material, not only increasing the absorption of the photon energy by the channel material and inducing the channel material to break through the energy limit of the barrier more easily to generate the positive and negative photoconductivity effect, but also reducing the energy consumption of the laser.

[0061] In the embodiment of the present application, the channel layer is a p-type two-dimensional material, which exhibits positive and negative photoconductivity effects under the irradiation of laser signals of a specific wavelength at different light powers, and when the first and second bottom gate electrodes are applied with voltages of -3 V and 3 V respectively, the current state of the drain current satisfies When the top gate electrode and the second bottom gate electrode are applied with voltages of -3 V and 3 V respectively, the current state of the drain current satisfies When the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction are irradiated with laser of the first wavelength and laser of the second wavelength respectively, the current state of the drain current variation satisfies The second wavelength is different from the first wavelength.

[0062] The single transistor device of the present application can realize the computing functions of the three logic gates of linear logic gate NAND, NOR and nonlinear logic gate XOR.

[0063] As a preferred scheme of the present application, the material of the channel layer includes 2h-MoTe2 and BP and other possible materials satisfying the above-mentioned channel material characteristics, which are not limited herein.

[0064] In the embodiment of the present application, the channel layer is exemplified by p-type 2h-MoTe2. For a laser wavelength of 633 nm or less, the p-type 2h-MoTe2 two-dimensional material channel layer exhibits positive photoconductivity and negative photoconductivity under irradiation of different optical power lasers, and these characteristics of the p-type 2h-MoTe2 material cannot be possessed or simultaneously possessed by other TMD family two-dimensional materials. The positive and negative photoconductivity is induced by the mechanism of the photo-induced structural phase transition of the p-type 2h-MoTe2 material. The change of the internal structure of the material changes the potential barrier of the carrier input channel, resulting in a change in the resistance of the whole device, so that the current of the loop changes under the bias voltage, and the current change conforms to digital logic calculation.

[0065] In the embodiment, the substrate includes a Si substrate 101 and a SiO2 layer 102 located above the Si substrate 101.

[0066] One embodiment of the present application provides a photoelectric full logic gate device based on a multi-region gate single-channel microcavity transistor, which uses the above-mentioned multi-region gate single-channel microcavity transistor as a photoelectric full logic gate device. The multi-region gate single-channel microcavity transistor is a single transistor, which realizes NOR logic gate, NAND logic gate and XOR logic gate by taking current signal as output signal.

[0067] The present application introduces a cavity structure in the transistor structure, avoids the problem of low light transmittance or no light transmittance of metal materials, successfully introduces the input of optical signals in the device structure, and develops related photoelectric applications by using the photoelectric effect of two-dimensional materials.

[0068] In the embodiment, the photoelectric full logic gate device based on the multi-region gate single-channel microcavity transistor provided by the present application is a three-gate transistor structure as a whole, as shown in Figures 1 to 2 The first bottom gate electrode and the second bottom gate electrode are staggered but not interconnected, and the area region of the first bottom gate electrode surrounds the second bottom gate electrode, that is, the photoelectric full logic gate device of the three-gate transistor structure of the present application only occupies one gate area in the same plane, so that the size of the logic gate device can be greatly reduced.

[0069] Figure 4 is a transistor circuit diagram provided by the present application for converting the output current signal into a voltage signal. As Figure 4As shown, the transistor circuit diagram includes a multi-region gate single-channel microcavity transistor 201 and a current-limiting resistor 202 connected in sequence between a source-drain bias voltage Vds and ground, wherein the multi-region gate single-channel microcavity transistor 201 is connected to a first pulse signal IN1 and a second pulse signal IN2, the first pulse signal includes a high-level pulse signal or a low-level pulse signal, the second pulse signal includes a high-level pulse signal or a low-level pulse signal, and the multi-region gate single-channel microcavity transistor 201 and the current-limiting resistor 202 are connected to a voltage output signal Vout.

[0070] Further, the present application realizes the use of a single transistor device to complete all linear and nonlinear logic gate computing functions of NAND, NOR, and XOR. In the present application, defining the use of a single transistor to realize a NAND logic gate as mode 1, using a single transistor to realize a NOR logic gate as mode 2, and using a single transistor to realize an XOR logic gate as mode 3. The implementation of the three types of NAND, NOR, and XOR logic gates will be described in detail below.

[0071] Mode 1: a NAND logic gate is composed of a second bottom gate electrode, a bottom gate dielectric layer, a channel layer, a source electrode and a drain electrode, a top gate dielectric layer, and a top gate electrode, wherein the top gate electrode and the second bottom gate electrode are used as the first input terminal and the second input terminal of the NAND logic gate, respectively; the source electrode and the drain electrode are used as the output terminal of the NAND logic gate. The specific working process is as follows:

[0072] The top gate electrode is used for inputting a first pulse signal IN1; the first pulse signal includes a high-level pulse signal or a low-level pulse signal; the second bottom gate electrode is used for inputting a second pulse signal IN2; the second pulse signal includes a high-level pulse signal or a low-level pulse signal; wherein the high-level pulse signal is used as the logic value 1 of the NAND logic gate device; the low-level pulse signal is used as the logic value 0 of the NAND logic gate device; the source electrode and the drain electrode are used for outputting a current; the output current is used to determine the result of the NAND logic calculation, wherein the output high-current signal is used as the logic value 1 of the NAND logic gate device; the output low-current signal is used as the logic value 0 of the NAND logic gate device.

[0073] As shown in FIG. 5, in the embodiment of the present application, as shown in FIG. 5(a), the device performs electrical calculation as a NAND logic gate. The voltage signal is the input signal, the logic "1" is defined as 3V, the logic "0" is defined as -3V, the top gate electrode voltage is the first input IN1, and the second bottom gate electrode voltage is the second input IN2. The source-drain current is the output signal, and when the output current signal is in the high current state, it is defined as logic "1", and when the output current signal is in the low current state, it is defined as logic "0". The state distinction between high current and low current satisfies The specific logic calculation process is: bias the drain-source voltage Vds to 1V, and correspondingly apply (-3V, -3V), (-3V, 3V), (3V, -3V), (3V, 3V) voltage states on the top gate electrode and the second bottom gate electrode (110, 104), respectively, corresponding to (0, 0), (0, 1), (1, 0), (1, 1) input signals, to obtain the output current state satisfying the NAND truth table shown in FIG. 5(b). The current output signal has been converted into a voltage output signal through a series resistor.

[0074] It should be noted that in this mode 1, the first bottom gate electrode has no voltage input or voltage set to 0V, and no laser signal input or laser intensity set to 0, i.e. only two input signals of the top gate electrode and the second bottom gate electrode, and no other input signals. When the output current signal is converted into a voltage signal, the device needs to be connected in series with a resistor, the device end is connected to the power supply VDD, the resistor end is grounded, and the connection point between the device and the resistor is the output end. This circuit is not an inverter circuit, only realizes the conversion of current signal into voltage signal, and does not realize the inversion of high and low voltage levels, i.e. the device itself can realize NAND, and does not need the level inversion function of the additional inverter circuit.

[0075] Mode 2: NOR logic gate composed of first bottom gate electrode and second bottom gate electrode, bottom gate dielectric layer, channel layer, source electrode and drain electrode, wherein the first bottom gate electrode and the second bottom gate electrode are respectively as the first input end and the second input end of the NOR logic gate; the source electrode and the drain electrode are both as the output end of the NOR logic gate. The specific working process is as follows:

[0076] The first bottom gate electrode is used for inputting a first pulse signal IN1; the first pulse signal includes a high-level pulse signal or a low-level pulse signal; the second bottom gate electrode is used for inputting a second pulse signal IN2; the second pulse signal includes a high-level pulse signal or a low-level pulse signal; wherein the high-level pulse signal is logic value 1 of the NOR logic gate device; the low-level pulse signal is logic value 0 of the NOR logic gate device; the source electrode and the drain electrode are used for outputting a current; the output current is used for determining the result of NOR logic calculation, wherein the output high-current signal is logic value 1 of the NOR logic gate device; the output low-current signal is logic value 0 of the NOR logic gate device;

[0077] For example, as shown in FIG. 6, in the embodiment of the present application, as shown in FIG. 6(a), the device performs electrical calculation as a NOR logic gate. The voltage signal is the input signal, the logic "1" is defined as 3V, the logic "0" is defined as -3V, the first bottom gate electrode voltage is the first input IN1, and the second bottom gate electrode voltage is the second input IN2. The source-drain current is the output signal, the output current signal is in a high current state, which is defined as logic "1", and the output current signal is in a low current state, which is defined as logic "0". The state distinction between the high current and the low current satisfies The specific logic calculation process is as follows: the drain-source voltage Vds is biased to 1V, and the voltages of (-3V, -3V), (-3V, 3V), (3V, -3V), and (3V, 3V) are applied to the first bottom gate electrode and the second bottom gate electrode (103, 104) respectively, corresponding to the input signals of (0, 0), (0, 1), (1, 0), and (1, 1) respectively. It can be seen that the state of the output current satisfies the NOR truth table shown in FIG. 6(b), and the current output signal has been converted into a voltage output signal through a series resistor.

[0078] It should be noted that in this mode 2, the top gate electrode has no voltage input or is set to 0V, and there is no laser signal input or the laser light intensity is set to 0. That is, there are only two input signals of the first bottom gate and the second bottom gate, and there is no other input signal. When the output current signal is converted into a voltage signal, the device needs to be connected in series with a resistor, the device end is connected to the power supply VDD, the resistor end is connected to the ground, and the connection point between the device and the resistor is the output end. This circuit is not an inverter circuit, only the current signal conversion into voltage signal is realized, and the high and low voltage level inversion is not realized, that is, the device itself can realize NOR, and no additional level inversion function of the inverter circuit is needed.

[0079] Mode 3: The photoelectric full logic gate device of the present application also comprises a first laser with a wavelength of 254nm to 633nm and a second laser with a wavelength of 635nm to 1550nm, the first laser and the second laser irradiate the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction at the same time; the substrate, the channel layer, the source electrode and the drain electrode, and the first laser and the second laser constitute an XOR logic gate; wherein the first laser and the second laser are respectively the first input end and the second input end of the XOR logic gate, and the source electrode and the drain electrode are both the output end of the XOR logic gate. In a preferred embodiment, the wavelength of the first laser is preferably 405nm, and the wavelength of the second laser is preferably 808nm.

[0080] The specific working process of the mode 3 is as follows:

[0081] The first laser with a wavelength of 254nm to 633nm is used to input a first laser pulse signal IN1; the first laser pulse signal includes an on signal or an off signal; the laser with a wavelength of 635-1550nm is used to input a second laser pulse signal IN2; the second laser pulse signal includes an on signal or an off signal; when the on signal is adopted, the first laser or the second laser irradiates the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction; when the off signal is adopted, the first laser or the second laser does not irradiate the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction. Among them, the on laser pulse signal is the input logic value 1 of the XOR logic gate device; the off laser pulse signal is the input logic value 0 of the XOR logic gate device; the source electrode and the drain electrode are used to output current; the output current is used to determine the result of XOR logic calculation, wherein the output high current change amount is the output logic value 1 of the XOR logic gate device; the output low current change amount is the logic value 0 of the XOR logic gate device; the current change amount is named I 突触后 In the following embodiments, the first laser is taken as an example of a laser with a wavelength of 405nm, and the second laser is taken as an example of a laser with a wavelength of 808nm, and the calculation process of the XOR logic gate of the present application is described in detail.

[0082] For example, as shown in FIG. 7(a), in the embodiment of the present application, the device is used as an XOR logic gate for electrical calculation. The laser pulse signals with wavelengths of 405nm and 808nm are used as input signals, the logic "1" is defined as the on laser pulse signal, the logic "0" is defined as the off laser pulse signal, the laser pulse signal with a wavelength of 405nm is the first input IN1, and the laser pulse signal with a wavelength of 808nm is the second input IN2. The change amount of the source-drain current is used as the output signal, and the change amount is named I突触后 , I 突触后 is high current state, defined as logic "1", I 突触后 is low current state, defined as logic "0". The state distinction between high current and low current satisfies The specific logic calculation process is: the drain-source voltage Vds is biased to 1V, and the voltage states of (OFF, OFF), (OFF, ON), (ON, OFF), (ON, ON) are set on the laser pulse signals with wavelengths of 405nm and 808nm respectively, and the input signals are (0, 0), (0, 1), (1, 0), (1, 1) respectively, it can be seen that the state of the output current I 突触后 satisfies the XOR truth table shown in Figure 7(b).

[0083] It should be noted that in this mode 3, the top gate electrode and the second bottom gate electrode have no voltage input or the voltage is set to 0V, and the first bottom gate electrode adjusts the calculation starting state value of the XOR calculation current in real time according to the current state input voltage signal. The specific input voltage value is directly related to the current source-drain current of the device, that is, there are only two laser input signals and the control signal of the first bottom gate, and no other input signals. The specific setting value of the laser power needs to satisfy the condition that I 突触后 generated by 405nm laser irradiation is equal to I 突触后 generated by 808nm laser irradiation.

[0084] It should be noted that in this mode 3, the laser is irradiated to the designed cavity structure region and the channel material region overlapping the cavity region in the vertical direction in the device of the present application, and the channel material has both positive and negative photoconductivity effects to different wavelengths or different light powers. The positive and negative photoconductivity effects are induced by the mechanism of the photo-induced structural phase transition of 2h-MoTe2 material. The change of the internal structure of the material changes the potential barrier of the carrier input channel, resulting in a change in the resistance of the whole device, thereby changing the current of the loop under the bias voltage, and the current change conforms to digital logic calculation. The circuit of the device connected with the resistance is not an inverter circuit, but only for realizing the conversion of the current signal to the voltage signal, and there is no need to realize the inversion of the high and low voltage levels, that is, the device itself can realize XOR, and there is no need for an inverter circuit.

[0085] Further, the material with structural phase transition characteristics or the material that can be induced to have both positive and negative photoconductivity effects by other mechanisms under this mode 3 can realize similar functions under the reference scheme of the embodiments of the present application, and the present application does not limit it here.

[0086] Embodiment 2

[0087] The application further provides a photoelectric full logic gate circuit based on a multi-region gate single-channel microcavity transistor and a control method thereof. The photoelectric full logic gate circuit comprises a NOR logic gate circuit, a NAND logic gate circuit and an XOR logic gate circuit. In this embodiment, the first laser is a laser with a wavelength of 254-633 nm, and the second laser is a laser with a wavelength of 635-1550 nm. In the following detailed description, the first laser is taken as a laser with a wavelength of 405 nm, and the second laser is taken as a laser with a wavelength of 808 nm. The control method comprises controlling the photoelectric full logic gate circuit to realize the following functions:

[0088] Function 1: setting the NOR logic gate to a high resistance state; inputting a first pulse signal to the first bottom gate electrode and a second pulse signal to the second bottom gate electrode; inputting a pre-set calculation voltage to the source electrode and the drain electrode; reading the output current of the source electrode or the drain electrode of the NOR logic gate; determining the output level of the NOR logic gate according to the output current to obtain the result of logic calculation.

[0089] Function 2: setting the NAND logic gate to a high resistance state; inputting a third pulse signal to the top gate electrode and a fourth pulse signal to the second bottom gate electrode; inputting a pre-set calculation voltage to the source electrode and the drain electrode; reading the output current of the source electrode or the drain electrode of the NAND logic gate; determining the output level of the NAND logic gate according to the output current to obtain the result of logic calculation.

[0090] Function 3: setting the XOR logic gate to a certain resistance state; inputting a laser with a wavelength of 405 nm as a first pulse signal to the first switch and inputting a laser with a wavelength of 808 nm as a second pulse signal to the second switch to change the resistance state of the XOR logic gate and the single-channel current change value state of the transistor in the transistor module; inputting a pre-set calculation voltage to the source electrode and the drain electrode; reading the output current change value of the source electrode or the drain electrode of the XOR logic gate; determining the output level of the XOR logic gate according to the output current change value to obtain the result of logic calculation.

[0091] The certain resistance state is the gate voltage added to the gate electrode when the current reaches the initial set value under the source-drain bias voltage, that is, the certain resistance state refers to that the device passes the current set value through the gate voltage adjustment under the source-drain bias voltage. The current change amount under the first laser irradiation with a wavelength of 405nm is Δa, and the current change amount under the second laser irradiation with a wavelength of 808nm is Δb, then when |Δa| = |Δb|, the XOR operation is satisfied. The two change amounts Δa and Δb are related to the laser power, and also related to the quality of the material itself, when these conditions are fixed, the initial current set value of a device is fixed. When a plurality of devices are prepared, the material quality is not necessarily the same, so the initial current of the device is not the same, and needs to be adjusted during operation.

[0092] Embodiment 3:

[0093] The application also provides a transistor consumption of a photoelectric full logic gate device based on a multi-region gate single-channel microcavity transistor under a CMOS process standard.

[0094] Firstly, for the field of semiconductor devices under the emerging process, the transistor consumption formula under the CMOS process standard is:

[0095]

[0096] Among them, C: C NAND , C NOR and C XOR represent the number of transistors required to build NAND, NOR and XOR logic gates in CMOS process, C NAND , C NOR and C XOR are 4, 4 and 12 respectively.

[0097] T: T NAND , T NOR and T XOR are the number of transistors required to build NAND, NOR and XOR logic gates under the emerging process T NAND , T NOR and T XOR .

[0098] N is the number of gates in the same plane of the used transistor.

[0099] The device of the application, when current is the output signal, one transistor can realize NAND, NOR, XOR; when voltage is the output signal, a resistor needs to be connected in series to convert the current and voltage signals, and then two transistors are equivalent to realize NAND, NOR, XOR, T = 2. In the CMOS process, the voltage is the output signal. The bottom gate electrode and the top gate electrode of the device are stacked in the vertical direction, and the first bottom gate electrode surrounds the second bottom gate electrode, that is, only one gate area is occupied in the same plane, N = 1. Therefore, the transistor consumption of the application is:

[0100]

[0101] It should be noted that the transistor is a current output type device, and the device based on the transistor structure is also a current output type device. If the output voltage signal is required, another resistor needs to be added to convert the signal type. That is, under the standard of CMOS process, theoretically, one transistor can be used to realize the three logic functions of NAND, NOR and XOR. When the voltage signal needs to be output, theoretically, two transistors are needed to realize the three logic gates. At this time, the transistor consumption under the standard of CMOS process will be reduced to the theoretical minimum value of 10%. Only the new voltage output type transistor device is born, the value can be further reduced theoretically. The transistor consumption of the application under the standard of CMOS process is successfully reduced to the theoretical minimum value of 10%, that is, the consumption is reduced by 90%, which further proves that the photoelectric full logic gate device of the application can directly reduce the transistor consumption compared with the existing logic gate device, greatly saving the manufacturing cost of the device and reducing the size of the device.

[0102] Example 4

[0103] The application also provides a preparation method of a photoelectric full logic gate device based on a multi-region gate single-channel microcavity transistor. The preparation method of a photoelectric full logic gate device based on a multi-region gate single-channel microcavity transistor as described in the above examples is as shown in the following formula: Figure 3 The preparation method includes preparing a first bottom gate electrode and a second bottom gate electrode, preparing a bottom gate dielectric layer and a channel layer, preparing a source electrode and a drain electrode, preparing a top gate dielectric layer, and preparing a top gate electrode. The channel layer is taken as an example of 2h-MoTe2. It should be understood that any material meeting the material property requirements of the channel layer described above can be used as a replacement to achieve similar effects, which is not limited herein. The specific steps include the following steps:

[0104] Step 1: Clean the SiO2 / Si substrate, and ultrasonically clean with acetone, isopropanol and deionized water for 10 minutes, and then dry with nitrogen.

[0105] Step 2: spin-coating photoresist, using a photoetching machine to pattern the photoresist, by controlling the pattern and spacing of the first bottom gate electrode and the second bottom gate electrode, so that the first bottom gate electrode and the second bottom gate electrode grooves corresponding to different regions of the channel material are formed on the photoresist, and the first bottom gate electrode and the second bottom gate electrode are prepared on the surface of the SiO2 substrate by using an electron beam evaporation process.

[0106] Step 3: by mechanical exfoliation method, respectively on the cleaned SiO2 / Si substrate to obtain h-BN sheet, 2h-MoTe2 sheet.

[0107] Step 4: using dry transfer, the bottom gate h-BN sheet is transferred to the whole region of the first bottom gate electrode and the second bottom gate electrode, so that the h-BN sheet completely covers the two bottom gate electrodes, and a cavity structure is formed between the h-BN sheet, the bottom gate electrode and the SiO2 substrate; the spacing of the first bottom gate electrode and the second bottom gate electrode determines the formation quality of the cavity structure.

[0108] Step 5: using dry transfer, the 2h-MoTe2 sheet is transferred to the h-BN obtained in step 3, so that the 2h-MoTe2 material spans the first bottom gate electrode and the second bottom gate electrode, and distinguishes the ohmic contact region and the channel region.

[0109] Step 6: using dry transfer, the top gate h-BN sheet is transferred to the 2h-MoTe2 sheet, covering the corresponding channel region.

[0110] Step 7: spin-coating photoresist, then using a photoetching machine to pattern the photoresist, by controlling the pattern and position of the top gate electrode, so that the top gate electrode groove corresponding to the material channel region is formed on the top gate h-BN sheet, and then using an electron beam evaporation process to prepare the top gate electrode on the top gate h-BN, to obtain a photoelectric full logic gate device based on the multi-region gate single-channel microcavity 2h-MoTe2 field effect transistor architecture.

[0111] The above embodiment is the preferred embodiment of the present application, but the embodiment of the present application is not limited to the above embodiment, and any change, modification, substitution, combination, simplification made without departing from the spirit and principles of the present application shall be an equivalent replacement mode, and all shall be included in the protection scope of the present application.

Claims

1. A multi-region gate single channel microcavity transistor, characterized by: The substrate, the bottom gate electrode layer, the bottom gate dielectric layer, the channel layer, the source electrode and the drain electrode, the top gate dielectric layer, and the top gate electrode are arranged in a stack. The bottom gate electrode layer is arranged on the substrate, and the bottom gate electrode layer comprises a first bottom gate electrode and a second bottom gate electrode, the first bottom gate electrode comprises a first sub-bottom gate electrode and a second sub-bottom gate electrode, and the second bottom gate electrode is arranged between the first sub-bottom gate electrode and the second sub-bottom gate electrode. The bottom gate dielectric layer is arranged on the bottom gate electrode, and the bottom gate dielectric layer forms a first cavity structure between the first sub-bottom gate electrode, the second bottom gate electrode, and the substrate, and forms a second cavity structure between the second sub-bottom gate electrode, the second bottom gate electrode, and the substrate. The channel layer is arranged on the bottom gate dielectric layer, and the source electrode and the drain electrode are arranged on the channel layer. The top gate dielectric layer is arranged on the source electrode, the drain electrode, and the channel layer. The top gate electrode is arranged on the top gate dielectric layer. The channel layer is a p-type two-dimensional material, and the p-type two-dimensional material exhibits positive photoconductivity and negative photoconductivity under irradiation of a laser of a first wavelength at different optical powers. The current state of the drain current when the first bottom gate electrode and the second bottom gate electrode are respectively applied with a voltage of -3V and 3V satisfies The current state of the drain current when the top gate electrode and the second bottom gate electrode are respectively applied with a voltage of -3 V and 3 V satisfies When the first cavity structure region and the second cavity structure region and a channel layer region overlapping the first cavity structure region and the second cavity structure region in a vertical direction are irradiated with the laser of the first wavelength and the laser of the second wavelength, respectively, a current state of a drain current variation amount satisfies The second wavelength is different from the first wavelength.

2. The multi-zone gate single-channel microcavity transistor of claim 1, wherein, The p-type two-dimensional material is selected from 2h-MoTe2 materials, and the thickness of the p-type two-dimensional material is 15-50 nm. The first wavelength is 254-633 nm, and the second wavelength is 635-1550 nm.

3. The multi-zone gate single-channel microcavity transistor according to claim 1 or 2, wherein The thickness of the bottom gate dielectric layer and the top gate dielectric layer is 15-40 nm, and the material of the bottom gate dielectric layer and the top gate dielectric layer is h-BN material.

4. The multi-zone gate single-channel microcavity transistor according to claim 1 or 2, wherein The thickness of the top gate electrode, the first sub-bottom gate electrode, the second sub-bottom gate electrode, and the second bottom gate electrode is 30-100 nm. The interval between the first sub-bottom gate electrode, the second sub-bottom gate electrode, and the second bottom gate electrode is 0.3-3 μm.

5. An optoelectronic all logic gate device based on multi-region gate single channel microcavity transistor characterized by: The multi-region gate single-channel microcavity transistor of any one of claims 1-4 is used as the optoelectronic full logic gate device, and the multi-region gate single-channel microcavity transistor is a single transistor that realizes NOR logic gates, NAND logic gates, and XOR logic gates with current signals as output signals.

6. A multi-region gate single channel microcavity transistor based optoelectronic all logic gate device according to claim 5, wherein: In the realization of the NOR logic gate, the first bottom gate electrode and the second bottom gate electrode are respectively used as a first input end and a second input end of the NOR logic gate, and the source electrode and the drain electrode are both used as output ends of the NOR logic gate.

7. A multi-region gate single channel microcavity transistor based optoelectronic all logic gate device as claimed in claim 5, wherein: In the realization of the NAND logic gate, the top gate electrode and the second bottom gate electrode are respectively used as a first input end and a second input end of the NAND logic gate, and the source electrode and the drain electrode are both used as output ends of the NAND logic gate.

8. A multi-region gate single channel microcavity transistor based optoelectronic all logic gate device as claimed in claim 5, wherein: The first laser of the first wavelength and the second laser of the second wavelength are further included, the second wavelength is different from the first wavelength, the first laser is used to irradiate the first cavity structure region, the second cavity structure region, and a channel layer region overlapping the first cavity structure region and the second cavity structure region in a vertical direction, and the second laser is used to irradiate the first cavity structure region, the second cavity structure region, and the channel layer region overlapping the first cavity structure region and the second cavity structure region in the vertical direction. In the implementation of the XOR logic gate, the first laser and the second laser are respectively the first input end and the second input end of the XOR logic gate, and the source electrode and the drain electrode are both the output end of the XOR logic gate.

9. A control method of an optoelectronic full logic gate device based on multi-region gate single channel microcavity transistor, applied to an optoelectronic full logic gate device based on multi-region gate single channel microcavity transistor according to any one of claims 5 to 8, characterized in that: The photoelectric full logic gate device includes a NOR logic gate, a NAND logic gate and an XOR logic gate, and the control method includes controlling the photoelectric full logic gate device to implement the following functions: Function 1: set the NAND logic gate to a high resistance state; input a first pulse signal to the top gate electrode, the first pulse signal including a high-level pulse signal or a low-level pulse signal, and input a second pulse signal to the second bottom gate electrode, the second pulse signal including a high-level pulse signal or a low-level pulse signal; input a pre-set calculation voltage to the source electrode and the drain electrode; read the output current of the source electrode or the drain electrode of the NAND logic gate; and determine the output level of the NAND logic gate according to the output current to obtain the result of logic calculation. Function 2: set the NOR logic gate to a high resistance state; input a first pulse signal to the first bottom gate electrode, the first pulse signal including a high-level pulse signal or a low-level pulse signal, and input a second pulse signal to the second bottom gate electrode, the second pulse signal including a high-level pulse signal or a low-level pulse signal; input a pre-set calculation voltage to the source electrode and the drain electrode; read the output current of the source electrode or the drain electrode of the NOR logic gate; and determine the output level of the NOR logic gate according to the output current to obtain the result of logic calculation. Function 3: set the XOR logic gate to a certain resistance state, the certain resistance state being a gate voltage added to the gate electrode when the current reaches an initial set value under the source-drain bias voltage; the first laser with a wavelength of 254-633 nm is a high-level pulse signal or a low-level pulse signal when irradiating or not irradiating the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction, and the second laser with a wavelength of 635-1550 nm is a high-level pulse signal or a low-level pulse signal when irradiating or not irradiating the first and second cavity structure regions and the channel layer region overlapping the first and second cavity structure regions in the vertical direction; input a pre-set calculation voltage to the source electrode and the drain electrode; read the output current change value of the source electrode or the drain electrode of the XOR logic gate; determine the output level of the XOR logic gate according to the output current change value to obtain the result of logic calculation.

10. An optoelectronic all logic gate circuit based on multi-region gate single channel microcavity transistor characterized by: The photoelectric full logic gate device based on the multi-region gate single-channel microcavity transistor includes a NOR logic gate, a NAND logic gate and an XOR logic gate.

Images