Solar cell and method of manufacturing the same, photovoltaic module

Abstract

The application relates to a solar cell, a preparation method thereof and a photovoltaic module. The preparation method of the solar cell comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface arranged oppositely; forming a first tunnel layer and a first doped semiconductor layer in a stack on the first surface; the first doped semiconductor layer is located on the side of the first tunnel layer away from the semiconductor substrate; adopting a microwave annealing process to activate the doped elements in the first doped semiconductor layer, and forming a first inner extension layer in the semiconductor substrate and connected with the first tunnel layer; and forming a first electrode in ohmic contact with the first doped semiconductor layer on the side of the first doped semiconductor layer away from the semiconductor substrate. The application can make the junction depth of the first inner extension layer shallower, is beneficial to reducing the recombination of carriers, and improves the conversion efficiency and stability of the solar cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar photovoltaic cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module. BACKGROUND

[0002] With the continuous development of solar cell technology, people's requirements for the photoelectric conversion efficiency of the cell are also getting higher and higher, but the improvement of the efficiency of the current industrialized cell still faces many challenges. Among them, the contact recombination of the metal and the silicon contact area and the Auger recombination and deep level recombination caused by diffusion in the silicon matrix are the main factors restricting the improvement of the cell efficiency. The TOPCon (Tunnel Oxide Passivated Contact) cell reduces the recombination of surface carriers by setting a passivation contact structure on the back surface of the silicon substrate. However, the junction depth of the inner extension layer of the current TOPCon cell is too deep, which is not conducive to improving the cell efficiency. SUMMARY

[0003] Therefore, it is necessary to provide a solar cell, a preparation method thereof and a photovoltaic module in view of the above problems.

[0004] In a first aspect, an embodiment of the present application provides a preparation method of a solar cell, comprising:

[0005] providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface arranged oppositely;

[0006] forming a first tunnel layer and a first doped semiconductor layer in a stack on the first surface; the first doped semiconductor layer is located on a side of the first tunnel layer away from the semiconductor substrate;

[0007] activating a doped element in the first doped semiconductor layer by a microwave annealing process, and forming a first inner extension layer in the semiconductor substrate and connected with the first tunnel layer;

[0008] forming a first electrode in ohmic contact with the first doped semiconductor layer on a side of the first doped semiconductor layer away from the semiconductor substrate.

[0009] In one of the embodiments, after the first tunnel layer and the first doped semiconductor layer in a stack are formed on the first surface, before the doped element in the first doped semiconductor layer is activated by the microwave annealing process and the first inner extension layer is formed in the semiconductor substrate, the method further comprises:

[0010] forming a second tunnel layer and a second doped semiconductor layer in a stack on the second surface; the second doped semiconductor layer is located on a side of the second tunnel layer away from the semiconductor substrate.

[0011] In one of the embodiments, the microwave annealing process activates the dopant elements in the first doped semiconductor layer and forms a first inner extension layer in the semiconductor substrate, which is in contact with the first tunneling layer, including:

[0012] The microwave annealing process activates the dopant elements in the first doped semiconductor layer and the dopant elements in the second doped semiconductor layer and forms a first inner extension layer in the semiconductor substrate, which is in contact with the first tunneling layer, and a second inner extension layer in the semiconductor substrate, which is in contact with the second tunneling layer.

[0013] In one of the embodiments, the second tunneling layer and the second doped semiconductor layer are formed on the second surface, including:

[0014] forming a second tunneling layer on the second surface;

[0015] forming an intrinsic semiconductor layer on a side of the second tunneling layer, which is away from the semiconductor substrate;

[0016] doping the intrinsic semiconductor layer to form the second doped semiconductor layer;

[0017] or,

[0018] forming a second tunneling layer on the second surface;

[0019] forming the second doped semiconductor layer on a side of the second tunneling layer, which is away from the semiconductor substrate.

[0020] In one of the embodiments, the microwave frequency of the microwave annealing process is between 1.5 GHz and 20 GHz;

[0021] and / or, the annealing time of the microwave annealing process is between 5 min and 60 min;

[0022] and / or, the annealing temperature of the microwave annealing process is between 50 °C and 400 °C.

[0023] In a second aspect, the embodiments of the present application provide a solar cell, including:

[0024] a semiconductor substrate, including a first surface and a second surface arranged oppositely;

[0025] a first tunneling layer arranged on the first surface;

[0026] a first doped semiconductor layer arranged on a side of the first tunneling layer, which is away from the semiconductor substrate;

[0027] a first inner diffusion layer, disposed in the semiconductor substrate and connected with the first tunneling layer; wherein the doping elements in the first doped semiconductor layer are activated by a microwave annealing process and diffuse into the semiconductor substrate to form the first inner diffusion layer;

[0028] a first electrode, disposed on a side of the first doped semiconductor layer away from the semiconductor substrate and in ohmic contact with the first doped semiconductor layer.

[0029] In one of the embodiments, the first inner diffusion layer has a junction depth of 0.15-0.25 μm;

[0030] And / or, the first inner diffusion layer has a doping concentration of 1×10 18 cm -3 -1×10 19 cm -3 .

[0031] In one of the embodiments, the solar cell further comprises:

[0032] a second tunneling layer, disposed on the second surface;

[0033] a second doped semiconductor layer, disposed on a side of the second tunneling layer away from the semiconductor substrate;

[0034] a second inner diffusion layer, disposed in the semiconductor substrate and connected with the second tunneling layer; wherein the doping elements in the second doped semiconductor layer are activated by a microwave annealing process and diffuse into the semiconductor substrate to form the second inner diffusion layer;

[0035] a second electrode, disposed on a side of the second doped semiconductor layer away from the semiconductor substrate and in ohmic contact with the second doped semiconductor layer.

[0036] In one of the embodiments, the second inner diffusion layer has a junction depth of 0.1-0.14 μm;

[0037] And / or, the second inner diffusion layer has a doping concentration of 5×10 20 cm -3 -8×10 20 cm -3 .

[0038] In a third aspect, the embodiments of the present application provide a photovoltaic module, comprising the solar cell of any of the embodiments of the second aspect.

[0039] The solar cell and the preparation method thereof and the photovoltaic module provided by the embodiments of the present application can activate the doping elements in the first doped semiconductor layer by using the microwave annealing process, which can effectively activate the doping elements and repair the lattice damage to achieve the annealing purpose; on the other hand, the frequency, temperature and time of the microwave annealing are controllable, which can effectively inhibit the redistribution of the doping elements, so that the junction depth of the first inner extension layer is relatively shallow, thereby being beneficial to reducing the recombination of the carriers and improving the conversion efficiency and stability of the solar cell. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments or the exemplary embodiments of the present application, the drawings needed to be used in the description of the embodiments or the exemplary embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0041] Figure 1 A flowchart of the preparation method of the solar cell provided by an embodiment of the present application is shown.

[0042] Figure 2 Another flowchart of the preparation method of the solar cell provided by an embodiment of the present application is shown.

[0043] Figure 3 A partial cross-sectional structure schematic diagram of the solar cell provided by an embodiment of the present application is shown. Figure 2 A partial cross-sectional structure schematic diagram of the solar cell provided by an embodiment of the present application is shown.

[0044] Figure 4 A partial cross-sectional structure schematic diagram of the solar cell provided by an embodiment of the present application is shown. Figure 2 A partial cross-sectional structure schematic diagram of the solar cell provided by an embodiment of the present application is shown.

[0045] Figure 5 A partial cross-sectional structure schematic diagram of the solar cell provided by an embodiment of the present application is shown. Figure 2 A partial cross-sectional structure schematic diagram of the solar cell provided by an embodiment of the present application is shown.

[0046] Figure 6 A partial cross-sectional structure schematic diagram of the solar cell provided by an embodiment of the present application is shown.

[0047] Reference signs:

[0048] 1. Solar cell; 11. Semiconductor substrate; 111. First surface; 112. Second surface; 121. First tunneling layer; 122. First doped semiconductor layer; 131. First inner extension layer; 132. Second inner extension layer; 141. First electrode; 142. Second electrode; 151. Second tunneling layer; 152. Second doped semiconductor layer; 16. Passivation layer; 17. First anti-reflective layer; 18. Second anti-reflective layer. DETAILED DESCRIPTION

[0049] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without using some or all of these specific details. In other instances, well-known process steps have not been described in detail in order to avoid obscuring the present application.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0051] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0052] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As should also be apparent, the term "comprising" or "containing" or "having" or the like means containing at least the stated feature, integer, step, operation, component, or combination thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, or combinations thereof. Also herein the term "and / or" includes any and all combinations of associated listed items.

[0054] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0055] In a related TOPCon cell technology, after a doping process is performed on a semiconductor film layer, an annealing process is performed, which aims to repair damage, activate doping elements, and restore the mobility of electrons and holes. The annealing temperature of a conventional annealing process is relatively high, generally above 900 DEG C, and the heating process and the cooling process are relatively slow, resulting in a relatively long heat treatment time, which causes serious redistribution of the doping elements, resulting in a high concentration and deep junction depth of the inner extension layer. The junction depth of the inner extension layer directly affects the generation and collection efficiency of photo-generated carriers, and further affects the conversion efficiency and stability of the cell.

[0056] In view of the above problems, the embodiments of the present application provide a solar cell and a preparation method thereof, and a photovoltaic module. By using a microwave annealing process to activate the doping elements in the first doped semiconductor layer, on the one hand, the doping elements can be effectively activated, and the lattice damage can be repaired to achieve the purpose of annealing; on the other hand, the frequency, temperature and time of the microwave annealing are controllable, which can effectively inhibit the redistribution of the doping elements, so that the junction depth of the first inner extension layer is shallow, which is conducive to reducing the recombination of carriers and improving the conversion efficiency and stability of the solar cell.

[0057] In a first aspect, referring to Figure 1 The embodiments of the present application provide a preparation method of a solar cell 1.

[0058] The preparation method specifically includes the following steps:

[0059] S100: providing a semiconductor substrate 11, the semiconductor substrate 11 including a first surface 111 and a second surface 112 arranged oppositely. Herein, one of the first surface 111 and the second surface 112 is a light-receiving surface, and the other is a back surface. It can be understood that the material of the semiconductor substrate 11 can be silicon, a compound semiconductor, and a wide-bandgap semiconductor material. Exemplarily, the silicon includes crystalline silicon and amorphous silicon. The compound semiconductor includes selenium, selenide, etc. The wide-bandgap semiconductor material includes silicon carbide, gallium nitride, diamond, etc. It should be noted that the semiconductor substrate 11 can be double-side polished in this step.

[0060] Further, the doping type of the semiconductor substrate 11 is N-type or P-type. When the doping type of the semiconductor substrate 11 is N-type, the doping elements can include any one or more of phosphorus (P), arsenic (As), bismuth (Bi) and antimony (Sb) in group V elements; when the doping type of the semiconductor substrate 11 is P-type, the doping elements can include any one or more of boron (B), aluminum (Al), gallium (Ga) and indium (In) in group III elements. In the embodiments of the present application, the doping type of the semiconductor substrate 11 is N-type.

[0061] S200: Forming a first tunneling layer 121 and a first doped semiconductor layer 122 on the first surface 111. Refer to FIG. 1B. Figure 3 As shown in FIG. 1B, the first doped semiconductor layer 122 is located on the side of the first tunneling layer 121 away from the semiconductor substrate 11. Exemplarily, the material of the first tunneling layer 121 can be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, titanium oxide, etc. The material of the first doped semiconductor layer 122 can be amorphous silicon, polysilicon, microcrystalline silicon, silicon carbide, etc. It can be understood that the first tunneling layer 121 and the first doped semiconductor layer 122 can be prepared by ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), etc. The doping type of the first doped semiconductor layer 122 can be N-type or P-type. It should be noted that in this step, a borosilicate glass layer or a phosphosilicate glass layer can also be formed on the first doped semiconductor layer 122 at the same time. In the embodiments of the present application, the doping type of the first doped semiconductor layer 122 is P-type.

[0062] S400: Activating the doping elements in the first doped semiconductor layer 122 by a microwave annealing process, and forming a first inner expansion layer 131 in the semiconductor substrate 11 and connected to the first tunneling layer 121. The structure after forming the first inner expansion layer 131 is shown in FIG. 1D. Figure 5

[0063] Here, it should be noted that the microwave annealing process can quickly and uniformly raise the temperature of the material by microwave radiation, thereby accelerating the physical and chemical change process of the material. The microwave annealing process has the following advantages: 1. Energy saving and high efficiency. Compared with the traditional annealing process, the microwave annealing can more quickly and uniformly raise the temperature of the material, thereby shortening the processing time and reducing the energy consumption. 2. Improve product quality. Improve the quality of the light absorption layer of the solar cell 1 and improve the photoelectric conversion efficiency. 3. Environmental protection. The microwave annealing process is cleaner, unlike traditional furnaces that accumulate chemicals, reducing pollution.

[0064] ​S500: forming a first electrode 141 in ohmic contact with the first doped semiconductor layer 122 on the side of the first doped semiconductor layer 122 away from the semiconductor substrate 11. The material of the first electrode 141 includes but is not limited to one or more of aluminum, titanium, nickel, cobalt, silver, copper and tin. The forming method of the first electrode 141 can include one of screen printing, laser transfer and electroplating. The structure after the formation of the first electrode 141 is shown in Figure 6 .

[0065] The preparation method of the solar cell 1 provided by the embodiments of the present application activates the doping elements in the first doped semiconductor layer 122 by using the microwave annealing process. On the one hand, the doping elements can be effectively activated, and the lattice damage can be repaired to achieve the annealing purpose. On the other hand, the frequency, temperature and time of the microwave annealing are controllable, which is conducive to reducing the heat treatment time and heat treatment temperature, thereby effectively inhibiting the redistribution of the doping elements, making the junction depth of the first inner extension layer 131 shallower, and further reducing the recombination of the carriers, and improving the conversion efficiency and stability of the solar cell 1.

[0066] In one of the embodiments, referring to Figure 2 , after the step of S200: forming the first tunneling layer 121 and the first doped semiconductor layer 122 in layers on the first surface 111, the step of S400: activating the doping elements in the first doped semiconductor layer 122 by using the microwave annealing process, and before the step of forming the first inner extension layer 131 in the semiconductor substrate 11, further includes the following steps:

[0067] S300: forming the second tunneling layer 151 and the second doped semiconductor layer 152 in layers on the second surface 112. The second doped semiconductor layer 152 is located on the side of the second tunneling layer 151 away from the semiconductor substrate 11. The structure after the formation of the second tunneling layer 151 and the second doped semiconductor layer 152 is shown in Figure 4The material of the second tunneling layer 151 can be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, titanium oxide, or the like. The material of the second doped semiconductor layer 152 can be amorphous silicon, polysilicon, microcrystalline silicon, silicon carbide, or the like. It can be understood that the second tunneling layer 151 and the second doped semiconductor layer 152 can be prepared by ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), or the like. The doping type of the second doped semiconductor layer 152 can be N-type or P-type, and the doping type of the second doped semiconductor layer 152 is opposite to that of the first doped semiconductor layer 122. In the embodiment of the present application, the doping type of the second doped semiconductor layer 152 is N-type.

[0068] In one embodiment, S400: activating the doping elements in the first doped semiconductor layer 122 by a microwave annealing process, and forming a first inner expansion layer 131 in the semiconductor substrate 11 and connected to the first tunneling layer 121, comprising:

[0069] S410: activating the doping elements in the first doped semiconductor layer 122 and the doping elements in the second doped semiconductor layer 152 by a microwave annealing process, and forming a first inner expansion layer 131 in the semiconductor substrate 11 and connected to the first tunneling layer 121, and forming a second inner expansion layer 132 in the semiconductor substrate 11 and connected to the second tunneling layer 151. The structure after forming the first inner expansion layer 131 and the second inner expansion layer 132 is shown in FIG. 4B. Figure 5

[0070] The embodiment can activate the doping elements in the first doped semiconductor layer 122 and the doping elements in the second doped semiconductor layer 152 in the same process, which can reduce the preparation process of the solar cell 1 and reduce the preparation cost.

[0071] In one embodiment, S300: forming the second tunneling layer 151 and the second doped semiconductor layer 152 in the second surface 112, comprising the following steps:

[0072] S310A: forming the second tunneling layer 151 in the second surface 112.

[0073] ​S320A: Forming an intrinsic semiconductor layer on the side of the second tunneling layer 151 away from the semiconductor substrate 11. Specifically, the intrinsic semiconductor layer can be intrinsic amorphous silicon, and the intrinsic semiconductor layer can be prepared by an LPCVD process.

[0074] S330A: Performing a doping treatment on the intrinsic semiconductor layer to form the second doped semiconductor layer 152.

[0075] In this way, the second doped semiconductor layer 152 is formed by a non-in-situ doping manner. It can be understood that in S330A, the intrinsic semiconductor layer is partially crystallized to form the second doped semiconductor layer 152 with a low crystallization rate. In S410, the second doped semiconductor layer 152 is further crystallized into a doped polysilicon layer.

[0076] In one of the embodiments, S300: forming the second tunneling layer 151 and the second doped semiconductor layer 152 in a stack on the second surface 112, specifically including the following steps:

[0077] S310B: Forming the second tunneling layer 151 on the second surface 112.

[0078] S320B: Forming the second doped semiconductor layer 152 on the side of the second tunneling layer 151 away from the semiconductor substrate 11. Specifically, the second doped semiconductor layer 152 can be prepared by a PECVD process.

[0079] In this way, the second doped semiconductor layer 152 is formed by an in-situ doping manner. The second doped semiconductor layer 152 can be amorphous silicon. In S410, the second doped semiconductor layer 152 is crystallized into a doped polysilicon layer.

[0080] It should be noted that the first doped semiconductor layer 122 can be formed by an in-situ doping or a non-in-situ doping manner, which will not be described herein.

[0081] In one of the embodiments, the microwave frequency of the microwave annealing process is between 1.5 GHz and 20 GHz. For example, the microwave frequency can be 1.5 GHz, 5 GHz, 10 GHz, 15 GHz, 18 GHz, 20 GHz, or between any two of the above values. By setting the microwave frequency within the above range, on the one hand, the temperature of the material can be quickly and uniformly raised, and on the other hand, the microwave annealing temperature can be within the preset temperature range, thereby facilitating the distribution of the doping elements to be more uniform, and the junction depth of the first inner expansion layer 131 and the second inner expansion layer 132 to be within the preset depth.

[0082] In one embodiment, the annealing time of the microwave annealing process is between 5 min and 60 min. Exemplarily, the annealing time can be 5 min, 15 min, 25 min, 35 min, 50 min, 60 min, or any two of the above values. By keeping the annealing time within the above range, it is beneficial to keep the annealing time within a preset time range, thereby improving the uniformity of the distribution of doped elements and ensuring that the junction depth of the first inner layer 131 and the second inner layer 132 is at a preset depth.

[0083] In one embodiment, the annealing temperature of the microwave annealing process is between 50°C and 400°C. Exemplarily, the annealing temperature can be 50°C, 150°C, 250°C, 300°C, 400°C, or any two of the above values. By keeping the annealing temperature within the above range, it is beneficial to achieve a higher uniformity in the distribution of doped elements and to ensure that the junction depth of the first inner extension layer 131 and the second inner extension layer 132 is at a predetermined depth. It is understood that the annealing temperature can be controlled by adjusting the microwave annealing power.

[0084] In one embodiment, the junction depth of the first inner layer 131 is between 0.15 μm and 0.25 μm. The junction depth of the first inner layer 131 is the distance from the first surface to the point where the concentration of the first inner layer 131 is equal to the concentration of the semiconductor substrate 11.

[0085] For example, the junction depth of the first inner layer 131 can be 0.15 μm, 0.2 μm, 0.23 μm, 0.25 μm or between any two of the above values.

[0086] The junction depth of the first inner expansion layer 131 is within the aforementioned range. On the one hand, this makes the junction depth of the first inner expansion layer 131 shallower, which can reduce carrier recombination and improve cell efficiency. On the other hand, it prevents the junction depth of the first inner expansion layer 131 from being too shallow and affecting the current collection efficiency of the solar cell 1.

[0087] In one embodiment, the doping concentration of the first inner layer 131 is between 1 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 For example, the doping concentration of the first inner layer 131 can be 1 × 10⁻⁶. 18 cm -3 5×10 18 cm -3 8×10 18 cm -3 1×10 19 cm -3 Or it may fall between any two of the above values. This helps reduce carrier recombination and improve battery efficiency.

[0088] In one embodiment, the second inner extension layer 132 has a junction depth of 0.1 μm to 0.14 μm. The junction depth of the second inner extension layer 132 is the distance between the second surface and the point where the concentration of the second inner extension layer 132 is equal to the concentration of the semiconductor substrate 11.

[0089] Exemplarily, the junction depth of the second inner extension layer 132 can be 0.1 μm, 0.11 μm, 0.12 μm, 0.14 μm, or between any two of the above values.

[0090] The junction depth of the second inner extension layer 132 is within the above range, on the one hand, the junction depth of the second inner extension layer 132 is shallow, which can reduce the recombination of carriers and improve the cell efficiency; on the other hand, the junction depth of the second inner extension layer 132 is not too shallow to affect the current collection efficiency of the solar cell 1.

[0091] In one embodiment, the second inner extension layer 132 has a doping concentration of 5 x 10 20 cm -3 ~ 8 x 10 20 cm -3 . Exemplarily, the doping concentration of the second inner extension layer 132 can be 5 x 10 20 cm -3 , 6 x 10 20 cm -3 , 5 x 10 20 cm -3 , or between any two of the above values. In this way, it is beneficial to reduce the recombination of carriers and improve the cell efficiency.

[0092] In one embodiment, after S200: forming the stacked first tunneling layer 121 and the first doped semiconductor layer 122 on the first surface 111, before S300: forming the stacked second tunneling layer 151 and the second doped semiconductor layer 152 on the second surface 112, the method can further include the following steps:

[0093] S250: cleaning the semiconductor substrate 11 and performing a texturing process on the second surface 112.

[0094] In one embodiment, after S400: using a microwave annealing process to activate the doping elements in the first doped semiconductor layer 122 and form a first inner extension layer 131 in the semiconductor substrate 11 and connected to the first tunneling layer 121, before S500: forming a first electrode 141 on the side of the first doped semiconductor layer 122 away from the semiconductor substrate 11 and ohmic contact with the first doped semiconductor layer 122, the method can further include the following steps:

[0095] S450: Forming a second anti-reflective layer 18 on the second doped semiconductor layer 152. Exemplarily, the second anti-reflective layer 18 can be prepared by plasma enhanced chemical vapor deposition, and can include single-layer or multi-layer SiNx. Specifically, the deposition of SiNx can employ a mixed gas of SiH4 and NH3, and the reaction temperature is 300-550°C.

[0096] S460: Forming a passivation layer 16 on the first doped semiconductor layer 122. Exemplarily, the material of the passivation layer 16 can be aluminum oxide. Specifically, the aluminum oxide can be deposited by atomic layer deposition or plasma enhanced chemical vapor deposition, and the deposition of aluminum oxide can employ a mixed gas of TMA and O2 or N2O, and the reaction temperature is 200-350°C.

[0097] S470: Forming a first anti-reflective layer 17 on the passivation layer 16. Exemplarily, the first anti-reflective layer 17 can be prepared by plasma enhanced chemical vapor deposition, and can include single-layer or multi-layer SiNx. Specifically, the deposition of SiNx can employ a mixed gas of SiH4 and NH3, and the reaction temperature is 300-550°C.

[0098] S480: Forming a second electrode 142 on the second doped semiconductor layer 152 away from the semiconductor substrate 11, and the second electrode 142 is in ohmic contact with the second doped semiconductor layer 152. The material of the second electrode 142 includes but is not limited to one or more of aluminum, titanium, nickel, cobalt, silver, copper, and tin. The formation of the second electrode 142 can include one of screen printing, laser transfer printing, and electroplating.

[0099] In a second aspect, referring to Figure 6 The solar cell 1 can be a TOPCon cell. Specifically, the solar cell 1 includes a semiconductor substrate 11, a first tunnel layer 121, a first doped semiconductor layer 122, a first inner diffusion layer 131, and a first electrode 141.

[0100] The semiconductor substrate 11 includes a first surface 111 and a second surface 112 arranged oppositely. One of the first surface 111 and the second surface 112 can be a light-facing surface, and the other can be a back light-facing surface. The first tunnel layer 121 is arranged on the first surface 111. The first doped semiconductor layer 122 is arranged on a side of the first tunnel layer 121 away from the semiconductor substrate 11. The first inner diffusion layer 131 is arranged in the semiconductor substrate 11 and is in contact with the first tunnel layer 121. The doping elements in the first doped semiconductor layer 122 are activated by a microwave annealing process and diffuse into the semiconductor substrate 11 to form the first inner diffusion layer 131. The first electrode 141 is arranged on a side of the first doped semiconductor layer 122 away from the semiconductor substrate 11 and is in ohmic contact with the first doped semiconductor layer 122.

[0101] The solar cell 1 provided by the embodiments of the present application activates the doping elements in the first doped semiconductor layer 122 by using the microwave annealing process, which can effectively activate the doping elements and repair the lattice damage to achieve the annealing purpose. In addition, the frequency, temperature and time of the microwave annealing are controllable, which is beneficial to reduce the heat treatment time and heat treatment temperature, thereby effectively inhibiting the redistribution of the doping elements, making the junction depth of the first inner extension layer 131 shallower, and further beneficial to reduce the recombination of the carriers and improve the conversion efficiency and stability of the solar cell 1.

[0102] In one of the embodiments, the junction depth of the first inner extension layer 131 is between 0.15 μm and 0.25 μm. The junction depth of the first inner extension layer 131 is the distance between the first surface and the position where the concentration of the first inner extension layer 131 is equal to the concentration of the semiconductor substrate 11.

[0103] Exemplarily, the junction depth of the first inner extension layer 131 can be 0.15 μm, 0.2 μm, 0.23 μm, 0.25 μm or between any two of the above values.

[0104] The junction depth of the first inner extension layer 131 is within the above range, which on the one hand makes the junction depth of the first inner extension layer 131 shallower, can reduce the recombination of the carriers and improve the cell efficiency, and on the other hand makes the junction depth of the first inner extension layer 131 not too shallow to affect the current collection efficiency of the solar cell 1.

[0105] In one of the embodiments, the doping concentration of the first inner extension layer 131 is between 1 x 1018cm-3 and 1 x 1020cm-3. 18 cm -3 ~ 1 x 1020cm-3 19 cm -3 . Exemplarily, the doping concentration of the first inner extension layer 131 can be 1 x 1018cm-3, 5 x 1018cm-3, 8 x 1018cm-3, 1 x 1019cm-3, 1 x 1020cm-3 or between any two of the above values. In this way, it is beneficial to reduce the recombination of the carriers and improve the cell efficiency. 18 cm -3 18 cm -3 18 cm -3 19 cm -3

[0106] ​​​​In one of the embodiments, the solar cell 1 further comprises a second tunneling layer 151, a second doped semiconductor layer 152, a second in-diffusion layer 132 and a second electrode 142. The second tunneling layer 151 is disposed on the second surface 112. The second doped semiconductor layer 152 is disposed on a side of the second tunneling layer 151 away from the semiconductor substrate 11. The second in-diffusion layer 132 is disposed in the semiconductor substrate 11 and is in contact with the second tunneling layer 151. In the second doped semiconductor layer 152, the doped elements are activated by a microwave annealing process and diffused into the semiconductor substrate 11 to form the second in-diffusion layer 132. The second electrode 142 is disposed on a side of the second doped semiconductor layer 152 away from the semiconductor substrate 11 and is in ohmic contact with the second doped semiconductor layer 152.

[0107] The solar cell 1 provided by the embodiments of the present application can effectively activate the doped elements in the second doped semiconductor layer 152 by using the microwave annealing process, thereby repairing the lattice damage and achieving the annealing purpose. In addition, the frequency, temperature and time of the microwave annealing are controllable, which is conducive to reducing the heat treatment time and heat treatment temperature, thereby effectively inhibiting the redistribution of the doped elements, making the junction depth of the second in-diffusion layer 132 shallower, and further reducing the recombination of the carriers and improving the conversion efficiency and stability of the solar cell 1.

[0108] In one of the embodiments, the junction depth of the second in-diffusion layer 132 is between 0.1 μm and 0.14 μm. The junction depth of the second in-diffusion layer 132 is the distance between the second surface and the position where the concentration of the second in-diffusion layer 132 is equal to the concentration of the semiconductor substrate 11.

[0109] For example, the junction depth of the second in-diffusion layer 132 can be 0.1 μm, 0.11 μm, 0.12 μm, 0.14 μm or between any two of the above values.

[0110] The junction depth of the second in-diffusion layer 132 is within the above range, which on the one hand makes the junction depth of the second in-diffusion layer 132 shallower, thereby reducing the recombination of the carriers and improving the cell efficiency, and on the other hand makes the junction depth of the second in-diffusion layer 132 not too shallow to affect the current collection efficiency of the solar cell 1.

[0111] In one of the embodiments, the doping concentration of the second in-diffusion layer 132 is between 5×10 20 cm -3 and 8×10 20 cm -3 . For example, the doping concentration of the second in-diffusion layer 132 can be 5×10 20 cm -3 , 6×10 20 cm -3 , 5×10 20 cm -3or between any two of the above values. In this way, recombination of carriers is reduced, and the efficiency of the battery is improved.

[0112] In one embodiment, the first surface 111 is a back surface, and the second surface 112 is a front surface. The second surface 112 is a pyramid texture structure. It is understood that the entire first surface 111 can be a planar structure. Alternatively, a portion of the first surface 111 can be a pyramid texture structure, and another portion can be a planar structure.

[0113] In one embodiment, the first tunneling layer 121 can be a dielectric material, such as at least one of silicon oxide, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. The first tunneling layer 121 can contain a doping element of the same type as the doping element of the semiconductor substrate 11. The first tunneling layer 121 reduces the interface defect state density of the first surface 111 by saturating dangling bonds on the surface of the semiconductor substrate 11, thereby reducing the recombination centers of the first surface 111 to reduce the recombination rate of carriers.

[0114] In one embodiment, the semiconductor substrate 11 is N-type doped, the first doped semiconductor layer 122 is P-type doped, and the second doped semiconductor layer 152 is N-type doped.

[0115] In one embodiment, the thickness of the first doped semiconductor layer 122 is between 3 nm and 150 nm. For example, the thickness of the first doped semiconductor layer 122 can be 3 nm, 20 nm, 50 nm, 80 nm, 120 nm, 150 nm, or between any two of the above values.

[0116] In one embodiment, the second tunneling layer 151 can be a dielectric material, such as at least one of silicon oxide, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. The second tunneling layer 151 can contain a doping element of the same type as the doping element of the semiconductor substrate 11.

[0117] In one embodiment, the thickness of the second doped semiconductor layer 152 is between 3 nm and 150 nm. For example, the thickness of the second doped semiconductor layer 152 can be 3 nm, 20 nm, 50 nm, 80 nm, 120 nm, 150 nm, or between any two of the above values.

[0118] In one embodiment, the second doped semiconductor layer 152 can also be doped with one or more of oxygen, carbon, and nitrogen elements.

[0119] In one of the embodiments, the solar cell 1 further comprises a second electrode 142, a passivation layer 16, a first anti-reflection layer 17 and a second anti-reflection layer 18. The passivation layer 16 is arranged on the side of the first doped semiconductor layer 122 away from the semiconductor substrate 11. The first anti-reflection layer 17 is arranged on the side of the passivation layer 16 away from the semiconductor substrate 11. The first electrode 141 penetrates the first anti-reflection layer 17 and the passivation layer 16 and contacts the first doped semiconductor layer 122. The second anti-reflection layer 18 is arranged on the side of the second doped semiconductor layer 152 away from the semiconductor substrate 11. The second electrode 142 penetrates the second anti-reflection layer 18 and contacts the second doped semiconductor layer 152.

[0120] In a third aspect, the embodiments of the present application provide a photovoltaic module comprising the solar cell of any one of the embodiments of the second aspect.

[0121] Exemplarily, the photovoltaic module comprises a plurality of solar cells. The plurality of solar cells can be connected in series by a solder strip, so as to collect the electric energy generated by the single solar cell for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked together in a shingle form.

[0122] Further, the photovoltaic module further comprises an encapsulation layer and a cover plate. The encapsulation layer is used to cover the surface of the cell string, and the cover plate is used to cover the surface of the encapsulation layer away from the cell string. The solar cells are electrically connected in a whole piece or multiple pieces to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or parallel. Specifically, in some embodiments, the plurality of cell strings can be electrically connected by a conductive strip. The encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation adhesive film such as an ethylene-vinyl acetate copolymer adhesive film, a polyethylene octene elastomer adhesive film or a polyethylene terephthalate adhesive film. The cover plate can be a glass cover plate, a plastic cover plate or the like cover plate having a light transmission function.

[0123] It should be understood that, in the embodiments of the present application, at least one part of the steps in the drawings can comprise a plurality of steps or stages, which do not necessarily be executed at the same time, but can be executed at different times. The execution order of the steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least one part of other steps or stages.

[0124] The technical features of the above-described embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0125] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for producing a solar cell, characterized by, The method comprises: providing a semiconductor substrate comprising a first surface and a second surface arranged oppositely; forming a first tunneling layer and a first doped semiconductor layer in sequence on the first surface; the first doped semiconductor layer is located on a side of the first tunneling layer away from the semiconductor substrate; activating the doped elements in the first doped semiconductor layer by a microwave annealing process, and forming a first inner diffusion layer in the semiconductor substrate and connected with the first tunneling layer; the annealing temperature of the microwave annealing process is between 50℃ and 250℃; forming a first electrode in ohmic contact with the first doped semiconductor layer on a side of the first doped semiconductor layer away from the semiconductor substrate.

2. The method of producing a solar cell according to claim 1, wherein After the step of forming the first tunneling layer and the first doped semiconductor layer in sequence on the first surface, before the step of activating the doped elements in the first doped semiconductor layer by the microwave annealing process, and forming the first inner diffusion layer in the semiconductor substrate and connected with the first tunneling layer, the method further comprises: forming a second tunneling layer and a second doped semiconductor layer in sequence on the second surface; the second doped semiconductor layer is located on a side of the second tunneling layer away from the semiconductor substrate.

3. The method of producing a solar cell according to claim 2, wherein The step of activating the doped elements in the first doped semiconductor layer by the microwave annealing process, and forming the first inner diffusion layer in the semiconductor substrate and connected with the first tunneling layer, comprises: activating the doped elements in the first doped semiconductor layer and the doped elements in the second doped semiconductor layer by the microwave annealing process, and forming the first inner diffusion layer in the semiconductor substrate and connected with the first tunneling layer, and forming a second inner diffusion layer in the semiconductor substrate and connected with the second tunneling layer.

4. The method for preparing a solar cell according to claim 2, characterized in that, The step of forming the second tunneling layer and the second doped semiconductor layer in sequence on the second surface, comprises: forming the second tunneling layer on the second surface; forming an intrinsic semiconductor layer on a side of the second tunneling layer away from the semiconductor substrate; doping the intrinsic semiconductor layer to form the second doped semiconductor layer; or, forming the second tunneling layer on the second surface; forming the second doped semiconductor layer on a side of the second tunneling layer away from the semiconductor substrate.

5. The method of producing a solar cell according to any one of claims 1 to 4, characterized in that, The microwave frequency of the microwave annealing process is between 1.5GHz and 20GHz; and / or, the annealing time of the microwave annealing process is between 5min and 60min.

6. A solar cell, characterized by, The method comprises: providing a semiconductor substrate comprising a first surface and a second surface arranged oppositely; a first tunneling layer arranged on the first surface; a first doped semiconductor layer arranged on a side of the first tunneling layer away from the semiconductor substrate; a first inner diffusion layer arranged in the semiconductor substrate and connected with the first tunneling layer; wherein the doped elements in the first doped semiconductor layer are activated by a microwave annealing process and diffused into the semiconductor substrate to form the first inner diffusion layer; the annealing temperature of the microwave annealing process is between 50℃ and 250℃; a first electrode arranged on a side of the first doped semiconductor layer away from the semiconductor substrate and in ohmic contact with the first doped semiconductor layer.

7. The solar cell according to claim 6, characterized in that, The junction depth of the first inner diffusion layer is between 0.15μm and 0.25μm. and / or, the first inner extension layer has a doping concentration of 1 x 1018 18 cm -3 ~ 1 x 1018 19 cm -3 .

8. The solar cell of claim 6, wherein, The solar cell further comprises: a second tunneling layer arranged on the second surface; a second doped semiconductor layer disposed on a side of the second tunneling layer distal to the semiconductor substrate; a second in-diffusion layer disposed in the semiconductor substrate and in contact with the second tunneling layer; wherein a dopant element in the second doped semiconductor layer is activated by a microwave annealing process and diffuses into the semiconductor substrate to form the second in-diffusion layer; a second electrode disposed on a side of the second doped semiconductor layer distal to the semiconductor substrate and in ohmic contact with the second doped semiconductor layer.

9. The solar cell of claim 8, wherein, a junction depth of the second in-diffusion layer is between 0.1 μm and 0.14 μm; and / or, the doping concentration of the second inner extension layer is between 5 x 1018cm-3 20 cm -3 ~ 8 x 1018cm-3 20 cm -3 .

10. A photovoltaic module, characterized by, a solar cell comprising any one of claims 6-9.

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