Semiconductor structure and preparation method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method for fabricating the same, comprising: providing a substrate having conductive pillars arranged in a first direction; introducing a reaction precursor into the gaps between adjacent conductive pillars to form an initial barrier layer; introducing a predetermined process gas into the gaps to convert the initial barrier layer into an intermediate barrier layer; wherein, under the same wet etching conditions, the etching rate of the intermediate barrier layer is less than the etching rate of the initial barrier layer, and under the same dry etching conditions, the etching rate of the intermediate barrier layer is equal to the etching rate of the initial barrier layer; and removing the substrate and a portion of the intermediate barrier layer between adjacent conductive pillars, with the remaining intermediate barrier layer constituting a target barrier layer, wherein the thickness of the target barrier layer is within a predetermined thickness range. The above-mentioned fabrication method can not only improve the film quality of the target barrier layer, but also alleviate the short circuit phenomenon in the bitline contact structure, thereby improving the yield of semiconductor products.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] In integrated circuit manufacturing, DRAM (Dynamic Random Access Memory) is widely used for large-capacity storage due to its high integration density, low power consumption, and low price. As semiconductor manufacturing processes continue to increase integration, increasing memory integration density has become a trend.

[0003] However, as the feature size of semiconductor structures continues to shrink, the bitline contact structure in memory devices is prone to short circuits. Therefore, there is an urgent need to provide a semiconductor structure and a method for fabricating it to prevent short circuits caused by poor fabrication processes, improve the film quality of the bitline contact structure, and thus increase memory yield. Summary of the Invention

[0004] The present disclosure provides a semiconductor structure and a preparation method thereof to optimize the preparation process of the bit line contact structure in a dynamic memory, avoid or improve the short circuit phenomenon of the memory structure caused by a poor preparation process and improve the quality of the film in the bit line contact structure, thereby reducing the product rework rate and improving the yield of the dynamic memory.

[0005] According to some embodiments, one aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate on which conductive pillars arranged at intervals along a first direction are formed; introducing a reaction precursor into a gap between adjacent conductive pillars to form an initial barrier layer on the outer wall of the conductive pillar; introducing a preset process gas into the gap to convert the initial barrier layer into an intermediate barrier layer; wherein, under the same wet etching conditions, the etching rate of the intermediate barrier layer is less than the etching rate of the initial barrier layer, and under the same dry etching conditions, the etching rate of the intermediate barrier layer is equal to the etching rate of the initial barrier layer; removing the substrate and part of the intermediate barrier layer between adjacent conductive pillars, and the remaining intermediate barrier layer constitutes a target barrier layer, and the thickness of the target barrier layer is within a preset thickness range.

[0006] In the semiconductor structure fabrication methods described in the above-described embodiments, an initial barrier layer is first formed by reacting different reaction precursors under certain process conditions. Due to factors such as the presence of multiple elements in the reaction precursors and the introduction of impurities into the film during the deposition process, the initial barrier layer contains a significant amount of impurities in addition to the primary material. Furthermore, a significant amount of reaction byproducts is present in the reaction chamber, which can affect the yield of subsequent etching and deposition processes. If the initial barrier layer is retained as a barrier structure, when the excess material at the bottom of the gap is etched prior to subsequent gap filling, the impurity-containing initial barrier layer will be partially etched away. Furthermore, due to the rapid wet etching rate of the impurity-containing initial barrier layer, a significant amount of the impurity-containing initial barrier layer will be etched away, exposing the conductive pillars and causing a short circuit in the formed memory structure. Therefore, after forming the initial barrier layer, the present invention introduces a preset process gas into the gap to transform the initial barrier layer into an intermediate barrier layer, thereby reducing impurities in the initial barrier layer and reducing its wet etching rate. The preset process gas can also remove residual reaction byproducts in the reaction chamber. During the subsequent wet etching process, the etching rate of the intermediate barrier layer is slowed down, and a certain film thickness can be retained, without exposing the conductive pillars or deteriorating the blocking effect. The intermediate barrier layer remaining after etching constitutes the target barrier layer. Due to the improvement of the preparation process disclosed in the present invention, the thickness of the target barrier layer can be ensured to be within a preset thickness range. When the gap is subsequently filled, the target barrier layer can effectively block the filling material from contacting the material in the conductive pillars, thereby avoiding or improving the short circuit phenomenon in the semiconductor structure, avoiding the generation of large currents, and avoiding mechanical damage to electronic components or even devices, thereby improving the quality of semiconductor products.

[0007] In some embodiments, a preset process gas is introduced into the gap to transform the initial barrier layer into an intermediate barrier layer, including: introducing a preset process gas into the gap, the preset process gas reacting with impurity ions in the initial barrier layer to remove at least a portion of the impurity ions in the initial barrier layer to transform the initial barrier layer into an intermediate barrier layer.

[0008] In some embodiments, the predetermined process gas reacts with impurity ions in the initial barrier layer to generate the target gas.

[0009] In some embodiments, the impurity ions include chloride ions, the predetermined process gas includes diborane, and the target gas includes boron trichloride gas and hydrogen chloride gas.

[0010] In some embodiments, the preset supply flow rate of the process gas is 0.7 slm to 0.9 slm.

[0011] In some embodiments, the preset supply time of the process gas is 1 second to 3 seconds.

[0012] In some embodiments, the material of the initial barrier layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0013] In some embodiments, the material of the intermediate barrier layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0014] In some embodiments, the material of the target barrier layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0015] In some embodiments, the process of forming the initial barrier layer includes an atomic layer deposition process.

[0016] In some embodiments, the reactive precursor includes a silicon-containing precursor and a nitrogen-containing precursor.

[0017] In some embodiments, the silicon-containing precursor includes dichlorosilane, and the nitrogen-containing precursor includes ammonia.

[0018] In some embodiments, the temperature of the atomic layer deposition process is 620° C. to 640° C.

[0019] In some embodiments, the supply flow rate of dichlorosilane is 0.7 slm to 0.9 slm, and the supply flow rate of ammonia is 9 slm to 11 slm.

[0020] In some embodiments, the pressure valve state of the atomic layer deposition process is fully open.

[0021] In some embodiments, after introducing the reaction precursor into the gap between adjacent conductive pillars and before introducing the preset process gas into the gap, the method further includes: introducing a cleaning gas into the reaction chamber and simultaneously pumping the cleaning gas to remove reaction byproducts near the surface of the initial barrier layer.

[0022] In some embodiments, the cleaning gas includes nitrogen.

[0023] In some embodiments, the cleaning gas is supplied for a time period of 1 second to 3 seconds.

[0024] In some embodiments, the reaction byproduct includes ammonium chloride.

[0025] According to some embodiments, the present disclosure further provides a semiconductor structure comprising a fabrication method according to any one of the embodiments of the present disclosure, comprising a substrate and a target barrier layer. The substrate is provided with conductive pillars spaced apart along a first direction; the target barrier layer is located on the outer sidewalls of the conductive pillars, and the thickness of the target barrier layer is within a predetermined thickness range.

[0026] In the semiconductor structure described in the above embodiment, the target barrier layer is located on the outer wall of the conductive column and its thickness is within a preset thickness range, which can ensure that the filling material between adjacent conductive columns does not contact the material in the conductive columns, and prevent the grains of the filling material from entering the conductive columns to cause a short circuit. In addition, the film quality and uniformity of the target barrier layer are improved, thereby improving the yield of the semiconductor structure and reducing the product rework rate.

[0027] In some embodiments, the conductive pillar comprises a bit line pillar.

[0028] In some embodiments, the bit line pillar includes a bit line contact plug, a bit line conductive layer, and a bit line protection layer stacked in sequence in a direction away from the substrate.

[0029] In some embodiments, the material of the bit line contact plug includes polysilicon and / or doped polysilicon.

[0030] In some embodiments, the material of the bit line conductive layer includes one or more of titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, and tungsten nitride.

[0031] In some embodiments, the material of the bit line protection layer includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0033] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0034] Figure 2-Figure 4 Schematic diagram of the cross-section of each step of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0035] Figure 5 A schematic flow chart of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0036] Figure 6-Figure 7 A schematic diagram showing the relationship between the supply flow rate of different gases and time in a method for preparing a semiconductor structure provided in different embodiments of the present disclosure;

[0037] Figures 8-13Schematic diagram of the chemical reaction process of particles in each step of a method for preparing a semiconductor structure provided in different embodiments of the present disclosure;

[0038] Figure 14 A schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure;

[0039] Figure 15 A schematic diagram of the etching rate of a barrier layer in a different semiconductor structure provided in one embodiment of the present disclosure.

[0040] Description of reference numerals:

[0041] 10. Substrate; 11. Conductive pillar; 111. Bit line contact plug; 112. Bit line conductive layer; 113. Bit line protection layer; 12. Initial barrier layer; 13. Intermediate barrier layer; 14. Target substrate; 15. Target barrier layer. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are for the purpose of describing specific embodiments only and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0045] Memory is a component used to store programs and various data. It can be categorized by type of memory used: ROM (Read-Only Memory) and RAM (Random Access Memory). Based on the operating principles of the memory cells, random access memory is divided into SRAM (Static RAM) and DRAM. DRAM is a type of semiconductor memory that uses the amount of charge stored in a capacitor to represent a binary bit as 1 or 0. Compared to SRAM, DRAM's advantage lies in its simpler structure—each bit of data requires only one capacitor and one transistor, compared to six transistors typically required for one bit in SRAM. Therefore, DRAM boasts very high density and a higher capacity per unit volume. Compared to SRAM, DRAM offers advantages such as high integration, low power consumption, and low price, making it widely used in large-capacity memory. As memories such as DRAM become more integrated and smaller, the density of the circuit structure within the memory is gradually increasing. This increase in density causes the width of the metal wires forming the circuit structure, as well as the spacing between two adjacent metal wires, to gradually decrease. When the size of the semiconductor is reduced, although the degree of integration is better and the performance is stronger, even small defects generated during the manufacturing process of the small-sized semiconductor structure can have a significant impact on the performance of the semiconductor.

[0046] The structure of a dynamic memory usually includes a capacitor and a transistor connected to the capacitor. The capacitor is used to store charges representing the stored information, and the transistor is a switch that controls the flow and release of charges in the capacitor. When writing data, the word line gives a high level, the transistor is turned on, and the bit line charges the capacitor. When reading, the word line also gives a high level, the transistor is turned on, the capacitor is discharged, and the bit line obtains a read signal. As the characteristic size of the semiconductor structure continues to shrink, the silicon nitride film in traditional technology is used as a barrier layer for the bit line structure. It is used as an etching barrier material when filling the gap between adjacent bit line contact structures to prevent the gap filling material from penetrating into the bit line contact structure and causing a short circuit. Therefore, it is necessary to ensure that the barrier layer has sufficient thickness. However, during the traditional barrier layer preparation process, the barrier layer formed contains a large number of impurities and has poor film uniformity. Before the subsequent gap filling material is deposited between adjacent bitline structures, the excess substrate material and barrier layer material at the bottom of the gap must be wet-etched. At this time, the barrier layer located on the sidewall surface of the conductive pillar is exposed in the gap and contacts the wet-etched material. Due to the large number of impurities in the barrier layer, the insufficient proportion of silicon nitride material, and the loose film structure, the wet etching will etch away a large portion of the barrier layer, causing the barrier layer to become thinner and even expose the surface of the bitline structure, or the thickness of the barrier layer is insufficient to achieve a blocking effect. Therefore, when filling the gap material, the gap material can easily penetrate the barrier layer and contact the bitline structure after deposition, resulting in a short circuit and reducing the yield of the dynamic memory.

[0047] Based on the above technical problems, the present disclosure provides a semiconductor structure and a preparation method thereof to optimize the preparation process of the bit line contact structure in the dynamic memory, prevent the defect of excessive etching of the barrier layer causing short circuit of the bit line contact structure, avoid or improve the device damage caused by the short circuit phenomenon in the memory structure, and improve the quality of the film in the bit line contact structure, thereby reducing the product rework rate and improving the yield of the dynamic memory.

[0048] As an example, see Figure 1 One aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0049] Step S2: providing a substrate, on which conductive pillars are formed and arranged at intervals along a first direction;

[0050] Step S4: introducing a reaction precursor into the gap between adjacent conductive pillars to form an initial barrier layer on the outer sidewalls of the conductive pillars;

[0051] Step S6: introducing a preset process gas into the gap so that the initial barrier layer becomes an intermediate barrier layer; wherein, under the same wet etching conditions, the etching rate of the intermediate barrier layer is lower than the etching rate of the initial barrier layer, and under the same dry etching conditions, the etching rate of the intermediate barrier layer is equal to the etching rate of the initial barrier layer;

[0052] Step S8: removing the substrate and part of the intermediate barrier layer between adjacent conductive pillars, and the remaining intermediate barrier layer constitutes a target barrier layer, and the thickness of the target barrier layer is within a preset thickness range.

[0053] As an example, the first direction may be the ox direction, and the second direction may be the oy direction. In other embodiments, the first direction may also be the oy direction, and the second direction may also be the ox direction.

[0054] In step S2, see Figure 1 Step S2 and Figure 2 The conductive pillar 11 may include a bit line pillar, and the bit line pillar may include a bit line contact plug 111 , a bit line conductive layer 112 , and a bit line protection layer 113 sequentially stacked in a direction away from the substrate 10 .

[0055] As an example, in step S2, conductive pillars 11 spaced apart along a first direction (eg, ox direction) are formed on the substrate 10. The conductive pillars 11 may be bit line pillars. The following steps may be included:

[0056] Step S21: forming a plurality of discrete bit line contact plugs on top of the substrate, wherein the bit line contact plugs are in contact with the substrate thereunder (e.g., the active area thereunder), and the bottom surface of the bit line contact plugs may be lower than the top surface of the substrate;

[0057] Step S22: forming a bit line conductive layer and a bit line protection layer in sequence on top of the bit line contact plug. The stacked bit line contact plug, the bit line conductive layer and the bit line protection layer together constitute a bit line pillar.

[0058] As an example, the material of the bitline contact plug 111 includes polysilicon and / or doped polysilicon. The bitline contact plug 111 is used to connect the active area in the substrate 10 and the bitline conductive layer 112, and its filling material can be the same as the filling material of the gap between adjacent bitline pillars.

[0059] As an example, the material of the bit line conductive layer 112 includes one or more of titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, and tungsten nitride. Specifically, the material of the bit line conductive layer 112 can be a low-resistance material such as tungsten or ruthenium to reduce resistance and increase device operating speed.

[0060] As an example, the material of the bit line protection layer 113 includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride. The preparation methods of each part of the bit line pillar structure are common knowledge to those skilled in the art and will not be elaborated here.

[0061] As an example, the substrate 10 can be made of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistor formed on the substrate 10, so the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0062] As an example, in an embodiment where the substrate 10 comprises a P-type substrate, an active region can be formed by implanting N-type ions; correspondingly, in an embodiment where the substrate 10 comprises an N-type substrate, an active region can be formed by implanting P-type ions. Accordingly, the active region can be a P-type active region or an N-type active region. A P-type active region can form an N-type metal oxide semiconductor (NMOS) device, and an N-type active region can form a P-type metal oxide semiconductor (PMOS) device.

[0063] As an example, P-type ions may include but are not limited to any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions, and N-type impurity ions may include but are not limited to any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0064] In step S4, see Figure 1 Step S4 and Figure 2A reactive precursor is introduced into the gaps between adjacent conductive pillars 11 to form an initial barrier layer 12 on the outer sidewalls of the conductive pillars 11. The initial barrier layer 12 extends along the outer sidewalls of the conductive pillars 11 in a second direction (e.g., the oy direction). In addition to being formed on the outer sidewalls of the conductive pillars 11, the initial barrier layer 12 also forms at the bottom of the gaps between adjacent conductive pillars 11, covering the top surface of the substrate 10. The initial barrier layer 12 formed in this step contains a high amount of impurities, resulting in a high wet etching rate and a tendency to be etched too thin, resulting in an insufficient barrier effect.

[0065] In step S6, refer to Figure 1 Step S6 and Figure 3 , a preset process gas is introduced into the gap to transform the initial barrier layer 12 into the intermediate barrier layer 13; wherein, under the same wet etching conditions, the etching rate of the intermediate barrier layer 13 is less than the etching rate of the initial barrier layer 12, and under the same dry etching conditions, the etching rate of the intermediate barrier layer 13 is equal to the etching rate of the initial barrier layer 12, so as to ensure the film thickness after the gap is subsequently wet-etched.

[0066] In step S8, refer to Figure 1 Step S8 and Figure 4 The substrate 10 and a portion of the intermediate barrier layer 13 between adjacent conductive pillars 11 are removed. The remaining intermediate barrier layer 13 forms a target barrier layer 15, the thickness of which is within a predetermined thickness range. Because the wet etching rate of the intermediate barrier layer 13 is reduced, the etching rate of the intermediate barrier layer 13 on the gap sidewalls is reduced while the wet etching rate of the substrate at the bottom of the gap remains unchanged. After the wet etching is completed, the thickness of the target barrier layer 15 is within the predetermined thickness range, serving as a barrier structure for the bitline contact plug 111. This ensures that the particles of the gapfill material penetrate into the interior of the bitline pillar, thereby improving the short circuit phenomenon of the bitline structure.

[0067] As an example, the etching material used for wet etching may include hydrofluoric acid (HF), which can react with the material of the intermediate barrier layer 13 at the bottom of the gap and the material of the substrate 10, thereby removing excess material at the bottom of the gap to facilitate subsequent filling of a new gap material layer. However, during the etching process, the etching material will contact the intermediate barrier layer 13 on the side wall of the gap, causing part of its volume to be etched away. Since the wet etching rate of the intermediate barrier layer 13 is relatively low, it can still maintain a certain thickness after wet etching, that is, the thickness of the target barrier layer 15 is within a preset thickness range, so as to ensure effective blocking effect on the conductive pillars 11 and improve the operating rate of the semiconductor structure and the electrical performance of the semiconductor structure.

[0068] As an example, after forming the target barrier layer 15, a gap material layer can be filled in the gap between adjacent conductive pillars 11. The gap material layer at least fills the gap between adjacent conductive pillars 11. The gap material layer contacts the target barrier layer 15 to prevent it from penetrating into the interior of the conductive pillars 11 and causing a short circuit.

[0069] In the semiconductor structure fabrication methods described in the above embodiments, an initial barrier layer 12 is first formed by reacting different reaction precursors under certain process conditions. Due to factors such as the presence of multiple elements in the reaction precursors and the introduction of impurities into the film during the deposition process, the initial barrier layer 12 contains a significant amount of impurities in addition to the primary material. Furthermore, a significant amount of reaction byproducts is present in the reaction chamber, which can affect the yield of subsequent processes. If the initial barrier layer 12 is retained as a barrier structure, when the excess material at the bottom of the gap is subsequently etched before filling the gap, the impurity-containing initial barrier layer 12 will be partially etched away. Furthermore, the impurity-containing initial barrier layer 12 exhibits a high wet etching rate and will be largely etched away, exposing the conductive pillars 11 and causing a short circuit in the resulting structure. Therefore, in the present disclosure, after forming the initial barrier layer 12, a predetermined process gas is introduced into the gap to transform the initial barrier layer 12 into an intermediate barrier layer 13. This reduces impurities in the initial barrier layer 12, thereby reducing its wet etching rate and removing residual reaction byproducts in the reaction chamber. During the subsequent wet etching process, the etching rate of the intermediate barrier layer 13 slows down, maintaining a certain film thickness and preventing the conductive pillars 11 from being exposed. The intermediate barrier layer 13 remaining after etching constitutes the target barrier layer 15. Due to the improvement of the preparation process disclosed in the present invention, the thickness of the target barrier layer 15 can be ensured to be within a preset thickness range. When the gap is subsequently filled, the target barrier layer 15 can effectively block the filling material from contacting the material in the conductive pillars 11, thereby avoiding or improving short circuits in the semiconductor structure, preventing the generation of large currents, and preventing mechanical damage to electronic components or even devices, thereby improving the operating speed and electrical performance of the semiconductor structure, and further improving the quality of semiconductor products.

[0070] As an example, see Figure 5 , introducing a preset process gas into the gap so that the initial barrier layer becomes an intermediate barrier layer, including:

[0071] Step S61: introducing a preset process gas into the gap, the preset process gas reacts with the impurity ions in the initial barrier layer, and removes at least a portion of the impurity ions in the initial barrier layer, so that the initial barrier layer becomes an intermediate barrier layer.

[0072] In step S61, refer to Figure 5In step S61, since the preset process gas can remove the residual reaction byproducts in the reaction chamber and the impurities in the initial barrier layer 12, the film quality of the intermediate barrier layer 13 is better than the film quality of the initial barrier layer 12, and the wet etching rate of the film is reduced.

[0073] As an example, a predetermined process gas reacts with impurity ions in the initial barrier layer 12 to generate a target gas. The target gas can remove the impurity ions from the initial barrier layer 12, thereby reducing the impurity content in the intermediate barrier layer 13 to less than that in the initial barrier layer 12. This increases the proportion of the primary material in the intermediate barrier layer 13, improves the film quality, and reduces its wet etching rate.

[0074] As an example, the impurity ions include chloride (Cl) ions, the preset process gas includes diborane (B2H6), and the target gas includes boron trichloride (BCl3) gas and hydrogen chloride (HCl) gas.

[0075] As an example, the preset supply flow rate of the process gas is 0.7 slm to 0.9 slm. Specifically, the preset supply flow rate of the process gas can be 0.7 slm, 0.75 slm, 0.8 slm, 0.85 slm, or 0.9 slm, etc.

[0076] As an example, the preset supply time of the process gas is 1 second to 3 seconds. Specifically, the preset supply time of the process gas can be 1 second, 1.5 seconds, 2 seconds, 2.5 seconds, or 3 seconds.

[0077] As an example, the material of the initial barrier layer 12 includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride. The material of the initial barrier layer 12 also includes impurity ions such as chloride ions.

[0078] As an example, the material of the intermediate barrier layer 13 includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride. The content of impurity ions in the intermediate barrier layer 13 is less than the content of impurity ions in the initial barrier layer 12.

[0079] As an example, the target barrier layer 15 is made of one or more materials selected from silicon nitride, silicon oxynitride, and silicon carbide nitride. The target barrier layer 15 is thinner than the intermediate barrier layer 13 and within a predetermined thickness range to ensure its blocking effect on the bitline pillars.

[0080] As an example, the process of forming the initial barrier layer 12 includes an atomic layer deposition (ALD) process and other methods. The ALD method can make the thickness of the obtained initial barrier layer 12 more uniform.

[0081] As an example, the reactive precursors include a silicon-containing precursor and a nitrogen-containing precursor. The silicon-containing precursor provides silicon elements for chemical reaction, and the nitrogen-containing precursor provides nitrogen elements for chemical reaction, so as to form the initial barrier layer 12 whose main material is silicon nitride.

[0082] As an example, the silicon-containing precursor includes dichlorosilane (SiH2Cl2), and the nitrogen-containing precursor includes ammonia (NH3). Since the silicon-containing precursor provides chloride ions for the reaction, and the chloride ions are located inside the initial barrier layer 12, the generation of impurity ions affects the quality of the silicon nitride film and the wet etching rate.

[0083] As an example, the temperature of the atomic layer deposition process is 620° C. to 640° C. Specifically, the temperature of the atomic layer deposition process can be 620° C., 625° C., 630° C., 635° C., or 640° C., etc., so that the atomic layer deposited thin film is more uniform and has better film quality.

[0084] As an example, the supply flow rate of dichlorosilane is 0.7 slm to 0.9 slm, and the supply flow rate of ammonia is 9 slm to 11 slm. Specifically, the supply flow rate of dichlorosilane can be 0.7 slm, 0.75 slm, 0.8 slm, 0.85 slm, or 0.9 slm, etc., and the supply flow rate of ammonia can be 9 slm, 9.5 slm, 10 slm, 10.5 slm, or 11 slm, etc. The chemical reaction formula of the reaction precursors in the gap is 3SiH2Cl2 + 10NH3 → Si3N4 + 6NH4Cl + 6H2.

[0085] By way of example, reaction byproducts include ammonium chloride (NH 4 Cl), hydrogen (H 2 ), and the like.

[0086] As an example, the pressure valve state of the atomic layer deposition process is fully open to release the pressure generated during the chemical reaction.

[0087] As an example, after the reaction precursor is introduced into the gap between adjacent conductive pillars 11 and before the preset process gas is introduced into the gap, the method further includes:

[0088] Step S5: introducing a cleaning gas into the reaction chamber and simultaneously pumping the cleaning gas to remove reaction byproducts near the surface of the initial barrier layer.

[0089] As an example, the cleaning gas includes nitrogen (N2). By introducing nitrogen into the reaction chamber and extracting the nitrogen using an air pump at the same time, the nitrogen can clean the relevant reaction by-products in the reaction chamber to ensure the normal progress of subsequent reaction processes.

[0090] As an example, the supply time of the cleaning gas is 1s to 3s. Specifically, the supply time of the cleaning gas can be 1s, 1.5s, 2s, 2.5s or 3s, etc. The cleaning gas is supplied in the gap where the reaction precursors are circulated to clean up the reaction by-products.

[0091] As an example, see Figure 6 In conventional processes, when forming a barrier layer on the sidewalls of bitline pillars via atomic layer deposition (ALD), the silicon-containing precursor used for ALD silicon nitride thin films is dichlorosilane. The presence of chlorine in dichlorosilane results in poor film quality, resulting in excessively high etch rates during wet etching and thin films, which can lead to short-circuit defects at the bitline contacts. First, during the period from 0 to t1, dichlorosilane is introduced to provide silicon and introduce chloride ion impurities. Then, during the period from t1 to t2, nitrogen is introduced to purge excess dichlorosilane. During the period from t2 to t3, ammonia is introduced to provide nitrogen, forming a silicon nitride film on the surface of the bitline pillars. During the period from t3 to t4, nitrogen is introduced again to purge excess reaction precursors and reaction byproducts. The steps from 0 to t4 are repeated until the silicon nitride film deposition is complete. The silicon nitride film formed using this deposition process contains a high level of impurities and exhibits poor film quality.

[0092] As an example, see Figure 7 In the preparation method provided herein, during the process of forming the target barrier layer 15 on the sidewalls of the bitline pillars by atomic layer deposition, the temperature of the atomic layer deposition process is 620°C to 640°C. Specifically, the temperature of the atomic layer deposition process can be 620°C, 625°C, 630°C, 635°C, or 640°C, etc. The reaction precursors can be dichlorosilane and ammonia, and the preset process gas can be diborane gas.

[0093] During the time 0-t1', see Figure 7 and Figure 8 First, dichlorosilane is introduced into the gap between adjacent bit line pillars to provide silicon elements, but chloride ion impurities are also introduced in this step. The supply flow rate of dichlorosilane is 0.7slm to 0.9slm. Specifically, the supply flow rate of dichlorosilane can be 0.7slm, 0.75slm, 0.8slm, 0.85slm or 0.9slm, etc.

[0094] During the time t1'-t2', see Figure 7 and Figure 9 Then, nitrogen gas is introduced to purge excess dichlorosilane to ensure that no excess dichlorosilane gas remains in the gap and only the dichlorosilane gas on the sidewall surface of the gap is retained.

[0095] During the time period t2'-t3', please continue to refer to Figure 7 、 Figure 9 and Figure 10 Ammonia gas is then introduced to provide nitrogen, and a silicon nitride film is deposited on the surface of the conductive pillars 11 to form an initial barrier layer 12. Initial barrier layer 12 is primarily made of silicon nitride, but contains a significant amount of chloride ion impurities. The ammonia gas is supplied at a flow rate of 9 to 11 slm. Specifically, the flow rate can be 9 slm, 9.5 slm, 10 slm, 10.5 slm, or 11 slm, among others.

[0096] In the above steps, the chemical reaction formula of the reaction precursor in the gap is 3SiH2Cl2+10NH3→Si3N4+6NH4Cl+6H2, and the excess reaction by-products and ammonia exist in the reaction chamber in the form of gas.

[0097] During the time period t3'-t4', see Figure 7 and Figure 11 , and then continue to introduce nitrogen, and the supply time of nitrogen is 1s to 3s; specifically, the supply time of nitrogen can be 1s, 1.5s, 2s, 2.5s or 3s, etc., and at the same time, the nitrogen is sucked by the air pump to form an air flow in the reaction chamber to purge excess reaction precursors and reaction by-products such as NH4Cl, and remove the reaction by-products on the surface of the initial barrier layer 12 to avoid reaction with the subsequently introduced diborane gas to cause gas loss, so as to enhance the effect of the subsequently introduced diborane gas.

[0098] During the time period t4'-t5', see Figure 7 and Figure 12 , diborane gas is introduced, which reacts with the chloride ions in the initial barrier layer 12 to generate a target gas, thereby forming an intermediate barrier layer 13, wherein the chloride ion content in the intermediate barrier layer 13 is less than the chloride ion content in the initial barrier layer 12, wherein the target gas can be boron trichloride (BCl3) gas and hydrogen chloride (HCl) gas.

[0099] During the time period t5'-t6', see Figure 7 and Figure 13 , nitrogen gas is introduced to remove the target gas and excess diborane gas, which can effectively reduce the chloride ion content in the silicon nitride film to optimize the film quality, so that the initial barrier layer 12 gradually changes into the intermediate barrier layer 13, thereby reducing the wet etching rate and avoiding short-circuit defects of the bit line contact plug 111.

[0100] After the steps 0 to t6' are completed, the steps 0 to t6' are continuously repeated until the silicon nitride film deposition is completed. At this time, the impurity content in the intermediate barrier layer 13 is reduced, the film quality is better, and the wet etching rate is lower.

[0101] It should be understood that, although the various steps in the flowchart of the present disclosure are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, although at least a portion of the steps in the present disclosure may include multiple steps or multiple stages, these steps or stages are not necessarily performed at the same time, but may be performed at different times, and the execution order of these steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0102] As an example, see Figure 14 The present disclosure further provides a semiconductor structure fabricated according to any one of the embodiments of the present disclosure, comprising a substrate 10 and a target barrier layer 15. The substrate 10 is provided with conductive pillars 11 spaced apart along a first direction. The target barrier layer 15 is located on the outer sidewalls of the conductive pillars 11, and the thickness of the target barrier layer 15 is within a predetermined thickness range.

[0103] In the semiconductor structure described in the above embodiment, the target barrier layer 15 is located on the outer wall of the conductive pillar 11 and its thickness is within a preset thickness range, which can ensure that the filling material between adjacent conductive pillars 11 does not contact the material in the conductive pillar 11, preventing the grains of the filling material from entering the conductive pillar 11 to cause a short circuit. In addition, the film quality and uniformity of the target barrier layer 15 are improved, thereby improving the yield of the semiconductor structure and reducing the product rework rate.

[0104] As an example, the conductive pillar 11 may include a bit line pillar.

[0105] As an example, the bitline pillar may include a bitline contact plug 111, a bitline pillar 111, a bitline conductive layer 112, and a bitline protection layer 113 stacked sequentially in a direction away from the substrate 10. The bitline contact plug 111 is in contact with the substrate 10 below it (e.g., the active area directly below it). The bottom surface of the bitline contact plug 111 may also be lower than the top surface of the substrate 10. The bitline contact plug 111 is used to connect the active area in the substrate 10 and the bitline conductive layer 112, and its filling material may be the same as the filling material of the gap between adjacent bitline pillars.

[0106] As an example, the material of the bit line contact plug 111 includes polysilicon and / or doped polysilicon.

[0107] As an example, the material of the bit line conductive layer 112 includes one or more of titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide, and tungsten nitride. Specifically, the material of the bit line conductive layer 112 can be a low-resistance material such as tungsten or ruthenium to reduce resistance and increase device operating speed.

[0108] As an example, the material of the bit line protection layer 113 includes one or more of silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0109] As an example, see Figure 15 The first group shows the etching rate of the initial barrier layer 12, with a wet etching rate of 12.25 nm / min and a dry etching rate of 34.51 nm / min. The second group shows the etching rate of the intermediate barrier layer 13, with a wet etching rate of 11.44 nm / min and a dry etching rate of 34.45 nm / min. It can be seen that after reducing the chloride ion impurity content in the intermediate barrier layer 13, the wet etching rate of the intermediate barrier layer 13 decreases significantly, while the dry etching rate remains almost unchanged. Therefore, when wet etching the intermediate barrier layer 13, the etching rate decreases and the etched volume decreases, thereby ensuring that the thickness of the target barrier layer 15 is within a preset thickness range, serving as a barrier layer for the sidewalls of the bitline pillars, thereby preventing short circuits in the bitline contact plugs 111, improving the yield of the memory device, reducing the rework rate, and thereby reducing the manufacturing cost of the semiconductor structure and improving its manufacturing efficiency.

[0110] In the semiconductor structure and preparation method thereof in the above-mentioned embodiment, an initial barrier layer containing impurity ions is first formed between adjacent conductive pillars, and then a preset process gas is introduced to remove the impurity ions in the initial barrier layer to form an intermediate barrier layer with a lower wet etching rate. This ensures that when the gap bottom material between adjacent conductive pillars is wet-etched, the etching rate of the intermediate barrier layer is low and the etched volume is small, thereby forming a target barrier layer with a thickness within a preset thickness range, which can prevent the gap material layer from penetrating into the interior of the conductive pillars, thereby avoiding short circuits in the conductive pillars, thereby improving the preparation yield of the semiconductor structure, avoiding the generation of large currents, and avoiding mechanical damage to electronic components or even devices, thereby improving the operating speed of the semiconductor structure and the electrical performance of the semiconductor structure, and thus improving the quality of semiconductor products.

[0111] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0112] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0113] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art could make various modifications and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which conductive pillars are formed and arranged at intervals along a first direction; Introducing a reaction precursor into the gap between adjacent conductive pillars to form an initial barrier layer on the outer sidewalls of the conductive pillars; A preset process gas is introduced into the gap so that the initial barrier layer becomes an intermediate barrier layer; wherein, under the same wet etching conditions, the etching rate of the intermediate barrier layer is less than the etching rate of the initial barrier layer, and under the same dry etching conditions, the etching rate of the intermediate barrier layer is equal to the etching rate of the initial barrier layer; removing the substrate and part of the intermediate barrier layer between adjacent conductive pillars, so that the remaining intermediate barrier layer constitutes a target barrier layer, and the thickness of the target barrier layer is within a preset thickness range; Introducing a preset process gas into the gap so that the initial barrier layer becomes an intermediate barrier layer, comprising: A preset process gas is introduced into the gap, and the preset process gas reacts with the impurity ions in the initial barrier layer to remove at least a portion of the impurity ions in the initial barrier layer, so that the initial barrier layer becomes an intermediate barrier layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The preset process gas reacts with the impurity ions in the initial barrier layer to generate a target gas.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The impurity ions include chloride ions, the preset process gas includes diborane, and the target gas includes boron trichloride gas and hydrogen chloride gas.

4. The method for preparing a semiconductor structure according to claim 3, wherein: The preset process gas supply flow rate is 0.7slm to 0.9slm; and / or The preset process gas supply time is 1s to 3s.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, wherein: Include at least one of the following features: The material of the initial barrier layer includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride; The material of the intermediate barrier layer includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride; The material of the target barrier layer includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 4, wherein: Include at least one of the following features: The process of forming the initial barrier layer includes an atomic layer deposition process; The reaction precursors include a silicon-containing precursor and a nitrogen-containing precursor.

7. The method for preparing a semiconductor structure according to claim 6, wherein: The silicon-containing precursor includes dichlorosilane, and the nitrogen-containing precursor includes ammonia.

8. The method for preparing a semiconductor structure according to claim 7, wherein: Include at least one of the following features: The temperature of the atomic layer deposition process is 620°C to 640°C; The supply flow rate of the dichlorosilane is 0.7slm to 0.9slm, and the supply flow rate of the ammonia is 9slm to 11slm; The pressure valve state of the atomic layer deposition process is fully open.

9. The method for preparing a semiconductor structure according to claim 8, wherein: After the reaction precursor is introduced into the gap between the adjacent conductive pillars and before the preset process gas is introduced into the gap, the method further includes: A cleaning gas is introduced into the reaction chamber and simultaneously the cleaning gas is pumped to remove reaction byproducts near the surface of the initial barrier layer.

10. The method for preparing a semiconductor structure according to claim 9, wherein: Include at least one of the following features: The cleaning gas includes nitrogen; The supply time of the cleaning gas is 1s to 3s; The reaction byproducts include ammonium chloride.

11. A semiconductor structure prepared by the method according to any one of claims 1 to 10, characterized in that: include: a substrate having conductive columns arranged at intervals along a first direction; The target barrier layer is located on the outer side wall of the conductive pillar, and the thickness of the target barrier layer is within a preset thickness range.

12. The semiconductor structure according to claim 11, wherein: The conductive pillars include bit line pillars.

13. The semiconductor structure according to claim 12, wherein: The bit line pillar includes a bit line contact plug, a bit line conductive layer and a bit line protection layer which are sequentially stacked in a direction away from the substrate.

14. The semiconductor structure according to claim 13, wherein: Include at least one of the following features: The material of the bit line contact plug includes polysilicon and / or doped polysilicon; The material of the bit line conductive layer includes one or more of titanium, tungsten, cobalt, nickel, tantalum, tantalum titanium, tungsten silicide and tungsten nitride; The material of the bit line protection layer includes one or more of silicon nitride, silicon oxynitride and silicon carbide nitride.

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