Memory and manufacturing method thereof, and electronic device

Abstract

The present disclosure relates to a memory, a manufacturing method thereof, and an electronic device. The memory includes a memory layer. The manufacturing method of the memory includes the following steps. An initial first insulating layer is formed to cover the sidewalls of the conductive pattern layer and the sidewalls of the sacrificial pattern layer. A word line hole is formed along a direction perpendicular to the substrate, penetrating the conductive unit and the corresponding sacrificial pattern layer. An initial semiconductor layer, a first dielectric layer, and a word line covering the first dielectric layer away from the surface of the initial semiconductor layer and filling the word line hole are sequentially formed on the sidewalls of the word line hole. The initial first insulating layer on the sidewalls of the sacrificial pattern layer is removed to form a first insulating layer. The sacrificial pattern layer is removed to expose the initial semiconductor layer in the word line hole in the sacrificial pattern layer. The initial semiconductor layer is etched to form semiconductor portions respectively located in the conductive unit. The present disclosure can realize the simple and convenient removal of parasitic transistors from the outside, thereby improving the performance of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the advancement of communications and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and higher performance. Three-dimensional dynamic random access memory (3D-DRAM) can achieve higher integration density and larger storage capacity. Currently, the performance of 3D-DRAM devices continues to improve. Summary of the Invention

[0003] Based on this, the embodiments of the present disclosure provide a memory and a manufacturing method thereof, and an electronic device, which are beneficial for reducing the parasitic capacitance of the memory to further improve the memory performance.

[0004] According to some embodiments, the present disclosure provides a method for manufacturing a memory, comprising the following steps:

[0005] A plurality of conductive pattern layers and a plurality of sacrificial pattern layers are alternately stacked in a direction perpendicular to the substrate; wherein the conductive pattern layers include: bit lines extending in a column direction, and a plurality of conductive units integrally connected to the bit lines and spaced apart in the column direction; an orthographic projection of the conductive pattern layer on the substrate is located within an orthographic projection of the sacrificial pattern layer on the substrate, and a gap exists between an outer boundary of the orthographic projection of the conductive pattern layer on the substrate and an outer boundary of the orthographic projection of the sacrificial pattern layer on the substrate;

[0006] forming an initial first insulating layer covering the sidewalls of the conductive pattern layer and the sidewalls of the sacrificial pattern layer, wherein the initial first insulating layer and the sacrificial pattern layer are made of different materials;

[0007] A wordline hole is formed perpendicularly to the substrate, penetrating the conductive unit and the corresponding sacrificial pattern layer. The wordline hole in the conductive unit exposes the sidewalls of the conductive pattern layer and the initial first insulating layer disposed on the same layer as the conductive pattern layer, so that each conductive unit is separated into two independent parts. The sacrificial pattern layer located between two adjacent conductive pattern layers is exposed, and the sacrificial pattern layer completely surrounds the wordline hole.

[0008] forming an initial semiconductor layer, a first dielectric layer, and a word line in sequence on the sidewalls of the word line hole;

[0009] Etching the initial first insulating layer in a region of the initial first insulating layer between two adjacent conductive units connected to the same bit line along a direction perpendicular to the substrate to form a through hole, wherein the sidewall of the through hole exposes the sacrificial pattern layer, and the patterned initial first insulating layer forms a first insulating layer;

[0010] removing the sacrificial pattern layer in each region between adjacent conductive pattern layers in the through hole to expose the initial semiconductor layer between the adjacent conductive pattern layers;

[0011] The initial semiconductor layer between adjacent conductive pattern layers is removed in the through hole to form a plurality of mutually independent semiconductor portions corresponding to the plurality of conductive units.

[0012] The removed area of ​​the sacrificial pattern layer and the etched area of ​​the initial semiconductor layer are backfilled with insulating material.

[0013] According to some embodiments, before sequentially forming an initial semiconductor layer, a first dielectric layer, and a word line covering a surface of the first dielectric layer facing away from the initial semiconductor layer and filling the word line hole on the sidewalls of the word line hole, the manufacturing method further includes:

[0014] forming a contact layer on the sidewall of the word line hole; wherein the contact layer is used to reduce the contact resistance between the conductive unit and the semiconductor portion, and the contact layer is in contact with the conductive pattern layer, the sacrificial pattern layer, and the initial first insulating layer;

[0015] The contact layer is patterned to retain an area in contact with the conductive pattern layer.

[0016] According to some embodiments, the distance between two etched surfaces of the sacrificial pattern layer exposed in the wordline hole and opposite to each other in the row direction is a first distance; the distance between two etched surfaces of the conductive unit exposed in the wordline hole is a second distance;

[0017] The thickness of the contact layer is less than or equal to half of the difference between the second distance and the first distance.

[0018] According to some embodiments, before forming the contact layer on the sidewall of the word line hole, the manufacturing method further includes: performing an etch-back process on the conductive pattern layer exposed by the word line hole;

[0019] The contact layer is patterned to retain only the area in contact with the conductive pattern layer, including: forming the contact layer on the sidewall of the word line hole, and then removing the contact layer in contact with the initial first insulating layer and the sacrificial pattern layer by dry etching in the word line hole.

[0020] According to some embodiments, forming multiple conductive pattern layers and multiple sacrificial pattern layers alternately stacked in a direction perpendicular to a substrate includes the following steps:

[0021] forming multiple layers of conductive material and multiple layers of sacrificial material alternately stacked in a direction perpendicular to the substrate;

[0022] forming a first mask layer above the multi-layer conductive material layer and the multi-layer sacrificial material layer; the first mask layer has a first pattern, and the first pattern is used to define the formation area of ​​the bit line and each conductive unit;

[0023] Anisotropically etching the multiple conductive material layers and the multiple sacrificial material layers to form multiple grooves penetrating the conductive material layers and the sacrificial material layers, so as to transfer the first pattern into the conductive material layers and the sacrificial material layers, thereby forming multiple initial conductive pattern layers and multiple sacrificial pattern layers that are alternately stacked;

[0024] removing the first mask layer;

[0025] An isotropic etching process is adopted in the trench to etch back the sidewalls of each initial conductive pattern layer to form a plurality of conductive pattern layers.

[0026] According to some embodiments, the first insulating layer and the sacrificial pattern layer are made of different materials, and the first insulating layer and the sacrificial pattern layer have different etching selectivities.

[0027] According to some embodiments, the material of the first insulating layer includes silicon oxide; and the material of the sacrificial pattern layer includes silicon nitride, aluminum oxide, or polysilicon.

[0028] According to some embodiments, before forming the word line holes penetrating the conductive units and the corresponding sacrificial pattern layers in a direction perpendicular to the substrate, the manufacturing method further includes the following steps:

[0029] forming a second mask layer above the initial first insulating layer, the multi-layer conductive pattern layer, and the multi-layer sacrificial pattern layer; the second mask layer has a first opening pattern, and the first opening pattern is used to define a formation area of ​​a storage capacitor;

[0030] Based on the first opening pattern, a portion of the initial first insulating layer and a portion of the sacrificial pattern layer are removed to expose ends of each conductive unit away from the bit line, where the ends constitute first electrodes of the storage capacitor;

[0031] Depositing a dielectric material on the upper and lower surfaces and sidewalls of the first electrode to form a second dielectric layer;

[0032] A conductive material is deposited on a surface of the second dielectric layer away from the first electrode to form a second electrode of the storage capacitor.

[0033] According to some embodiments, depositing a conductive material on a surface of the second dielectric layer facing away from the first electrode to form a second electrode of the storage capacitor further includes the following steps:

[0034] Depositing a conductive material on a surface of the second dielectric layer facing away from the first electrode to form a second electrode material layer;

[0035] The second electrode material layer is ground using the top sacrificial pattern layer as a grinding stop layer and the second mask layer is removed simultaneously to form a second electrode.

[0036] According to some embodiments, removing a portion of the initial first insulating layer and a portion of the sacrificial pattern layer based on the first opening pattern includes the following steps:

[0037] Based on the first opening pattern, removing a portion of the initial first insulating layer;

[0038] The sacrificial pattern layer is isotropically etched based on the first opening pattern to remove the sacrificial pattern layer below the first opening pattern.

[0039] According to some embodiments, after forming the second electrode of the storage capacitor, forming a word line hole penetrating the conductive unit and the corresponding sacrificial pattern layer in a direction perpendicular to the substrate includes the following steps:

[0040] forming a third mask layer over the second electrode, the initial first insulating layer, the multi-layer conductive pattern layer, and the multi-layer sacrificial pattern layer; the third mask layer having a second opening pattern, the second opening pattern being used to define a word line formation area;

[0041] Based on the second opening pattern, etching the multi-layer conductive pattern layer and the multi-layer sacrificial pattern layer to form a word line initial accommodating groove;

[0042] removing the third mask layer;

[0043] An isotropic etching process is adopted to etch back the surface of each conductive unit exposed in the initial word line receiving groove to form a word line hole.

[0044] According to some embodiments, removing the initial first insulating layer on the sidewalls of the sacrificial pattern layer includes the following steps:

[0045] forming a fourth mask layer over the second electrode, the initial first insulating layer, the multi-layer conductive pattern layer, and the multi-layer sacrificial pattern layer; the fourth mask layer having a third opening pattern, the third opening pattern being used to define a removal area of ​​the initial first insulating layer;

[0046] Based on the second opening pattern, the initial first insulating layer on the sidewall of the sacrificial pattern layer is removed to form a through hole; the through hole exposes a portion of the sidewall of the sacrificial pattern layer and a portion of the surface of the second dielectric layer;

[0047] The fourth mask layer is removed.

[0048] According to some embodiments, the sacrificial pattern layer is removed by an isotropic etching process based on the through hole.

[0049] The initial semiconductor layer is etched to form semiconductor portions respectively located in the conductive units, including: using the first dielectric layer as an etch stop layer, isotropically etching the initial semiconductor layer exposed in the through hole to form the semiconductor portions.

[0050] According to some embodiments, another aspect of the present disclosure provides a memory device comprising: a substrate and a plurality of conductive layers stacked in a direction perpendicular to the substrate. Each conductive layer comprises: a bit line extending in a column direction, and a plurality of conductive units arranged in a column direction; the conductive units comprise a first conductive portion integrally connected to the bit line, and a second conductive portion spaced apart from the first conductive portion in a row direction; the row direction and the column direction are parallel to the substrate and intersect.

[0051] The memory further includes: a plurality of word lines, a plurality of semiconductor parts, a plurality of first insulating layers and a second insulating layer. The word line extends in a direction perpendicular to the substrate and is located between the first conductive part and the second conductive part of the corresponding conductive unit; the side wall of the word line is covered with a first dielectric layer. The semiconductor part surrounds the word line and is located on the surface of the first dielectric layer facing away from the word line, and between the first conductive part and the second conductive part of the corresponding conductive unit. The first insulating layer is located in the gap between two adjacent conductive units in the column direction, and covers the side walls of the corresponding first conductive part, the second conductive part and the semiconductor part in the row direction, and extends to cover the side walls of the bit line located in the gap. The second insulating layer is located on the upper and lower surfaces of each conductive layer, and extends to cover the side walls of the first insulating layer exposed in the gap, and is connected to the multiple first insulating layers to form an integrated structure.

[0052] According to some embodiments, the memory further includes: a contact layer between each semiconductor portion and the first conductive portion, and a contact layer between each semiconductor portion and the second conductive portion; the work function of the contact layer is between the work function of the conductive unit and the work function of the semiconductor portion.

[0053] According to some embodiments, the material of the contact layer includes titanium, titanium nitride, thallium, or thallium nitride, the material of the first conductive portion and the second conductive portion includes tungsten, and the material of the semiconductor portion is a metal oxide semiconductor.

[0054] According to some embodiments, the present disclosure provides, in another aspect, an electronic device, comprising: a memory as described in any one of the aforementioned embodiments.

[0055] The embodiments of the present disclosure may or may have at least the following advantages:

[0056] In the disclosed embodiments, wordline holes are formed perpendicular to the substrate, penetrating multiple layers of conductive units and corresponding sacrificial pattern layers. An initial semiconductor layer is then formed on the sidewalls of the wordline holes. The sacrificial pattern layer is removed to expose the initial semiconductor layer within the wordline holes, and then the initial semiconductor layer is etched to form multiple independent semiconductor portions. By exposing the initial semiconductor layer and then etching, parasitic transistors can be simply and conveniently removed from the outside, effectively reducing the parasitic capacitance of transistors within the memory, thereby improving memory performance.

[0057] Furthermore, in some embodiments of the present disclosure, before forming the initial semiconductor layer, contact layers are formed on the two etched surfaces of the conductive elements exposed within the wordline holes. This allows the contact layer to be selectively retained between the wordline holes and the multi-layer conductive pattern layer, effectively reducing the contact resistance of the memory device and further improving memory performance by utilizing the contact layer as the contact structure between the semiconductor portion and the conductive elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0059] Figure 1 A schematic flow chart of a method for manufacturing a memory provided in some embodiments;

[0060] Figure 2 A schematic diagram of a process for forming a conductive pattern layer and a sacrificial pattern layer in a method for manufacturing a memory provided in some embodiments;

[0061] Figure 3 A schematic diagram of a process for forming a first insulating layer in a method for manufacturing a memory provided in some embodiments;

[0062] Figure 4 A schematic diagram of a process for forming a word line hole in a method for manufacturing a memory provided in some embodiments;

[0063] Figure 5 Schematic diagram of the structure obtained in S11 in some embodiments;

[0064] Figure 5a for Figure 5 A schematic cross-sectional view of a structure shown at section C1;

[0065] Figure 5b for Figure 5 A schematic cross-sectional view of a structure shown at section C2;

[0066] Figure 5c for Figure 5 A schematic cross-sectional view of a structure shown at section C3;

[0067] Figure 6 Schematic diagram of the structure obtained in S13 in some embodiments;

[0068] Figure 6a for Figure 6 A schematic cross-sectional view of a structure shown at section C1;

[0069] Figure 6b for Figure 6 A schematic cross-sectional view of a structure shown at section C2;

[0070] Figure 6c for Figure 6 A schematic cross-sectional view of a structure shown at section C3;

[0071] Figure 7 Schematic diagram of the structure obtained in S14 in some embodiments;

[0072] Figure 7a for Figure 7 A schematic cross-sectional view of a structure shown at section C1;

[0073] Figure 7b for Figure 7 A schematic cross-sectional view of a structure shown at section C2;

[0074] Figure 7c for Figure 7 A schematic cross-sectional view of a structure shown at section C3;

[0075] Figure 8 Schematic diagram of the structure obtained in S20 in some embodiments;

[0076] Figure 8a for Figure 8 A schematic cross-sectional view of a structure shown at section C1;

[0077] Figure 8b for Figure 8 A schematic cross-sectional view of a structure shown at section C2;

[0078] Figure 8c for Figure 8 A schematic cross-sectional view of a structure shown at section C3;

[0079] Figure 9 Schematic diagram of the structure obtained in S220 in some embodiments;

[0080] Figure 9a for Figure 9 A schematic cross-sectional view of a structure shown at section C1;

[0081] Figure 9b for Figure 9 A schematic cross-sectional view of a structure shown at section C2;

[0082] Figure 9c for Figure 9 A schematic cross-sectional view of a structure shown at section C3;

[0083] Figure 10 Schematic diagram of the structure obtained in S240 in some embodiments;

[0084] Figure 10a for Figure 10 A schematic cross-sectional view of a structure shown at section C1;

[0085] Figure 10b for Figure 10 A schematic cross-sectional view of a structure shown at section C2;

[0086] Figure 10c for Figure 10 A schematic cross-sectional view of a structure shown at section C3;

[0087] Figure 11 Schematic diagram of the structure obtained in S32 in some embodiments;

[0088] Figure 11a for Figure 11 A schematic cross-sectional view of a structure shown at section C1;

[0089] Figure 11b for Figure 11 A schematic cross-sectional view of a structure shown at section C2;

[0090] Figure 11c for Figure 11 A schematic cross-sectional view of a structure shown at section C3;

[0091] Figure 12 Schematic diagram of the structure obtained in S34 in some embodiments;

[0092] Figure 12a for Figure 12 A schematic cross-sectional view of a structure shown at section C1;

[0093] Figure 12b for Figure 12 A schematic cross-sectional view of a structure shown at section C2;

[0094] Figure 12c for Figure 12 A schematic cross-sectional view of a structure shown at section C3;

[0095] Figure 13 Schematic diagram of the structure obtained in S40 in some embodiments;

[0096] Figure 13a for Figure 13 A schematic cross-sectional view of a structure shown at section C1;

[0097] Figure 13b for Figure 13A schematic cross-sectional view of a structure shown at section C2;

[0098] Figure 13c for Figure 13 A schematic cross-sectional view of a structure shown at section C3;

[0099] Figure 14 Schematic diagram of the structure obtained in S52 in some embodiments;

[0100] Figure 14a for Figure 14 A schematic cross-sectional view of a structure shown at section C1;

[0101] Figure 14b for Figure 14 A schematic cross-sectional view of a structure shown at section C2;

[0102] Figure 14c for Figure 14 A schematic cross-sectional view of a structure shown at section C3;

[0103] Figure 15 Schematic diagram of the structure obtained in S70 in some embodiments;

[0104] Figure 15a for Figure 15 A schematic cross-sectional view of a structure shown at section C1;

[0105] Figure 15b for Figure 15 A schematic cross-sectional view of a structure shown at section C2;

[0106] Figure 15c for Figure 15 A schematic cross-sectional view of a structure shown at section C3;

[0107] Figure 16 Schematic diagram of the structure obtained in S80 in some embodiments;

[0108] Figure 16a for Figure 16 A schematic cross-sectional view of a structure shown at section C1;

[0109] Figure 16b for Figure 16 A schematic cross-sectional view of a structure shown at section C2;

[0110] Figure 16c for Figure 16 The structure shown is a cross-sectional schematic diagram at section C3.

[0111] Description of reference numerals:

[0112] 1-substrate; A-first electrode; B-second electrode; BL-bit line; WL-word line; G-groove; G1-word line initial receiving groove; G11-word line hole; G2-through hole;

[0113] L1-conductive material layer; L2-sacrificial material layer; Y1-first mask material layer; Y11-first mask layer; L11-initial conductive pattern layer; 111-conductive unit; L111-conductive pattern layer; L21-sacrificial pattern layer; L3-initial first insulating layer; L31-first insulating layer; Y2-second mask layer; L4-second dielectric layer; L5-contact layer; L6-initial semiconductor layer; L7-first dielectric layer; L8-second insulating layer. DETAILED DESCRIPTION

[0114] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0115] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0116] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0117] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0118] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0119] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0120] According to some embodiments, the present disclosure provides, on one hand, a memory manufacturing method applicable to 3D stacking of one-transistor or two-transistor memory cells, as well as 3D stacking of memory cells with or without capacitors. This disclosure uses a memory cell with one transistor and one capacitor as an example for illustration.

[0121] See also Figure 1 , a memory manufacturing method includes steps S10 to S80.

[0122] S10, forming a plurality of alternating conductive pattern layers and a plurality of sacrificial pattern layers in a direction perpendicular to the substrate; wherein the conductive pattern layer includes: a bit line extending in a column direction, and a plurality of conductive units integrally connected to the bit line and arranged at intervals in the column direction; the orthographic projection of the conductive pattern layer on the substrate is located within the orthographic projection of the sacrificial pattern layer on the substrate, and there is a gap between the outer boundary of the orthographic projection of the conductive pattern layer on the substrate and the outer boundary of the orthographic projection of the sacrificial pattern layer on the substrate.

[0123] S20 , forming an initial first insulating layer covering the sidewalls of the conductive pattern layer and the sidewalls of the sacrificial pattern layer, wherein the initial first insulating layer and the sacrificial pattern layer are made of different materials.

[0124] S30, forming a word line hole penetrating the conductive unit and the corresponding sacrificial pattern layer along a direction perpendicular to the substrate; the word line hole in the conductive unit exposes the side wall of the conductive pattern layer and the initial first insulating layer arranged on the same layer as the conductive pattern layer, so that each conductive unit is separated into two independent parts, and at the same time exposes the sacrificial pattern layer located between the two adjacent conductive pattern layers, and the sacrificial pattern layer completely surrounds the word line hole.

[0125] S40 , sequentially forming an initial semiconductor layer, a first dielectric layer, and a word line on the sidewall of the word line hole.

[0126] S50, etching the initial first insulating layer in the initial first insulating layer region between two adjacent conductive units connected to the same bit line along a direction perpendicular to the substrate to obtain a through hole, with the sidewall of the through hole exposing the sacrificial pattern layer, and forming the first insulating layer after patterning.

[0127] S60 , removing the sacrificial pattern layer in each region between adjacent conductive pattern layers in the through hole to expose the initial semiconductor layer between the adjacent conductive pattern layers.

[0128] S70 , removing the initial semiconductor layer between adjacent conductive pattern layers in the through hole to form a plurality of mutually independent semiconductor portions corresponding to the plurality of conductive units.

[0129] S80 , backfilling the removed area of ​​the sacrificial pattern layer and the etched area of ​​the initial semiconductor layer with an insulating material.

[0130] In an embodiment of the present disclosure, a method for removing parasitic transistors in a vertical 3D stacked memory is provided. After forming alternating layers of conductive pattern layers and sacrificial pattern layers, and after initially etching the trenches, the initial semiconductor layer is etched back. This process is then used to remove the initial semiconductor layer between two adjacent initial semiconductor layers outside the wordline holes, thereby removing the parasitic transistors. This simple process effectively reduces the parasitic capacitance of transistors within the memory, thereby improving memory performance. It also effectively protects the channel region and the source and drain regions from contamination from multiple etching steps.

[0131] In some embodiments, see Figure 2 Step S10 forms multiple conductive pattern layers and multiple sacrificial pattern layers alternately stacked along a direction perpendicular to the substrate, including steps S11 to S15.

[0132] S11 , forming multiple conductive material layers and multiple sacrificial material layers alternately stacked in a direction perpendicular to the substrate.

[0133] S12 , forming a first mask layer above the multiple conductive material layers and the multiple sacrificial material layers; the first mask layer has a first pattern, and the first pattern is used to define the formation areas of the bit lines and each conductive unit.

[0134] S13, anisotropically etching the multiple conductive material layers and the multiple sacrificial material layers to form multiple grooves penetrating the conductive material layers and the sacrificial material layers, so as to transfer the first pattern to the conductive material layers and the sacrificial material layers, thereby forming multiple initial conductive pattern layers and multiple sacrificial pattern layers that are alternately stacked.

[0135] S14, removing the first mask layer.

[0136] S15, etching back the sidewalls of each initial conductive pattern layer in the trench using an isotropic etching process to form a plurality of conductive pattern layers.

[0137] In some embodiments, see Figure 3 Step S50 removes the initial first insulating layer on the sidewall of the sacrificial pattern layer, including steps S51 to S53.

[0138] S51, forming a fourth mask layer above the second electrode, the initial first insulating layer, the multi-layer conductive pattern layer and the multi-layer sacrificial pattern layer; the fourth mask layer has a third opening pattern, and the third opening pattern is used to define a removal area of ​​the initial first insulating layer.

[0139] S52 , based on the second opening pattern, removing the initial first insulating layer on the sidewall of the sacrificial pattern layer to form a through hole; the through hole exposes a portion of the sidewall of the sacrificial pattern layer and a portion of the surface of the second dielectric layer.

[0140] S53, removing the fourth mask layer.

[0141] In some embodiments, step S70 etches the initial semiconductor layer to form semiconductor portions respectively located in the conductive units, including: using the first dielectric layer as an etch stop layer, isotropically etching the initial semiconductor layer exposed in the through hole to form the semiconductor portions.

[0142] It should be noted that in the above embodiments, there is no strict order restriction for the execution of the steps in the method. These steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily have to be completed at the same time, but may be executed at different times. The order of execution of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps. The method is limited to being able to achieve the preparation of the corresponding memory.

[0143] Based on this, with respect to the manufacturing methods provided in some of the above embodiments, the present disclosure provides some methods in the following embodiments as possible implementations of the above manufacturing methods.

[0144] In some embodiments, see Figure 4 Before step S30 forms a word line hole penetrating the conductive unit and the corresponding sacrificial pattern layer in a direction perpendicular to the substrate, the manufacturing method further includes steps S210 to S240.

[0145] S210 , forming a second mask layer above the initial first insulating layer, the multi-layer conductive pattern layer, and the multi-layer sacrificial pattern layer; the second mask layer has a first opening pattern, and the first opening pattern is used to define a formation area of ​​a storage capacitor.

[0146] S220 , based on the first opening pattern, removing a portion of the initial first insulating layer and a portion of the sacrificial pattern layer to expose ends of each conductive unit away from the bit line, the ends forming first electrodes of the storage capacitor.

[0147] S230 , depositing a dielectric material on the upper and lower surfaces and sidewalls of the first electrode to form a second dielectric layer.

[0148] S240 , depositing a conductive material on a surface of the second dielectric layer facing away from the first electrode to form a second electrode of the storage capacitor.

[0149] In some embodiments, step S220 removes a portion of the initial first insulating layer and a portion of the sacrificial pattern layer based on the first opening pattern, and includes steps S221 - S222 .

[0150] S221 , based on the first opening pattern, removing a portion of the initial first insulating layer.

[0151] S222 , performing isotropic etching on the sacrificial pattern layer based on the first opening pattern to remove the sacrificial pattern layer below the first opening pattern.

[0152] In some embodiments, step S240 deposits a conductive material on a surface of the second dielectric layer facing away from the first electrode to form a second electrode of the storage capacitor, and further includes steps S241 - S242 .

[0153] S241 , depositing a conductive material on a surface of the second dielectric layer facing away from the first electrode to form a second electrode material layer.

[0154] S242 , using the top sacrificial pattern layer as a grinding stop layer, grinding the second electrode material layer and simultaneously removing the second mask layer to form a second electrode.

[0155] In some embodiments, please refer to Figure 4 After forming the second electrode of the storage capacitor in step S240, step S30 forms a word line hole penetrating the conductive unit and the corresponding sacrificial pattern layer in a direction perpendicular to the substrate, including the following steps.

[0156] S31, forming a third mask layer above the second electrode, the initial first insulating layer, the multi-layer conductive pattern layer and the multi-layer sacrificial pattern layer; the third mask layer has a second opening pattern, and the second opening pattern is used to define a word line formation area.

[0157] S32 , etching the multiple conductive pattern layers and the multiple sacrificial pattern layers based on the second opening pattern to form initial word line accommodating grooves.

[0158] S33, removing the third mask layer.

[0159] S34 , using an isotropic etching process, etching back the surface of each conductive unit exposed in the initial word line receiving groove to form a word line hole.

[0160] In some embodiments, the orthographic projection of the wordline hole on the substrate comprises a rectangular shape. The initial first insulating layer is exposed on opposite sidewalls of the wordline hole in the column direction. In step S40, before sequentially forming an initial semiconductor layer, a first dielectric layer, and a wordline covering the first dielectric layer and facing away from the initial semiconductor layer and filling the wordline hole on the sidewalls of the wordline hole, the manufacturing method further comprises: forming a contact layer on the sidewalls of the wordline hole; wherein the contact layer is used to reduce the contact resistance between the conductive unit and the semiconductor portion, and the contact layer is in contact with the conductive pattern layer, the sacrificial pattern layer, and the initial first insulating layer; and patterning the contact layer to retain an area in contact with the conductive pattern layer.

[0161] In some embodiments of the present disclosure, before forming the initial semiconductor layer, contact layers are formed on the two etched surfaces of the conductive unit exposed within the wordline hole. This allows the contact layer to be selectively retained between the wordline hole and the multi-layer conductive pattern layer, allowing it to serve as the contact structure between the semiconductor portion and the conductive unit, effectively reducing the contact resistance of the memory device and further improving memory performance.

[0162] In some embodiments of the present disclosure, before forming the contact layer on the sidewall of the word line hole, the manufacturing method further includes: performing an etch-back process on the conductive pattern layer exposed by the word line hole.

[0163] The contact layer is patterned to retain only the area in contact with the conductive pattern layer, including: forming the contact layer on the sidewall of the word line hole, and then removing the contact layer in contact with the initial first insulating layer and the sacrificial pattern layer by dry etching in the word line hole.

[0164] In order to more clearly illustrate the manufacturing method provided by the above embodiment, Figures 5 to 16c The manufacturing method is described in detail.

[0165] In some embodiments, see Figure 2 Step S10 forms multiple conductive pattern layers and multiple sacrificial pattern layers alternately stacked along a direction perpendicular to the substrate, including steps S11 to S15.

[0166] In step S11, refer to Figure 5 and Figure 5a 、 Figure 5b 、 Figure 5c , multiple conductive material layers L1 and multiple sacrificial material layers L2 are alternately stacked along a direction perpendicular to the substrate 1 (eg, the Z direction).

[0167] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0168] Illustratively, the conductive material layer L1 includes a metal layer, such as a metal tungsten layer.

[0169] For example, the sacrificial material layer L2 includes but is not limited to a silicon nitride layer. In this way, the structure of alternating conductive material layers L1 and sacrificial material layers L2 (such as silicon nitride layers) can effectively adjust the stress problem between the multilayer structures, thereby further improving memory performance.

[0170] Specifically, compared with the embodiment in which the sacrificial material layer L2 is silicon oxide, the sacrificial material layer L2 is silicon nitride, which can adjust the stress between the sacrificial material layer L2 and the conductive material layer L1 (such as a metal layer) to ensure higher film quality of the conductive material layer L1 and the sacrificial material layer L2.

[0171] Specifically, during the process, by doping or controlling the ratio of nitrogen and silicon in silicon nitride, the degree of stress matching between the silicon nitride and the conductive material layer L1 can be controlled.

[0172] Here, the number of stacked conductive material layers L1 can be set according to the number of stacked storage layers in the memory. Furthermore, the sacrificial material layer L2 can be located between adjacent conductive layers L1 or on one side of the first and last conductive material layers L1. The number of sacrificial material layers L2 can match the number of stacked conductive material layers L1. Each conductive material layer L1 and each sacrificial material layer L2 can be formed using a deposition process.

[0173] In addition, after forming the alternately stacked multiple conductive layers L1 and multiple first sacrificial layers L2, a first mask material layer Y1, such as a photoresist layer and / or a hard mask layer, may be formed on the upper surface of the top first sacrificial layer L2.

[0174] In step S12, refer to Figure 6 and Figure 6a 、 Figure 6b 、 Figure 6c A first mask layer Y11 is formed above the multi-layer conductive material layer L1 and the multi-layer sacrificial material layer L2; the first mask layer has a first pattern, and the first pattern is used to define the formation area of ​​the bit line and each conductive unit.

[0175] In some examples, forming the first mask layer Y11 over the multi-layer conductive material layer L1 and the multi-layer sacrificial material layer L2 includes: patterning the first mask material layer Y1 to form the first mask layer Y11 .

[0176] In step S13, please continue to refer to Figure 6 and Figure 6a 、 Figure 6b 、 Figure 6c , the multi-layer conductive material layer L1 and the multi-layer sacrificial material layer L2 are anisotropically etched to form a plurality of grooves G penetrating each conductive material layer L1 and each sacrificial material layer L2, so as to transfer the first pattern to each conductive material layer L1 and each sacrificial material layer L2, thereby forming a plurality of initial conductive pattern layers L11 and a plurality of sacrificial pattern layers L21 that are alternately stacked.

[0177] For example, the initial conductive pattern layer L11 and the sacrificial pattern layer L21 may be formed by etching based on the pattern of the first mask layer Y11 to have the same pattern, such as Figure 8a As shown in .

[0178] In step S14, refer to Figure 7 and Figure 7a 、 Figure 7b 、 Figure 7c , remove the first mask layer Y11.

[0179] For example, a grinding process may be used to remove the first mask layer Y11 and ensure that the surface of the top sacrificial pattern layer L21 is flat. The grinding process includes but is not limited to chemical mechanical polishing (CMP).

[0180] In step S15, refer to Figure 7 and Figure 7a 、 Figure 7b 、 Figure 7c , an isotropic etching process is used in the trench G to etch back the sidewalls of each initial conductive pattern layer L11 to form a plurality of conductive pattern layers L111.

[0181] Here, see Figure 7a The conductive pattern layer L111 includes a bit line BL extending along a column direction (e.g., the Y direction) and a plurality of conductive units 111 integrally connected to the bit line and spaced apart in the column direction. Each conductive unit 111 extends along the X direction and spaced apart in the Y direction. Optionally, each conductive unit 111 is symmetrically distributed around the bit line BL.

[0182] In addition, the orthographic projection of the conductive pattern layer L111 on the substrate 1 is located within the orthographic projection of the sacrificial pattern layer L21 on the substrate 1 , and there is a gap between the outer boundary of the orthographic projection of the conductive pattern layer L111 on the substrate 1 and the outer boundary of the orthographic projection of the sacrificial pattern layer L21 on the substrate 1 .

[0183] In step S20, refer to Figure 8 and Figure 8a 、 Figure 8b 、 Figure 8c , forming an initial first insulating layer L3 covering the sidewalls of the conductive pattern layer L111 and the sidewalls of the sacrificial pattern layer L21 , wherein the initial first insulating layer and the sacrificial pattern layer are made of different materials.

[0184] For example, the material of the initial first insulating layer L3 includes but is not limited to oxide, such as silicon oxide or other low dielectric constant K materials.

[0185] Illustratively, the initial first insulating layer L3 is formed by a deposition process.

[0186] For example, the deposition processes mentioned above and below include but are not limited to atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, molecular layer deposition (MLD) process, etc.

[0187] In step S30, refer to Figure 4 Before step S30 forms a word line hole penetrating the conductive unit and the corresponding sacrificial pattern layer in a direction perpendicular to the substrate, the manufacturing method further includes steps S210 to S240.

[0188] In step S210, refer to Figure 9 and Figure 9a 、 Figure 9b 、 Figure 9c A second mask layer Y2 is formed above the initial first insulating layer L3, the multi-layer conductive pattern layer L111, and the multi-layer sacrificial pattern layer L21; the second mask layer Y2 has a first opening pattern, and the first opening pattern is used to define a formation area of ​​a storage capacitor.

[0189] In step S220, please continue to refer to Figure 9 and Figure 9a 、 Figure 9b 、 Figure 9c Based on the first opening pattern, a portion of the initial first insulating layer L3 and a portion of the sacrificial pattern layer L21 are removed to expose the end of each conductive unit 111 away from the bit line BL, which constitutes the first electrode A of the storage capacitor.

[0190] In some embodiments, step S220 removes part of the initial first insulating layer L3 and part of the sacrificial pattern layer L21 based on the first opening pattern, including: removing part of the initial first insulating layer L3 based on the first opening pattern; and isotropically etching the sacrificial pattern layer L21 based on the first opening pattern to remove the sacrificial pattern layer L21 under the first opening pattern.

[0191] In step S230, refer to Figure 10 and Figure 10a 、 Figure 10b 、 Figure 10c , a dielectric material is deposited on the upper and lower surfaces and sidewalls of the first electrode A to form a second dielectric layer L4.

[0192] For example, the second dielectric layer L4 includes but is not limited to an HK (high-K) dielectric layer, where the HK dielectric layer refers to a dielectric layer having a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0193] In step S240, please continue to refer to Figure 10 and Figure 10a 、 Figure 10b 、 Figure 10c , a conductive material is deposited on a surface of the second dielectric layer L4 away from the first electrode A to form a second electrode B of the storage capacitor.

[0194] Illustratively, the material of the second electrode B includes but is not limited to polysilicon.

[0195] For example, after the second electrode B is formed by a deposition process, the upper surface of the second electrode B may be polished by a CMP process.

[0196] In some embodiments, step S240 deposits a conductive material on the surface of the second dielectric layer L4 away from the first electrode A to form a second electrode B of the storage capacitor, and also includes: depositing a conductive material on the surface of the second dielectric layer L4 away from the first electrode A to form a second electrode material layer (not shown); using the top sacrificial pattern layer as a grinding stop layer, grinding the second electrode material layer and simultaneously removing the second mask layer Y2 to form a second electrode B.

[0197] In some embodiments, please refer to Figure 4 After forming the second electrode of the storage capacitor in step S240, a word line hole is formed along a direction perpendicular to the substrate, penetrating the conductive unit and the corresponding sacrificial pattern layer, including steps S31 to S34.

[0198] In step S31, refer to Figure 11 and Figure 11a 、 Figure 11b 、 Figure 11c A third mask layer Y3 is formed above the second electrode B, the initial first insulating layer L3, the multi-layer conductive pattern layer L111 and the multi-layer sacrificial pattern layer L21; the third mask layer has a second opening pattern, and the second opening pattern is used to define the word line formation area.

[0199] In step S32, please continue to refer to Figure 11 and Figure 11a 、 Figure 11b 、 Figure 11c Based on the second opening pattern, the multi-layer conductive pattern layer L111 and the multi-layer sacrificial pattern layer L21 are etched to form a word line initial accommodating groove G1.

[0200] In step S33, refer to Figure 12 and Figure 12a 、 Figure 12b 、 Figure 12c , remove the third mask layer Y3.

[0201] In step S34, please continue to refer to Figure 12 and Figure 12a 、 Figure 12b 、 Figure 12c , an isotropic etching process is used to etch back the surface of each conductive unit 111 exposed in the word line initial receiving groove G1 to form a word line hole G11.

[0202] In some embodiments, the orthographic projection shape of the word line hole G11 on the substrate 1 includes a rectangle; opposite sidewalls of the word line hole G11 in the column direction (eg, the Y direction) expose the initial first insulating layer L3 .

[0203] See also Figure 13 and Figure 13a 、 Figure 13b 、 Figure 13c Before step S40 of sequentially forming an initial semiconductor layer L6, a first dielectric layer L7, and a word line WL covering a surface of the first dielectric layer L7 facing away from the initial semiconductor layer L6 and filling the word line hole G11 on the sidewall of the word line hole G11, the manufacturing method further includes:

[0204] Contact layers L5 are formed on the two etched surfaces of the conductive unit 111 exposed in the wordline hole G11. Here, the wordline WL can serve as a gate wordline, that is, it can function as a memory wordline WL and also as the gate of the transistor in each corresponding memory cell, thereby controlling the on and off of the transistor.

[0205] For example, the material of the word line WL includes metal, such as metal tungsten or metal copper.

[0206] For example, the contact layer L5 includes, but is not limited to, a nitride layer, such as a titanium nitride layer. Thus, the contact layer L5 is formed on the two etched surfaces of the conductive unit 111 exposed within the wordline hole G11. The contact layer L5 (e.g., a titanium nitride layer) serves as the contact structure between the wordline hole G11 and the multi-layer conductive pattern layer L111, effectively reducing the contact resistance of the memory, thereby further improving memory performance.

[0207] The initial semiconductor layer L6 is formed on the surfaces of the contact layer L5 , the initial first insulating layer L3 , and the sacrificial pattern layer L21 exposed in the wordline hole G11 .

[0208] Illustratively, the initial semiconductor layer L6 includes, but is not limited to, a metal oxide semiconductor layer.

[0209] It is understood that the material of the metal oxide semiconductor layer can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor is small (leakage current is less than or equal to 10A to 15A), thereby ensuring a low refresh rate of the dynamic memory.

[0210] It should be noted that the metal oxide material can also be ITO, IWO, ZnOx 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a 、Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a 、Ga x Zn y SnzOa、Zr x Zn y Sn z O a , InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, it can be adjusted according to actual conditions.

[0211] For example, the initial semiconductor layer L6 may be formed by a deposition process, such as an ALD process.

[0212] For example, the first dielectric layer L7 includes but is not limited to an HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0213] According to some embodiments, the distance between two etched surfaces of the sacrificial pattern layer L21 exposed in the word line hole G11 and opposite to each other in the row direction (e.g., the X direction) is a first distance; the distance between two etched surfaces of the conductive unit 111 exposed in the word line hole G11 is a second distance;

[0214] The thickness of the contact layer L5 is less than or equal to half of the difference between the second distance and the first distance.

[0215] In some embodiments, see Figure 3 Step S50 removes the initial first insulating layer L3 on the sidewall of the sacrificial pattern layer L21, including steps S51 to S53.

[0216] S51, forming a fourth mask layer above the second electrode, the initial first insulating layer, the multi-layer conductive pattern layer and the multi-layer sacrificial pattern layer; the fourth mask layer has a third opening pattern, and the third opening pattern is used to define a removal area of ​​the initial first insulating layer.

[0217] For some examples, see Figure 14 and Figure 14a 、 Figure 14b 、 Figure 14c A fourth mask layer (not shown) is formed above the second electrode B, the initial first insulating layer L3, the multi-layer conductive pattern layer L111 and the multi-layer sacrificial pattern layer L21; the fourth mask layer has a third opening pattern, and the third opening pattern is used to define the removal area of ​​the initial first insulating layer L3.

[0218] S52 , based on the second opening pattern, removing the initial first insulating layer on the sidewall of the sacrificial pattern layer to form a through hole G2 ; the through hole G2 exposes part of the sidewall of the sacrificial pattern layer L21 and part of the surface of the second dielectric layer L4 .

[0219] For some examples, see Figure 14 and Figure 14a 、 Figure 14b 、 Figure 14c Based on the second opening pattern, the initial first insulating layer L3 on the sidewall of the sacrificial pattern layer L21 is removed to form a through hole G2; the through hole G2 exposes part of the sidewall of the sacrificial pattern layer L21 and part of the surface of the second dielectric layer L4.

[0220] S53, removing the fourth mask layer.

[0221] In some embodiments, see Figure 15 and Figure 15a 、 Figure 15b 、 Figure 15cIn step S60 , the sacrificial pattern layer L21 in each region between adjacent conductive pattern layers L1 is removed in the through hole to expose the initial semiconductor layer L6 between the adjacent conductive pattern layers L1 .

[0222] For example, the sacrificial pattern layer L21 is removed by an isotropic etching process based on the through hole G2.

[0223] In some embodiments, please refer to Figure 15 and Figure 15a 、 Figure 15b 、 Figure 15c In step S70, the initial semiconductor layer L6 between adjacent conductive pattern layers L1 is removed in the through hole to form a plurality of independent semiconductor portions corresponding to the plurality of conductive units 111, including: using the first dielectric layer L7 as an etch stop layer, isotropically etching the initial semiconductor layer L6 exposed in the through hole G2 to form the semiconductor portion.

[0224] In some embodiments, see Figure 16 and Figure 16a 、 Figure 16b 、 Figure 16c In step S80 , the removed area of ​​the sacrificial pattern layer L21 and the etched area of ​​the initial semiconductor layer L6 are backfilled with insulating material to form a second insulating layer L8 .

[0225] For example, the material of the second insulating layer L8 includes but is not limited to oxide, such as silicon oxide or other low dielectric constant K materials.

[0226] The materials of the first insulating layer and the second insulating layer can be the same or different, as long as they are materials with low dielectric constants, for example, Si and Si are both materials with low dielectric constants K. x O y It can be understood that the ratio of the number of Si and O atoms is not limited here.

[0227] Illustratively, the second insulating layer L8 is formed by a deposition process.

[0228] Some embodiments of the present disclosure further provide a memory, see Figures 5 to 16a The memory device includes a substrate 1 and multiple conductive layers L111 stacked in a direction perpendicular to the substrate (e.g., the Z direction). Each conductive layer L111 includes a bit line BL extending in a column direction (e.g., the Y direction) and a plurality of conductive units 111 arranged in a column direction (e.g., the Y direction). The conductive units 111 include a first conductive portion integrally connected to the bit line BL and a second conductive portion spaced apart from the first conductive portion in a row direction (e.g., the X direction). The row direction (e.g., the X direction) and the column direction (e.g., the Y direction) are parallel to and intersect the substrate 1.

[0229] The memory device further includes: a plurality of word lines WL, a plurality of semiconductor portions, a plurality of first insulating layers L31, and a second insulating layer L8. The word lines WL extend in a direction perpendicular to the substrate 1 (e.g., the Z direction) and are located between the first conductive portion and the second conductive portion of the corresponding conductive unit 111. The sidewalls of the word lines WL are covered with a first dielectric layer L7. The semiconductor portion surrounds the word lines and is located on the surface of the first dielectric layer L7 facing away from the word lines WL, as well as between the first conductive portion and the second conductive portion of the corresponding conductive unit 111. The first insulating layer L31 is located within the gap between two adjacent conductive units 111 in the column direction (e.g., the Y direction), covers the sidewalls of the corresponding first conductive portion, second conductive portion, and semiconductor portion in the row direction (e.g., the X direction), and extends to cover the sidewalls of the bit lines BL within the gap. The second insulating layer L8 is located on the upper and lower surfaces of each conductive layer and extends to cover the sidewalls of the first insulating layer L31 exposed within the gap, forming a single integrated structure connected to the plurality of first insulating layers L31.

[0230] In the embodiment of the present disclosure, the memory adopts the above structure. The technical effect that can be achieved by the memory is the same as the technical effect that can be achieved by the manufacturing method of the memory in the aforementioned embodiment, and will not be described in detail here.

[0231] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0232] Illustratively, the conductive layer L111 includes a metal layer, such as a metal tungsten layer.

[0233] By way of example, the material of the word lines WL and the bit lines BL includes metal, such as metal tungsten or metal copper.

[0234] In some embodiments, the outer boundary of the orthographic projection of the semiconductor portion on the substrate 1 comprises a rectangle. The memory further comprises: a plurality of contact layers 15 located on the sidewalls of each semiconductor portion in the column direction.

[0235] For example, the contact layer L5 includes, but is not limited to, a nitride layer, such as a titanium nitride layer. Thus, the contact layer L5 is formed on the two etched surfaces of the conductive unit 111 exposed within the wordline hole G11. The contact layer L5 (e.g., a titanium nitride layer) serves as the contact structure between the wordline hole G11 and the multi-layer conductive pattern layer L111, effectively reducing the contact resistance of the memory, thereby further improving memory performance.

[0236] In some embodiments, the memory further includes multiple storage capacitors; the storage capacitors include a first electrode A, a second dielectric layer L4, and a second electrode B. The end of the second conductive portion away from the bit line BL constitutes the first electrode A. The second dielectric layer L4 is located on the upper and lower surfaces and sidewalls of the first electrode A, and extends to cover the sidewalls of the first insulating layer L31 and the second insulating layer L8 exposed between the first electrode A and the adjacent first electrode A. The second electrode B is located on the surface of the second dielectric layer L4 away from the first electrode A.

[0237] Illustratively, the material of the second electrode B includes but is not limited to polysilicon.

[0238] For example, the second dielectric layer L4 includes but is not limited to an HK (high-K) dielectric layer, where the HK dielectric layer refers to a dielectric layer having a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0239] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include a housing, a circuit board disposed within the housing, and a memory integrated on the circuit board. For the structure of the memory, please refer to the relevant description of some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0240] In some embodiments, an external control device, such as a processor or actuator, coupled to the memory may also be integrated on the circuit board. For example, the electronic device may further include a processor integrated on the circuit board. The processor is coupled to the memory and can control read and write operations of the memory.

[0241] In some embodiments, the memory is 3D-DRAM.

[0242] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0243] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A method for manufacturing a memory, characterized in that: include: A plurality of conductive pattern layers and a plurality of sacrificial pattern layers are alternately stacked in a direction perpendicular to the substrate; wherein the conductive pattern layers include: bit lines extending in a column direction, and a plurality of conductive units integrally connected to the bit lines and spaced apart in the column direction; the orthographic projection of the conductive pattern layers on the substrate is located within the orthographic projection of the sacrificial pattern layers on the substrate, and a gap exists between the outer boundary of the orthographic projection of the conductive pattern layers on the substrate and the outer boundary of the orthographic projection of the sacrificial pattern layers on the substrate; forming an initial first insulating layer covering the sidewalls of the conductive pattern layer and the sidewalls of the sacrificial pattern layer, wherein the initial first insulating layer and the sacrificial pattern layer are made of different materials; A word line hole is formed in a direction perpendicular to the substrate, penetrating the conductive unit and the corresponding sacrificial pattern layer; the word line hole in the conductive unit exposes the sidewalls of the conductive pattern layer and the initial first insulating layer disposed on the same layer as the conductive pattern layer, so that each conductive unit is separated into two independent parts, and the sacrificial pattern layer located between two adjacent conductive pattern layers is exposed, and the sacrificial pattern layer completely surrounds the word line hole; forming an initial semiconductor layer, a first dielectric layer, and a word line in sequence on the sidewalls of the word line hole; Etching the initial first insulating layer in a region of the initial first insulating layer between two adjacent conductive units connected to the same bit line in a direction perpendicular to the substrate to form a through hole, wherein the sidewall of the through hole exposes the sacrificial pattern layer, and patterning the initial first insulating layer to form a first insulating layer; removing the sacrificial pattern layer in each region between adjacent conductive pattern layers in the through hole to expose the initial semiconductor layer between adjacent conductive pattern layers; removing the initial semiconductor layer between adjacent conductive pattern layers in the through hole to form a plurality of mutually independent semiconductor portions corresponding to the plurality of conductive units; The removed area of ​​the sacrificial pattern layer and the etched area of ​​the initial semiconductor layer are backfilled with insulating material.

2. The method for manufacturing a memory according to claim 1, wherein: Before sequentially forming an initial semiconductor layer, a first dielectric layer, and a word line covering a surface of the first dielectric layer facing away from the initial semiconductor layer and filling the word line hole on the sidewall of the word line hole, the manufacturing method further includes: forming a contact layer on the sidewall of the word line hole; wherein the contact layer is used to reduce the contact resistance between the conductive unit and the semiconductor portion, and the contact layer is in contact with the conductive pattern layer, the sacrificial pattern layer, and the initial first insulating layer at the same time; The contact layer is subjected to a patterning process to retain an area in contact with the conductive pattern layer.

3. The method for manufacturing a memory according to claim 2, wherein: The distance between the two etched surfaces of the sacrificial pattern layer exposed in the word line hole and opposite to each other in the row direction is a first distance; the distance between the two etched surfaces of the conductive unit exposed in the word line hole is a second distance; Wherein, the thickness of the contact layer is less than or equal to half of the difference between the second distance and the first distance.

4. The method for manufacturing a memory according to claim 2, wherein: Before forming the contact layer on the sidewall of the word line hole, the manufacturing method further comprises: performing an etching back process on the conductive pattern layer exposed by the word line hole; The patterning process of the contact layer to retain the area in contact with the conductive pattern layer includes: after forming the contact layer on the sidewall of the word line hole, removing the contact layer in contact with the initial first insulating layer and the sacrificial pattern layer by dry etching in the word line hole.

5. The method for manufacturing a memory according to claim 1, wherein: The method of forming multiple conductive pattern layers and multiple sacrificial pattern layers alternately stacked in a direction perpendicular to the substrate comprises: forming multiple layers of conductive material and multiple layers of sacrificial material alternately stacked in a direction perpendicular to the substrate; forming a first mask layer over the multi-layer conductive material layer and the multi-layer sacrificial material layer; the first mask layer having a first pattern, the first pattern being used to define a formation area of ​​the bit line and each of the conductive units; Anisotropically etching the multiple conductive material layers and the multiple sacrificial material layers to form multiple grooves penetrating the conductive material layers and the sacrificial material layers, so as to transfer the first pattern into the conductive material layers and the sacrificial material layers, thereby forming a plurality of initial conductive pattern layers and a plurality of sacrificial pattern layers that are alternately stacked; removing the first mask layer; An isotropic etching process is adopted in the groove to etch back each of the initial conductive pattern layers to form a plurality of conductive pattern layers.

6. The method for manufacturing a memory according to claim 1, wherein: The first insulating layer and the sacrificial pattern layer are made of different materials, and the first insulating layer and the sacrificial pattern layer have different etching selectivities.

7. The method for manufacturing a memory according to claim 1, wherein: The material of the first insulating layer includes silicon oxide; the material of the sacrificial pattern layer includes silicon nitride, aluminum oxide or polysilicon.

8. The method for manufacturing a memory according to any one of claims 1 to 7, wherein: Before forming the word line hole penetrating the conductive unit and the corresponding sacrificial pattern layer in a direction perpendicular to the substrate, the manufacturing method further includes: forming a second mask layer over the initial first insulating layer, the multi-layer conductive pattern layer, and the multi-layer sacrificial pattern layer; the second mask layer having a first opening pattern, the first opening pattern being used to define a formation area for a storage capacitor; Based on the first opening pattern, removing a portion of the initial first insulating layer and a portion of the sacrificial pattern layer to expose an end portion of each of the conductive units away from the bit line, wherein the end portion constitutes a first electrode of the storage capacitor; Depositing a dielectric material on the upper and lower surfaces and sidewalls of the first electrode to form a second dielectric layer; A conductive material is deposited on a surface of the second dielectric layer facing away from the first electrode to form a second electrode of the storage capacitor.

9. The method for manufacturing a memory according to claim 8, wherein: Depositing a conductive material on a surface of the second dielectric layer away from the first electrode to form a second electrode of the storage capacitor further comprises: Depositing a conductive material on a surface of the second dielectric layer facing away from the first electrode to form a second electrode material layer; The second electrode material layer is ground using the top sacrificial pattern layer as a grinding stop layer and the second mask layer is removed simultaneously to form the second electrode.

10. The method for manufacturing a memory according to claim 9, wherein: The removing of a portion of the initial first insulating layer and a portion of the sacrificial pattern layer based on the first opening pattern includes: Based on the first opening pattern, removing a portion of the initial first insulating layer; The sacrificial pattern layer is isotropically etched based on the first opening pattern to remove the sacrificial pattern layer below the first opening pattern.

11. The method for manufacturing a memory according to claim 9, wherein: After forming the second electrode of the storage capacitor, forming a word line hole penetrating the conductive unit and corresponding to the sacrificial pattern layer in a direction perpendicular to the substrate includes: forming a third mask layer over the second electrode, the initial first insulating layer, the multi-layer conductive pattern layer, and the multi-layer sacrificial pattern layer; the third mask layer having a second opening pattern, the second opening pattern being used to define a formation area of ​​the word line; Based on the second opening pattern, etching the multi-layer conductive pattern layer and the multi-layer sacrificial pattern layer to form a word line initial accommodating groove; removing the third mask layer; An isotropic etching process is adopted to etch back the surface of each conductive unit exposed in the initial word line receiving groove to form the word line hole.

12. The method for manufacturing a memory according to claim 11, wherein: The removing of the initial first insulating layer on the sidewall of the sacrificial pattern layer comprises: forming a fourth mask layer over the second electrode, the initial first insulating layer, the multi-layer conductive pattern layer, and the multi-layer sacrificial pattern layer; the fourth mask layer having a third opening pattern, the third opening pattern being used to define a removal area of ​​the initial first insulating layer; Based on the second opening pattern, the initial first insulating layer on the sidewall of the sacrificial pattern layer is removed to form a through hole; the through hole exposes a portion of the sidewall of the sacrificial pattern layer and a portion of the surface of the second dielectric layer; The fourth mask layer is removed.

13. The method for manufacturing a memory according to claim 12, wherein: The sacrificial pattern layer is removed by an isotropic etching process based on the through hole; The etching of the initial semiconductor layer to form semiconductor portions respectively located in the conductive units includes: using the first dielectric layer as an etching stop layer, and isotropically etching the initial semiconductor layer exposed in the through hole to form the semiconductor portions.

14. A memory, characterized in that: include: A substrate and multiple conductive layers stacked at intervals in a direction perpendicular to the substrate; each conductive layer includes: a bit line extending in a column direction, and a plurality of conductive units arranged at intervals in the column direction; the conductive units include a first conductive portion integrally connected to the bit line, and a second conductive portion spaced apart from the first conductive portion in a row direction; the row direction and the column direction are parallel to the substrate and intersect with each other; Wherein, the memory further includes: A plurality of word lines; the word lines extend in a direction perpendicular to the substrate and are located between the first conductive portion and the second conductive portion corresponding to the conductive unit; sidewalls of the word lines are covered with a first dielectric layer; a plurality of semiconductor portions; the semiconductor portions surround the word lines and are located on a surface of the first dielectric layer facing away from the word lines, and between the first conductive portion and the second conductive portion corresponding to the conductive unit; a plurality of first insulating layers; the first insulating layer being located in a gap between two adjacent conductive units in the column direction, and covering sidewalls of the corresponding first conductive portion, the second conductive portion, and the semiconductor portion in the row direction, and extending to cover sidewalls of the bit line located in the gap; The second insulating layer is located on the upper and lower surfaces of each of the conductive layers, extends to cover the sidewalls of the first insulating layer exposed in the gap, and is connected with the first insulating layers to form an integrated structure.

15. The memory according to claim 14, wherein: The memory further includes: a contact layer between each semiconductor portion and the first conductive portion, and a contact layer between each semiconductor portion and the second conductive portion; the work function of the contact layer is between the work function of the conductive unit and the work function of the semiconductor portion.

16. The memory according to claim 15, wherein: The material of the contact layer includes titanium, titanium nitride, thallium or thallium nitride. The material of the first conductive part and the second conductive part includes tungsten. The material of the semiconductor part is a metal oxide semiconductor.

17. An electronic device, characterized in that: include: The memory according to any one of claims 14 to 16.

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