Memory, manufacturing method thereof, and electronic device

Abstract

The present disclosure relates to a memory and a manufacturing method thereof, and an electronic device. The memory includes a substrate and one or more repeating units and a plurality of word lines arranged on the substrate. The repeating unit includes: two bit lines extending along a first direction and spaced apart, and an isolation layer arranged in the space between the two bit lines; a support layer arranged on the side wall of the bit line away from the isolation layer; the support layer includes a plurality of sub-support portions spaced apart in the first direction, and the space between adjacent sub-support portions constitutes a word line hole; the transistor is located in the word line hole and includes a semiconductor layer surrounding the side wall of the word line and a gate insulating layer arranged between the side wall of the word line and the inner side wall of the semiconductor layer; the outer side wall of the semiconductor layer away from the corresponding bit line is flush with the side wall of the adjacent sub-support portion away from the same bit line. The present disclosure can greatly reduce the difficulty of the subsequent process of removing parasitic transistors, thereby improving memory performance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the advancement of communications and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and higher performance. Three-dimensional dynamic random access memory (3D-DRAM), with its higher integration density and larger storage capacity, has gradually become a key research direction in memory technology. However, the current 3D-DRAM fabrication process still faces significant challenges in the metal / oxide stack etching process and the removal of parasitic transistors. This significantly limits the advantages of 3D-DRAM and hinders its development and promotion. Summary of the Invention

[0003] Based on this, the embodiments of the present disclosure provide a memory and a manufacturing method thereof, and an electronic device, which are beneficial for reducing the parasitic capacitance of the memory to further improve the memory performance.

[0004] According to some embodiments, the present disclosure provides a memory. The memory includes a substrate, one or more repeating units disposed on the substrate, and a plurality of word lines. The repeating units include:

[0005] Two bit lines extending along a first direction and spaced apart, and an isolation layer disposed between the two bit lines;

[0006] A support layer is provided on a sidewall of the bit line away from the isolation layer; the support layer includes a plurality of sub-support portions spaced apart in a first direction, and the intervals between adjacent sub-support portions form word line holes;

[0007] The word line is located in the word line hole and extends in a direction perpendicular to the substrate;

[0008] A plurality of transistors are arranged in a row along a first direction on a side of any bit line facing away from the isolation layer; the transistors are located in the word line hole and include: a semiconductor layer surrounding the sidewalls of the word line, and a gate insulating layer arranged between the sidewalls of the word line and the inner sidewalls of the semiconductor layer; wherein the outer sidewall of the semiconductor layer facing away from the corresponding bit line is flush with the sidewall of the adjacent sub-support portion facing away from the same bit line.

[0009] According to some embodiments, the repeating unit further includes: a plurality of storage capacitors arranged in a row along a first direction on a side of any bit line facing away from the isolation layer. The storage capacitors include: a first electrode, a dielectric layer, and a second electrode; the first electrode is located on an outer sidewall of the semiconductor layer facing away from the corresponding bit line and extends away from the bit line; the dielectric layer covers the outer surface of the first electrode, and the second electrode covers the outer surface of the dielectric layer; and an insulating layer is located on a sidewall of each sub-support portion facing away from the corresponding bit line and between adjacent first electrodes in the first direction.

[0010] According to some embodiments, the support layer includes a silicon nitride layer; and the insulating layer includes a silicon oxide layer.

[0011] According to some embodiments, multiple dielectric layers of a column of storage capacitors are connected integrally and cover sidewalls of corresponding insulating layers behind ion support portions; and multiple second electrodes of a column of storage capacitors are connected integrally.

[0012] According to some embodiments, there are multiple repeating units, and the multiple repeating units are arranged in a row along a second direction. The second direction is parallel to the substrate and intersects the first direction. In a row of repeating units, the second electrodes of adjacent storage capacitors are integrally connected.

[0013] According to some embodiments, there are multiple repeating units, and the multiple repeating units are stacked in a direction perpendicular to the substrate. The insulating layer further extends between adjacent support layers in the direction perpendicular to the substrate, and between adjacent semiconductor layers in the direction perpendicular to the substrate.

[0014] According to some embodiments, the present disclosure provides a method for manufacturing a memory, comprising the following steps.

[0015] Multiple sacrificial material layers and multiple supporting material layers are alternately stacked along a direction perpendicular to the substrate.

[0016] The multi-layer sacrificial material layer and the multi-layer supporting material layer are subjected to a single etching process to form a multi-layer sacrificial pattern layer and a multi-layer supporting pattern layer having the same pattern.

[0017] The concave regions of each sacrificial pattern layer and each supporting pattern layer are backfilled with sacrificial material to form an initial sacrificial layer.

[0018] An etching process is performed on the initial sacrificial layer and each supporting pattern layer to form a first trench extending along a first direction.

[0019] Each supporting pattern layer is etched back to expose two sidewalls in the first trench to form a bit line trench and an initial supporting layer extending along the first direction.

[0020] A bit line is formed in the bit line trench.

[0021] An isolation layer is formed in the first trench.

[0022] A plurality of word line holes are formed in the initial support layer to obtain a support layer; the support layer includes a plurality of sub-support portions spaced apart in a first direction; the word line holes are located between adjacent sub-support portions and expose the sidewalls of the corresponding initial sacrificial layer and the bit line.

[0023] A semiconductor layer, a gate insulating layer and a word line are sequentially formed in the word line hole.

[0024] According to some embodiments, sequentially forming a semiconductor layer, a gate insulating layer, and a word line in a word line hole includes the following steps.

[0025] An initial semiconductor layer is conformally formed on the inner wall of the word line hole.

[0026] A gate insulating layer is conformally formed on a surface of the initial semiconductor layer away from the inner wall of the word line hole.

[0027] A word line filling the word line hole is formed on a surface of the gate insulation layer facing away from the initial semiconductor layer.

[0028] The initial sacrificial layer is removed.

[0029] The initial semiconductor layer between adjacent supporting layers in a direction perpendicular to the substrate is removed to form a semiconductor layer.

[0030] The removed area of the initial sacrificial layer is filled with an insulating material to form an insulating layer.

[0031] According to some embodiments, the support pattern layer includes a main body extending along a first direction and branches arranged at intervals in the first direction and extending in a direction away from the main body.

[0032] Before performing an etching process on the initial sacrificial layer and each supporting pattern layer to form a first trench extending along the first direction, the manufacturing method further includes the following steps.

[0033] Based on the sidewall of the branch away from the main body, the branch is removed by etching to form a first electrode accommodating groove.

[0034] A first electrode is formed in the first electrode receiving groove.

[0035] The initial sacrificial layer is patterned to expose a portion of the surface of each first electrode.

[0036] A dielectric layer is formed to cover the exposed surface of the first electrode.

[0037] A second electrode is formed to cover the exposed surface of the dielectric layer.

[0038] The word line hole also exposes the surface of the first electrode facing the bit line.

[0039] According to some embodiments, the present disclosure provides, in another aspect, an electronic device, comprising the memory as described in some of the above embodiments.

[0040] The embodiments of the present disclosure may or may have at least the following advantages:

[0041] In the embodiment of the present disclosure, the two bit lines of any repeating unit are spaced apart and isolated by an isolation layer. The support layer is arranged on the side wall of the bit line away from the isolation layer, and includes a plurality of sub-support portions spaced apart in the direction of extension of the bit line. The spacing between adjacent sub-support portions can be used to form a word line hole, thereby forming a transistor in the word line hole. In this way, the embodiment of the present disclosure is convenient for forming a bit line groove and an initial support layer located on one side of the bit line groove by etching back the support pattern layer to expose the inner side wall of the first groove after etching the initial sacrificial layer and the support pattern layer to form a first groove. Moreover, after forming the bit line in the bit line groove and forming the isolation layer in the first groove, a word line hole can be formed by etching the initial support layer and the initial sacrificial layer to form a transistor in the word line hole.

[0042] On this basis, the disclosed embodiments arrange the outer sidewall of the semiconductor layer in the transistor facing away from the corresponding bit line to be flush with the sidewall of the adjacent sub-support portion facing away from the same bit line. This not only facilitates increasing the operating space for removing the parasitic transistor by removing the initial sacrificial layer area, thereby increasing the process window, but also allows the sub-support portion of the support layer covering the corresponding semiconductor layer sidewall to serve as a protective layer to retain the semiconductor layer when the parasitic transistor is removed. This allows the parasitic transistor to be removed simply and conveniently, greatly reducing the process difficulty of removing the parasitic transistor, which in turn helps improve memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0044] Figure 1 A schematic structural diagram of a memory provided in some embodiments;

[0045] Figure 1a for Figure 1 A schematic cross-sectional view of a memory device shown at section C1;

[0046] Figure 1b for Figure 1 A schematic cross-sectional view of a memory device shown at section C2;

[0047] Figure 1c for Figure 1 A schematic cross-sectional view of a memory device shown at section C3;

[0048] Figure 2 A schematic flow chart of a method for manufacturing a memory provided in some embodiments;

[0049] Figure 3 A schematic diagram of a process for forming a semiconductor layer, a gate insulating layer, and a word line in a method for manufacturing a memory provided in some embodiments;

[0050] Figure 4 for Figure 3 A schematic flow chart of some intermediate steps of the manufacturing method shown;

[0051] Figure 5 is a schematic structural diagram of a structure obtained in S10 in a method for manufacturing a memory provided in some embodiments;

[0052] Figure 5a for Figure 5 A schematic cross-sectional view of a structure shown at section C1;

[0053] Figure 5b for Figure 5 A schematic cross-sectional view of a structure shown at section C2;

[0054] Figure 5c for Figure 5 A schematic cross-sectional view of a structure shown at section C3;

[0055] Figure 6 is a schematic structural diagram of a structure obtained in S20 in a method for manufacturing a memory provided in some embodiments;

[0056] Figure 6a for Figure 6 A schematic cross-sectional view of a structure shown at section C1;

[0057] Figure 6b for Figure 6 A schematic cross-sectional view of a structure shown at section C2;

[0058] Figure 6c for Figure 6 A schematic cross-sectional view of a structure shown at section C3;

[0059] Figure 7 is a schematic structural diagram of a structure obtained in S30 in a method for manufacturing a memory provided in some embodiments;

[0060] Figure 7a for Figure 7 A schematic cross-sectional view of a structure shown at section C1;

[0061] Figure 7b for Figure 7A schematic cross-sectional view of a structure shown at section C2;

[0062] Figure 7c for Figure 7 A schematic cross-sectional view of a structure shown at section C3;

[0063] Figure 8 is a schematic structural diagram of a structure obtained in S40 in a method for manufacturing a memory provided in some embodiments;

[0064] Figure 8a for Figure 8 A schematic cross-sectional view of a structure shown at section C1;

[0065] Figure 8b for Figure 8 A schematic cross-sectional view of a structure shown at section C4;

[0066] Figure 8c for Figure 8 A schematic cross-sectional view of a structure shown at section C3;

[0067] Figure 9 is a schematic structural diagram of a structure obtained in S310 in a method for manufacturing a memory provided in some embodiments;

[0068] Figure 9a for Figure 9 A schematic cross-sectional view of a structure shown at section C1;

[0069] Figure 9b for Figure 9 A schematic cross-sectional view of a structure shown at section C4;

[0070] Figure 9c for Figure 9 A schematic cross-sectional view of a structure shown at section C3;

[0071] Figure 10 is a schematic structural diagram of a structure obtained in S320 in a method for manufacturing a memory provided in some embodiments;

[0072] Figure 10a for Figure 10 A schematic cross-sectional view of a structure shown at section C1;

[0073] Figure 10b for Figure 10 A schematic cross-sectional view of a structure shown at section C2;

[0074] Figure 10c for Figure 10 A schematic cross-sectional view of a structure shown at section C3;

[0075] Figure 11is a schematic structural diagram of a structure obtained in S330 in a method for manufacturing a memory provided in some embodiments;

[0076] Figure 11a for Figure 11 A schematic cross-sectional view of a structure shown at section C1;

[0077] Figure 11b for Figure 11 A schematic cross-sectional view of a structure shown at section C2;

[0078] Figure 11c for Figure 11 A schematic cross-sectional view of a structure shown at section C3;

[0079] Figure 12 is a schematic structural diagram of a structure obtained in S350 in a method for manufacturing a memory provided in some embodiments;

[0080] Figure 12a for Figure 12 A schematic cross-sectional view of a structure shown at section C1;

[0081] Figure 12b for Figure 12 A schematic cross-sectional view of a structure shown at section C2;

[0082] Figure 12c for Figure 12 A schematic cross-sectional view of a structure shown at section C3;

[0083] Figure 13 is a schematic structural diagram of a structure obtained in S50 in a method for manufacturing a memory provided in some embodiments;

[0084] Figure 13a for Figure 13 A schematic cross-sectional view of a structure shown at section C1;

[0085] Figure 13b for Figure 13 A schematic cross-sectional view of a structure shown at section C2;

[0086] Figure 13c for Figure 13 A schematic cross-sectional view of a structure shown at section C3;

[0087] Figure 14 is a schematic structural diagram of a structure obtained in S70 in a method for manufacturing a memory provided in some embodiments;

[0088] Figure 14a for Figure 14 A schematic cross-sectional view of a structure shown at section C1;

[0089] Figure 14b for Figure 14 A schematic cross-sectional view of a structure shown at section C2;

[0090] Figure 14c for Figure 14 A schematic cross-sectional view of a structure shown at section C3;

[0091] Figure 15 is a schematic structural diagram of a structure obtained in S93 in a memory manufacturing method provided in some embodiments;

[0092] Figure 15a for Figure 15 A schematic cross-sectional view of a structure shown at section C1;

[0093] Figure 15b for Figure 15 A schematic cross-sectional view of a structure shown at section C2;

[0094] Figure 15c for Figure 15 A schematic cross-sectional view of a structure shown at section C3;

[0095] Figure 16 is a schematic structural diagram of a structure obtained in S95 in a memory manufacturing method provided in some embodiments;

[0096] Figure 16a for Figure 16 A schematic cross-sectional view of a structure shown at section C1;

[0097] Figure 16b for Figure 16 A schematic cross-sectional view of a structure shown at section C2;

[0098] Figure 16c for Figure 16 A schematic cross-sectional view of a structure shown at section C3;

[0099] Figure 17 is a schematic structural diagram of a structure obtained in S96 in a memory manufacturing method provided in some embodiments;

[0100] Figure 17a for Figure 17 A schematic cross-sectional view of a structure shown at section C1;

[0101] Figure 17b for Figure 17 A schematic cross-sectional view of a structure shown at section C2;

[0102] Figure 17c for Figure 17 The structure shown is a cross-sectional schematic diagram at section C3. Description of the drawings:

[0104] 1-substrate; M-transistor; BL-bit line; WL-word line;

[0105] A-first electrode; B-second electrode; C-storage capacitor;

[0106] Y10-first mask material layer; Y1-first mask layer; Y2-second mask;

[0107] G1-first trench; G2-first electrode receiving groove; G3-bit line trench;

[0108] 210 - sacrificial material layer; 21 - sacrificial pattern layer; 21a - initial sacrificial layer;

[0109] 220 - support material layer; 22 - support pattern layer; 221 - initial support layer; 222 - support layer; 2221 - sub-support portion;

[0110] 23 - dielectric layer; 24 - isolation layer; 250 - initial semiconductor layer; 25 - semiconductor layer; 26 - gate insulating layer; 27 - insulating layer. DETAILED DESCRIPTION

[0111] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0112] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0113] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0114] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0115] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0116] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0117] Some embodiments of the present disclosure provide a memory. Figure 1 and Figure 1a 、 Figure 1b 、 Figure 1c The memory includes: a substrate 1 and one or more repeating units and a plurality of word lines WL arranged on the substrate 1. The repeating units include:

[0118] Two bit lines BL are extended along a first direction (eg, the Y direction) and spaced apart from each other, and an isolation layer 24 is disposed in the space between the two bit lines BL.

[0119] The support layer 222 is disposed on the sidewall of the bit line BL away from the isolation layer 24 . The support layer 222 includes a plurality of sub-support portions 2221 spaced apart in a first direction (eg, the Y direction), and the spaces between adjacent sub-support portions 2221 form word line holes.

[0120] The word line WL is located in the word line hole and extends in a direction perpendicular to the substrate 1 (eg, the Z direction).

[0121] Multiple transistors M are arranged in a row along a first direction (for example, the Y direction) on a side of any bit line BL away from the isolation layer 24; the transistor M is located in the word line hole, including: a semiconductor layer 25 surrounding the side wall of the word line WL, and a gate insulation layer 26 arranged between the side wall of the word line WL and the inner side wall of the semiconductor layer 25; wherein the outer side wall of the semiconductor layer 25 away from the corresponding bit line BL is flush with the side wall of the adjacent sub-support portion 2221 away from the same bit line BL.

[0122] In the embodiment of the present disclosure, the two bit lines BL of any repeating unit are spaced apart and isolated by an isolation layer 24. The support layer 222 is provided on the sidewall of the bit line away from the isolation layer 24 and includes a plurality of sub-support portions 2221 spaced apart and distributed in the direction of extension of the bit line BL. The spacing between adjacent sub-support portions 2221 can be used to form a word line hole, thereby forming a transistor M in the word line hole. In this way, the embodiment of the present disclosure facilitates the formation of a bit line trench and an initial support layer located on one side of the bit line trench by etching back the support pattern layer to expose the inner sidewall of the first trench after etching the initial sacrificial layer and the support pattern layer to form a first trench. Furthermore, after forming the bit line BL in the bit line BL trench and forming the isolation layer 24 in the first trench, a word line hole can be formed by etching the initial support layer and the initial sacrificial layer to form a transistor M in the word line hole.

[0123] On this basis, the disclosed embodiment arranges the outer sidewall of the semiconductor layer in the transistor M facing away from the corresponding bit line BL to be flush with the sidewall of the adjacent sub-support portion 2221 facing away from the same bit line BL. This not only facilitates increasing the operating space for removing the parasitic transistor by removing the initial sacrificial layer area, thereby increasing the process window, but also allows the sub-support portion 2221 in the support layer 222, which covers the sidewall of the corresponding semiconductor layer 25, to serve as a protective layer to retain the semiconductor layer 25 when the parasitic transistor is removed. This allows the parasitic transistor to be removed simply and conveniently, greatly reducing the difficulty of the parasitic transistor removal process. This in turn helps improve memory performance.

[0124] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0125] For example, the support layer 222 includes, but is not limited to, a silicon nitride layer. The isolation layer 24 includes, but is not limited to, a silicon oxide layer.

[0126] Optionally, the semiconductor layer 25 may be an indium gallium zinc oxide (IGZO) layer, but is not limited thereto.

[0127] For example, the gate insulating layer 26 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0128] By way of example, the bit line BL includes, but is not limited to, a conductive metal, such as a copper-tungsten alloy.

[0129] By way of example, the word line WL includes, but is not limited to, a conductive metal, such as a copper-tungsten alloy.

[0130] In some embodiments, the repeating unit further includes: a plurality of storage capacitors C and an insulating layer 27. The plurality of storage capacitors C are arranged in a row along a first direction (e.g., the Y direction) on a side of any bit line BL away from the isolation layer 24. The storage capacitor C includes: a first electrode A, a dielectric layer 23, and a second electrode B; the first electrode A is located on the outer side wall of the semiconductor layer 25 away from the corresponding bit line BL, and extends in a direction away from the bit line BL; the dielectric layer 23 covers the outer surface of the first electrode A, and the second electrode B covers the outer surface of the dielectric layer 23. The insulating layer 27 is located on the side wall of each sub-support portion 2221 away from the corresponding bit line BL, and is located between adjacent first electrodes A in the first direction (e.g., the Y direction).

[0131] For example, the first electrode A includes but is not limited to a conductive metal. For example, the first electrode A may be a copper-tungsten alloy.

[0132] Illustratively, the second electrode B includes but is not limited to polysilicon.

[0133] In some embodiments, the insulating layer 27 includes a silicon oxide layer.

[0134] In some embodiments, multiple dielectric layers 23 of a column of storage capacitors C are connected integrally and cover the sidewalls of the corresponding insulating layer 27 behind the ion support portion 2221 ; multiple second electrodes B of a column of storage capacitors C are connected integrally.

[0135] In some embodiments, there are multiple repeating units, and the multiple repeating units are arranged in a row along a second direction (e.g., the X direction). The second direction (e.g., the X direction) is parallel to the substrate 1 and intersects the first direction (e.g., the Y direction). In a row of repeating units, the second electrodes B of adjacent storage capacitors C are integrally connected.

[0136] In some embodiments, there are multiple repeating units, and the multiple repeating units are stacked in a direction perpendicular to the substrate 1 (e.g., the Z direction). The insulating layer 27 also extends between adjacent support layers 222 in the direction perpendicular to the substrate 1 (e.g., the Z direction), and between adjacent semiconductor layers 25 in the direction perpendicular to the substrate 1 (e.g., the Z direction).

[0137] Some embodiments of the present disclosure also provide a method for manufacturing a memory, which is used to manufacture the memory described in some of the above embodiments. The manufacturing method also has the technical advantages of the above memory. Figure 2 , the manufacturing method includes the following steps.

[0138] S10: forming multiple layers of sacrificial material layers and multiple layers of supporting material layers alternately stacked in a direction perpendicular to the substrate.

[0139] S20: performing an etching process on the multi-layer sacrificial material layer and the multi-layer supporting material layer to form a multi-layer sacrificial pattern layer and a multi-layer supporting pattern layer having the same pattern.

[0140] S30: backfilling sacrificial material in the concave regions of each sacrificial pattern layer and each supporting pattern layer to form an initial sacrificial layer.

[0141] S40: performing an etching process on the initial sacrificial layer and each supporting pattern layer to form a first trench extending along a first direction.

[0142] S50: etching back each support pattern layer to expose two sidewalls in the first trench, forming a bit line trench and an initial support layer extending along the first direction.

[0143] S60: forming a bit line in the bit line trench.

[0144] S70: forming an isolation layer in the first trench.

[0145] S80: forming a plurality of word line holes in the initial support layer to obtain a support layer; the support layer includes a plurality of sub-support portions 2221 spaced apart in a first direction; the word line holes are located between adjacent sub-support portions 2221 and expose sidewalls of the corresponding initial sacrificial layer and bit lines.

[0146] S90: forming a semiconductor layer, a gate insulating layer and a word line in sequence in the word line hole.

[0147] In some embodiments, see Figure 3 Step S90 sequentially forms a semiconductor layer, a gate insulating layer, and a word line in the word line hole, including the following steps.

[0148] S91: Conformally forming an initial semiconductor layer on the inner wall of the word line hole.

[0149] S92: Conformally forming a gate insulating layer on a surface of the initial semiconductor layer away from the inner wall of the word line hole.

[0150] S93: forming a word line filling the word line hole on a surface of the gate insulating layer facing away from the initial semiconductor layer.

[0151] S94: removing the initial sacrificial layer.

[0152] S95: removing the initial semiconductor layer between adjacent supporting layers in a direction perpendicular to the substrate to form a semiconductor layer.

[0153] S96: Filling the area where the initial sacrificial layer is removed with an insulating material to form an insulating layer.

[0154] It should be noted that in the above embodiments, there is no strict order restriction for the execution of the steps in the method. These steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a portion of any of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily have to be completed at the same time, but may be executed at different times. The order of execution of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternating with other steps or at least a portion of the sub-steps or stages of other steps. The method is limited to being able to achieve the preparation of the corresponding memory.

[0155] Based on this, with respect to the manufacturing methods provided in some of the above embodiments, the present disclosure provides some methods in the following embodiments as possible implementations of the above manufacturing methods.

[0156] In some embodiments, see Figure 4 Before performing an etching process on the initial sacrificial layer and each supporting pattern layer to form a first trench extending along the first direction in step S40, the manufacturing method further includes the following steps.

[0157] S310: etching and removing the branch based on the sidewall of the branch away from the main body to form a first electrode accommodating groove.

[0158] S320: forming a first electrode in the first electrode receiving groove.

[0159] S330: Patterning the initial sacrificial layer to expose a portion of the surface of each first electrode.

[0160] S340: forming a dielectric layer covering the exposed surface of the first electrode.

[0161] S350: forming a second electrode covering the exposed surface of the dielectric layer.

[0162] The word line hole also exposes the surface of the first electrode facing the bit line.

[0163] In order to more clearly illustrate the manufacturing method provided by the above embodiment, Figures 5 to 17c The manufacturing method is described in detail.

[0164] In step S100, refer to Figure 5 and Figure 5a 、 Figure 5b 、 Figure 5c , multiple layers of sacrificial material layers 210 and multiple layers of supporting material layers 220 are alternately stacked along a direction perpendicular to the substrate 1 (eg, the Z direction).

[0165] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0166] By way of example, the sacrificial material layer 210 includes, but is not limited to, a silicon oxide layer.

[0167] For example, the support material layer 220 includes but is not limited to a silicon nitride layer. Thus, by depositing the silicon oxide layer and the silicon nitride layer in a stacked manner, the challenges of etching the metal layer / silicon oxide layer stacked to the process are avoided.

[0168] Here, the sacrificial material layer 210 can be located between adjacent supporting material layers 220 or on one side of the first and last supporting material layers 220, and the number of sacrificial material layers 210 can match the number of stacked supporting material layers 220. Each sacrificial material layer 210 and each supporting material layer 220 can be formed using a deposition process.

[0169] For example, the deposition processes mentioned above and below include but are not limited to atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, molecular layer deposition (MLD) process, etc.

[0170] In addition, after forming the alternating stack of multiple sacrificial material layers 210 and multiple supporting material layers 220, a first mask layer Y1, such as a photoresist layer and / or a hard mask layer, can be formed on the upper surface of the top sacrificial material layer 210, thereby facilitating the subsequent etching of each sacrificial material layer 210 and each supporting material layer 220 based on the mask pattern in the first mask layer Y1.

[0171] For example, forming the first mask layer Y1 on the upper surface of the top sacrificial material layer 210 includes:

[0172] See also Figure 5 , forming a first mask material layer Y10 on the upper surface of the top sacrificial material layer 210;

[0173] See also Figure 6 , patterning the first mask material layer Y10 to form a first mask layer Y1.

[0174] In step S20, refer to Figure 6 and Figure 6a 、 Figure 6b 、 Figure 6c , the multi-layer sacrificial material layer 210 and the multi-layer supporting material layer 220 are subjected to an etching process to form a multi-layer sacrificial pattern layer 21 and a multi-layer supporting pattern layer 22 having the same pattern.

[0175] In some examples, the sacrificial pattern layer 21 and the supporting pattern layer 22 each include a plurality of repeating patterns to subsequently form a plurality of repeating units as described in the aforementioned embodiments.

[0176] In some embodiments, see Figure 6a The supporting pattern layer 22 includes a main body extending along a first direction (eg, Y direction) and branches spaced apart in the first direction (eg, Y direction) and extending in a direction away from the main body.

[0177] In step S30, refer to Figure 7 and Figure 7a 、 Figure 7b 、 Figure 7c , a sacrificial material is backfilled in the recessed areas of each sacrificial pattern layer 21 and each supporting pattern layer 22 to form an initial sacrificial layer 21 a.

[0178] Illustratively, the initial sacrificial layer 21 a includes, but is not limited to, a silicon oxide layer.

[0179] Here, the material of the initial sacrificial layer 21a is the same as that of the sacrificial pattern layer 21. Based on this, the initial sacrificial layer 21a and the sacrificial pattern layer 21 can be etched using the same process later.

[0180] Illustratively, the initial sacrificial layer 21 a may be formed using a deposition process.

[0181] Here, after the sacrificial material is backfilled using a deposition process, the upper surface of the initial sacrificial layer 21 a may be ground using a CMP process.

[0182] In step S40, refer to Figure 8 and Figure 8a 、 Figure 8b 、 Figure 8c , an etching process is performed on the initial sacrificial layer 21 a and each supporting pattern layer 22 to form a first groove G1 extending along a first direction (eg, Y direction).

[0183] In some examples, before performing an etching process on the initial sacrificial layer 21 a and each supporting pattern layer 22 to form the first trench G1 extending along the first direction (eg, the Y direction), the manufacturing method further includes steps S310 to S350 .

[0184] S310: etching and removing the branch based on the sidewall of the branch away from the main body to form a first electrode accommodating groove.

[0185] See also Figure 9 and Figure 9a 、 Figure 9b 、 Figure 9c Based on the side wall of the branch away from the main body, the branch is etched away to form the first electrode accommodating groove G2.

[0186] S320: forming a first electrode in the first electrode receiving groove.

[0187] For example, the first electrode A includes but is not limited to a conductive metal. For example, the first electrode A may be a copper-tungsten alloy.

[0188] See also Figure 10 and Figure 10a 、 Figure 10b 、 Figure 10c, forming the first electrode A in the first electrode receiving groove G2.

[0189] In some examples, forming the first electrode A in the first electrode receiving groove G2 includes filling the first electrode receiving groove G2 with an electrode material to form the first electrode A. In this case, before forming the first electrode A, the step further includes removing the electrode material covering the first mask layer Y1 and the upper surface of the initial sacrificial layer 21 a.

[0190] For example, the first electrode A may be formed by using an anisotropic process.

[0191] Illustratively, after forming the first electrode A, the manufacturing method further includes: removing the first mask layer Y1 .

[0192] Optionally, a grinding process may be used to remove the first mask layer Y1 to ensure a smooth surface of the top sacrificial pattern layer 21. The grinding process includes but is not limited to chemical mechanical polishing (CMP).

[0193] S330: Patterning the initial sacrificial layer to expose a portion of the surface of each first electrode.

[0194] See also Figure 11 and Figure 11a 、 Figure 11b 、 Figure 11c , patterning the initial sacrificial layer 21a to expose a portion of the surface of each first electrode A.

[0195] S340: forming a dielectric layer covering the exposed surface of the first electrode.

[0196] S350: forming a second electrode covering the exposed surface of the dielectric layer.

[0197] See also Figure 12 and Figure 12a 、 Figure 12b 、 Figure 12c , forming a dielectric layer 23 covering the exposed surface of the first electrode A. , forming a second electrode B covering the exposed surface of the dielectric layer 23.

[0198] Illustratively, the second electrode B includes but is not limited to polysilicon.

[0199] In step S50, refer to Figure 13 and Figure 13a 、 Figure 13b 、 Figure 13c , each support pattern layer 22 is etched back to expose two sidewalls in the first trench G1 to form a bit line trench G3 and an initial support layer 221 extending along the first direction (eg, Y direction).

[0200] In some examples, forming the bit line trench G3 includes: etching back each support pattern layer 22 to expose two sidewalls in the first trench G1 based on the second mask Y2 to form the bit line trench G3.

[0201] For example, the bit line trench G3 may be formed by an isotropic etching process.

[0202] Illustratively, after forming the bit line trench G3 , the manufacturing method further includes: removing the second mask layer Y2 .

[0203] Optionally, a grinding process may be used to remove the second mask layer Y2 to ensure that the surfaces of the top sacrificial pattern layer 21 and the second electrode B are flat. The grinding process includes but is not limited to CMP.

[0204] In step S60, refer to Figure 14 and Figure 14a 、 Figure 14b 、 Figure 14c , forming a bit line BL in the bit line trench G3.

[0205] By way of example, the bit line BL includes, but is not limited to, a conductive metal, such as a copper-tungsten alloy.

[0206] For example, the bit lines BL may be formed by using an anisotropic etching process.

[0207] In step S70, please refer to Figure 14 and Figure 14a 、 Figure 14b 、 Figure 14c , forming an isolation layer 24 in the first trench.

[0208] Illustratively, the isolation layer 24 includes, but is not limited to, a silicon oxide layer.

[0209] Here, the isolation layer 24, the initial sacrificial layer 21a, and the sacrificial pattern layer 21 are made of the same material. For ease of illustration, the isolation layer 24, the initial sacrificial layer 21a, and the sacrificial pattern layer 21 are subsequently filled with the same pattern. Furthermore, the isolation layer 24, the initial sacrificial layer 21a, and the sacrificial pattern layer 21 can be subsequently etched using the same process.

[0210] In step S80, refer to Figure 15 and Figure 15a 、 Figure 15b 、 Figure 15c , a plurality of word line holes are formed in the initial support layer 221 to obtain a support layer 222; the support layer 222 includes a plurality of sub-support portions 2221 spaced apart in a first direction (e.g., the Y direction); the word line holes are located between adjacent sub-support portions 2221 and expose the sidewalls of the corresponding initial sacrificial layer 21a and the bit line BL.

[0211] In some examples, the word line hole also exposes the surface of the first electrode A toward the bit line BL.

[0212] For example, the support layer 222 may be formed by an isotropic etching process.

[0213] In step S90, please continue to refer to Figure 15 and Figure 15a 、 Figure 15b 、 Figure 15c , a semiconductor layer 25, a gate insulating layer 26 and a word line WL are sequentially formed in the word line hole.

[0214] In some embodiments, step S90 sequentially forms a semiconductor layer, a gate insulating layer, and a word line in the word line hole, and includes steps S91 to S96 .

[0215] S91: Conformally forming an initial semiconductor layer on the inner wall of the word line hole.

[0216] For some examples, see Figure 15 and Figure 15a 、 Figure 15b 、 Figure 15c An initial semiconductor layer 250 is conformally formed on the inner wall of the wordline hole. A gate insulating layer 26 is conformally formed on the surface of the initial semiconductor layer 250 facing away from the inner wall of the wordline hole. A word line WL is formed on the surface of the gate insulating layer 26 facing away from the initial semiconductor layer 250 to fill the wordline hole.

[0217] For example, the initial semiconductor layer 250 includes but is not limited to a metal oxide semiconductor layer, such as indium gallium zinc oxide (IGZO).

[0218] For example, the initial semiconductor layer 250 can be formed by a deposition process, such as an ALD process. After the initial semiconductor layer 250 is formed by the deposition process, the upper surface of the resulting structure can be polished by a CMP process to ensure that the exposed initial semiconductor layer 250 has good surface quality.

[0219] S92: Conformally forming a gate insulating layer on a surface of the initial semiconductor layer away from the inner wall of the word line hole.

[0220] For example, the gate insulating layer 26 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0221] For example, the gate insulating layer 26 can be formed using a deposition process, such as an ALD process. Furthermore, after the gate insulating layer 26 is formed using the deposition process, the upper surface of the resulting structure can be polished using a CMP process to ensure that the exposed gate insulating layer 26 has a good surface quality. In this way, before forming the word lines WL, the material near the word lines WL is selectively retained, avoiding the risks of subsequent deposition fill and the degree of retention of the support layer 222, thereby reducing the process risks of ALD and dry etching.

[0222] S93: forming a word line filling the word line hole on a surface of the gate insulating layer facing away from the initial semiconductor layer.

[0223] By way of example, the word line WL includes, but is not limited to, a conductive metal, such as a copper-tungsten alloy.

[0224] For example, the word lines WL may be formed using a deposition process, such as an ALD process. Furthermore, after the word lines WL are formed using the deposition process, a CMP process may be used to polish the upper surface of the resulting structure to ensure that the exposed word lines WL have good surface quality.

[0225] S94: removing the initial sacrificial layer.

[0226] For some examples, see Figure 16 and Figure 16a 、 Figure 16b 、 Figure 16c , the initial sacrificial layer 21a may be removed by an isotropic etching process.

[0227] For example, while removing the initial sacrificial layer 21 a , the manufacturing method further includes: simultaneously removing the isolation layer 24 and the sacrificial pattern layer 21 .

[0228] S95: removing the initial semiconductor layer between adjacent supporting layers in a direction perpendicular to the substrate to form a semiconductor layer.

[0229] For some examples, see Figure 16 and Figure 16a 、 Figure 16b 、 Figure 16c , the initial semiconductor layer 250 between adjacent support layers 222 in a direction perpendicular to the substrate (eg, Z direction) is removed to form a semiconductor layer 25 .

[0230] For example, an isotropic etching process may be used to remove the initial semiconductor layer 250 between adjacent support layers 222 in a direction perpendicular to the substrate 1 (eg, the Z direction).

[0231] S96: Filling the area where the initial sacrificial layer is removed with an insulating material to form an insulating layer.

[0232] For some examples, see Figure 17 and Figure 17a 、 Figure 17b 、 Figure 17c , an insulating material is filled in the removed area of the initial sacrificial layer 21 a to form an insulating layer 27 .

[0233] For example, the insulating layer 27 may be formed by a deposition process. After the insulating layer 27 is formed by the deposition process, the upper surface of the resulting structure may be polished by a CMP process to ensure that the exposed insulating layer 27 has a good surface quality.

[0234] Illustratively, the insulating layer 27 includes, but is not limited to, a silicon oxide layer.

[0235] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include a housing, a circuit board disposed within the housing, and a memory integrated on the circuit board. For the structure of the memory, please refer to the relevant description of some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0236] In some embodiments, an external control device, such as a processor or actuator, coupled to the memory may also be integrated on the circuit board. For example, the electronic device may further include a processor integrated on the circuit board. The processor is coupled to the memory and can control read and write operations of the memory.

[0237] In some embodiments, the memory is 3D-DRAM.

[0238] It should be added that the "one-time etching process" mentioned in some of the above embodiments can be understood as: etching based on the pattern of the same mask layer to form the same pattern; and it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.

[0239] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include a housing, a circuit board disposed within the housing, and a memory integrated on the circuit board. For the structure of the memory, please refer to the relevant description of some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0240] In some embodiments, an external control device, such as a processor or actuator, coupled to the memory may also be integrated on the circuit board. For example, the electronic device may further include a processor integrated on the circuit board. The processor is coupled to the memory and can control read and write operations of the memory.

[0241] In some embodiments, the memory is 3D-DRAM.

[0242] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0243] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A memory, characterized in that: include: A substrate and one or more repeating units and a plurality of word lines disposed on the substrate; Wherein, the repeating unit comprises: Two bit lines extending along a first direction and spaced apart, and an isolation layer disposed between the two bit lines; a support layer disposed on a sidewall of the bit line facing away from the isolation layer; the support layer comprising a plurality of sub-support portions spaced apart in the first direction, with spaces between adjacent sub-support portions forming word line holes; the word line being located within the word line hole and extending in a direction perpendicular to the substrate; A plurality of transistors are arranged in a row along the first direction on a side of any bit line away from the isolation layer; the transistors are located in the word line hole and include: a semiconductor layer surrounding the sidewalls of the word line, and a gate insulating layer disposed between the sidewalls of the word line and the inner sidewalls of the semiconductor layer; The outer sidewall of the semiconductor layer away from the corresponding bit line is flush with the sidewall of the adjacent sub-support portion away from the same bit line.

2. The memory according to claim 1, wherein The repeating unit further comprises: A plurality of storage capacitors are arranged in a row along the first direction on a side of any one of the bit lines away from the isolation layer; the storage capacitors include: a first electrode, a dielectric layer, and a second electrode; the first electrode is located on an outer sidewall of the semiconductor layer away from the corresponding bit line and extends in a direction away from the bit line; the dielectric layer covers an outer surface of the first electrode, and the second electrode covers an outer surface of the dielectric layer; The insulating layer is located on a side wall of each of the sub-support portions away from the corresponding bit line and between the first electrodes adjacent to each other in the first direction.

3. The memory according to claim 2, wherein: The supporting layer includes a silicon nitride layer; and the insulating layer includes a silicon oxide layer.

4. The memory according to claim 2, wherein: The plurality of dielectric layers of a column of the storage capacitors are connected as a whole and cover the sidewalls of the corresponding insulating layers away from the sub-support portion; the plurality of second electrodes of a column of the storage capacitors are connected as a whole.

5. The memory according to claim 2, wherein: There are multiple repeating units, and the multiple repeating units are arranged in a row along a second direction; the second direction is parallel to the substrate and intersects the first direction; In a row of the repeating units, the second electrodes of adjacent storage capacitors are integrally connected.

6. The memory according to claim 2, wherein: There are multiple repeating units, and the multiple repeating units are stacked in a direction perpendicular to the substrate; The insulating layer further extends between the support layers adjacent to each other in a direction perpendicular to the substrate, and between the semiconductor layers adjacent to each other in a direction perpendicular to the substrate.

7. A method for manufacturing a memory, characterized in that: include: forming multiple layers of sacrificial material and multiple layers of supporting material alternately stacked in a direction perpendicular to the substrate; Performing a single etching process on the multi-layer sacrificial material layer and the multi-layer supporting material layer to form a multi-layer sacrificial pattern layer and a multi-layer supporting pattern layer having the same pattern; Backfilling sacrificial material in the concave regions of each sacrificial pattern layer and each supporting pattern layer to form an initial sacrificial layer; Performing an etching process on the initial sacrificial layer and each of the support pattern layers to form a first trench extending along a first direction; etching back each of the support pattern layers to expose two sidewalls in the first trench to form a bit line trench and an initial support layer extending along the first direction; forming a bit line in the bit line trench; forming an isolation layer in the first trench; forming a plurality of wordline holes in the initial support layer to obtain a support layer; the support layer includes a plurality of sub-support portions spaced apart in the first direction; the wordline holes are located between adjacent sub-support portions and expose sidewalls corresponding to the initial sacrificial layer and the bit lines; A semiconductor layer, a gate insulating layer and a word line are sequentially formed in the word line hole.

8. The method for manufacturing a memory according to claim 7, wherein: The step of sequentially forming a semiconductor layer, a gate insulating layer, and a word line in the word line hole includes: Conformally forming an initial semiconductor layer on the inner wall of the word line hole; Conformally forming the gate insulating layer on a surface of the initial semiconductor layer away from the inner wall of the word line hole; forming the word line filling the word line hole on a surface of the gate insulating layer facing away from the initial semiconductor layer; removing the initial sacrificial layer; removing the initial semiconductor layer between adjacent support layers in a direction perpendicular to the substrate to form the semiconductor layer; An insulating material is filled in the removed area of the initial sacrificial layer to form an insulating layer.

9. The method for manufacturing a memory according to claim 7 or 8, wherein: The support pattern layer includes a main body extending along the first direction and branches arranged at intervals in the first direction and extending in a direction away from the main body; Before performing a single etching process on the initial sacrificial layer and each of the support pattern layers to form a first trench extending along the first direction, the manufacturing method further includes: Based on the sidewall of the branch away from the main body, etching and removing the branch to form a first electrode accommodating groove; forming a first electrode in the first electrode receiving groove; patterning the initial sacrificial layer to expose a portion of the surface of each of the first electrodes; forming a dielectric layer covering the exposed surface of the first electrode; forming a second electrode covering the exposed surface of the dielectric layer; The word line hole further exposes a surface of the first electrode facing the bit line.

10. An electronic device, characterized in that: include: The memory according to any one of claims 1 to 6.

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