A method for preparing a semiconductor structure and a semiconductor structure thereof

Abstract

A method for manufacturing a semiconductor structure and the semiconductor structure thereof. The method comprises: providing a substrate; forming a stacked structure on the substrate, the stacked structure being composed of a first layer and a second layer alternately stacked in a third direction, the third direction being perpendicular to the substrate surface; forming a first opening, the first opening passing through the stacked structure along the third direction and extending into the substrate; forming a filling layer in the first opening, the top surface of the filling layer being no lower than the upper surface of the substrate, and the remaining first opening serving as a second opening; etching away a portion of the second layer through the second opening to form a third opening; forming a bitline structure in the third opening, the bitline structure extending along the second direction and spaced apart in both the first and third directions; and forming a dielectric layer, the dielectric layer at least filling the second opening.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Art

[0002] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As semiconductor device structures shrink in size, the technical barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is an effective means to break through existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM) meets these needs. However, existing 3D DRAM may damage the substrate during the lateral etching process, affecting the performance and yield of the semiconductor structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure thereof, which are at least beneficial for protecting a substrate and improving the performance and yield of a semiconductor memory device.

[0005] According to some embodiments of the present disclosure, one aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate;

[0006] forming a laminated structure on a substrate, wherein the laminated structure is formed by alternating first and second layers in a third direction, wherein the third direction is perpendicular to the surface of the substrate;

[0007] forming a first opening, the first opening passing through the laminated structure along a third direction and extending into the substrate;

[0008] forming a filling layer in the first opening, wherein the top surface of the filling layer is not lower than the upper surface of the substrate, and the remaining first opening serves as the second opening;

[0009] etching away a portion of the second layer through the second opening to form a third opening;

[0010] forming a bit line structure in the third opening, the bit line structure extending along the second direction and spaced apart in both the first direction and the third direction;

[0011] A dielectric layer is formed, wherein the dielectric layer at least fills the second opening.

[0012] In some embodiments, the top surface of the filling layer is flush with the top surface of the bottommost first layer in the stacked structure.

[0013] In some embodiments, there is a first distance between the bottom first layer and the second bottom first layer, and the top surface of the filling layer is located at one third of the first distance and is close to the bottom first layer.

[0014] In some embodiments, the depth of the first opening extending into the substrate is a first depth, and forming a filling layer in the first opening specifically includes: forming a prefabricated filling layer, which at least fills the first opening; removing part of the prefabricated filling layer to form a filling layer, which is not lower than the substrate.

[0015] In some embodiments, before forming the prefabricated filling layer, the method further includes forming a first protective layer, where the first protective layer at least covers the sidewalls and the bottom of the first opening.

[0016] In some embodiments, the process of removing part of the prefabricated filling layer to form the filling layer also includes: simultaneously removing part of the first protective layer to form a second protective layer, the second protective layer having a second depth along the sidewall of the first opening, and the second depth is equal to the first depth.

[0017] In some embodiments, after forming the filling layer, the method further includes: removing a portion of the first protection layer to form a second protection layer, wherein the second protection layer has a second depth along the sidewall of the first opening, and the second depth is not less than the first depth.

[0018] In some embodiments, the process of etching and removing a portion of the second layer to form the third opening further includes: removing the filling layer to form a fourth opening, and the second opening and the fourth opening together constitute a fifth opening.

[0019] In some embodiments, the dielectric layer fills the fifth opening, the dielectric layer is at least located on the second protective layer, the dielectric layer has a corner on top of the second protective layer, and the contact surface between the second protective layer and the dielectric layer is inverted convex.

[0020] In some embodiments, the dielectric layer is at least located on the filling layer, and a contact surface between the filling layer and the dielectric layer is linear.

[0021] Another aspect of the present disclosure provides a semiconductor structure, including:

[0022] substrate;

[0023] A laminated structure is provided on a substrate, wherein the laminated structure is formed by alternately stacking a first layer and a second layer in a third direction, wherein the third direction is perpendicular to a surface of the substrate;

[0024] a first opening passing through the laminated structure along a third direction and extending into the substrate;

[0025] a filling structure located in the first opening and not lower than the upper surface of the substrate;

[0026] a third opening formed by removing a portion of the second layer;

[0027] A bit line structure, wherein in the third opening, the bit line structure extends along the second direction and is spaced apart in both the first direction and the third direction;

[0028] The dielectric layer is located above the filling structure and between adjacent bit line structures.

[0029] In some embodiments, the filling structure includes at least a filling layer, and a top surface of the filling structure is flush with a top surface of a bottommost first layer in the stacked structure.

[0030] In some embodiments, the filling structure includes at least a filling layer, and there is a first distance between the bottom first layer and the second bottom first layer. The top surface of the filling structure is located at one-third of the first distance and the top surface of the filling structure is close to the bottom first layer.

[0031] In some embodiments, the dielectric layer is at least located on the filling layer, and a contact surface between the filling layer and the dielectric layer is linear.

[0032] In some embodiments, the filling structure includes a second protection layer, the filling structure only covers the bottom and a portion of the sidewall of the first opening, and the top of the filling structure is flush with the top surface of the bottommost first layer in the stacked structure.

[0033] In some embodiments, the filling structure includes a second protective layer, there is a first distance between the bottom first layer and the second bottom first layer, the top of the filling structure is located at one-third of the first distance and the top of the filling structure is close to the bottom first layer.

[0034] In some embodiments, the dielectric layer is at least located on the filling structure, the dielectric layer has a corner on the top of the filling structure, and the contact surface between the filling structure and the dielectric layer is in an inverted convex shape.

[0035] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by setting a first opening in the stacked structure and forming a filling layer in the first opening, and the top surface of the filling layer is not lower than the upper surface of the substrate, in the process of performing lateral etching to remove part of the second layer to form the third opening, the filling layer can serve as a protective layer of the substrate to prevent the substrate from being damaged by etching, thereby improving the performance and yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1A flowchart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0038] Figure 2A 2M is a process flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0039] Figure 3 A three-dimensional schematic diagram of a bit line structure provided in one embodiment of the present disclosure.

[0040] Figures 4A to 4K A process flow chart of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure.

[0041] Figures 5A to 5C A schematic diagram of a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0042] Figures 6A to 6C A schematic diagram of a semiconductor structure provided in accordance with another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0044] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0045] It will be understood that the meanings of “on,” “over,” and “over” throughout this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0046] In the embodiments of the present disclosure, the terms "first," "second," "third," etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0047] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0048] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0049] Figure 1 A flowchart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0050] Figure 2A 2M is a process flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0051] Figure 3 A three-dimensional schematic diagram of a bit line structure provided in one embodiment of the present disclosure.

[0052] Figures 4A to 4K A process flow chart of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure.

[0053] Figures 5A to 5C A schematic diagram of a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0054] Figures 6A to 6C A schematic diagram of a semiconductor structure provided in accordance with another embodiment of the present disclosure.

[0055] like Figure 1 As shown, the preparation method includes at least the following steps: S10 providing a substrate; S20 forming a stacked structure on the substrate, the stacked structure being formed by alternating a first layer and a second layer in a third direction, the third direction being perpendicular to the surface of the substrate; S30 forming a first opening, the first opening passing through the stacked structure along the third direction and extending into the substrate; S40 forming a filling layer in the first opening, the top surface of the filling layer being not lower than the upper surface of the substrate, and the remaining first opening serving as a second opening; S50 etching away a portion of the second layer through the second opening to form a third opening; S60 forming a bit line structure in the third opening, the bit line structure extending along the second direction and being spaced apart in both the first direction and the third direction; S70 forming a dielectric layer, the dielectric layer at least filling the second opening.

[0056] The specific embodiments of the semiconductor structure and the method for forming the same proposed by the present invention are described in detail below with reference to the accompanying drawings.

[0057] See also Figure 1 and Figure 2A , providing a substrate 10; the substrate 10 includes an upper surface S1 and a lower surface S2, and a laminated structure 101 is formed on the substrate, wherein the laminated structure 101 is formed by alternating first layers 102 and second layers 103 in a third direction Z, and the third direction Z is perpendicular to the surface of the substrate 10;

[0058] The substrate material can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the substrate material is silicon. The first layer 102 can be silicon-germanium (GeSi), and the second layer 10 can be silicon (Si). That is, the stacked structure 101 is composed of silicon-germanium and silicon alternately stacked on the upper surface S1 of the substrate 10.

[0059] Next, please refer to Figure 1 and Figures 2B-2C , forming a first opening 301, the first opening 301 passes through the stacked structure 101 along the third direction Z and extends into the substrate 10, and the depth of the first opening 301 extending into the substrate 10 is a first depth D1; before forming the first opening 301, it also includes: forming a mask layer 201 on the stacked structure 101, the mask layer may include one or more layers, forming a photoresist layer (not shown in the figure) on the mask layer, the photoresist layer having an opening (not shown in the figure), and forming the first opening 301 after photolithography along the opening.

[0060] Next, please refer to Figure 2D-2H(d) A filling layer 404 is formed in the first opening 301, wherein the top surface of the filling layer 404 is not lower than the upper surface S1 of the substrate 10, and the remaining first opening 301 serves as the second opening 302. Forming the filling layer 404 in the first opening 301 specifically includes: forming a prefabricated filling layer 402', wherein the prefabricated filling layer 402' at least fills the first opening 301; and removing a portion of the prefabricated filling layer 402' to form a filling layer 404, wherein the filling layer 404 is not lower than the substrate 10. Methods for forming the prefabricated filling layer 402' include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and the like.

[0061] For details, please refer to 2D-2F. Before forming the filling layer 404, a prefabricated filling layer 402' is also formed. The material of the prefabricated filling layer 402' can be silicon or polysilicon. In order to prevent damage to the stacked structure 101 during the subsequent etching of the prefabricated filling layer 402', a first protective layer 401' can be formed before the prefabricated filling layer 402'. The first protective layer 401' covers the sidewalls and bottom of the first opening 301 and covers the surface of the mask layer 201. The material of the first protective layer 401' can be silicon oxide, silicon nitride or silicon oxynitride. The material of the first protective layer 401' is different from that of the prefabricated filling layer 402'. Figure 2E As shown, a prefabricated filling layer 402' is formed, and the prefabricated filling layer 402' covers the first protective layer 401' and fills the remaining first opening 301; Figure 2F As shown, the first protection layer 401 ′ and the prefabricated filling layer 402 ′ on the top of the stacked structure 101 are removed, and the remaining first protection layer 401 ′ only covers the sidewalls and bottom of the first opening, and the surface of the remaining prefabricated filling layer 402 ′ is flush with the surface of the stacked structure.

[0062] Next, please refer to Figure 2G(a) 、 2G(b) and 2G(c), removing part of the prefabricated filling layer 402' to form a filling layer 404, the filling layer 404 is not lower than the substrate 10. Figure 2G(a) 、 2G(b)and 2G(c) are schematic diagrams of filling layers 404 of different depths; as shown in FIG2G(a), part of the prefabricated filling layer 402' is etched away to form a filling layer 404, and the depth of the filling layer 404 is equal to the first depth D1; as shown in FIG2G(b), part of the prefabricated filling layer 402' is etched away to form a filling layer 404, and the top surface of the filling layer 404 is flush with the top surface of the bottom first layer 102 in the stacked structure; as shown in FIG2G(c), part of the prefabricated filling layer 402' is etched away to form a filling layer 404, and there is a first distance D between the bottom first layer 102 and the second bottom first layer 102, and the top surface of the filling layer 404 is located at one-third of the first distance D and the top surface of the filling layer 404 is close to the bottom first layer 102. The Bosch process can be used to remove part of the prefabricated filling layer 402' to form a filling layer 404. The Bosch process is also called the Bosch process because it was first proposed by Robert Bosch. The Bosch process refers to passivation on the etched sidewalls to protect the sidewalls in order to prevent or weaken lateral etching in integrated circuit manufacturing. This process first uses fluorine-based active groups to etch silicon, and then passivates the sidewalls. The etching and protection steps are performed alternately. Etching and sidewall passivation are achieved by alternating between etching gases and passivation gases. The specific process of the Bosch process is an etching process and a passivation process. The etching process mainly introduces etching gases such as sulfur hexafluoride SF6, and the passivation process mainly introduces passivation gases such as carbon fluoride C4F8. Since the passivation gas has a high carbon content, it is easy to adhere to and deposit on the surface of the film layer to protect the sidewalls.

[0063] Next, please refer to Figure 2H(a) 、 2H(b) In step 2H(c), a portion of the first protective layer 401' is removed to form a second protective layer 403. The second protective layer 403 has a second depth D2 along the sidewall of the first opening 301, and the second depth D2 is not less than the first depth D1. The space in the first opening excluding the filling layer 404 and the second protective layer 403 forms a second opening 302. As shown in FIG. 2H(a), the second depth D2 is equal to the first depth D1. Figures 2H(b)-2H(d)The second depth D2 shown is greater than the first depth D1. As shown in FIG2H(b), the second depth D2 is equal to the distance from the top surface of the bottom first layer 102 in the laminate structure to the bottom of the first opening 301. As shown in FIG2H(c), there is a first spacing D between the bottom first layer 102 and the second bottom first layer 102. The top surface of the filling layer 404 is located at one-third of the first spacing D and the top surface of the filling layer 404 is close to the bottom first layer 102. The second depth D2 is the depth of the filling layer 404. As shown in FIG2H(d), the top surface of the filling layer 404 is flush with the top surface of the bottom first layer 102 in the laminate structure. The second depth D2 is higher than the filling layer 404. The top surface of the filling layer 404 is lower than the top surface of the second layer 103 at the bottom, and D2 is preferably located at the lower third of the first distance D; the reason for setting the filling layer 404 and the second protective layer 403 is to prevent damage to the substrate 10 when a portion of the second layer 103 is subsequently etched away. Without the protection of the filling layer 404, the substrate 10 is easily etched during the etching process, causing damage to the substrate 10, generating leakage current and even short circuit, affecting the performance and yield of the semiconductor device; in the present application, the setting of the filling layer 404 and the second protective layer 403 can protect the substrate 10, prevent leakage current and short circuit, and improve the performance and yield of the semiconductor device.

[0064] Next, please refer to Figure 2I(a) to Figure 2J(c) , a portion of the second layer 103 is etched away through the second opening 302 to form a third opening 303; there are two specific ways to form the third opening 303. One is to Figure 2H(a) to Figure 2H(d) Direct etching is performed on the basis of the second layer 103 and the filling layer 404 to form Figure 2J(a) to Figure 2J(c) , a portion of the second layer 103 is removed to form a third opening 303, and a filling layer 404 is removed to form a fourth opening 304; the second opening 302 and the fourth opening 304 together constitute a fifth opening 305; in this embodiment, since the second layer is made of silicon and the filling layer 404 is also made of silicon or polysilicon, the filling layer 404 can be simultaneously etched and removed during the process of etching to form the third opening 303. In this way, during the process of lateral etching to form the third opening 303, not only can the substrate 10 be protected from damage but also the process steps can be simplified; another method is as follows Figure 2I(a) to Figure 2I(c) As shown, in Figure 2H(a) to Figure 2H(d)On the basis of the present invention, the filling layer 404 is first etched away to form the fourth opening 304. The second opening 302 and the fourth opening 304 together constitute the fifth opening 305. A portion of the second layer 103 is etched away through the fifth opening 305 to form the third opening 303. Since the filling layer 404 is removed in advance, the influence of the residual filling layer 404 on the semiconductor performance can be prevented. In addition, it should be noted that the first protective layer 401' and the second protective layer 403 are necessary in this embodiment. Because the material of the filling layer 404 has a relatively low etching selectivity compared to the material of the stacked structure 101, the presence of the first protective layer 401' and the second protective layer 403 can protect the stacked structure and prevent damage during the process of etching away the prefabricated filling layer 402' and laterally etching away the second layer 103.

[0065] No matter which method is chosen during the process of forming the third opening 303, it is necessary to ensure that the substrate 10 is not damaged; as shown in Figure 2H(a), the depth of the filling layer 404 is D2, the depth of the second protective layer 403 along the side wall of the first opening 301 is also D2, the depth of the first opening 301 extending into the substrate 10 is the first depth D1, and the first depth D1 is equal to the second depth D2, so as to ensure that the substrate 10 is not etched when the third opening 303 is formed by lateral etching; as shown in Figure 2H(b), the top surface of the filling layer 404 is flush with the top surface of the bottom first layer 102 in the stacked structure 101, the depth of the filling layer 404 is the second depth D2, the depth of the second protective layer 403 along the side wall of the first opening 301 is also D2, and the second depth D2 is greater than the first depth D1, so that the substrate 10 can be better protected and prevented from being damaged when the third opening 303 is formed by lateral etching. As shown in FIG2H(c), there is a first distance D between the bottom first layer 102 and the second bottom first layer 102. The top surface of the filling layer 404 is located at one-third of the first distance D and the top surface of the filling layer 404 is close to the bottom first layer 102. The second depth D2 is the depth of the filling layer 404. The depth of the second protective layer 403 is also D2. The second depth D2 is greater than the first depth D1. The reason for this setting is that the deeper the depth of the filling layer 404 and the second protective layer 403, the better the protection effect on the substrate 10. However, the filling layer 404 and the second protective layer 403 cannot exceed the bottom second layer 101 in the stacked structure 101. 03, if it exceeds the top surface of the second layer 103, it may cause the bottom second layer 103 to fail, because the second layer 103 will be ion doped to form a source and drain region later. If the filling layer 404 and the second protective layer 403 exceed the top surface of the second layer 103, the second layer 103 will not be able to form a source and drain region, affecting the density and efficiency during the process. In this embodiment, the top surface of the filling layer 404 is located at one-third of the first distance D and the top surface of the filling layer 404 is close to the bottom first layer 102. This arrangement not only protects the substrate 10, but also reserves sufficient space for the subsequent etching to form the third opening 303, and will not affect the subsequent formation of the source and drain. As shown in Figure 2H (d), the top surface of the filling layer 404 is flush with the top surface of the bottom first layer 102 in the stacked structure, and the second depth D2 of the second protective layer 403 is higher than the top surface of the filling layer 404. As mentioned above, the depth of the second protective layer 403 is preferably located at the lower third of the first distance D.

[0066] If the filling layer 404 is first etched away and then the third opening 303 is formed through the fifth opening 305, only the second protective layer 403 protects the substrate 10 during the process of etching to form the third opening 303. Figure 2I(a) to Figure 2I(c). In FIG2I(a), the depth of the first opening 301 extending into the substrate 10 is a first depth D1, and the depth of the second protective layer 403 along the sidewall of the first opening 301 is D2. The first depth D1 is equal to the second depth D2. Since the etching selectivity of the second protective layer 403 and the second layer 103 is relatively large, retaining only the second protective layer 403 can also protect the substrate 10. In FIG2I(b), the top of the sidewall of the second protective layer 403 is flush with the top surface of the bottom first layer. In this way, the deeper sidewall depth of the second protective layer 403 can better protect the substrate 10. In FIG2I(c), there is a first spacing D between the bottom first layer 102 and the second bottom first layer 102. The top of the sidewall of the second protective layer 403 is located at one-third of the first spacing and close to the bottom first layer. This arrangement not only protects the substrate 10, but also reserves sufficient space for the subsequent formation of the third opening 303, and will not affect the formation of the source and drain in the later stage.

[0067] Then please combine Figures 2K(a)-2K(c) and Figure 3 As shown, a bitline structure 50 is formed in the third opening 303. The bitline structure 50 extends along the second direction Y and is spaced apart in both the first direction X and the third direction Z. The bitline structure 50 includes a first metal layer 501 and a second metal layer 502. Metal ions are injected into the second layer 103, where they react with silicon in the second layer 103. After annealing, a metal silicide layer, namely the second metal layer 502, is formed. Unreacted metal ions constitute the first metal layer 501. The metal ions may include one or more of titanium (Ti), cobalt (Co), nickel (Ni), and molybdenum (Mo). The metal silicide may include titanium silicide (TiSix), cobalt cobalt (CoSix), nickel silicide (NiSix), titanium nickel silicon (TiNiSix), cobalt nickel silicon (CoNiSix), molybdenum nickel silicon (MoNiSix), etc. Before forming the bitline structure 50, ion doping is performed on the second layer 103 exposed by the third opening 303 to form source and drain regions (not shown). The source and drain regions are electrically connected to the bitline structure 50.

[0068] Next, please refer to Figures 2L(a)-2M(c) A dielectric layer 60 is formed in the fifth opening 305. The dielectric layer 60 includes a first dielectric layer 601 and a second dielectric layer 602. The dielectric layer 60 fills the fifth opening 305. The dielectric layer 60 is mainly used to isolate the bit line structure 50. The dielectric layer 60 is located on the second protective layer 403. The dielectric layer 60 has a corner on the top of the second protective layer 403. The contact surface between the second protective layer 403 and the dielectric layer 60 is inverted. Figure 2L(a)-Figure 2L(c) As shown, a first dielectric layer 601 is first formed in the fifth opening 305. The first dielectric layer 601 covers the bottom and sidewalls of the fifth opening 305. Figure 2M(a)-Figure 2M(c)As shown, a second dielectric layer 602 is formed on the first dielectric layer 601. The second dielectric layer 602 fills the remaining fifth opening 305. The first dielectric layer 601 and the second dielectric layer 602 together constitute a dielectric layer 60. The top surface of the dielectric layer 60 is flush with the mask layer 201. Figure 2M(a)-Figure 2M(c) It can be seen that the dielectric layer 60 is located on the second protective layer 403, and the dielectric layer 60 has a corner A on the top of the second protective layer 403. As shown in the enlarged view, when the first protective layer 601 is deposited, due to the presence of the second protective layer 403, the first dielectric layer 601 has a corner A on the top of the second protective layer 403. When the second dielectric layer 602 is subsequently formed, a corner will also be formed here, that is, the contact surface between the finally formed dielectric layer 60 and the second protective layer 403 is inverted convex.

[0069] In this embodiment, at least by forming the second protection layer 403 , the silicon substrate 10 can be protected when a portion of the second layer 103 is removed by lateral etching, thereby preventing the substrate 10 from being damaged.

[0070] Figures 4A to 4K This is a process flow chart of a semiconductor structure preparation method provided by another embodiment of the present disclosure; since some process steps of this embodiment are the same or corresponding to those of the previous embodiment, the same or corresponding parts as those of the previous embodiment can refer to the corresponding description of the previous embodiment, and the specific details can refer to Figures 4A-4C The semiconductor structure forming method of the present invention comprises the following steps: Figure 4A As shown, a substrate 10 is provided; the substrate 10 includes an upper surface S1 and a lower surface S2, and a laminated structure 101 is formed on the substrate. The laminated structure 101 is formed by alternating first layers 102 and second layers 103 in a third direction Z, and the third direction Z is perpendicular to the surface of the substrate 10;

[0071] The substrate material can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the substrate material is silicon. The first layer 102 can be silicon-germanium (GeSi), and the second layer 10 can be silicon (Si). That is, the stacked structure 101 is composed of silicon-germanium and silicon alternately stacked on the upper surface S1 of the substrate 10.

[0072] Next, please refer to Figure 1 and Figures 4B-4C, forming a first opening 301, the first opening 301 passes through the stacked structure 101 along the third direction Z and extends into the substrate 10, and the depth of the first opening 301 extending into the substrate 10 is a first depth D1; before forming the first opening 301, it also includes: forming a mask layer 201 on the stacked structure 101, the mask layer may include one or more layers, forming a photoresist layer (not shown in the figure) on the mask layer, the photoresist layer having an opening (not shown in the figure), and forming the first opening 301 after photolithography along the opening.

[0073] Next, please refer to Figure 4D-4G(c) A filling layer 404 is formed in the first opening 301, wherein the top surface of the filling layer 404 is not lower than the upper surface S1 of the substrate 10, and the remaining first opening 301 serves as the second opening 302. The forming of the filling layer 404 in the first opening 301 specifically includes: forming a prefabricated filling layer 402', wherein the prefabricated filling layer 402' at least fills the first opening 301; removing a portion of the prefabricated filling layer 402' to form a filling layer 404, wherein the filling layer 404 is not lower than the substrate 10. The forming method of the prefabricated filling layer 402' includes, but is not limited to, spin-on dielectric layer (SOD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0074] For details, please refer to Figure 4D -4F, before forming the filling layer 404, it also includes forming a prefabricated filling layer 402', such as Figure 4E The prefabricated filling layer 402' fills the first opening 301 and covers the surface of the mask layer 201, as shown in FIG. Figure 4F(a) and 4F(b) As shown, the portion of the prefabricated filling layer 402' above the mask layer 201 is removed so that the remaining prefabricated filling layer 402' is flush with the mask layer 201. Figure 4DAs shown, if the prefabricated filling layer 402' is formed by the SOD process, it is necessary to form a first protective layer 401' before filling the prefabricated filling layer 402'. Since the SOD process requires an annealing process, in order to prevent the stacked structure 101 from being oxidized during the annealing process, it is necessary to form the first protective layer 401' before the SOD to protect the stacked structure; the material of the prefabricated filling layer 402' is the same as that of the first protective layer 401', such as silicon oxide, silicon nitride, silicon oxynitride, etc. The material of the prefabricated filling layer 402' is the same as that of the first protective layer 401', which can simplify the process steps and prevent multiple step-by-step etching caused by different materials. If the prefabricated filling layer 402' is formed by other processes, such as CVD, PECVD, ALD, etc., there is no need to form the first protective layer 401' before filling the prefabricated filling layer 402'. That is, if CVD, PECVD, or ALD processes are used, the prefabricated filling layer 402' can be directly deposited and filled in the first opening 301, and the portion of the prefabricated filling layer 402' above the mask layer 201 can be removed so that the remaining prefabricated filling layer 402' is flush with the mask layer 201.

[0075] The following description will be made by taking the first opening 301 having both the first protection layer 401 ′ and the prefabricated filling layer 402 ′ as an example. It should be noted that the first opening 301 may be filled with only the prefabricated filling layer 402 ′.

[0076] Next, please refer to Figures 4G(a)-4G(c), and at the same time, the first protective layer 401' and the prefabricated filling layer 402' are removed to form a second protective layer 403 and a filling layer 404. The top surface of the filling layer 404 is not lower than the upper surface S1 of the substrate 10. The top of the side wall of the second protective layer is flush with the top surface of the filling layer 404. The remaining first opening 301 serves as the second opening 302. Since the first protective layer 401' and the prefabricated filling layer 402' are made of the same material, they can be etched simultaneously. Compared with the previous embodiment, this embodiment can simplify the process steps. In addition, the difference between this embodiment and the previous embodiment lies in the different etching methods. In the previous embodiment, the Bosch process is used to remove part of the prefabricated filling layer 402' to form the filling layer 404. Because this process first uses fluorine-based active groups to etch silicon, and then performs sidewall passivation, the etching and protection steps are performed alternately. Sidewall passivation mainly refers to depositing a protective layer on the sidewall. The Bosch process can effectively protect the sidewall, but when the size is miniaturized and the size of the trench becomes smaller and smaller, it is difficult to deposit the sidewall to achieve the passivation purpose, and the Bosch process will be limited. Therefore, in this embodiment, the etching process is further optimized. In the process of removing part of the prefabricated filling layer 402' to form the filling layer 404, vapor oxidation etching is used instead of the Bosch process. The gas introduced into the vapor oxidation etching is generally HF or NH3, which are highly corrosive gases. The reaction process is pure etching and does not include a passivation process. The gas molecules are small and can easily enter small-sized structures. Generally, it can be used in semiconductor structures less than 10nm. Vapor oxidation etching can overcome the problem of the Bosch process in which small-sized structures cannot be covered due to the simultaneous passivation and etching in the future size reduction process.

[0077] A portion of the prefabricated filling layer 402' is removed to form a filling layer 404, which is not lower than the substrate 10. Figure 4G(a) 、 4GB)Figures 4G(a) and 4G(c) are schematic diagrams of filling layers 404 having different depths. As shown in Figure 4G(a), the depth of filling layer 404 is a second depth D2, which is equal to the first depth D1. As shown in Figure 4G(b), the top surface of filling layer 404 is flush with the top surface of the bottom-most first layer 102 in the stacked structure. As shown in Figure 4G(c), a first spacing D is defined between the bottom-most first layer 102 and the second-bottom-most first layer 102, and the top surface of filling layer 404 is located at one-third of the first spacing D, with the top surface of filling layer 404 being close to the bottom-most first layer 102. Different depths of filling layer 404 result in different final structures. Figure 4G(b) will be used as an example to illustrate other process steps. The reason for setting the filling layer 404 and the second protective layer 403 is to prevent damage to the substrate 10 when the second layer 103 is subsequently etched and removed. Without the protection of the filling layer 404, the substrate 10 is easily etched during the etching process, causing damage to the substrate 10, resulting in leakage current and even short circuit, affecting the performance and yield of the semiconductor device. In this application, only the filling layer 404 is set or the filling layer 404 and the second protective layer 403 are set at the same time to protect the substrate 10, prevent leakage current and short circuit, and improve the performance and yield of the semiconductor device.

[0078] Next, please refer to Figure 4H The second layer 103 is partially etched away through the second opening 302 to form a third opening 303. Since the substrate 10 is covered by the filling layer 404 and the second protection layer 403, the substrate 10 will not be damaged during the process of forming the third opening 303.

[0079] Next, please refer to Figure 4I and Figure 3 As shown, a bitline structure 50 is formed in the third opening 303. The bitline structure 50 extends along the second direction Y and is spaced apart in both the first direction X and the third direction Z. The bitline structure 50 includes a first metal layer 501 and a second metal layer 502. Metal ions are injected into the second layer 103, where they react with silicon in the second layer 103. After annealing, a metal silicide layer, namely the second metal layer 502, is formed. Unreacted metal ions constitute the first metal layer 501. The metal ions may include one or more of titanium (Ti), cobalt (Co), nickel (Ni), and molybdenum (Mo). The metal silicide may include titanium silicide (TiSix), cobalt cobalt (CoSix), nickel silicide (NiSix), titanium nickel silicon (TiNiSix), cobalt nickel silicon (CoNiSix), molybdenum nickel silicon (MoNiSix), etc. Before forming the bitline structure 50, ion doping is performed on the second layer 103 exposed by the third opening 303 to form source and drain regions (not shown). The source and drain regions are electrically connected to the bitline structure 50.

[0080] Next, please refer to Figures 4J-4KA dielectric layer 60 is formed in the second opening 302. The dielectric layer 60 includes a first dielectric layer 601 and a second dielectric layer 602. The dielectric layer 60 fills the second opening 302 and is primarily used to isolate the bitline structure 50. The dielectric layer 60 is located on the second protective layer 403 and the filling layer 404. The contact surface between the dielectric layer 60, the filling layer 40, and the second protective layer 403 is linear. In the previous embodiment, the first dielectric layer 601 had a corner A at the top of the second protective layer 403, and the contact surface between the dielectric layer 60 and the second protective layer 403 was inverted. Compared to the previous embodiment, the contact surface between the dielectric layer 60, the filling layer 40, and the second protective layer 403 in this embodiment is linear, resulting in a smoother contact surface between the dielectric layer 60, the filling layer 40, and the second protective layer 403, and a stronger bonding force.

[0081] This embodiment forms a second protective layer 403 and optimizes the etching process so that when a portion of the second layer 103 is removed by lateral etching, the silicon substrate 10 can be protected and smaller structures can be applied. This embodiment also simplifies the process steps and reduces the overall manufacturing cost.

[0082] Figures 5A to 5C A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 5A 、 Figure 5B and Figure 5C The main difference is the depth of the filling structure 405, which will be described below respectively.

[0083] like Figures 5A to 5C The semiconductor structure shown includes: a substrate 10; a stacked structure 101, the stacked structure 101 is arranged on the substrate 10, and the stacked structure 101 is formed by alternating first layers 102 and second layers 103 in a third direction Z, wherein the third direction Z is perpendicular to the surface of the substrate 10; a first opening 301 shown by a bold dashed line, passing through the stacked structure 101 along the third direction Z and extending into the substrate 10; a filling structure 405, located in the first opening 301 and not lower than the upper surface of the substrate 10; a third opening 303 shown by a bold dashed line, formed by removing Except for a portion of the second layer 103, the bitline structure 50 is located in the third opening 303. The bitline structure 303 extends along the second direction Y and is spaced apart in the first direction X and the third direction Z. The dielectric layer 60 is located above the filling structure 405 and between adjacent bitline structures 50. The top surface of the dielectric layer 60 is flush with the top surface of the mask layer 201. The top surface of the dielectric layer 60 is flush with the top surface of the mask layer 201. The dielectric layer 60 includes a first dielectric layer 601 and a second dielectric layer 602. The filling structure 405 includes a filling layer 404 and a second protective layer 403. Figure 5AThe depth of the filling structure 405 is the second depth D2, and the depth of the first opening 301 extending to the substrate 10 is the first depth D1. The first depth D1 is equal to the second depth D2, that is, the top surface of the filling structure 405 is not lower than the upper surface S1 of the substrate 10. Figure 5B As shown, the depth of the filling structure 405 is the second depth D2, the depth of the first opening 301 extending to the substrate 10 is the first depth D1, and the second depth D2 is greater than the first depth D1, that is, the top surface of the filling structure 405 is higher than the upper surface S1 of the substrate 10, and the top surface of the filling structure 404 is flush with the top surface of the bottom first layer 102 in the stacked structure 101. Figure 5C As shown, the depth of the filling structure 405 is the second depth D2, the depth of the first opening 301 extending to the substrate 10 is the first depth D1, and the second depth D2 is greater than the first depth D1, that is, the top surface of the filling structure 405 is higher than the upper surface S1 of the substrate 10, and there is a first distance D between the bottommost first layer 102 and the second bottom first layer 102. The top surface of the filling structure 405 is located at one-third of the first distance D and is close to the bottommost first layer 102. It should be noted that the filling structure 405 can also be composed of only the filling layer 404.

[0084] Figures 6A to 6C This is a schematic diagram of a semiconductor structure provided by another embodiment of the present disclosure. Figure 6A 、 Figure 6B and Figure 6C The main difference is the depth of the filling structure 405, which will be described below respectively.

[0085] like Figures 6A to 6C The semiconductor structure shown includes: a substrate 10; a stacked structure 101 disposed on the substrate 10, the stacked structure 101 being formed by alternating first and second layers 102 and 103 in a third direction Z, the third direction Z being perpendicular to the surface of the substrate 10; a first opening 301, indicated by a bold dashed line, extending through the stacked structure 101 along the third direction Z and into the substrate 10; a filling structure 405, located in the first opening 301 and not lower than the upper surface of the substrate 10; a third opening 303, indicated by a bold dashed line, formed by removing a portion of the second layer 103; bitline structures 50, located in the third opening 303, extending along the second direction Y and spaced apart in both the first direction X and the third direction Z; and a dielectric layer 60, located above the filling structure 405 and between adjacent bitline structures 50. The top surface of the dielectric layer 60 is flush with the top surface of the mask layer 201. The dielectric layer 60 includes a first dielectric layer 601 and a second dielectric layer 602. The difference from the previous embodiment is that the filling structure 405 of this embodiment is only composed of the second protective layer 403, that is, Figures 6A-6CThe filling structure 405 is the second protective layer 403 . The dielectric layer 60 has a corner at the top of the filling structure 405 . The contact surface between the filling structure 405 and the dielectric layer 60 is inverted convex.

[0086] like Figure 6A The depth of the filling structure 405 is shown as the second depth D2, and the depth of the first opening 301 extending to the substrate 10 is the first depth D1. The first depth D1 is equal to the second depth D2, that is, the top of the filling structure 405 is not lower than the upper surface S1 of the substrate 10. As shown in the original circular dotted line, the enlarged view of the filling structure 405 and the first dielectric layer 601 is shown. From the enlarged view, it can be seen that the first dielectric layer 601 has a corner A at the top of the filling structure 405. The existence of corner A causes the second dielectric layer 602 to also have the same corner at this location. Therefore, the contact surface between the dielectric layer 60 and the filling structure 405 is finally formed into an inverted convex shape. Figure 6B As shown, the depth of the filling structure 405 is the second depth D2, and the depth of the first opening 301 extending to the substrate 10 is the first depth D1. The second depth D2 is greater than the first depth D1, that is, the top of the filling structure 405 is higher than the upper surface S1 of the substrate 10, and the top of the filling structure 404 is flush with the top surface of the bottom first layer 102 in the stacked structure 101. From the enlarged view, it can be seen that the first dielectric layer 601 has a corner A at the top of the filling structure 405, and the contact surface between the dielectric layer 60 and the filling structure 405 is an inverted convex shape. Figure 6C As shown, the depth of the filling structure 405 is the second depth D2, the depth of the first opening 301 extending to the substrate 10 is the first depth D1, the second depth D2 is greater than the first depth D1, that is, the top surface of the filling structure 405 is higher than the upper surface S1 of the substrate 10, and there is a first distance D between the bottom first layer 102 and the second bottom first layer 102, the top of the filling structure 405 is located at one-third of the first distance D and the top of the filling structure 405 is close to the bottom first layer 102.

[0087] In the semiconductor structure disclosed herein, the presence of the filling structure 405 prevents damage to the substrate 10 during the process of forming the third opening 303 by lateral etching, thereby improving the performance and yield of the semiconductor memory device.

[0088] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a laminated structure on the substrate, wherein the laminated structure is formed by alternating stacking of first and second layers in a third direction, wherein the third direction is perpendicular to the surface of the substrate; forming a first opening, wherein the first opening passes through the stacked structure along the third direction and extends into the substrate, and the depth to which the first opening extends into the substrate is a first depth; forming a first protective layer, wherein the first protective layer at least covers the sidewalls and the bottom of the first opening; forming a prefabricated filling layer in the first opening, the prefabricated filling layer at least filling the first opening, removing a portion of the prefabricated filling layer to form a filling layer, and simultaneously removing a portion of the first protective layer to form a second protective layer, wherein the second protective layer has a second depth along the sidewall of the first opening, the second depth being equal to the first depth, a top surface of the filling layer being no lower than the upper surface of the substrate, and the remaining first opening serving as a second opening; etching and removing a portion of the second layer through the second opening to form a third opening; forming a bit line structure in the third opening, wherein the bit line structure extends along the second direction and is spaced apart in the first direction and the third direction; A dielectric layer is formed, wherein the dielectric layer at least fills the second opening.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The top surface of the filling layer is flush with the top surface of the bottommost first layer in the stacked structure.

3. The method for preparing a semiconductor structure according to claim 1, wherein: There is a first distance between the bottommost first layer and the second-bottommost first layer, and the top surface of the filling layer is located at one-third of the first distance and is close to the bottommost first layer.

4. The method for preparing a semiconductor structure according to claim 1, wherein: After forming the filling layer, the method further includes: removing a portion of the first protection layer to form a second protection layer, wherein the second protection layer has a second depth along the sidewall of the first opening, and the second depth is not less than the first depth.

5. The method for preparing a semiconductor structure according to claim 4, wherein: The process of etching away a portion of the second layer to form the third opening further includes: removing the filling layer to form a fourth opening, and the second opening and the fourth opening together constitute a fifth opening.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The dielectric layer fills the fifth opening, the dielectric layer is at least located on the second protective layer, the dielectric layer has a corner on the top of the second protective layer, and the contact surface between the second protective layer and the dielectric layer is in an inverted convex shape.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The dielectric layer is at least located on the filling layer, and a contact surface between the filling layer and the dielectric layer is linear.

8. A semiconductor structure formed by the method according to any one of claims 1 to 7, characterized in that: include: substrate; a laminated structure disposed on the substrate, wherein the laminated structure is formed by alternately stacking a first layer and a second layer in a third direction, wherein the third direction is perpendicular to a surface of the substrate; a first opening passing through the laminated structure along the third direction and extending into the substrate; a filling structure, located in the first opening and not lower than the upper surface of the substrate; a third opening formed by removing a portion of the second layer; A bit line structure is located in the third opening, the bit line structure extends along the second direction and is spaced apart in the first direction and the third direction; The dielectric layer is located above the filling structure and between adjacent bit line structures.

9. The semiconductor structure according to claim 8, wherein: The filling structure includes at least a filling layer, and a top surface of the filling structure is flush with a top surface of the bottommost first layer in the stacked structure.

10. The semiconductor structure according to claim 8, wherein: The filling structure includes at least a filling layer, and there is a first distance between the bottom first layer and the second bottom first layer. The top surface of the filling structure is located at one third of the first distance and is close to the bottom first layer.

11. The semiconductor structure according to any one of claims 9 to 10, characterized in that: The dielectric layer is at least located on the filling structure, and a contact surface between the filling structure and the dielectric layer is linear.

12. The semiconductor structure according to claim 8, wherein: The filling structure includes a second protection layer. The filling structure only covers the bottom and a portion of the sidewall of the first opening. The top of the filling structure is flush with the top surface of the bottommost first layer in the stacked structure.

13. The semiconductor structure according to claim 8, wherein: The filling structure includes a second protective layer, a first distance is provided between the bottom first layer and the second bottom first layer, the top of the filling structure is located at one third of the first distance and is close to the bottom first layer.

14. The semiconductor structure according to any one of claims 12 to 13, wherein: The dielectric layer is at least located on the filling structure. The dielectric layer has a corner on the top of the filling structure. The contact surface between the filling structure and the dielectric layer is in an inverted convex shape.

Images