A multi-chip test system based on a single FPGA

Abstract

The present invention belongs to the technical field of integrated circuit testing, and particularly relates to a multi-chip testing system based on a single-chip FPGA. The programmable logic controller FPGA includes: a control core; a one-master multi-slave arbiter, the master-end input of the one-master multi-slave arbiter is connected to one of the control cores; a multi-master multi-slave arbiter, the master-end inputs of the multi-master multi-slave arbiter are respectively and correspondingly connected to the other control cores, and the slave-end outputs of the one-master multi-slave arbiter are respectively connected to the master-end inputs of the multi-master multi-slave arbiter; a control logic, the control logic is connected to the slave-end outputs of the multi-master multi-slave arbiter, and the control logic is connected to the chips under test through IO pins; an address allocation logic, the address allocation logic pre-defines a set of unique address spaces for each control core. The present invention makes full use of the parallel processing ability of the FPGA, can realize the simultaneous operation of 5 or more control cores, and can meet the requirements of high-performance testing scenarios for multiple chips under test.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit testing, and particularly relates to a multi-chip testing system based on a single FPGA. Background Art

[0002] In modern electronic design, the testing and verification of chips are crucial steps to ensure their functionality and reliability. With the rapid development of integrated circuit technology, the complexity and integration level of chips have increased rapidly. To complete the testing of chips, several testing platforms often need to be built, which affects the testing efficiency.

[0003] FPGA and SOC are two commonly used master chips during chip testing, and are also the testing platforms that need to be built to simulate the user usage scenarios during chip testing. Due to its high programmability and flexibility, FPGA has increasingly become an ideal choice for chip testing systems. By using the ARM hard core integrated inside the FPGA or the soft core synthesized from logic resources, the usage scenarios of SOC users can be conveniently simulated.

[0004] Benefiting from the parallel processing ability of FPGA, compared with SOC chips, FPGA can expand more control cores to achieve the purpose of simultaneously testing multiple chips to be tested, and can also simulate the usage scenarios of SOC users, greatly improving the testing efficiency of chips. For the functional tests of common functions such as CAN bus, UART, and video interface, the interconnection and functional tests can be completed on one testing platform. Since multiple chips to be tested are placed on the testing platform at the same time, it is extremely convenient to construct complex scenarios of the chips, greatly simplifying the construction of the testing platform.

[0005] Therefore, a highly scalable multi-chip testing system based on a single FPGA is proposed, aiming to improve the chip testing efficiency, open up multiple control cores with a single FPGA, simulate the usage scenarios of SOC and FPGA, and simultaneously build a testing platform for the functional tests of multiple chips to be tested. Summary of the Invention

[0006] The object of the present invention is to provide a multi-chip test system based on a single FPGA. The present invention makes full use of the parallel processing ability of the FPGA, can realize the simultaneous operation of 5 or more control cores, and can meet the high-performance test scenario requirements of multiple chips to be tested. At the same time, the address mapping can also be fully utilized to realize the low-performance scenario test requirements of a control core controlling multiple chips to be tested. Moreover, the test system of the present invention has the advantages of high performance, high generality and high flexibility. At the same time, in order to realize the on-chip data transmission of non-standard protocols and improve the generality and flexibility of the test system, a corresponding custom data bus transmission logic is specially designed to replace the standard protocol arbiter; or after protocol conversion, multiple control cores using non-standard protocols for data transmission are connected to the arbiter using the standard data transmission protocol.

[0007] To solve the above technical problems, the present invention provides a multi-chip test system based on a single FPGA, relying on the programmable logic controller FPGA on the test platform. The programmable logic controller FPGA includes:

[0008] Control cores, the number of which can be expanded to multiple according to the number of chips to be tested participating in the test;

[0009] A master-slave arbiter, the master input terminal of which is connected to one of the control cores;

[0010] A multi-master multi-slave arbiter, the master input terminals of which are respectively connected to the other control cores in one-to-one correspondence, and the slave output terminals of the master-slave arbiter are respectively connected to the master input terminals of the multi-master multi-slave arbiter;

[0011] Control logic, which is connected to the slave output terminals of the multi-master multi-slave arbiter, and the control logic is connected to the chips to be tested through IO pins;

[0012] Address allocation logic, which predefines a set of unique address spaces for each control core; multiple control cores are routed through the master-slave arbiter and multiple multi-master multi-slave arbiters, so that the control cores can access the specified address spaces.

[0013] Preferably, when the control core adopts a non-standard data transmission protocol, it further includes a custom data bus transmission logic for data transmission of the non-standard data transmission protocol;

[0014] Wherein the custom data bus transmission logic includes:

[0015] The request generation module receives the control signal start_req from the control core to enable the channel, and generates data request signals rd_req and wr_req based on the status of the read channel buffer and the write channel buffer;

[0016] The channel arbitration module uses read arbitration and write arbitration to output the arbitration result, and realizes read data strobe and write data strobe according to the port address range set by the address allocation logic; and the read arbitration and the write arbitration are independent of each other, supporting full-duplex transmission of the read and write channels.

[0017] Preferably, data is transmitted between the control core and the control logic through the non-standard data transmission protocol.

[0018] Preferably, the custom data bus transmission logic further includes a protocol conversion module to realize signal data conversion from the non-standard data transmission protocol to the standard data transmission protocol;

[0019] The protocol conversion module includes a plurality of independent protocol conversion channels, and the protocol conversion channel includes a read data channel rd_in_data, a write data channel wr_out_data, and a conversion interface axi_master for initiating a data transmission request.

[0020] Preferably, the protocol conversion module can access the master-end input of the multi-master multi-slave arbiter and the master-end input of the one-master multi-slave arbiter through the conversion interface axi_master.

[0021] Preferably, the implementation type of the control core includes any one or several of ARM hard core, soft core, and RTL code, and the number and implementation type of the control core can be flexibly expanded, and the number of the control cores participating in the test can be selectively accessed according to needs during the operation and test phase.

[0022] Preferably, when the control core uses an ARM hard core and a soft core, it is loaded through a user program written in the corresponding language; when the control core uses RTL code, it is loaded through the BIT file of the programmable logic controller FPGA.

[0023] Preferably, when using the standard data transmission protocol, the arbitration modes of the one-master multi-slave arbiter and the multi-master multi-slave arbiter include polling, read priority, and write priority arbitration modes.

[0024] Preferably, the control logic serves as the destination node for data routing of the control core, and the control logic includes logic codes for data encoding and decoding and peripheral circuits required for the normal operation of the chip under test; and multiple control logics can realize the test of the same function of multiple chips under test and the simultaneous test of different functions to be measured of multiple chips under test.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The present invention supports flexible expansion of the number and type of control cores, and specifies the control cores participating in the test during the operation and test phase, without the need to build the hardware platform of the test platform multiple times, eliminating the software code modification work caused by the change of the hardware platform.

[0027] 2. The present invention supports data transmission using a non-standard data transmission protocol. The designed custom data bus transmission logic can replace the arbitration logic of the general standard bus transmission, or convert the non-standard bus to a standard bus transmission and then connect it to the test platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of an embodiment of a multi-chip test system based on a single FPGA provided by the present invention.

[0029] Figure 2 It is a schematic diagram of the address allocation table of multiple control cores provided by the present invention.

[0030] Figure 3 It is a schematic diagram of another embodiment provided by the present invention in which there are multiple control cores and the control cores simultaneously use standard and non-standard data bus transmission protocols for data transmission.

[0031] Figure 4 It is a schematic diagram of the working principle of the custom data bus transmission logic provided by the present invention.

[0032] Figure 5 It is a schematic diagram of the working principle of the request generation module generating data requests in the custom data bus transmission logic provided by the present invention.

[0033] Figure 6 It is a schematic diagram of the working principle of the channel arbitration module in the custom data bus transmission logic provided by the present invention.

[0034] Figure 7 It is a schematic diagram of the working principle of the protocol conversion module in the custom data bus transmission logic provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. Embodiment

[0036] As Figure 1And Figure 2 As shown in Figure 2 , when using the standard data transfer protocol, an embodiment of the present invention provides a multi-chip test system based on a single FPGA, relying on the programmable logic controller FPGA on the test platform. The programmable logic controller FPGA includes:

[0037] A control core for running typical scenarios for implementing functional tests of the chips under test; the number of control cores can be flexibly expanded according to the number of chips under test participating in the test;

[0038] A one-master multi-slave arbiter for a test scenario where one control core controls multiple chips under test and corresponding to low real-time requirements. The master input terminal of the one-master multi-slave arbiter is connected to one of the control cores; address access to multiple control logics is realized through the one-master multi-slave arbiter;

[0039] A multi-master multi-slave arbiter, the master input terminals of the multi-master multi-slave arbiter are respectively connected to the other control cores in one-to-one correspondence, and the slave output terminals of the one-master multi-slave arbiter are respectively connected to the master input terminals of the multi-master multi-slave arbiter;

[0040] Control logic for realizing the drive from the on-chip bus to the IO pins, which is determined according to the different functions to be realized by the chips under test; the control logic is connected to the slave output terminals of the multi-master multi-slave arbiter, and the control logic is connected to the chips under test through the IO pins to complete the conversion from the on-chip bus address to the actual physical address.

[0041] Address allocation logic for address allocation to ensure the data path from the master end to the slave end and correct address mapping; the address allocation logic pre-defines a set of unique address spaces for each control core to ensure that different control cores do not have address conflicts; multiple control cores are routed through the one-master multi-slave arbiter and multiple multi-master multi-slave arbiters, enabling the control cores to access the specified address spaces. That is, the control core generates a data request, and through the use of the one-master multi-slave arbiter and multiple multi-master multi-slave arbiters for request arbitration, the request with the arbitration priority is forwarded to the target slave end to realize address access to the specified address space, as Figure 2 shown, control core 5 can access all slave addresses, and control cores 1-4 can access some slave addresses. Moreover, when the one-master multi-slave arbiter and the multi-master multi-slave arbiter adopt the standard data transfer protocol AXI bus, multiple arbitration priority settings can be realized.

[0042] Furthermore, when using the standard data transfer protocol, the arbitration modes of the one-master multi-slave arbiter and the multi-master multi-slave arbiter include polling, read priority, and write priority arbitration modes.

[0043] Further, the control logic serves as the destination node for data routing of the control core. The control logic includes logic codes for data encoding and decoding and peripheral circuits required for the normal operation of the chip under test. As Figure 3 shown in the functional interface, it can be used for different functional pins of the same chip under test or for different functional pins of multiple chips under test, and can be flexibly bound according to actual needs. That is, multiple control logics can implement the test of the same function of multiple chips under test and the simultaneous test of different functions to be tested of multiple chips under test. Embodiment

[0044] As Figures 3 to 7 shown, when the control core adopts a non-standard data transmission protocol, to ensure the normal operation of the test system, on the basis of the above Embodiment 1, a custom data bus transmission logic is further included for data transmission of the non-standard data transmission protocol;

[0045] wherein the custom data bus transmission logic includes:

[0046] A request generation module that receives a control signal start_req from the control core to enable the channel, and generates data request signals rd_req and wr_req according to the states of the read channel buffer and the write channel buffer; As Figure 5 shown, in this embodiment, the control cores 1 to 3 respectively generate 3 read requests and 3 write requests;

[0047] A channel arbitration module that uses read arbitration and write arbitration to output arbitration results, and realizes read data gating and write data gating according to the port address range set by the address allocation logic; And the read arbitration and the write arbitration are independent of each other, supporting full-duplex transmission of the read and write channels. As Figure 6 shown, in this embodiment, 3 read requests and 3 write requests participate in arbitration, and according to the arbitration results, 3 read data and 3 write data are gated. The address allocation logic pre-sets the address ranges that can be accessed by each port of the read data channel and the write data channel.

[0048] Data is transmitted between the control core and the control logic through the non-standard data transmission protocol. That is, the control cores 1 to 3 adopt the non-standard data transmission protocol, and the custom bus transmission logic uses the request generation module and the channel arbitration module to replace the one-master multi-slave arbiter and the multi-master multi-slave arbiter to realize data adjustment between multiple control cores.

[0049] Further, the custom data bus transmission logic further includes an optional protocol conversion module to realize signal data conversion from the non-standard data transmission protocol to the standard data transmission protocol; As Figure 7Among them, the protocol conversion module includes a plurality of independent protocol conversion channels. The protocol conversion channels include a read data channel rd_in_data, a write data channel wr_out_data, and a conversion interface axi_master for initiating a data transmission request. Each data port includes two paths of read data and write data, and each protocol conversion channel is independent of each other, enabling full-duplex operation of reading and writing data.

[0050] Furthermore, the protocol conversion module can access the master input end of the multi-master multi-slave arbiter and the master input end of the one-master multi-slave arbiter through the conversion interface axi_master. Through the above-mentioned optional protocol conversion module, the control cores 1 to 3 with non-standard interfaces can be seamlessly connected to the multi-master multi-slave arbiter and the one-master multi-slave arbiter ( Figure 3 Only one case of accessing the multi-master multi-slave arbiter is shown).

[0051] The implementation types of the control core include any one or several of ARM hard cores, soft cores, and RTL codes. Moreover, the number and implementation types of the control cores can be flexibly expanded, and the number of control cores participating in the test can be selectively accessed according to needs during the operation and test phase.

[0052] When the control core uses an ARM hard core and a soft core, it is loaded through a user program written in the corresponding language; when the control core uses RTL code, it is loaded through the BIT file of the programmable logic controller FPGA.

[0053] Specifically, as Figure 3 shown, in this embodiment, for the implementation types of 5 control cores, control cores 1 to 3 are written in RTL code and use a non-standard bus transmission protocol for data transmission; control core 4 is implemented with a soft core and uses the standard data transmission protocol AXI bus; control core 5 is implemented with a higher-performance ARM hard core and is used to implement a control core 5 accessing multiple chips under test simultaneously. Control core 5 also uses the standard data transmission protocol AXI bus for data transmission.

[0054] Moreover, to further illustrate the advantages of the present invention, a brief description of the following usage scenarios is provided:

[0055] Scenario 1: Implementation of a multi-core multi-chip test system based on C code (selective access):

[0056] When writing a test program in C / C++ code for a scenario, an FPGA with an ARM core or an FPGA without an ARM core can be selected. The former usually has one or two control cores. The IO performance is usually the bottleneck of the test system. Therefore, when there are multiple chips under test, the number of control cores can be increased by instantiating the MicroBlaze soft core with FPGA resources to improve the peak performance of functional testing.

[0057] When running the test code, using the above multi-chip test system, several of the multiple control cores can be selectively accessed as needed to achieve specific test purposes and test performance, without repeatedly compiling the hardware code project of the test system, saving a large amount of test time.

[0058] When implementing a multi-chip test system in the above manner, it is recommended to use the AXI bus for in-chip data transmission and finally implement the conversion from the AXI interface to the driving timing in the control logic module.

[0059] Scenario 2: Implementation of a multi-core multi-chip test system based on RTL code (image processing):

[0060] This typical scenario is the implementation of a multi-core multi-chip test system based on RTL code. Digital images usually have standard line and field synchronization signals. When the chip under test is a storage chip, using the test system of the present invention, it is convenient to implement data writing, reading, and data arbitration for multiplexed storage through expansion.

[0061] In this scenario, there is no need for a standard data transmission bus. The data transmitted can be further extended to the implementation of high-speed AD / DA data transmission, and the code is implemented through RTL code, which is suitable for scenarios with high requirements for transmission performance.

[0062] Scenario 3: Random number testing in the data interaction of a multi-core multi-chip test system (within the same in-chip system, data is mutually visible):

[0063] In the design stage of a chip, the general verification methodology (UVM) usually uses a scoreboard to compare the expected value and the actual value of the chip under test to verify the correctness of the function of the chip under test. During pure software simulation verification, random data can be recorded by the system, so relevant verification can be achieved. In the actual test of the chip under test, the test platforms are independent of each other, and one platform cannot obtain the random data sent by another platform in real time and conveniently.

[0064] Using the multi-chip test system of the present invention, a single FPGA is used to control the chips under test with multiple cores, and the data between each control core is visible, which greatly facilitates the implementation of random test cases on the chips under test and helps improve the reliability of functional testing.

[0065] Specifically, when implemented in the form of C / C++ code among multiple control cores, MAILBOX can be used to notify other control cores of the expected values; when implemented in RTL code, a simple FIFO cache mechanism can be used to achieve data sharing among control cores.

[0066] In summary, for the test system of the present invention, when developing with ARM hard cores and soft cores, the hardware part of the project does not need to be modified anymore. During testing, only the loaded test program needs to be changed, which can save a large amount of software compilation time. When implementing functions with RTL code, the parallel operation characteristics of the FPGA can be fully utilized to easily achieve the interactive transmission of a large amount of data. When developing with soft cores, the number of control cores that can be extended is much larger than that of ARM hard cores, and they can be used in combination with ARM hard cores and RTL logic, with the data throughput doubling geometrically. The test system can use the standard AXI bus for data transmission. At the same time, it is not limited to the standard on-chip interconnection bus transmission protocol, and a custom data transmission protocol can also be used, which has wide applications in scenarios with obvious driving timings such as image processing.

[0067] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A multi-chip test system based on a single FPGA, relying on the programmable logic controller FPGA on the test platform, characterized in that, The programmable logic controller FPGA includes: A control core, the number of which can be expanded to multiple according to the number of chips under test participating in the test; A one-master multi-slave arbiter, the master input terminal of which is connected to one of the control cores; A multi-master multi-slave arbiter, the master input terminals of which are respectively connected to the other control cores in a one-to-one correspondence, and the slave output terminals of the one-master multi-slave arbiter are respectively connected to the master input terminals of the multi-master multi-slave arbiter; Control logic, which is connected to the slave output terminals of the multi-master multi-slave arbiter, and the control logic is connected to the chips under test through IO pins; An address allocation logic, which pre-defines a unique address space for each of the control cores; multiple control cores are routed through the one-master multi-slave arbiter and multiple multi-master multi-slave arbiters, enabling the control cores to access the specified address space.

2. The multi-chip test system based on a single FPGA as claimed in claim 1, wherein, When the control core adopts a non-standard data transmission protocol, it further includes a custom data bus transmission logic for data transmission of the non-standard data transmission protocol; Wherein the custom data bus transmission logic includes: A request generation module, which receives a control signal start_req from the control core to enable the channel, and generates data request signals rd_req and wr_req according to the states of the read channel cache and the write channel cache; A channel arbitration module, which outputs arbitration results by adopting read arbitration and write arbitration, and realizes read data gating and write data gating according to the port address range set by the address allocation logic; and the read arbitration and the write arbitration are independent of each other, supporting full-duplex transmission of the read and write channels.

3. The multi-chip test system based on a single FPGA according to claim 2, characterized in that Data is transmitted between the control core and the control logic through the non-standard data transmission protocol.

4. A multi-chip test system based on a single FPGA as described in claim 2, characterized in that, The custom data bus transmission logic further includes a protocol conversion module to realize signal data conversion from the non-standard data transmission protocol to the standard data transmission protocol; Wherein the protocol conversion module includes a plurality of independent protocol conversion channels, and the protocol conversion channels include a read data channel rd_in_data, a write data channel wr_out_data, and a conversion interface axi_master for initiating a data transmission request.

5. The multi-chip test system based on a single FPGA according to claim 4, characterized in that, The protocol conversion module can be connected to the master input terminals of the multi-master multi-slave arbiter and the master input terminal of the one-master multi-slave arbiter through the conversion interface axi_master.

6. The multi-chip test system based on a single FPGA according to claim 1, characterized in that, The implementation types of the control core include any one or several of ARM hard cores, soft cores, and RTL codes, and the number and implementation types of the control cores can be flexibly expanded, and the number of the control cores participating in the test can be selectively connected according to needs during the running test stage.

7. A multi-chip test system based on a single FPGA as claimed in claim 6, wherein, When the control core uses an ARM hard core and a soft core, it is loaded through a user program written in the corresponding language; when the control core uses RTL code, it is loaded through the BIT file of the programmable logic controller FPGA.

8. The multi-chip test system based on a single FPGA according to claim 1, characterized in that, When using a standard data transmission protocol, the arbitration modes of the one-master-multi-slave arbiter and the multi-master-multi-slave arbiter include polling, read priority, and write priority arbitration modes.

9. A multi-chip test system based on a single FPGA according to any one of claims 1 to 8, characterized in that The control logic serves as the destination node for data routing of the control core. The control logic includes logic codes for data encoding and decoding and peripheral circuits required to enable the normal operation of the chip under test. Moreover, multiple control logics can implement the testing of the same function of multiple chips under test and the simultaneous testing of different functions to be tested of multiple chips under test.

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