Chip layout double-step lithography hotspot detection method and system based on deep learning

Abstract

The present application provides a method and system for double-step lithography hotspot detection of chip layout based on deep learning, which belongs to the field of semiconductor design and verification. The method includes: using a defect feature extraction model and a layout classification model to perform lithography hotspot detection on the layout to be detected; the model training method is: constructing a layout data set with classification labels and its corresponding defect marking data set; training a defect feature extraction model based on the layout and its corresponding pre-processed defect marking to identify the lithography hotspot distribution pattern and generate a defect position feature map; combining the defect position feature map, the chip layout and the effective area feature map to obtain a combined feature; using the classification label of the layout data as the learning target of the layout classification model, and using the combined feature as the input of the layout classification model to complete the training of the layout classification model. The present application solves the problem that the interpretability results of the lithography hotspot detection model based on a deep neural network are quite different from the actual lithography defect area.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor design, and more specifically, to a method and system for detecting hotspots in double-step lithography of chip layout based on deep learning. Background Art

[0002] As the size of manufacturing processes shrinks, the sensitivity of certain special distribution patterns in chip layouts to factors such as optical diffraction increases dramatically, which can easily cause faults such as short circuits or open circuits during the manufacturing process, leading to tape-out failures or reduced product yields. Therefore, it has become a necessary step in advanced manufacturing processes to detect and correct these hotspot distribution patterns in the layout that are prone to defects during the design phase.

[0003] The prior art proposes various lithography hotspot detection methods, including: methods based on lithography simulation, methods based on pattern matching, methods based on machine learning, and methods based on deep learning. The method based on lithography simulation uses physical and mathematical models of the manufacturing process to simulate the manufacturing results and locate the hotspots. Because the consistency between the lithography simulation and the manufacturing process is high, this method has high accuracy, but because the simulation process is very time-consuming, it is difficult to meet the cycle requirements of product iteration as the complexity of the chip layout increases sharply. The pattern matching method provides a faster hotspot detection speed, but its limitation is that it can only identify the recorded hotspot distribution pattern and has no recognition ability for the unrecorded hotspot pattern. The method based on machine learning has a certain generalization ability, but it is heavily dependent on the effect of artificially designed feature extraction, and it is easy to lose key features, so the detection accuracy is low and the false alarm rate is often high. The method based on deep learning can learn to automatically extract features with discrimination through end-to-end training and has a stronger generalization ability, so it can provide high detection accuracy. However, these automatically learned features are learned on the training set, which means that these features may only have good discrimination for data under this distribution, but have nothing to do with the actual hotspot distribution pattern. In addition, this inconsistency of features leads to a large difference between the explanation provided by the model and the principle of lithography hotspot detection, making it difficult for users to judge the rationality of the prediction results. Summary of the invention

[0004] In response to the defects of the prior art, the purpose of this application is to provide a chip layout two-step lithography hotspot detection method and system based on deep learning, aiming to solve the problem that the explanation provided by the model based on deep learning in the lithography hotspot detection method is quite different from the principle of lithography hotspot detection, resulting in the inability to judge the rationality of the prediction results.

[0005] To achieve the above objectives, in the first aspect, the present application provides a two-step interpretable lithography hotspot detection method based on deep learning, specifically: using a trained defect feature extraction model and a layout classification model to perform lithography hotspot detection on a chip layout to be inspected;

[0006] Among them, the training methods of the defect feature extraction model and the layout classification model are:

[0007] S1: According to the chip layout defect position obtained by lithography simulation, the original defect mark is searched and preprocessed to build a defect mark data set; at the same time, the original defect mark is detected using the effective area window, and the layout classification label is generated to build a layout data set with classification labels; wherein the classification label includes hotspot or non-hotspot;

[0008] S2: Input the chip layout and its corresponding defect marking data set into the defect location feature extraction model for training, identify the hot spot distribution pattern of the layout, and generate a defect location feature map;

[0009] S3: combining the defect location feature map, the chip layout and the effective area feature map to obtain a combined feature;

[0010] S4: Use the classification label of the chip layout as the learning target of the layout classification model, and use the combined features as the input of the layout classification model to complete the training of the layout classification model.

[0011] Further preferably, S1 specifically comprises the following steps:

[0012] Perform lithography simulation and defect detection on chip layout, and mark the defect locations with original defects;

[0013] Calculate the minimum circumscribed circle for each original defect mark, and replace the original defect mark with the minimum circumscribed circle;

[0014] For each replaced circular defect mark, the radius is divided into three regions with three equal parts as the boundary. The three divided regions are filled with different intensity values ​​from the center of the circle outward in turn to generate the preprocessed defect mark and construct the defect mark data set.

[0015] Use the effective area window for detection and calculate the overlap area ratio between the original defect mark and the effective area window. If the overlap area ratio exceeds the preset threshold, the layout classification label is set as a hotspot, otherwise it is set as a non-hotspot, and a layout dataset with classification labels is constructed.

[0016] Further preferably, S2 specifically includes the following steps:

[0017] The defect location feature extraction model is trained based on the layout dataset with classification labels and its corresponding defect marking dataset to learn the correspondence between the local distribution pattern of the layout and the defect location, identify the hot spot distribution pattern in the layout and generate error marks at the defect location;

[0018] The root mean square error between the generated error mark and the preprocessed defect mark is used as the cost function, and the defect location feature extraction model is iteratively optimized using the back propagation algorithm;

[0019] The trained defect location feature extraction model takes the chip layout to be inspected as input and the defect location feature map as output.

[0020] Further preferably, S4 specifically includes the following steps:

[0021] The combined features are encoded in turn through the convolutional layers of the layout classification model, and after the pooling layer, they are passed through the first fully connected layer and the second fully connected layer to output the predicted probability of each category;

[0022] The cross entropy loss between the one-hot code of the classification label and the predicted probability of each category is used as the cost function, and the layout classification model is iteratively updated through back propagation;

[0023] Among them, the trained layout classification model uses the combined features for forward calculation and outputs the category with the highest prediction probability.

[0024] Further preferably, the chip layout double-step lithography hotspot detection method based on deep learning also includes interpretability analysis of the trained defect position feature extraction model and layout classification model, specifically including the following steps:

[0025] S5.1: Extract each feature map in the defect location feature extraction model and the layout classification model as a mask, and perform point-to-point multiplication with the chip layout after upsampling;

[0026] S5.2: The point-to-point multiplication results obtained from each feature map are sequentially combined with the defect location feature map and the effective area map to form a combined feature, and the predicted probability of the hotspot category is obtained through the layout classification model;

[0027] S5.3: Calculate the difference between the predicted probability obtained in S5.2 and the predicted probability obtained by taking the chip layout as input as the weight of the feature map;

[0028] S5.4: Perform a weighted summation on all feature maps to obtain an explanation of the predicted classification result; wherein the explanation of the predicted classification result is the explanation of the classification result predicted by inputting the chip layout into the trained defect location feature extraction model and layout classification model.

[0029] In the second aspect, the present application provides a chip layout dual-step lithography hotspot detection system based on deep learning, which performs lithography hotspot detection on the chip layout to be detected, including: a defect feature extraction module and a layout classification model;

[0030] The defect feature extraction module includes: a first data set construction submodule and a first model training submodule;

[0031] The first data set construction submodule is used to obtain original defect marks according to chip layout defect positions obtained by lithography simulation and perform preprocessing to generate preprocessed defect marks, and construct a preprocessed defect mark data set;

[0032] The first model training submodule is used to train the defect location feature extraction model, and the training is based on the chip layout and its corresponding defect labeling data set to identify the hot spot distribution pattern of the layout and generate a defect location feature map;

[0033] The layout classification model includes: a feature combination submodule, a second data set construction submodule and a second model training submodule;

[0034] The feature combination submodule is used to combine the defect position feature map, the chip layout and the effective area feature map to obtain a combined feature;

[0035] The second data set construction submodule is used to detect the original defect marks obtained by the lithography simulation using the effective area window, classify the chip layout, and construct a layout data set with classification labels; wherein the classification labels include hot spots or non-hot spots;

[0036] The second model training submodule is used to use the classification label of the layout data as the learning target of the layout classification model and the combined features as the input of the layout classification model to complete the training of the layout classification model.

[0037] Further preferably, the first model training submodule includes: a first model training unit, an error label generation unit and a first model optimization unit;

[0038] The first model training unit is used to train the defect location feature extraction model according to the chip layout and its corresponding defect marking data set;

[0039] The error mark generation unit is used to identify the hotspot distribution pattern in the layout and generate an error mark at the defect position according to the correspondence between the local distribution pattern of the layout and the defect position learned in the process of training the defect position feature extraction model;

[0040] The first model optimization unit is used to use the root mean square error between the generated error mark and the preprocessed defect mark as a cost function, and use the back propagation algorithm to iteratively optimize the defect position feature extraction model;

[0041] Among them, the trained defect location feature extraction model takes the chip layout to be detected as input and the defect location feature map as output.

[0042] Further preferably, the second model training submodule comprises: a category prediction unit and a second model optimization unit;

[0043] The category prediction unit is used to encode the combined features in sequence through the convolutional layers of the layout classification model, expand them through the pooling layer, pass them through the first fully connected layer and the second fully connected layer, and output the predicted probability of each category;

[0044] The second model optimization unit is used to use the cross entropy loss of the one-hot code of the classification label and the predicted probability of each category as a cost function, and iteratively update the layout classification model through back propagation;

[0045] Among them, the trained layout classification model uses the combined features for forward calculation and outputs the category with the highest prediction probability.

[0046] Further preferably, the first data set construction submodule includes: a defect mark acquisition unit, a defect mark conversion unit and a defect intensity filling unit;

[0047] The defect mark acquisition unit is used to perform lithography simulation and defect detection on the chip layout and to perform original defect marks on the defect positions;

[0048] The defect mark conversion unit is used to calculate the minimum circumscribed circle of the polygon of each original defect mark, and replace the original defect mark with the circumscribed circle;

[0049] The defect intensity filling unit is used to divide each replaced circular defect mark into three areas with the radius trisection position as the boundary, and fill the three divided areas with different intensity values ​​from the center of the circle outward in turn to generate a preprocessed defect mark and construct a defect mark data set.

[0050] Further preferably, the chip layout double-step lithography hotspot detection system further includes an interpretability analysis module, which includes:

[0051] A mask processing unit is used to extract each feature map in the defect position feature extraction model and the layout classification model as a mask, and perform point-to-point multiplication with the chip layout after upsampling;

[0052] The explainability category prediction unit is used to combine the point-to-point multiplication results of each feature map with the defect location feature map and the effective area map in sequence to form a combined feature, and obtain the prediction probability of the hotspot category through the layout classification model;

[0053] A feature value weight calculation unit, used to use the difference between the prediction probability obtained by the interpretability category prediction unit and the prediction probability obtained by taking the chip layout as input as the weight of the feature map;

[0054] An interpretable result acquisition unit is used to perform weighted summation on all feature maps to obtain an explanation of the predicted classification result; wherein the explanation of the predicted classification result is the explanation of the classification result predicted by inputting the chip layout into the trained defect location feature extraction model and layout classification model.

[0055] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0056] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0057] In a fifth aspect, the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0058] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0059] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0060] The present application provides a two-step lithography hotspot detection method for chip layout based on deep learning. In the first stage, a feature extractor extracts features in the layout and predicts potential hotspot locations, so that the feature extraction in the first stage can focus on the recognition of hotspot distribution patterns, thereby enabling the model to extract features consistent with the lithography hotspot detection principle for back-end layout classification, overcoming the problems of low detection accuracy, high false alarm rate and inconsistency between model interpretation results and hotspot detection principles caused by existing hotspot detection models based on deep learning using features unrelated to hotspots for classification.

[0061] The present application provides a method for detecting hotspots in a chip layout using two-step lithography based on deep learning. After the defect position feature extraction in the first stage is completed, the extracted defect position feature map is combined with the layout and the effective area map as features for the second stage layout classification to overcome the problem of noise or loss of key distribution information in the defect position features. At the same time, the effective area window range is used as an explicit feature to simplify the hotspot detection task.

[0062] The present application provides a dual-step lithography hotspot detection method for chip layout based on deep learning. After executing layout classification to obtain the hotspot detection result of the layout, each feature map in the defect position feature extraction model and the layout classification model is extracted as a mask, and after upsampling, point-to-point multiplication is performed with the chip layout respectively; the point-to-point multiplication result obtained from each feature map is sequentially combined with the defect position feature map and the effective area map to form a combined feature, and the predicted probability of the hotspot category is obtained through the layout classification model; the difference between the predicted probability and the predicted probability of the original layout is used as the weight of the feature map; all the feature maps are weighted and summed to obtain the classification interpretation result; according to the classification interpretation result, it can be judged whether the prediction of the model conforms to the physical rules of hotspot detection, and lithography simulation is performed on a small number of layouts whose prediction results and interpretation results are inconsistent, so as to avoid the omission of hotspots caused by model errors, and then cause huge losses caused by tape-out failure or low product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 It is the design layout of the chip to be detected and the corresponding defect schematic diagram provided in the embodiment of the present application;

[0064] Figure 2 It is a flow chart of a chip layout double-step lithography hotspot detection method based on deep learning provided in an embodiment of the present application;

[0065] Figure 3 is a hotspot detection flow chart of the model provided in the embodiment of the present application;

[0066] Figure 4 It is a schematic diagram of the network structure provided by the embodiment of the present application;

[0067] Figure 5 It is the classification interpretation result provided by the embodiment of the present application;

[0068] Figure 6 is a flow chart for obtaining a training data set provided in an embodiment of the present application;

[0069] FIG. 7( a ) is a diagram showing the effect of defect location extraction after the first-stage defect location feature extractor provided in an embodiment of the present application is trained on the error mark before preprocessing;

[0070] FIG. 7( b ) is a diagram showing the effect of defect position extraction after the first-stage defect position feature extractor provided in an embodiment of the present application is trained on the preprocessed error marks;

[0071] Figure 8 It is the confusion matrix of the hotspot detection accuracy of the model provided in the embodiment of the present application. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0073] The terms “first”, “second” and the like in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects.

[0074] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0075] In the description of the embodiments of the present application, unless otherwise specified, “plurality” means two or more than two.

[0076] like Figure 1 The design layout of the chip to be tested shown includes various designed distribution patterns. Because some distribution patterns are sensitive to optical diffraction, defects are easily generated in these distribution patterns. The actual lithography manufacturing layout often differs from the designed layout and causes defects. The existing hotspot detection method based on deep learning uses an automatic learning feature extraction method to extract features unrelated to hotspot detection from the layout for classification, resulting in low actual test accuracy and high false alarm rate despite good training results; in addition, because the deep learning-based method cannot provide an accurate explanation of the prediction results, it is impossible to determine whether the prediction results are correct, so the errors of the model cannot be discovered, resulting in huge losses; the algorithm proposed in this application proposes a lithography hotspot detection model for this application scenario that can extract defect locations as features to realize hotspot detection in the chip design stage, and provide an explanation that conforms to the physical principles of hotspot detection, thereby avoiding tape-out failures and improving product yields.

[0077] The technical features of this application are described in more detail below.

[0078] The present application provides a deep learning-based two-step interpretable lithography hotspot detection method and system based on defect location features, aiming to solve the problems of poor performance, inaccurate use of features and poor interpretability of existing lithography hotspot detection methods.

[0079] First, as Figure 2 Shown and Figure 3 As shown, the deep learning-based chip layout double-step lithography hotspot detection method based on defect position features provided in the present application includes the following steps:

[0080] S1: Obtain chip design layout and perform lithography simulation;

[0081] S2: Locate the defect position according to the simulation results and generate a preprocessed defect mark, determine the preprocessed defect mark as the center of the polygonal circumscribed circle and replace the original defect mark with a circle of uniform size, and use the pixel value that decays from the inside to the outside to represent the regional importance of the defect mark;

[0082] S3: Use the preprocessed defect marks as labels to construct a "layout-defect location mark" dataset; divide the dataset into a training set and a test set;

[0083] S4: Build the first-stage defect location feature extraction model and use the “layout-defect location marking” dataset to train and test the model;

[0084] Among them, Figure 4 As shown, the first stage defect position feature extraction model includes: a first convolution block, a second convolution block, a third convolution block, a fourth convolution block, a fifth convolution block, a first full convolution layer, a second full convolution layer, a first upsampling layer, a second upsampling layer, a third upsampling layer and a third full convolution layer in sequence;

[0085] The structure of the first convolution block and the second convolution block is convolution layer-convolution layer-maximum pooling layer; the structure of the third convolution block, the fourth convolution block and the fifth convolution block is convolution layer-convolution layer-convolution layer-maximum pooling layer; the first upsampling layer and the second upsampling layer use the output of the third convolution block and the fourth convolution block as input respectively; the third upsampling layer uses the output of the second full convolution layer, the first upsampling layer and the second upsampling layer as input;

[0086] It should be pointed out here that Figure 4 This is a special case of the defect location feature extraction model. Other convolutional networks can also be applied and are not limited to this application. Figure 4 The only publicly available convolutional network structure;

[0087] S5: using the defect location feature map extracted in the first stage, the original chip layout and the effective area map to obtain the combined features;

[0088] S6: using the effective area window to detect the original defect mark, and labeling the chip design layout, wherein the label content is a hot spot or a non-hot spot;

[0089] S7: Use the above labels to construct a "landscape-classification label" dataset, and divide the dataset into a training set and a test set;

[0090] S8: Build the second-stage layout classification model and use the "layout-classification label" dataset for training and testing;

[0091] Among them, the second stage layout classification model includes a first convolution layer, a first maximum pooling layer, a second convolution layer, a second maximum pooling layer, a third convolution layer, a third maximum pooling layer, a first fully connected layer and a second fully connected layer arranged in sequence;

[0092] The structure of the layout classification model here is not limited to the structure provided in this application, and different structures can be selected according to actual needs;

[0093] S9: Use the trained first-stage defect feature extraction model and the second-stage layout classification model to detect the layout to be inspected;

[0094] S10: Use the model interpreter to obtain the model's explanation of the hotspot detection results;

[0095] Among them, Figure 5 As shown in the figure, the implementation process of the model interpreter is as follows: extract each feature map in the defect location feature extraction model and the layout classification model as a mask, and perform point-to-point multiplication with the chip layout after upsampling; combine the point-to-point multiplication results of each feature map with the defect location feature map and the effective area map in turn to form a combined feature, and obtain the predicted probability of the hotspot category through the layout classification model; use the difference between the predicted probability and the predicted probability of the original layout as the weight of the feature map, and perform weighted summation on all feature maps to obtain the classified interpretation result.

[0096] Example 1

[0097] 1. Dataset

[0098] like Figure 6 As shown, for a complete or partial chip design layout, its interior is composed of multiple polygons, which represent the spatial information of the distribution of metal layers, etc. in the layout. Step 1.1 of this application is to construct a data set using the collected layout;

[0099] The data set construction process of this embodiment includes the following steps:

[0100] Performing lithography simulation on the collected design layouts to generate simulated manufacturing layouts;

[0101] Conduct defect detection on the simulated manufacturing layout and mark the defect locations;

[0102] Preprocess the defect mark pattern to construct a "layout-defect position mark", obtain the layout classification label to construct a "layout-classification label" data set; layout classification includes hotspot layout and non-hotspot layout; when there is a defect in the effective area of ​​the layout, it is determined that there is a hotspot in the layout;

[0103] Step 1.2 The pretreatment process specifically includes the following steps:

[0104] For each defect mark, calculate the minimum circumscribed circle of its polygon;

[0105] Replace the original defect mark polygon with a circle, with the center of the smallest circumscribed circle as the center and one-tenth of the side length of the layout as the radius, so that all defect marks are of the same size;

[0106] For each replaced circular defect mark, divide it into three areas with the radius divided into three equal parts as the boundary;

[0107] For the three divided areas, fill in values ​​of different strengths from the center of the circle to the outside to indicate the importance of different areas from the inside to the outside, and generate pre-processed defect marks; for example, fill in values ​​of 255, 255*(2 / 3), and 255*(1 / 3) strengths from the center of the circle to the outside to indicate the importance of different areas from the inside to the outside;

[0108] Step 1.3 The process of obtaining the layout classification label includes the following steps:

[0109] Use the effective area window for detection and calculate the overlap ratio between the original defect mark and the effective area window;

[0110] If the overlap area exceeds 30%, the layout classification label is set to "hotspot", otherwise it is set to "non-hotspot";

[0111] Step 1.4 divides the data set into training set and test set;

[0112] 2. Defect feature extraction

[0113] Build as Figure 3The first stage defect location feature extraction model is shown, and the "layout-defect location mark" data set is used for training and testing; in the defect feature extraction model training stage, the layout does not distinguish between hot spots and non-hot spots, and the model learns the correspondence between the local distribution pattern of the layout and the defect location, so that it can identify the hot spot distribution pattern in the layout and generate error marks at the defect location; the root mean square error between the generated error mark and the preprocessed defect mark is used as the cost function, the back propagation algorithm is used to calculate the gradient and iteratively optimize the model; after the training, the model receives the layout to be detected as input, and outputs the predicted defect location marks shown in Figure 7(a) and Figure 7(b);

[0114] Three: Combination Features

[0115] After the defect feature extractor extracts the defect position features from the layout, the distribution information of the layout will be lost; therefore, the extracted defect position features are spliced ​​with the layout to increase the diversity of model features; at the same time, because the effective area window is fixed and known in the training and testing stages, the effective area window is explicitly represented as a layer of features, thereby simplifying the model's learning of "effective area detection" into a linear mathematical model, reducing the learning difficulty of the hotspot detection task;

[0116] 4. Layout Classification

[0117] Build as Figure 4 The second-stage layout classification model shown in the figure uses the "layout-classification label" data set to train the model; the layout first uses the first-stage defect position feature extractor to extract the potential defect position feature map, and then combines it with the layout and the effective area map into three-layer features as the layout classification model input; the combined features are encoded in turn through the convolution layer with a channel number of 32-64-128-256, and after the flattening layer is expanded, the nonlinear mapping relationship between the encoding vector and the predicted category is described through the first and second fully connected layers, and finally the predicted probability corresponding to each category is output; the unique hot code of the "classification label" and the cross entropy loss of the model prediction probability are used as the cost function and the model is iteratively updated through back propagation; after the training, the test process of the model is as follows Figure 3 As shown, by forward calculation of the combined features, the category with the highest predicted probability is output;

[0118] 5. Hotspot detection results

[0119] The test results after model training are as follows: Figure 8 The confusion matrix shown in the figure has a vertical axis representing the true category of the data and a horizontal axis representing the predicted category of the model; the experimental results show that the model proposed in this application achieves a detection accuracy of 98% for all hotspot maps and a detection accuracy of 96% for all non-hotspot maps;

[0120] 6. Explainability Analysis

[0121] After the hotspot detection is completed using the above method, the interpreter can be used to obtain the model's explanation of the layout prediction results. This process includes the following steps:

[0122] Each feature map in the defect location feature extraction model and the layout classification model is extracted as a mask, and after upsampling, it is point-to-point multiplied with the chip layout;

[0123] The point-to-point multiplication results of each feature map are combined with the defect location feature map and the effective area map in sequence to form a combined feature, and the predicted probability of the hotspot category is obtained through the layout classification model;

[0124] The difference between the predicted probability and the predicted probability of the original map is used as the weight of the feature map;

[0125] The weighted sum of all feature maps is used to obtain the classification explanation result.

[0126] Example 2

[0127] The embodiment of the present application provides a two-stage interpretable lithography hotspot detection system, which performs lithography hotspot detection on a layout to be detected, including: a defect feature extraction module and a layout classification module;

[0128] The defect feature extraction module includes: a first data set construction submodule and a first model training submodule;

[0129] The first data set construction submodule is used to generate preprocessed defect marks for chip layout defect positions obtained by lithography simulation, and to construct a preprocessed defect mark data set;

[0130] The first model training submodule is used to train the defect location feature extraction model, and the training is based on a layout data set with classification labels and its corresponding defect marking data set to identify the hotspot distribution pattern of the layout and generate a defect location feature map;

[0131] The layout classification model includes: a feature combination submodule, a second data set construction submodule and a second model training submodule;

[0132] The feature combination submodule is used to combine the defect location feature map, the chip layout and the effective area map to obtain a combined feature;

[0133] The second data set construction submodule is used to detect the original defect marks obtained by the lithography simulation using the effective area window, classify the chip layout, and construct a layout data set with classification labels; wherein the classification labels include hot spots or non-hot spots;

[0134] The second model training submodule is used to use the classification label of the layout data as the output target of the layout classification model and the combined features as the input of the layout classification model to complete the training of the layout classification model.

[0135] Further preferably, the first model training submodule includes: a first model training unit, an error label generation unit and a first model optimization unit;

[0136] The first model training unit is used to train the defect location feature extraction model according to the chip layout and its corresponding defect marking data set;

[0137] The error mark generation unit is used to identify the hotspot distribution pattern in the layout and generate an error mark at the defect position according to the correspondence between the local distribution pattern of the layout and the defect position learned in the process of training the defect position feature extraction model;

[0138] The first model optimization unit is used to use the root mean square error between the generated error mark and the preprocessed defect mark as a cost function, and use the back propagation algorithm to iteratively optimize the defect position feature extraction model;

[0139] Among them, the trained defect location feature extraction model takes the chip layout to be detected as input and the defect location feature map as output.

[0140] Further preferably, the second model training submodule comprises: a category prediction unit and a second model optimization unit;

[0141] The category prediction unit is used to encode the combined features in sequence through the convolutional layers of the layout classification model, expand them through the pooling layer, pass them through the first fully connected layer and the second fully connected layer, and output the predicted probability of each category;

[0142] The second model optimization unit is used to use the cross entropy loss of the one-hot code of the classification label and the predicted probability of each category as a cost function, and iteratively update the layout classification model through back propagation;

[0143] Among them, the trained layout classification model uses the combined features for forward calculation and outputs the category with the highest prediction probability.

[0144] Further preferably, the first data set construction submodule includes: a defect mark acquisition unit, a defect mark conversion unit and a defect intensity filling unit;

[0145] The defect mark acquisition unit is used to perform lithography simulation and defect detection on the chip layout and to perform original defect marks on the defect positions;

[0146] The defect mark conversion unit is used to calculate the minimum circumscribed circle of the polygon of each original defect mark, and replace the original defect mark with the circumscribed circle;

[0147] The defect intensity filling unit is used to divide each replaced circular defect mark into three areas with the radius trisection position as the boundary, and fill the three divided areas with different intensity values ​​from the center of the circle outward in turn to generate a preprocessed defect mark and construct a defect mark data set.

[0148] Further preferably, the chip layout double-step lithography hotspot detection system further includes an interpretability analysis module, which includes:

[0149] A mask processing unit is used to extract each feature map in the defect position feature extraction model and the layout classification model as a mask, and perform point-to-point multiplication with the chip layout after upsampling;

[0150] The explainability category prediction unit is used to combine the point-to-point multiplication results of each feature map with the defect location feature map and the effective area in sequence to form a combined feature, and obtain the prediction probability of the hotspot category through the layout classification model;

[0151] A feature value weight calculation unit, used to use the difference between the prediction probability obtained by the interpretability category prediction unit and the prediction probability obtained by taking the chip layout as input as the weight of the feature map;

[0152] An interpretable result acquisition unit is used to perform weighted summation on all feature maps to obtain an explanation of the predicted classification result; wherein the explanation of the predicted classification result is the explanation of the classification result predicted by inputting the chip layout into the trained defect location feature extraction model and layout classification model.

[0153] In summary, compared with the prior art, the present application has the following advantages:

[0154] In the first stage of the present application, a feature extractor extracts features in the layout and predicts potential hotspot locations, so that the feature extraction in the first stage can focus on the recognition of hotspot distribution patterns, so that the model can extract features consistent with the principle of lithography hotspot detection for back-end layout classification, overcoming the problems of low detection accuracy, high false alarm rate and inconsistency between model interpretation results and hotspot detection principles caused by the existing deep learning-based hotspot detection model using features unrelated to hotspots for classification; after the first stage of defect position feature extraction is completed, the extracted defect position features are combined with the layout and the detection window as features for the second stage layout classification, so as to overcome the problem of noise or loss of key distribution information in the defect position features, and at the same time, the detection window range is used as an explicit feature to simplify The hotspot detection task is performed; after executing layout classification to obtain the hotspot detection result of the layout, the feature maps in the defect position feature extraction model and the layout classification model are extracted as masks, and after upsampling, they are multiplied with the input layout; the processed input is used as input to obtain the model's predicted probability of the hotspot category under the input; the difference between the predicted probability and the predicted probability of the original layout is used as the weight of the feature map; all the feature maps are weighted and summed to obtain the classification interpretation result; according to the classification interpretation result, it can be judged whether the model's prediction conforms to the physical rules of hotspot detection, and lithography simulation is performed on a small number of layouts whose prediction results and interpretation results are inconsistent, so as to avoid the omission of hotspots caused by model errors, which in turn leads to huge losses caused by tape-out failure or low product yield.

[0155] It should be understood that the above-mentioned system is used to execute the methods in the above-mentioned embodiments. The implementation principles and technical effects of the corresponding program modules in the system are similar to those described in the above-mentioned methods. The working process of the system can refer to the corresponding process in the above-mentioned method and will not be repeated here.

[0156] Based on the method in the above embodiment, an embodiment of the present application provides an electronic device. The device may include: at least one memory for storing programs and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the above embodiment.

[0157] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0158] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0159] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0160] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0161] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable system. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0162] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0163] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A chip layout double-step lithography hotspot detection method based on deep learning, characterized in that: The trained defect feature extraction model and layout classification model are used sequentially to perform lithography hotspot detection on the chip layout to be inspected; Among them, the training methods of the defect feature extraction model and the layout classification model are: S1: obtaining the original defect mark according to the chip layout defect position obtained by lithography simulation, and then preprocessing it to generate the preprocessed defect mark, and construct a defect mark data set; at the same time, using the effective area window to detect the original defect mark, generate layout classification labels, and construct a layout data set with classification labels; wherein the classification labels include hot spots or non-hot spots; S2: Input the chip layout and its corresponding defect marking data set into the defect location feature extraction model for training, identify the hot spot distribution pattern of the layout, and generate a defect location feature map; S3: combining the defect location feature map, the chip layout and the effective area feature map to obtain a combined feature; S4: Using the classification label of the chip layout as the learning target of the layout classification model and the combined features as the input of the layout classification model to complete the training of the layout classification model; S1 specifically includes the following steps: Perform lithography simulation and defect detection on chip layout, and mark the defect location with original defects; Calculate the minimum circumscribed circle for each original defect mark, and replace the original defect mark with the minimum circumscribed circle; For each replaced circular defect mark, the radius is divided into three regions with three equal parts as the boundary. The three divided regions are filled with different intensity values ​​from the center of the circle outward in turn to generate the preprocessed defect mark and construct the defect mark data set. Use the effective area window for detection and calculate the overlap area ratio between the original defect mark and the effective area window. If the overlap area ratio exceeds the preset threshold, the layout classification label is set as a hotspot, otherwise it is set as a non-hotspot, and a layout dataset with classification labels is constructed.

2. The chip layout double-step lithography hotspot detection method according to claim 1, characterized in that: S2 specifically includes the following steps: The defect location feature extraction model is trained based on the layout dataset with classification labels and its corresponding defect marking dataset to learn the correspondence between the local distribution pattern of the layout and the defect location, identify the hot spot distribution pattern in the layout and generate error marks at the defect location; The root mean square error between the generated error mark and the preprocessed defect mark is used as the cost function, and the defect location feature extraction model is iteratively optimized using the back propagation algorithm; The trained defect location feature extraction model takes the chip layout to be inspected as input and the defect location feature map as output.

3. The chip layout double-step lithography hotspot detection method according to claim 1 or 2, characterized in that: S4 specific The following steps are involved: The combined features are encoded in turn through the convolutional layers of the layout classification model, and then through the first fully connected layer and the second fully connected layer after the pooling layer to output the predicted probability of each category; The cross entropy loss between the one-hot code of the classification label and the predicted probability of each category is used as the cost function, and the layout classification model is iteratively updated through back propagation; Among them, the trained layout classification model uses the combined features for forward calculation and outputs the category with the highest prediction probability.

4. The chip layout double-step lithography hotspot detection method according to claim 1, characterized in that: It also includes interpretability analysis of the trained defect location feature extraction model and layout classification model, which specifically includes the following steps: S5.1: Extract each feature map in the defect location feature extraction model and the layout classification model as a mask, and perform point-to-point multiplication with the chip layout after upsampling; S5.2: The point-to-point multiplication results obtained from each feature map are sequentially combined with the defect location feature map and the effective area map to form a combined feature, and the predicted probability of the hotspot category is obtained through the layout classification model; S5.3: Calculate the difference between the predicted probability obtained in S5.2 and the predicted probability obtained by taking the chip layout as input as the weight of the feature map; S5.4: Perform a weighted summation on all feature maps to obtain an explanation of the predicted classification result; wherein the explanation of the predicted classification result is the explanation of the classification result predicted by inputting the chip layout into the trained defect location feature extraction model and layout classification model.

5. A chip layout double-step lithography hotspot detection system based on deep learning, characterized in that: Perform lithography hotspot detection on the chip layout to be inspected, including: defect feature extraction module and layout classification model; The defect feature extraction module includes: a first data set construction submodule and a first model training submodule; The first data set construction submodule is used to obtain original defect marks according to chip layout defect positions obtained by lithography simulation and perform preprocessing to generate preprocessed defect marks, and construct a preprocessed defect mark data set; The first model training submodule is used to train the defect location feature extraction model, and the training is based on the chip layout and its corresponding defect labeling data set to identify the hot spot distribution pattern of the layout and generate a defect location feature map; The layout classification model includes: a feature combination submodule, a second data set construction submodule and a second model training submodule; The feature combination submodule is used to combine the defect position feature map, the chip layout and the effective area feature map to obtain a combined feature; The second data set construction submodule is used to detect the original defect marks obtained by the lithography simulation using the effective area window, classify the chip layout, and construct a layout data set with classification labels; wherein the classification labels include hot spots or non-hot spots; The second model training submodule is used to use the classification label of the layout data as the learning target of the layout classification model and the combined features as the input of the layout classification model to complete the training of the layout classification model; The first data set construction submodule includes: a defect mark acquisition unit, a defect mark conversion unit and a defect intensity filling unit; The defect mark acquisition unit is used to perform lithography simulation and defect detection on the chip layout and to perform original defect marks on the defect positions; The defect mark conversion unit is used to calculate the minimum circumscribed circle of the polygon of each original defect mark, and replace the original defect mark with the circumscribed circle; The defect intensity filling unit is used to divide each replaced circular defect mark into three areas with the radius trisection position as the boundary, and fill the three divided areas with different intensity values ​​from the center of the circle outward in turn to generate a preprocessed defect mark and construct a defect mark data set.

6. The chip layout double-step lithography hotspot detection system according to claim 5, characterized in that: The first model training submodule includes: a first model training unit, an error mark generation unit and a first model optimization unit; The first model training unit is used to train the defect location feature extraction model according to the chip layout and its corresponding defect marking data set; The error mark generation unit is used to identify the hotspot distribution pattern in the layout and generate an error mark at the defect position according to the correspondence between the local distribution pattern of the layout and the defect position learned in the process of training the defect position feature extraction model; The first model optimization unit is used to use the root mean square error between the generated error mark and the preprocessed defect mark as a cost function, and use the back propagation algorithm to iteratively optimize the defect position feature extraction model; Among them, the trained defect location feature extraction model takes the chip layout to be detected as input and the defect location feature map as output.

7. The chip layout double-step lithography hotspot detection system according to claim 5 or 6, characterized in that: The second model training submodule includes: a category prediction unit and a second model optimization unit; The category prediction unit is used to encode the combined features in sequence through the convolutional layers of the layout classification model, expand them through the pooling layer, pass them through the first fully connected layer and the second fully connected layer, and output the predicted probability of each category; The second model optimization unit is used to use the cross entropy loss of the one-hot code of the classification label and the predicted probability of each category as a cost function, and iteratively update the layout classification model through back propagation; Among them, the trained layout classification model uses the combined features for forward calculation and outputs the category with the highest prediction probability.

8. The chip layout double-step lithography hotspot detection system according to claim 5, characterized in that: It also includes an interpretability analysis module, which includes: A mask processing unit is used to extract each feature map in the defect position feature extraction model and the layout classification model as a mask, and perform point-to-point multiplication with the chip layout after upsampling; The explainability category prediction unit is used to combine the point-to-point multiplication results of each feature map with the defect location feature map and the effective area map in sequence to form a combined feature, and obtain the prediction probability of the hotspot category through the layout classification model; A feature value weight calculation unit, used to use the difference between the prediction probability obtained by the interpretability category prediction unit and the prediction probability obtained by taking the chip layout as input as the weight of the feature map; An interpretable result acquisition unit is used to perform weighted summation on all feature maps to obtain an explanation of the predicted classification result; wherein the explanation of the predicted classification result is the explanation of the classification result predicted by inputting the chip layout into the trained defect location feature extraction model and layout classification model.

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