Multi-point initiation power supply energy release system and control method

Abstract

The application discloses a multi-point initiation power supply and energy release system and a control method, and relates to the field of energy release systems.The system comprises a logic control module, an isolation circuit, a first-stage switch, a second-stage switch, a third-stage switch, a multi-channel high-voltage conversion circuit, a multi-channel energy release circuit and a feedback circuit.The logic control module comprises an FPGA circuit and a CPLD circuit.The multi-channel energy release circuit comprises a plurality of energy release circuits with the same number of channels, a high-voltage capacitor, a high-voltage switch and an energy release channel, etc.The application adopts an electronic safety system to realize power supply and energy release control of a multi-point warhead, can greatly reduce the volume and weight of the system, reduce the cost, and can code control the energy release units of different channels, realize conversion of multiple energy release modes, reduce the debugging difficulty and the energy release time dispersion of each energy release channel, and improve the combat effectiveness of the multi-point warhead.

Description

Technical Field

[0001] This invention relates to the field of energy storage system technology, specifically to a multi-point initiation power supply and energy release system and control method. Background Technology

[0002] A multi-mode warhead is a warhead that adaptively selects different modes of action based on the target type. This is primarily achieved by altering the detonation method and detonation point, and rationally controlling the detonation waveform to create different types of damage elements and produce varying degrees of damage effects. To achieve multi-mode detonation, the warhead's power supply and energy release system needs a corresponding number of channels based on the number of detonation points, and the ability to select the appropriate channel for energy release based on commands. Since the system controls the power supply and energy release of the warhead, to ensure its safety and reliability, it requires multiple levels of switches. Energy release can only occur when these switches simultaneously and reliably close, meeting certain logical relationships.

[0003] The existing power supply and energy release control scheme for multi-point detonation warheads using a fully electronic safety system involves each high-voltage detonation circuit connected in series with a detonation device. This means that all detonation devices can only detonate simultaneously, making it impossible to switch between multiple damage modes of the warhead by controlling whether or not the detonation devices in different locations detonate and the timing of the detonation. Summary of the Invention

[0004] Technical objective: In order to realize the conversion of multiple damage modes of multi-mode warheads while ensuring the safe detonation of multi-mode warheads, this invention proposes a power supply and energy release system and control method for multi-point detonation.

[0005] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution:

[0006] A multi-point detonation power supply and energy release system includes an external platform and a power supply and energy release device. The power supply and energy release device includes a logic control module, a first-level switch, a second-level switch, a third-level switch, an isolation circuit, a multi-channel high-voltage conversion circuit, a multi-channel energy release circuit, and a feedback circuit. The logic control module is equipped with an FPGA circuit and a CPLD circuit. The multi-channel high-voltage conversion circuit includes N high-voltage conversion circuits, and the multi-channel energy release circuit includes N energy release circuits. Each energy release circuit is equipped with a high-voltage switch, a high-voltage capacitor, and an energy release channel. N is any natural number greater than or equal to 2. The first-level switch, the second-level switch, the third-level switch, and the high-voltage switch are all equipped with a control terminal, a first terminal, and a second terminal.

[0007] The CPLD circuit is connected to the control terminal of the first-stage switch through an isolation circuit. The first terminal of the first-stage switch receives the power release signal, and the second terminal is connected to the first terminal of the third-stage switch.

[0008] The FPGA circuit connects the control terminals of the second-level switch and the third-level switch through an isolation circuit; the second terminal of the third-level switch is connected to the first terminal of the second-level switch, and the second terminal of the second-level switch is grounded.

[0009] The input terminals of each high-voltage conversion circuit are connected to the third-stage switch, and the output terminals are connected to an energy release circuit respectively. In each energy release circuit, one end of the high-voltage capacitor is connected to the first terminal of the high-voltage switch, and the other end is connected to one end of the energy release channel. The two ends of the high-voltage capacitor are connected in parallel with the output terminal of the corresponding high-voltage conversion circuit. The other end of the energy release channel is connected to the second terminal of the high-voltage switch. The control terminals of the high-voltage switch are connected to the logic control module through an isolation circuit.

[0010] The feedback circuit includes a feedback information encoding module and N feedback sampling circuits. The feedback sampling circuits are used to detect the voltage across the high-voltage capacitor. The output of each feedback sampling circuit is connected to the feedback information encoding module. The feedback information encoding module is connected to the logic control module through an isolation circuit.

[0011] The external platform is used to send various control commands to the FPGA circuit, including working signals, switching closure commands at various levels, and energy release control commands, and to receive information returned by the FPGA circuit.

[0012] Preferably, the system adopts a modular design for each high-voltage conversion circuit and energy release circuit, so that each channel can release energy independently without interference. Each high-voltage conversion circuit is equipped with a transformer and a fast recovery diode. The third-stage switch adopts a field-effect transistor. The gate of the field-effect transistor is connected to the second terminal of the second-stage switch, the source is grounded, and the drain is connected to the second terminal of the primary side of the transformer. The first terminal of the primary side of the transformer is connected to a DC power supply, the first terminal of the secondary side of the transformer is connected to the positive terminal of the fast recovery diode, the second terminal of the secondary side of the transformer is connected to the first terminal of the high-voltage capacitor, and the negative terminal of the fast recovery diode is connected to the second terminal of the high-voltage capacitor.

[0013] Preferably, the feedback sampling circuit uses a hysteresis voltage comparator to monitor whether the voltage across the high-voltage capacitor reaches a preset voltage threshold.

[0014] Preferably, the first-stage switch, the second-stage switch, the third-stage switch, and the high-voltage switch are all implemented using field-effect transistors.

[0015] Preferably, the external platform consists of a computer and two DC power supplies. The computer is connected to the logic control module via a 422 serial port and sends working signals, second-level switch closing instructions, third-level switch dynamic closing instructions, and energy release control instructions or self-destruct instructions to the logic control module in sequence. The first DC power supply provides the system with 5V / 2A working power, and the second DC power supply provides the system with a 24V / 2A boost power signal.

[0016] Preferably, the multi-channel high-voltage conversion circuit includes 14 high-voltage conversion circuits, and the multi-channel energy release circuit includes 14 high-voltage capacitors, 14 high-voltage switches, and 14 energy release channels. The system is used to control 14 detonation points.

[0017] A control method for a multi-point initiation power supply and energy release system, comprising the following steps:

[0018] S1. The system powers on and performs a self-test. The FPGA circuit sends the self-test result to the external platform. If the self-test result is normal, proceed to step S2.

[0019] S2. After receiving the working signal sent by the external platform, the FPGA circuit sends a first-level switch closing command to the CPLD circuit.

[0020] S3. If the CLPD circuit receives a first-level switch closing command, the first-level switch will not close, the system will enter a fault-protected state, and the system will no longer respond to any commands; if the CLPD circuit receives a first-level switch closing command, it will close the first-level switch and return a first-level switch closing success signal to the FPGA circuit, and proceed to step S4.

[0021] S4. After receiving the first-level switch closing success signal returned by the CPLD circuit, the FPGA circuit detects the second-level switch closing command sent by the external platform. If no second-level switch closing command is detected, the system enters a fault-safe state and no longer responds to any commands; if a second-level switch closing command is detected, the second-level switch closing command is recorded and the process proceeds to step S5.

[0022] S5. The FPGA circuit detects the boost power signal provided by the external platform. If no boost power signal is detected, it continues to monitor for the arrival of the boost power signal. If the boost power signal is detected, the second-stage switch is closed, and the process proceeds to step S6.

[0023] S6. The FPGA circuit detects the dynamic closing command of the third-level switch sent by the external platform. If the dynamic closing command of the third-level switch is not detected, the system will continue to monitor the arrival of the dynamic closing command of the third-level switch. If the dynamic closing command of the third-level switch is detected, the system controls the dynamic closing of the third-level switch and proceeds to step S7.

[0024] S7. After the third-level switch dynamically closes to generate a PWM signal, all high-voltage conversion circuits are turned on, the high-voltage capacitors begin to charge, generating high voltage that can be used for detonation. After all channels are charged, the system enters the energy release state and at the same time, the timing zero point is reset to start timing.

[0025] S8, the FPGA circuit continuously monitors the energy release control commands sent by the external platform;

[0026] If the FPGA circuit receives an energy release control command sent by an external platform, the FPGA circuit adopts the corresponding energy release mode according to the content of the energy release control command, shapes the energy release signal and outputs it to the corresponding channel at the same time, and opens the high voltage switch of the corresponding energy release circuit according to the delayed start time in the command, so that the corresponding energy release channel releases energy.

[0027] If the timing reaches the preset maximum energy release time without receiving an energy release control command from the external platform, all energy release channels will be shut down, the energy stored in the high-voltage capacitor will be dissipated, and the system will enter a no-fire state.

[0028] Preferably, in step S1, both the CPLD circuit and the FPGA circuit perform system self-tests. If the CPLD circuit self-test result is normal, the first self-test result is sent to the FPGA circuit; otherwise, the CPLD circuit re-executes the system self-test.

[0029] After confirming the first self-test result and its own self-test result, the FPGA circuit sends the second self-test result to the external platform. If both the first self-test result and its own self-test result are normal, then proceed to step S2; otherwise, the FPGA circuit and CPLD circuit re-execute the system self-test.

[0030] Preferably, in step S8, the external platform sends an RS422 serial communication format release control command to the system via 422 serial communication. The FPGA chip pre-generates a release control command data table. After receiving the release control command sent by the platform, it determines the release mode to be executed by querying the data table.

[0031] Preferably, the first and second frames of the energy release control command sent by the external platform are frame headers, the third frame is the energy release channel address, the fourth frame is the energy release channel sequence number and grouping relationship, the fifth and sixth frames are the energy release delay start control time, and the seventh to ninth frames are check codes.

[0032] Beneficial effects: Due to the adoption of the above technical solution, the present invention has the following beneficial effects:

[0033] This invention employs an electronic safety system to control the power supply and energy release of a multi-point warhead, which can significantly reduce the size and weight of the system, lower costs, and enable the switching of multiple energy release modes, reduce the energy release time dispersion of each energy release channel, and improve the combat effectiveness of the multi-point warhead.

[0034] This invention employs a three-stage switch control system for energy release. If any stage switch fails to function properly, the high-voltage conversion circuit cannot generate high voltage, thus preventing energy release through the energy release channel. Furthermore, this invention sets a maximum energy release time, ensuring that even without receiving an energy release control command, the system can safely dissipate the energy stored in the high-voltage capacitor within a certain timeframe, significantly improving the system's safety during commissioning and operation.

[0035] This invention employs multiple high-voltage conversion circuits and multiple energy release circuits to control energy release at multiple points. This not only ensures that each channel can release energy independently without interference, but also adopts a modular design for the high-voltage conversion circuits and energy release circuits, reducing the difficulty of debugging and calibration. If a high-voltage conversion circuit or energy release circuit in one channel fails, a new high-voltage conversion circuit module or energy release circuit module can be directly replaced, greatly improving the maintainability of the system.

[0036] This invention controls the switching of multiple energy release modes of the system through energy release control commands. An external platform sends energy release control commands as needed. After receiving the commands, the FPGA chip can quickly determine the energy release mode and output it to the corresponding channel, effectively improving the combat effectiveness of the warhead. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of the present invention;

[0038] Figure 2 This is a schematic diagram of an example of a high-voltage conversion circuit in this invention;

[0039] Figure 3 This is a schematic diagram of an example of an energy-releasing circuit in this invention;

[0040] Figure 4 This is a flowchart illustrating the operation of the CPLD circuit in this invention.

[0041] Figure 5 This is a flowchart illustrating the operation of the FPGA circuit in this invention. Detailed Implementation

[0042] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0043] Example 1

[0044] This invention provides a multi-point detonation power supply and energy release system, which includes a logic control module, an isolation circuit, a high-voltage conversion circuit, an energy release circuit, and a feedback circuit.

[0045] like Figure 1 In the embodiment shown, the system is equipped with a 14-channel high-voltage conversion circuit, a 14-channel energy release circuit, and a 14-channel feedback circuit to realize 14 detonation points.

[0046] The logic control module consists of one FPGA chip and one CPLD chip. Its input is connected to an external platform via a 422 serial communication port, and its output is connected to an isolation module. The logic control module uses three-stage switches (SW1, SW2, SWD) to control the power supply for energy release, reliably controlling the switches according to a set timing and conditions to ensure system safety. The CPLD circuit primarily performs system self-testing and first-stage switch control, with its output connected to the first-stage switch via an isolation circuit. The FPGA circuit primarily performs system self-testing, second-stage switch control, and third-stage switch control, with its output connected to the second and third-stage switches via isolation circuits. One end of the first-stage switch SW1 is connected to the de-energized power supply, and the other end is connected to the second-stage switch SW2. The two ends of the second-stage switch SW2 are connected to both the first-stage switch SW2 and the third-stage switch SWD. One end of the third-stage switch SWD is connected to the second-stage switch SW2, and the other end is grounded. Preferably, the first-stage switches SW1, SW2, and SWD are XNM30P10D5.

[0047] like Figure 1 As shown, the system incorporates an isolation circuit to separate the high-voltage and logic circuits, ensuring system safety. The input of the isolation circuit is connected to the logic module and the 14-channel feedback circuit, while the output is connected in parallel to a 14-channel high-voltage conversion circuit and a 14-channel energy release circuit. The high-voltage conversion circuit can employ a flyback converter or a boost circuit based on a flyback converter. When the first-stage switch, the second-stage switch, and the third-stage switch dynamically close to generate a PWM signal, the high-voltage conversion circuit receives this PWM signal and converts the low voltage into a high voltage sufficient for detonation. The energy release circuit stores the high voltage generated by the high-voltage conversion circuit onto a high-voltage capacitor. Upon receiving an energy release command, it opens the high-voltage switch of the corresponding channel, allowing the corresponding energy release channel to release energy.

[0048] The feedback circuit includes a feedback information encoding module and 14 feedback sampling circuits. The input of each feedback sampling circuit is connected to a high-voltage conversion circuit and an energy release circuit, and its output is connected to the feedback information encoding module. The output of the feedback information encoding module is connected to the logic control circuit via an isolation circuit. The feedback sampling circuit uses a hysteresis voltage comparator to monitor whether the voltage across the capacitor reaches a preset voltage threshold range. When the voltage across the high-voltage capacitor reaches the set voltage threshold, the feedback information encoding module sends a charging completion signal to the logic control circuit. Once the voltage deviates from the threshold, the feedback circuit returns feedback information. The logic control module then determines whether to continue outputting a PWM signal to the high-voltage conversion module based on the feedback information to ensure that the voltage across the high-voltage capacitor remains near the set voltage threshold.

[0049] like Figure 1 As shown, the external platform connected to this system consists of a computer and two DC power supplies. The computer is connected to the logic control module of this system via 422 serial communication. The computer sequentially sends working signals, second-level switch closing instructions, third-level switch dynamic closing instructions, and finally energy release control instructions or self-destruct instructions to the logic control module. The first DC power supply provides the system with 5V / 2A working power, and the second DC power supply provides the system with 24V / 2A boost power signals.

[0050] like Figure 2 The illustrated embodiment is a schematic diagram of a high-voltage conversion circuit channel in this system. The high-voltage conversion circuit of the system adopts a boost circuit based on a flyback converter. One channel includes a transformer T1, a fast recovery diode D1, and a high-voltage capacitor. The third-stage switch SWD is implemented using a field-effect transistor. The first terminal of the primary side of the transformer T1 is connected to an external platform and powered by the external platform. The second terminal of the primary side is connected to the drain of the third-stage switch SWD. The gate of the third-stage switch SWD is connected to the boost power supply signal through the first-stage switch and the second-stage switch, dynamically closing to generate a PWM signal. The source of the third-stage switch SWD is grounded. The first terminal of the secondary side of the transformer T1 is connected to the high-voltage capacitor, and the second terminal is connected to the first terminal of the fast recovery diode D1. The second terminal of the fast recovery diode D1 is connected to the high-voltage capacitor. Other channels in the high-voltage conversion circuit contain the same electronic components and are connected in the same way as the channel shown in the figure.

[0051] like Figure 3 The illustrated embodiment is a schematic diagram of the structure of one energy release circuit channel of this system. One channel of the energy release circuit of the system includes a high-voltage switch, an energy release channel, and a high-voltage capacitor. The gate of the high-voltage switch is connected to the logic control module through an isolation module. The source of the high-voltage switch is connected to ground and the first terminal of the high-voltage capacitor. The drain of the high-voltage switch is connected to the first terminal of the energy release channel. The second terminal of the energy release channel is connected to the second terminal of the high-voltage capacitor. Other channels in the energy release circuit contain the same electronic components and are connected in the same way as the channel shown in the figure.

[0052] This invention employs an electronic safety system to control the power supply and energy release of a multi-point warhead. Compared to an electromechanical control structure, the all-electronic safety system not only reduces costs but also significantly reduces the system's size and weight. By using two different types of logic chips to perform logic control on the system, common-cause failures are reduced, and the system's reliability is improved.

[0053] This system uses multiple high-voltage conversion circuits and multiple energy release circuits to control energy release at multiple points. The high-voltage conversion circuits and energy release circuits adopt a modular design, which not only ensures that each channel can release energy independently without interference, reducing the difficulty of debugging and calibration, but also allows for direct replacement of a new high-voltage conversion circuit module or energy release circuit module if a high-voltage conversion circuit or energy release circuit of one channel fails, greatly improving the maintainability of the system.

[0054] This invention features a three-stage switch, with the third stage being a dynamic switch. When the third stage switch fails to close dynamically, a PWM signal usable by subsequent circuits cannot be generated. Even if the first and second stage switches close normally, the high-voltage conversion circuit cannot generate high voltage, making it impossible for the energy release channel to release energy. Furthermore, after the third stage switch dynamically closes and generates a PWM signal, the system resets the timing zero point and starts timing, setting a maximum energy release time. This ensures that even if the system fails to receive an energy release control command, it can safely dissipate the energy stored in the high-voltage capacitor within a certain time, greatly improving the safety of the system during debugging and reducing the debugging difficulty.

[0055] Example 2

[0056] This invention provides a control method for a power supply and energy release system adapted to a multi-mode detonation system of a distributed multi-point warhead. Based on operational requirements, the system simultaneously releases energy to the detonation points on one side of the warhead. Figure 4 Figure 5 The specific control steps are as follows:

[0057] (1) The system connects to an external platform via 422 serial communication. At this time, the external platform is the missile-borne host computer platform.

[0058] (2) The system performs a self-test after power-on;

[0059] (3) If the system self-test result is normal, after the FPGA circuit receives the working signal sent by the external platform, it sends a first-level switch closing instruction to the CPLD circuit. After receiving the instruction, the CLPD circuit closes the first-level switch and returns a first-level switch closing success signal to the FPGA circuit.

[0060] (4) After the FPGA circuit receives the first-level switch closing success signal returned by the CPLD circuit, if it receives the second-level switch closing instruction from the external platform, it records the second-level switch closing instruction and detects the boost power signal provided by the external platform. If the boost power signal is detected, the second-level switch is closed.

[0061] (5) After the FPGA circuit closes the first-stage switch and the second-stage switch in the correct timing sequence and detects the 24V / 2A boost power supply signal given by the external platform, it will receive the dynamic closing command of the third-stage switch sent by the external platform and dynamically close the third-stage switch to generate a PWM signal.

[0062] (6) After the third-level switch of the system dynamically closes to generate a PWM signal, all high-voltage conversion circuits of all channels are turned on, the high-voltage capacitors start to charge, and generate high voltage that can be used for detonation. When the feedback sampling circuit collects the voltage across the high-voltage capacitors and the voltage threshold is reached, the feedback information encoding module sends a charging completion signal to the logic control circuit. Before all channels are fully charged, the system does not respond to the energy release control command and self-destruct command sent by the external platform. When all channels are fully charged, the system enters the energy release state and continuously monitors the energy release control command or self-destruct command sent by the external platform. At the same time, the timing zero point is reset and the timing starts.

[0063] (7) If the system receives the energy release control command sent by the platform, the system adopts the corresponding energy release mode according to the content of the energy release control command, shapes the energy release signal and outputs it to the corresponding channel at the same time, and simultaneously opens the high voltage switch of the energy release circuit of the corresponding channel, and releases energy in the corresponding channel to complete multi-point detonation.

[0064] In step (3), if the system self-test result is abnormal, the system will immediately terminate the workflow and re-enter the self-test state; if the CPLD circuit does not receive the first-level switch closing instruction, the system will enter the fault protection state and will no longer respond to any instructions.

[0065] In step (4), if no secondary switch closing command is received, the system enters a fault-safe state and no longer responds to any commands; if no boost power signal provided by the external platform is detected, the system will continue to monitor for the arrival of the boost power signal.

[0066] In step (5), if the third-level switch dynamic closing command is not received, the system will continue to monitor for the arrival of the third-level switch dynamic closing command.

[0067] In step (7), if the system time reaches the specified maximum energy release time but does not receive the energy release control command sent from the platform, the system will close the energy release channel, dissipate the energy stored on the high-voltage capacitor, and the system will enter a no-fire state.

[0068] In step (7), to quickly achieve energy release control in different modes, the energy release control commands sent by the platform cannot be too complex. Therefore, the command content mainly consists of two pieces of information: the energy release channel sequence number and grouping relationship, and the energy release delay start time. Considering that the warhead adapted to this system requires a synchronization error of less than 100ns for the energy release channel, and that the microprocessor clock in the FPGA chip is usually between 4 and 50MHz, with a maximum of no more than 100MHz, the energy release delay start step size is proposed to be 20ns. The delay time between the pre-stage and main charge of the tandem warhead is usually no more than 100ns. Therefore, the maximum count for the energy release delay start time encoding is set to 5000, which can be represented by two bytes. Thus, according to the RS422 serial communication format, the first and second frames of the control command encoding are the frame header, the third frame is the energy release channel address, the fourth frame is the energy release channel sequence number and grouping relationship, the fifth and sixth frames are the energy release delay start control time, and the seventh to ninth frames are the checksum. The FPGA chip forms an energy release control command data table by pre-generating the energy release control commands. After receiving the energy release control commands sent by the platform, it can quickly determine its own energy release mode by querying the data table. In this embodiment, to enable the system to simultaneously release energy at the detonation points on one side of the warhead, the energy release channel address corresponding to the detonation point needs to be input in the third frame of the command, the grouping relationship of the energy release channels needs to be input in the fourth frame (simultaneous release), and the energy release delay start time is set to 1000ns in the fifth and sixth frames.

[0069] Example 3

[0070] This invention provides a control method for a multi-mode initiation power supply and energy release system adapted to a deep-hole loosening blasting system in rock tunnels. To reduce the difficulty of mine rock excavation, this system needs to release energy sequentially at different points with the same time delay, thereby improving the loosening effect in deep-hole rock tunnels. The specific control steps are the same as in Embodiment 1, with the following differences:

[0071] In step (1), the system connects to an external platform via 422 serial communication, where the external platform is a computer platform.

[0072] In step (7), considering that the blasting system adapted to this system requires a synchronization error of less than 100 for the energy release channel, Meanwhile, the microprocessor clock within the FPGA chip is typically between 4 and 50 MHz, with a maximum of 100 MHz. Therefore, the energy release delay start-up step size is proposed to be 20. Since the detonation delay time of the blasting system is typically no more than 20ms, the maximum count of the energy release delay start time code is set to 1000, which can be represented by two bytes. In this embodiment, to enable the system to release energy sequentially at different points at the same time interval, the energy release channel address corresponding to the detonation point needs to be input in the third frame of the instruction, the grouping relationship of the energy release channels needs to be input in the fourth frame so that they are released sequentially with the same time delay, and the energy release delay start time is set to 5ms in the fifth and sixth frames.

[0073] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A multi-point detonation power supply and energy release system, characterized in that: The device includes an external platform and a power supply and energy release device. The power supply and energy release device includes a logic control module, a first-level switch, a second-level switch, a third-level switch, an isolation circuit, a multi-channel high-voltage conversion circuit, a multi-channel energy release circuit, and a feedback circuit. The logic control module is equipped with an FPGA circuit and a CPLD circuit. The multi-channel high-voltage conversion circuit includes N high-voltage conversion circuits. The multi-channel energy release circuit includes N energy release circuits. Each energy release circuit is equipped with a high-voltage switch, a high-voltage capacitor, and an energy release channel. N is any natural number greater than or equal to 2. The first-level switch, the second-level switch, the third-level switch, and the high-voltage switch are all equipped with a control terminal, a first terminal, and a second terminal. The CPLD circuit is connected to the control terminal of the first-stage switch through an isolation circuit. The first terminal of the first-stage switch receives the power release signal, and the second terminal is connected to the first terminal of the second-stage switch. The FPGA circuit connects the control terminals of the second-level switch and the third-level switch through an isolation circuit; the second terminal of the second-level switch is connected to the first terminal of the third-level switch, and the second terminal of the third-level switch is grounded. The input terminals of each high-voltage conversion circuit are connected to the third-stage switch, and the output terminals are connected to an energy release circuit respectively. In each energy release circuit, one end of the high-voltage capacitor is connected to the first terminal of the high-voltage switch, and the other end is connected to one end of the energy release channel. The two ends of the high-voltage capacitor are connected in parallel with the output terminal of the corresponding high-voltage conversion circuit. The other end of the energy release channel is connected to the second terminal of the high-voltage switch. The control terminals of the high-voltage switch are connected to the logic control module through an isolation circuit. The feedback circuit includes a feedback information encoding module and N feedback sampling circuits. The feedback sampling circuits are used to detect the voltage across the high-voltage capacitor. The output of each feedback sampling circuit is connected to the feedback information encoding module. The feedback information encoding module is connected to the logic control module through an isolation circuit. The external platform is used to send various control commands to the FPGA circuit, including working signals, switching closure commands at each level, and energy release control commands, and to receive information returned by the FPGA circuit. Each high-voltage conversion circuit is equipped with a transformer and a fast recovery diode. The third-stage switch uses a field-effect transistor. The gate of the field-effect transistor is connected to the second terminal of the second-stage switch, the source is grounded, and the drain is connected to the second terminal of the primary side of the transformer. The first terminal of the primary side of the transformer is connected to a DC power supply, the first terminal of the secondary side of the transformer is connected to the positive terminal of the fast recovery diode, the second terminal of the secondary side of the transformer is connected to the first terminal of the high-voltage capacitor, and the negative terminal of the fast recovery diode is connected to the second terminal of the high-voltage capacitor. The feedback sampling circuit uses a hysteresis voltage comparator to monitor whether the voltage across the high-voltage capacitor reaches a preset voltage threshold. The first-stage switch, second-stage switch, third-stage switch, and high-voltage switch are all implemented using field-effect transistors.

2. The multi-point initiation power supply and energy release system according to claim 1, characterized in that: The external platform consists of a computer and two DC power supplies. The computer is connected to the logic control module via a 422 serial port and sends working signals, second-level switch closing instructions, third-level switch dynamic closing instructions, and energy release control instructions or self-destruct instructions to the logic control module in sequence. The first DC power supply provides the system with 5V / 2A working power, and the second DC power supply provides the system with a 24V / 2A boost power signal.

3. The multi-point initiation power supply and energy release system according to claim 1, characterized in that: The multi-channel high-voltage conversion circuit includes 14 high-voltage conversion circuits, and the multi-channel energy release circuit includes 14 energy release circuits, 14 high-voltage capacitors, 14 high-voltage switches, and 14 energy release channels. The system is used to control 14 detonation points.

4. A control method for a multi-point initiation power supply and energy release system, applicable to the system described in claim 1, characterized in that, Including the following steps: S1. The system powers on and performs a self-test. The FPGA circuit sends the self-test result to the external platform. If the self-test result is normal, proceed to step S2. S2. After receiving the working signal sent by the external platform, the FPGA circuit sends a first-level switch closing command to the CPLD circuit. S3. If the CLPD circuit does not receive the first-level switch closing command, the first-level switch will not close, the system will enter the fault protection state, and the system will no longer respond to any commands; if the CLPD circuit receives the first-level switch closing command, it will close the first-level switch and return a first-level switch closing success signal to the FPGA circuit, and proceed to step S4. S4. After receiving the first-level switch closing success signal returned by the CPLD circuit, the FPGA circuit detects the second-level switch closing command sent by the external platform. If no second-level switch closing command is detected, the system enters a fault-safe state and no longer responds to any commands; if a second-level switch closing command is detected, the second-level switch closing command is recorded and the process proceeds to step S5. S5. The FPGA circuit detects the boost power signal provided by the external platform. If no boost power signal is detected, it continues to monitor for the arrival of the boost power signal. If the boost power signal is detected, the second-stage switch is closed, and the process proceeds to step S6. S6. The FPGA circuit detects the dynamic closing command of the third-level switch sent by the external platform. If the dynamic closing command of the third-level switch is not detected, the system will continue to monitor the arrival of the dynamic closing command of the third-level switch. If the dynamic closing command of the third-level switch is detected, the system controls the dynamic closing of the third-level switch and proceeds to step S7. S7. After the third-level switch dynamically closes to generate a PWM signal, all high-voltage conversion circuits are turned on, the high-voltage capacitors begin to charge, generating high voltage that can be used for detonation. After all channels are charged, the system enters the energy release state and at the same time, the timing zero point is reset to start timing. S8, the FPGA circuit continuously monitors the energy release control commands sent by the external platform; If the FPGA circuit receives an energy release control command sent by an external platform, the FPGA circuit adopts the corresponding energy release mode according to the content of the energy release control command, shapes the energy release signal and outputs it to the corresponding channel at the same time, and synchronously opens the high voltage switch of the corresponding energy release circuit to release the energy of the corresponding energy release channel. If the timing reaches the preset maximum energy release time without receiving an energy release control command from the external platform, all energy release channels will be shut down, the energy stored in the high-voltage capacitor will be dissipated, and the system will enter a no-fire state.

5. The control method for a multi-point initiation power supply and energy release system according to claim 4, characterized in that: In step S1, both the CPLD circuit and the FPGA circuit perform system self-tests. If the CPLD circuit self-test result is normal, the first self-test result is sent to the FPGA circuit; otherwise, the CPLD circuit re-executes the system self-test. After confirming the first self-test result and its own self-test result, the FPGA circuit sends the second self-test result to the external platform. If both the first self-test result and its own self-test result are normal, then proceed to step S2; otherwise, the FPGA circuit and CPLD circuit re-execute the system self-test.

6. The control method for a multi-point initiation power supply and energy release system according to claim 5, characterized in that: In step S8, the external platform sends an RS422 serial communication format release control command to the system via 422 serial communication. The FPGA chip pre-generates a release control command data table. After receiving the release control command sent by the platform, it determines the release mode to be executed by querying the data table.

7. The control method for a multi-point initiation power supply and energy release system according to claim 6, characterized in that: The first and second frames of the energy release control command sent by the external platform are the frame headers, the third frame is the energy release channel address, the fourth frame is the energy release channel sequence number and grouping relationship, the fifth and sixth frames are the energy release delay start control time, and the seventh to ninth frames are the check codes.

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