A Fast TDC Measurement System and Method Based on Differential Carry Chain

Abstract

The present invention discloses a fast TDC measurement system and method based on a differential carry chain, belonging to the technical field of time-of-flight measurement of lidar. The system includes a coarse counting unit, a fine counting unit, a counting calibration unit, and a data combination and storage and transmission unit; the fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit, and a Fast double-edge counting unit; the ring oscillator is composed of a carry chain, NOT gates, and AND gates. By adopting the above-mentioned fast TDC measurement system and method based on a differential carry chain, the present invention can effectively reduce the oscillation times of the ring oscillator, improve the measurement accuracy of the fine counting unit, and effectively shorten the conversion time.

Description

Technical Field

[0001] The present invention relates to the technical field of lidar time-of-flight measurement, and in particular to a fast TDC measurement system and method based on a differential carry chain. Background Art

[0002] In the prior art, high-precision time measurement is of great significance in the field of lidar. The azimuth distance is perceived by measuring the round-trip time of laser pulses. The commonly used time measurement methods include the ASIC-TDC design method and the FPGA-TDC design method. However, the ASIC-TDC method has a slow interface reading speed and a long development time cycle during the design process. The FPGA-based design method has a low cost, a large number of adjustable resources, a relatively short time to complete one measurement, and a relatively high measurable laser point frequency.

[0003] In the FPGA-based design method, the commonly used method is the fast carry chain method. By using a tapped delay line, a sub-nanosecond resolution can be obtained. By discriminating the position of the high and low level transitions of the thermometer code, the corresponding measurement time can be calculated according to the delay time of a single carry chain. However, this method is restricted by the basic delay time of the internal delay structure, especially by the minimum delay unit, and is also affected by the uneven delay distribution, resulting in relatively large measurement errors and relatively more logic resources required.

[0004] In order to further improve the resolution and accuracy of the TDC implemented in the FPGA, a cursor delay line or a cursor ring oscillator can be used to implement a TDC with a sub-gate resolution. The resolution of the above method is determined by the difference in the delay times of two delay units and can be unrestricted by the internal delay structure. However, this method mainly has the problems of a short measurable time range, a reduced accuracy due to a large number of oscillations, and a relatively long TDC conversion time. Summary of the Invention

[0005] The object of the present invention is to provide a fast TDC measurement system and method based on a differential carry chain, which can reduce the number of oscillations of the ring oscillator, improve the measurement accuracy of the fine counting unit, and the conversion time.

[0006] To achieve the above object, the present invention provides a fast TDC measurement system based on a differential carry chain, including a coarse counting unit, a fine counting unit, a counting calibration unit, and a data combination and storage transmission unit;

[0007] The fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit, and a Fast double-edge counting unit; the ring oscillator includes a fast loop part and a slow loop part composed of a carry chain, NOT gates, and AND gates; the input end of the AND gate in the slow loop part is connected to the input and output end of the pulse shaping unit and the inverted input end of the oscillation signal in the slow loop part, and the input end of the AND gate in the fast loop part is connected to the input and output end of the clock synchronization unit and the inverted input end of the oscillation signal in the fast loop part.

[0008] Preferably, the coarse counting unit is a two-stage counter, including a low-order counter and a high-order counter. The low-order counter is a Gray code counter, and the output end of the low-order counter is connected to the input end of the high-order counter.

[0009] Preferably, the pulse shaping unit is composed of a single-level D flip-flop. The clock input end of the D flip-flop is connected to the echo start or stop pulse signal, the data input end is connected to a high level, and the data clear end clrn is connected to the inverted output end real_locked of the double-edge phase detector.

[0010] Preferably, the clock synchronization unit is a three-bit shift register structure, including a first-stage D flip-flop, a second-stage D flip-flop, and a third-stage D flip-flop; among them, the clock input end of the first-stage D flip-flop is connected to the echo start or stop pulse signal, the data input end is connected to a high level, and the data clear end clrn is connected to the inverted output end real_locked of the double-edge phase detector; the clock input end of the second-stage D flip-flop is connected to the system clock signal, and the data input end is connected to the data output end of the first-stage D flip-flop; the clock input end of the third-stage D flip-flop is connected to the system clock signal, and the data input end is connected to the data output end of the second-stage D flip-flop.

[0011] Preferably, the fast loop part and the slow loop part are composed of carry chains with different delay times, and the period of the slow loop part is greater than that of the fast loop part.

[0012] Preferably, the double-edge phase detector is composed of a rising edge-rising edge edge coincidence detection part and a rising edge-falling edge edge coincidence detection part;

[0013] The rising edge-rising edge edge coincidence detection part is composed of two-stage D flip-flops. The outputs of the fast loop part and the slow loop part are the clock input and data input of the first-stage D flip-flop, and the data input and clock input of the second-stage D flip-flop. After passing through the delay unit, the first-stage D flip-flop and the second-stage D flip-flop are output through an AND gate;

[0014] The rising edge - falling edge coincidence detection part is also composed of two - stage D - flip - flops. The outputs of the fast - loop part and the slow - loop part are the inverted clock input and data input of the first - stage D - flip - flop, and the data input and inverted clock input of the second - stage D - flip - flop. After passing through a delay unit, the first - stage D - flip - flop and the second - stage D - flip - flop are output through an AND gate.

[0015] The outputs of the AND gates of the rising edge - rising edge coincidence detection part and the rising edge - falling edge coincidence detection part are output through an OR gate.

[0016] Preferably, the feedback counting latch is composed of D - flip - flops. The data input terminal is connected to a high - level signal, and the clock input terminal is connected to the output terminal of the dual - edge phase detector; the inverted output of the feedback counting latch is connected to the pulse shaping unit and the clock synchronization unit.

[0017] Preferably, the Slow dual - edge counting unit and the Fast dual - edge counting unit have the same structure as the coarse counting unit.

[0018] A fast TDC measurement method based on a differential carry chain includes the following steps:

[0019] S1. The echo start pulse signal is first converted into a single - edge signal by the pulse shaping unit, which drives the oscillation loop of the slow - loop part to generate oscillations. The Slow dual - edge counting unit starts to count the rising edges and falling edges of the slow - loop part. Then, the echo start pulse signal extracts the clock synchronization signal through the clock synchronization unit, which drives the oscillation loop of the fast - loop part to generate oscillations. The Fast dual - edge counting unit starts to count the rising edges and falling edges of the fast - loop part.

[0020] S2. When the clock synchronization signal of the echo start pulse signal is detected, the coarse counting unit starts to count the rising edges of the system clock.

[0021] S3. The dual - edge phase detector detects the rising edge - rising edge or rising edge - falling edge coincidence moment of the fast - loop part and the slow - loop part, and outputs a high - level signal to the feedback counting latch; the feedback counting latch outputs the first rising edge of the extracted multi - edge signal.

[0022] S4. When the Slow dual - edge counting unit and the Fast dual - edge counting unit detect the rising edge of the latch signal, they stop counting; when the pulse shaping unit and the clock synchronization unit detect the inverted output of the latch signal, they trigger the data clear terminal clrn of the D - flip - flop, pull down the output level, and wait for the next measurement input.

[0023] S5. After the counting data is calibrated, it enters the data combination and storage and transmission unit, outputs the measurement completion flag signal of the Start part fine - counting unit, and all counting units enter the zero - reset state, waiting for the next measurement by the Stop part fine - counting unit.

[0024] S6. The echo stop pulse signal is the same as the echo start pulse signal, and steps S1 - S5 are repeated;

[0025] S7. When the clock synchronization signal of the echo stop pulse signal is detected, the coarse counting unit stops counting;

[0026] S8. Combine the measurement results of the primary coarse counting unit and the measurement results of the Start and Stop fine counting units to complete a time measurement. The result expression is:

[0027] T coarse = N coarse T sys_clk

[0028]

[0029] T = T coarse + T start_fine - T stop_fine

[0030] where, T sys_clk , T slow_ro and T fast_ro represent the system clock, the oscillation period time of the slow loop part, and the oscillation period time of the fast loop part respectively; T is the flight time of the overall measurement, representing the measurement result of data combination, storage and transmission. T coarse is the main part time of the wide - range time measured by the coarse counting unit, and T start_fine and T stop_fine represent the start fine time and the stop fine time of the remaining edge part of the measurement time respectively; N coarse represents the count value of the coarse counting unit, N slow_start and N fast_start represent the double - edge count values of the double - edges of the slow loop part and the fast loop part of the echo start pulse signal respectively, and N slow_stop and N fast_stop represent the double - edge count values of the double - edges of the slow loop part and the fast loop part of the echo stop pulse signal respectively;

[0031] S9. Repeat steps S1 - S8 to continuously measure the flight time in a loop.

[0032] Therefore, the beneficial effects of the present invention adopting the above - mentioned fast TDC measurement system and method based on a differential carry chain are as follows:

[0033] (1) Compared with the traditional differential structure that uses a single D - flip - flop to enable counting, the measurement range of the fine counting unit that can be measured by the present invention is increased, and it can handle the measurement range exceeding an integer number of oscillation clock cycles

[0034] (2) The resolution is improved to 51 ps by using a differential carry chain structure compared with the dedicated carry chain method.

[0035] (3) The oscillation times of the ring oscillator can be significantly reduced, and the measurement accuracy of the fine counting unit is improved to 48 ps.

[0036] (4) The maximum encodings of the double-edge detection counting results output by the fast loop part and the slow loop part are 86 and 88 respectively, and the maximum measurement time of the fine counting unit is half a period of the slow loop part. Compared with the differential carry chain method using a conventional phase detector structure with the same resolution, the maximum relative conversion time is reduced by 50%. And as the oscillation frequency of the loop decreases, the actual conversion time will be further reduced.

[0037] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Description of the Drawings

[0038] Figure 1 is a structural diagram of a fast TDC measurement system based on a differential carry chain of the present invention;

[0039] Figure 2 is a circuit diagram of the clock synchronization unit and the pulse shaping unit of a fast TDC measurement system based on a differential carry chain of the present invention;

[0040] Figure 3 is a circuit diagram of the double-edge phase detector structure of a fast TDC measurement system based on a differential carry chain of the present invention;

[0041] Figure 4 is a schematic diagram of the double-edge phase detection process;

[0042] Figure 5 is a code density test chart of the fine counting unit;

[0043] Figure 6 is a differential nonlinearity graph;

[0044] Figure 7 is an integral nonlinearity graph;

[0045] Figure 8 is a time measurement accuracy graph. Detailed Embodiments

[0046] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0047] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The "first", "second" and similar terms used in the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0048] Embodiment 1

[0049] As Figure 1 shown, the present invention provides a fast TDC measurement system based on a differential carry chain, including a coarse counting unit, a fine counting unit, a counting calibration unit, and a data combination and storage and transmission unit;

[0050] The fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit, and a Fast double-edge counting unit.

[0051] Among them, the coarse counting unit is used to measure the main part of the wide-range time. The coarse counting unit is a two-stage counter, including a low-order counter and a high-order counter. The low-order counter is a Gray code counter, and the output end of the low-order counter is connected to the input end of the high-order counter. The counting result of the coarse counting unit is the sum of two parts, and the result is expressed as:

[0052] N = N H <<2 + N L

[0053] The fine counting unit is used to measure the remaining edge part, constituting the fine time measurement part of the time measurement result.

[0054] The pulse shaping unit converts the input echo start or stop pulse signal into a start single-edge signal, which is used to start the oscillation of the slow loop part.

[0055] The clock synchronization unit is used to obtain the single-edge signal for the fine counting unit to stop counting, and at the same time serves as the start measurement signal or stop measurement signal for the coarse counting unit.

[0056] As Figure 2As shown in (a), the general clock synchronization unit and pulse shaping unit use M delay buffers to make the phase difference between the start signal and the stop signal less than 180°, which is used to offset the delay time introduced by two D flip-flops. The present invention designs a new pulse shaping unit and clock synchronization unit on the basis of Figure 2 On the basis of (a). The clock synchronization unit used is a three-bit shift register structure, and the inputs are a high-frequency clock signal and an echo start or stop pulse signal. The clock input terminal of the first-stage D flip-flop is connected to the echo start or stop pulse signal, the data input terminal is connected to a high level, and the data clear terminal clrn is connected to the reverse output terminal real_locked of the double-edge phase detector. The clock input terminal of the second-stage D flip-flop is connected to the system clock signal, and the data input terminal is connected to the data output terminal of the first-stage D flip-flop. The clock input terminal of the third-stage D flip-flop is connected to the system clock signal, and the data input terminal is connected to the data output terminal of the second-stage D flip-flop.

[0057] The pulse shaping unit consists of a D flip-flop and a delay unit. The clock input terminal of the D flip-flop is connected to the echo start or stop pulse signal, the data input terminal is connected to a high level, the pulse signal is converted into a single-edge signal that can form an oscillating output, and the data clear terminal clrn is connected to the reverse output terminal real_locked of the double-edge phase detector.

[0058] The advantage of the structure (b) of the present invention compared with the structure (a) is that it is not necessary to repeatedly adjust the number of delay stages to determine the specific size of M, and at the same time, it is not necessary to consider the extra delay time caused by N flip-flops, which is convenient for the adjustment of the overall system.

[0059] The ring oscillator includes a fast loop part and a slow loop part composed of a carry chain, NOT gates and AND gates. The input terminal of the AND gate of the slow loop part is connected to the input and output terminal of the pulse shaping unit and the reverse input terminal of the oscillation signal of the slow loop part. The input terminal of the AND gate of the fast loop part is connected to the input and output terminal of the clock synchronization unit and the reverse input terminal of the oscillation signal of the fast loop part. The fast loop part and the slow loop part are composed of carry chains with different delay times, and the period of the slow loop part is greater than the period of the fast loop part.

[0060] The double-edge phase detector is used to output the phase synchronization signals of the fast loop part and the slow loop part. The double-edge phase detector needs to detect both the rising edge coincidence moment of the fast loop part and the slow loop part, and at the same time, it also needs to detect the edge coincidence moment of the rising edge of the fast loop part and the falling edge of the slow loop part.

[0061] Assume that the initial phase difference between the fast loop part and the slow loop part is And The frequencies of the slow loop and the fast loop are f s And f k . 2n c π corresponds to the slow clock n c Ts The time difference. When the rising edges of the fast clock and the slow clock are aligned by the double-edge phase detector, the fast clock n k The count is:

[0062]

[0063] Assume that the initial phase difference between the fast loop part and the slow loop part is And Then the fast clock n k The count is:

[0064]

[0065] For an uncompensated ring oscillator, the root mean square error σ increases proportionally to the square root of the total number of oscillations n.

[0066]

[0067] In the above formula, σ is the root mean square error measured by the system, ΔT represents the time interval to be measured, res is the system resolution, and T ro is the oscillation period of the oscillator. It can be seen from the above formula that shortening the time interval to be measured will reduce the root mean square error measured by the system.

[0068] According to the characteristics of the double-edge phase detector, the maximum count result of the fast loop part is:

[0069]

[0070] It can be seen from the above formula that the double-edge phase detector can reduce the number of oscillations of n to half of the original, which not only effectively reduces the root mean square error, but also reduces the overall measurement time.

[0071] The double-edge phase detector consists of a rising edge-rising edge coincidence detection part and a rising edge-falling edge coincidence detection part. Specifically:

[0072] The rising edge-rising edge coincidence detection part is composed of two-stage D flip-flops. The outputs of the fast loop part and the slow loop part are the clock input and data input of the first-stage D flip-flop, and the data input and clock input of the second-stage D flip-flop. After passing through the delay unit, the first-stage D flip-flop and the second-stage D flip-flop are output through an AND gate. When the rising edges of the fast loop part and the slow loop part coincide, the output of the AND gate is high level, indicating that the phase difference between the fast loop part and the slow loop part after phase shift is 0°.

[0073] The rising edge - falling edge coincidence detection part is also composed of two - stage D - flip - flops. The outputs of the fast - loop part and the slow - loop part are the inverted clock input and data input of the first - stage D - flip - flop, and the data input and inverted clock input of the second - stage D - flip - flop. After passing through a delay unit, the first - stage D - flip - flop and the second - stage D - flip - flop are output through an AND gate. When the rising edge of the fast - loop part coincides with the falling edge of the slow - loop part, the output of the AND gate is high level, indicating that the phase difference between the fast - loop and the slow - loop is 180° after phase shift.

[0074] The outputs of the AND gates of the rising edge - rising edge coincidence detection part and the rising edge - falling edge coincidence detection part are output through an OR gate. When the output of the OR gate is high level, it indicates that the phase discrimination is completed. At this time, the phase difference between the fast - loop part and the slow - loop part is 0° or 180°.

[0075] The Slow double - edge counting unit and the Fast double - edge counting unit have the same structure as the coarse counting unit, and are respectively used to count the number of double - edges of the slow - loop part and the fast - loop part. Its structure is divided into a rising - edge counter and a falling - edge counter. Both the rising - edge counter and the falling - edge counter are of double - cascade structure, and the sum of the two is the output of the double - edge counting result.

[0076] The feedback counting latch is used to output the counting stop signals of the Slow double - edge counting unit and the Fast double - edge counting unit. The feedback counting latch is composed of a single D - flip - flop, the data input terminal is at high level, and the clock input signal is connected to the output of the double - edge phase discriminator. Since the output of the double - edge phase discriminator may be a multi - pulse signal, after passing through the feedback counting latch, only the first rising edge of the output of the double - edge phase discriminator is extracted as the final latch signal. At the same time, the inverted output of the feedback counting latch is connected to the pulse shaping unit and the clock synchronization unit. Once entering the latch state, the ring oscillation stops immediately.

[0077] The counting calibration unit is used to calibrate the data of the fine counting unit and the coarse counting unit, and the data combination and storage transmission unit is used to output the overall time measurement result.

[0078] As Figure 3 shown, DFF1 and DFF2 are used to detect the 0° synchronous position of the phases of the slow - loop part and the fast - loop part, and DFF3 and DFF4 are used to detect the 180° synchronous position of the phases of the slow - loop part and the fast - loop part.

[0079] The clock input terminal of DFF1 is the oscillation output of the fast - loop part, and the data input terminal is the oscillation output of the slow - loop part. The clock input terminal of DFF2 is the oscillation output of the slow - loop part, and the data input terminal is the oscillation output of the fast - loop part. As Figure 4 (1) shown, let the initial phases of the fast - loop part and the slow - loop part be and The phase detection results are shown in Table 1 below:

[0080] Table 1 Phase detection results of Q1 and Q2

[0081] Q1 Q2 Phase relationship 1 0 Leading 1 1 In phase with 0° 0 1 Lagging

[0082] When the outputs of Q1 and Q2 are ANDed through an AND gate and the output is 1, it indicates that phase synchronization is achieved at point A. At this time, the counting latch result output is 1, and the counting results of the fast loop part and the slow loop part are latched.

[0083] The clock input terminal of DFF3 is the inverted oscillation output of the fast loop part, and the data input terminal is the oscillation output of the slow loop part. The clock input terminal of DFF4 is the inverted oscillation output of the slow loop part, and the data input terminal is the oscillation output of the fast loop part. As Figure 4 (2) shows, let the initial phases of the fast loop part and the slow loop part be and The phase detection results are shown in Table 2 below: Table 2 Phase detection results of Q3 and Q4

[0084] Q3 Q4 Phase relationship 1 0 Leading 1 1 In phase with 180° 0 1 Lagging

[0085] When the outputs of Q3 and Q4 are ANDed through an AND gate and the output is 1, it indicates that phase synchronization is achieved at point B. At this time, the counting latch result output is 1, and the counting results of the fast loop part and the slow loop part are latched.

[0086] As Figure 3 shown, the delay units τ1 and τ2 in the double-edge phase detector are used to adjust the phase detection output and shape the output pulse of the AND gate.

[0087] As Figure 4 shown, the double-edge phase detector outputs the phase detection position through an OR gate. When the phase is first output at the 0° synchronization position; when , the phase is first output at 180° synchronization, and the time interval to be measured can be controlled within half a cycle.

[0088] The input of the feedback counting latch is the output of the double-edge phase detector. Since there may be multiple phase synchronization positions in the double-edge phase detector, it is necessary to use the feedback counting latch to only output the first rising edge position as the final phase detection result. When the data combination and the timing result of the storage and transmission unit are completed, the feedback counting latch is reset.

[0089] The present invention also provides a fast TDC measurement method based on a differential carry chain, including the following steps:

[0090] S1. The echo start pulse signal is first converted into a single-edge signal by the pulse shaping unit, which drives the slow-loop oscillation loop to generate oscillations. The Slow dual-edge counting unit starts to count the rising and falling edges of the slow-loop part. Then, the echo start pulse signal extracts the clock synchronization signal through the clock synchronization unit, which drives the fast-loop oscillation loop to generate oscillations. The Fast dual-edge counting unit starts to count the rising and falling edges of the fast-loop part;

[0091] S2. When the clock synchronization signal of the echo start pulse signal is detected, the coarse counting unit starts to count from the rising edge of the system clock;

[0092] S3. The dual-edge phase detector detects the coincidence moment of the rising edge - rising edge or rising edge - falling edge of the fast-loop part and the slow-loop part, and outputs a high level to the feedback counting latch; the feedback counting latch outputs the first rising edge of the extracted multi-edge signal;

[0093] S4. After the Slow dual-edge counting unit and the Fast dual-edge counting unit detect the rising edge of the latch signal, they stop counting; when the pulse shaping unit and the clock synchronization unit detect the reverse output of the latch signal, they trigger the data clear terminal clrn of the D flip-flop, pull down the output level, and wait for the next measurement input;

[0094] S5. After the counting data is calibrated, it enters the data combination and storage transmission unit, outputs the measurement completion flag signal of the Start part fine counting unit, and all counting units enter the zero state, waiting for the next measurement by the Stop part fine counting unit;

[0095] S6. The echo stop pulse signal is the same as the echo start pulse signal, and steps S1 - S5 are repeated;

[0096] S7. When the clock synchronization signal of the echo stop pulse signal is detected, the coarse counting unit stops counting;

[0097] S8. Combining the measurement results of the coarse counting unit once and the measurement results of the Start and Stop fine counting units completes a time measurement, and the result expression is:

[0098] T coarse =N coarse T sys_clk

[0099]

[0100] T=T coarse +T start_fine -T stop_fine

[0101] where T sys_clk ,T slow_roand T fast_ro represent the oscillation period time of the system clock, the slow-loop part, and the fast-loop part respectively; T is the overall measured time of flight, representing the measurement results of data combination, storage, and transmission. T coarse is the main part time of the wide-range time measured by the coarse counting unit. T start_fine and T stop_fine represent the start fine time and the stop fine time of the remaining edge part of the measurement time respectively; N coarse represents the count value of the coarse counting unit. N slow_start and N fast_start represent the double-edge count values of the double edges of the slow-loop part and the fast-loop part of the echo start pulse signal respectively. N slow_stop and N fast_stop represent the double-edge count values of the double edges of the slow-loop part and the fast-loop part of the echo stop pulse signal respectively;

[0102] S9. Repeat steps S1 - S8 to continuously measure the time of flight in a loop.

[0103] In this embodiment, the present invention is implemented on Altera FPGA. The design tools are Quartus II 15.0 version and Modelsim 10.7 version. The Quartus software provided by Altera Corporation includes the LogicLock logic locking function design and the TIMEQuest timing analysis tool, which can use the Assignment editor to perform Location constraints on the relevant structures and can view the specific layout content in the ChipPlanner. Similarly, the relevant principle content of this solution can also be implemented through the design of other models of FPGA such as Xilinx.

[0104] The specific implementation steps are as follows:

[0105] (1) To obtain two oscillation loops with close frequencies, utilize the difference in the characteristics of the carry chain structure or construct different numbers of delay chain structures to obtain stable oscillation loops with close frequencies.

[0106] (2) Build the specific TDC design scheme according to the structure shown, and design the specific circuit in combination with tools such as ChipPlanner.

[0107] (3) Use a signal generator or the internal phase-locked loop of the FPGA to generate a stable square wave signal, input it to the stop / start port and connect it to an oscilloscope for testing and observation to determine whether a stable oscillation loop is formed, and determine the oscillation frequencies of the fast-loop part and the slow-loop part as f s and f k , and obtain the oscillation period of the slow-loop part as T s .

[0108] (4) Simulate the start signal with a large number of random pulse signals, set the number of samples to 200,000 times, and the counting result distribution of the fine counting units in the fast loop part is as follows Figure 5 as shown.

[0109] (5)

[0110] (6) Calculate the resolution of the fast loop part by the formula as 2218 (half period of the slow loop part) / 43 (distribution series) = 51.6 ps. In fact, the statistical result shows that the rising edge of the fast loop part coincides with the rising edge or falling edge of the slow loop part. Therefore, the statistical count of the fast loop part shows the characteristic of odd distribution. For the convenience of time calibration, compress the count of the fast loop part to N' k , and the relationship between the compressed count value and the original count value N k satisfies

[0111] (7) The differential non - linearity and integral non - linearity of the fast loop part obtained are as follows Figure 6 and Figure 7 as shown. It can be seen from the experimental results that for the timestamp results measured by the ring - carry - chain TDC circuit based on the fine - delay phase - shift structure of the present invention, both DNL and INL are within the range of (-0.5 LSB, 0.5 LSB). Compared with the tapped - type TDC circuit, the DNL and INL results obtained by the present invention are relatively low. Since the oscillation number range of the TDC of this structure is 86 and it is compressed to 43 after compression.

[0112] (8) Construct a look - up table structure. Similarly, obtain the fast loop part of the stop part in the same way as above, and establish a look - up table structure for the stop part to calibrate each level of the fine counting unit.

[0113] (9) Independently establish a multi - stage carry - link structure, adjust the number of carry - chain stages, use it as a precision - measurement delay line, and obtain delay times of 5 ns and 10 ns respectively for this test.

[0114] (10) The precision test analysis is as follows Figure 8 as shown. The measured time mean value at about 5 ns of time delay is 5.14 ns, and the variance is 48.2 ps. The measured time mean value at 10 ns is 10.36 ns, and the variance is 49.6 ps. The result obtained by using the double - edge phase - detector structure is 48 ps. Changing the phase - detector structure to only use the single - edge phase - detector, the RMS precision is about 70 ps. In contrast, the improvement effect of the double - edge phase - detector structure is significantly improved.

[0115] (11) The ring - carry chain TDC circuit based on fine - delay phase - shift measurement proposed by the present invention can reduce the maximum oscillation period number and the count value of the fine - counting unit by half, thus significantly reducing the RMS error and improving the resolution. It can be seen from the experimental results that this circuit structure improves the accuracy from the order of 70 ps to the order of 48 ps, and has good integral non - linearity and differential non - linearity. The present invention can be widely applied to high - precision time - interval measurement and related fields.

[0116] Therefore, by adopting the above - mentioned fast TDC measurement system and method based on a differential carry chain, the present invention can effectively reduce the oscillation times of the ring oscillator, improve the measurement accuracy of the fine - counting unit and the conversion time.

[0117] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions of the present invention or make equivalent replacements, and these modifications or equivalent replacements do not make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A fast TDC measurement system based on a differential carry chain, characterized in that: It includes a coarse counting unit, a fine counting unit, a counting calibration unit, a data combination, and a storage and transmission unit; The fine counting unit specifically includes a pulse shaping unit, a clock synchronization unit, a ring oscillator, a double-edge phase detector, a feedback counting latch, a Slow double-edge counting unit, and a Fast double-edge counting unit; The ring oscillator includes a fast loop part and a slow loop part composed of a carry chain, NOT gates, and AND gates; The input end of the AND gate in the slow loop part is connected to the input and output end of the pulse shaping unit and the reverse input end of the oscillation signal in the slow loop part, and the input end of the AND gate in the fast loop part is connected to the input and output end of the clock synchronization unit and the reverse input end of the oscillation signal in the fast loop part; The double-edge phase detector is composed of a rising edge-rising edge edge coincidence detection part and a rising edge-falling edge edge coincidence detection part; The rising edge-rising edge edge coincidence detection part is composed of two-stage D flip-flops. The outputs of the fast loop part and the slow loop part are the clock input and data input of the first-stage D flip-flop, and the data input and clock input of the second-stage D flip-flop. The first-stage D flip-flop and the second-stage D flip-flop pass through a delay unit and are output through an AND gate; The rising edge-falling edge edge coincidence detection part is also composed of two-stage D flip-flops. The outputs of the fast loop part and the slow loop part are the reverse clock input and data input of the first-stage D flip-flop, and the data input and reverse clock input of the second-stage D flip-flop. The first-stage D flip-flop and the second-stage D flip-flop pass through a delay unit and are output through an AND gate; The output ends of the AND gates in the rising edge-rising edge edge coincidence detection part and the rising edge-falling edge edge coincidence detection part are output through an OR gate; 2. The fast TDC measurement system based on a differential carry chain according to claim 1, wherein: The coarse counting unit is a two-stage counter, including a low-order counter and a high-order counter. The low-order counter is a Gray code counter, and the output end of the low-order counter is connected to the input end of the high-order counter; 3. A fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: The pulse shaping unit is composed of a single-level D flip-flop. The clock input end of the D flip-flop is connected to the echo start or stop pulse signal, the data input end is connected to a high level, and the data clear end clrn is connected to the reverse output end real_locked of the double-edge phase detector; 4. A fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: The clock synchronization unit is a three-bit shift register structure, including a first-stage D flip-flop, a second-stage D flip-flop, and a third-stage D flip-flop; Among them, the clock input end of the first-stage D flip-flop is connected to the echo start or stop pulse signal, the data input end is connected to a high level, and the data clear end clrn is connected to the reverse output end real_locked of the double-edge phase detector; The clock input end of the second-stage D flip-flop is connected to the system clock signal, and the data input end is connected to the data output end of the first-stage D flip-flop; The clock input end of the third-stage D flip-flop is connected to the system clock signal, and the data input end is connected to the data output end of the second-stage D flip-flop; 5. A fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: The fast loop part and the slow loop part are composed of carry chains with different delay times. The period of the slow loop part is greater than that of the fast loop part; 6. The fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: The feedback counting latch is composed of a D flip-flop. The data input end is connected to a high level, and the clock input end is connected to the output end of the double-edge phase detector; The reverse output of the feedback counting latch is connected to the pulse shaping unit and the clock synchronization unit; 7. A fast TDC measurement system based on a differential carry chain according to claim 1, characterized in that: The structures of the Slow dual-edge counting unit and the Fast dual-edge counting unit are the same as that of the coarse counting unit.

8. A fast TDC measurement method based on a differential carry chain, characterized in that, It includes the following steps: S1. The echo start pulse signal is first converted into a single-edge signal by the pulse shaping unit, which drives the oscillation loop of the slow loop part to generate oscillation. The Slow dual-edge counting unit starts to count the rising edges and falling edges of the slow loop part. Then, the echo start pulse signal extracts the clock synchronization signal through the clock synchronization unit, which drives the oscillation loop of the fast loop part to generate oscillation. The Fast dual-edge counting unit starts to count the rising edges and falling edges of the fast loop part. S2. When the clock synchronization signal of the echo start pulse signal is detected, the coarse counting unit starts to count from the rising edge of the system clock. S3. The dual-edge phase detector detects the coincidence moment of the rising edge-rising edge or rising edge-falling edge of the fast loop part and the slow loop part, and outputs a high level to the feedback counting latch; the feedback counting latch outputs the first rising edge of the extracted multi-edge signal. S4. When the Slow dual-edge counting unit and the Fast dual-edge counting unit detect the rising edge of the latch signal, they stop counting. When the pulse shaping unit and the clock synchronization unit detect the reverse output of the latch signal, they trigger the data clear terminal clrn of the D flip-flop, pull down the output level, and wait for the next measurement input. S5. After the counting data is calibrated, it enters the data combination and storage and transmission unit, outputs the measurement completion flag signal of the Start part fine counting unit, and all counting units enter the zero state, waiting for the next measurement by the Stop part fine counting unit. S6. The echo stop pulse signal is the same as the echo start pulse signal, and steps S1 - S5 are repeated. S7. When the clock synchronization signal of the echo stop pulse signal is detected, the coarse counting unit stops counting. S8. Combining the measurement results of the coarse counting unit once and the measurement results of the Start and Stop fine counting units completes one time measurement. The result expression is: T coarse = N coarse T sys_clk T = T coarse + T start_fine - T stop_fine Among them, T sys_clk , T slow_ro and T fast_ro respectively represent the oscillation period times of the system clock, the slow loop part and the fast loop part; T is the overall measured time of flight, representing the data combination and storing the transmitted measurement result, T coarse is the main part time of the wide-range time measured by the coarse counting unit, T start_fine and T stop_fine respectively represent the starting fine time and the stopping fine time of the remaining edge part of the measurement time; N coarse represents the count value of the coarse counting unit, N slow_start and N fast_start respectively represent the double-edge count values of the double edges of the slow loop part and the fast loop part of the echo start pulse signal, N slow_stop and N fast_stop respectively represent the double-edge count values of the double edges of the slow loop part and the fast loop part of the echo stop pulse signal; S9. Repeat steps S1 - S8 to continuously measure the flight time in a loop.

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