A memory access method, device cache consistency access system and chip

Abstract

The present application provides a memory access method, a device cache consistency access system and a chip, the method comprising: upon receiving a memory access request sent by a peripheral device, determining whether the memory access request participates in cache consistency sharing, and when determining that the memory access request does not participate in cache consistency sharing, shunting the memory access request to a memory bus, and responding to the memory access request through the memory bus. In this way, the memory bandwidth occupied by the peripheral device can be reduced, thereby improving the memory access efficiency of the processor, and further improving the efficiency of the device cache consistency access system.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and more specifically, to a memory access method, a device cache consistency access system and a chip. Background Art

[0002] Currently, in order to improve computing efficiency, a larger number of processors are set in the device cache consistency access system. In order to ensure cache consistency between processors, the caches of each processor in the device cache consistency access system are connected through a cache bus.

[0003] Some peripheral devices are usually set up in the device cache consistency access system. The peripheral devices can access the memory in the device cache consistency access system through direct memory access. In order to improve the data access efficiency of the peripheral devices, one method is to connect the peripheral devices to the cache bus so that the peripheral devices can quickly access the data in the memory through the cache bus. When the peripheral devices are connected to the cache bus, the memory access requests of the peripheral devices will participate in the cache consistency sharing process between the processors, which may occupy part of the bandwidth of the processor to access the memory, thereby reducing the memory access efficiency of the processor. Summary of the invention

[0004] The present application provides a memory access method, a device cache consistency access system and a chip, which can reduce the memory bandwidth occupied by peripheral devices and improve the memory access efficiency of the processor.

[0005] In a first aspect, a memory access method is provided, the method comprising:

[0006] Receive memory access requests sent by peripheral devices;

[0007] Determining whether the memory access request participates in cache coherence sharing;

[0008] If not, the memory access request is shunted to a memory bus, so as to respond to the memory access request through the memory bus.

[0009] In the embodiment of the present application, when a memory access request sent by a peripheral device is received, it is first determined whether the memory access request participates in cache consistency sharing. When it is determined that the memory access request does not participate in cache consistency sharing, the memory access request is shunted to the memory bus, and the memory access request is responded to through the memory bus. In this way, the memory bandwidth occupied by the peripheral device can be reduced, thereby improving the memory access efficiency of the processor, and further improving the efficiency of the device cache consistency access system.

[0010] Optionally, determining whether the memory access request participates in cache consistency sharing includes: obtaining sharing attribute information; wherein the sharing attribute information indicates whether the memory access request participates in cache consistency sharing or does not participate in cache consistency sharing; and determining whether the memory access request participates in cache consistency sharing based on the sharing attribute information.

[0011] Optionally, obtaining shared attribute information includes: determining a memory access mode pre-configured for the peripheral device; when the memory access mode is a first memory access mode, obtaining the shared attribute information included in the memory access request; when the memory access mode is a second memory access mode, obtaining the shared attribute information pre-configured for the peripheral device.

[0012] Optionally, before receiving the memory access request sent by the peripheral device, the method also includes: if it is determined that a part of the memory access requests sent by the peripheral device participate in cache consistency sharing and another part of the memory access requests do not participate in cache consistency sharing, then configure the memory access mode to the first memory access mode; or, if it is determined that each of the memory access requests sent by the peripheral device participates in cache consistency sharing, then configure the memory access mode to the second memory access mode, and configure the sharing attribute information for the peripheral device to the first sharing attribute information; wherein the first sharing attribute information is the sharing attribute information indicating that the memory access request participates in cache consistency sharing; or, if it is determined that each of the memory access requests sent by the peripheral device does not participate in cache consistency sharing, then configure the memory access mode to the second memory access mode, and configure the sharing attribute information for the peripheral device to the second sharing attribute information; wherein the second sharing attribute information is the sharing attribute information indicating that the memory access request does not participate in cache consistency sharing.

[0013] Optionally, determining whether the memory access request participates in cache consistency sharing includes: determining a first memory space accessed by the memory access request and a second memory space currently accessed by the processor; and when the first memory space overlaps with the second memory space, determining that the memory access request participates in cache consistency sharing.

[0014] Optionally, the method further includes: if the memory access request participates in cache coherence sharing, the memory access request is diverted to a cache bus, so as to respond to the memory access request through the cache bus.

[0015] In a second aspect, a chip is provided, including:

[0016] A plurality of processors, caches of the plurality of processors are interconnected via a cache bus, and the cache bus is connected to the memory of the chip via a memory bus;

[0017] A shunt module, the shunt module is connected to the cache bus and the memory bus respectively, and the shunt module is connected to the peripheral device of the chip, and the shunt module is used to execute the memory access method as described in the first aspect.

[0018] Optionally, the diversion module includes a distributor and a splitter; the distributor is connected to the peripheral device and the memory bus respectively, and is used to divert the memory access request to the memory bus when the memory access request does not participate in cache consistency sharing; the distributor is also connected to the splitter, and is used to divert the memory access request to the splitter when the memory access request participates in cache consistency sharing; the splitter is connected to the cache bus, and is used to split the memory access request into at least one sub-memory access request, and send the sub-memory access request to the cache bus, each of the sub-memory access requests corresponding to a memory row accessed by the memory access request.

[0019] Optionally, the diversion module also includes a bit width converter; the bit width converter is connected to the distributor and the splitter respectively, and is used to perform bit width conversion on the memory access request output by the distributor when the bit width of the memory access request is greater than the bit width of the cache bus, so as to obtain and send the converted memory access request to the splitter; wherein the bit width of the converted memory access request matches the bit width of the cache bus.

[0020] Optionally, the allocator includes a logic unit, a cache array, a first selector, and a second selector; the cache array is used to store flag information corresponding to the memory access request, and the flag information is used to identify whether the memory access request participates in cache consistency sharing or does not participate in cache consistency sharing;

[0021] The distributor is connected to the peripheral device, the cache array and the splitter respectively, and is used to obtain the flag information corresponding to the memory access request from the cache array after receiving the memory access request, and to divert the memory access request to the memory bus or the splitter according to the flag information; the first selector is connected to the splitter, the memory bus, the peripheral device and the cache array respectively, and is used to send the data read by the memory access request returned by the splitter or the memory bus to the peripheral device based on the flag information corresponding to the memory access request stored in the cache array when the memory access request is a read request; the second selector is connected to the splitter, the memory bus, the peripheral device and the cache array respectively, and is used to send the response information of the memory access request returned by the splitter or the memory bus to the peripheral device based on the flag information corresponding to the memory access request stored in the cache array when the memory access request is a write request.

[0022] In a third aspect, a device cache consistency access system is provided, comprising the chip as described in the second aspect above.

[0023] In a fourth aspect, a memory access device is provided, the device comprising:

[0024] A receiving module, used for receiving a memory access request sent by a peripheral device;

[0025] A determination module, used to determine whether the memory access request participates in cache coherence sharing;

[0026] The shunt module is used for, if not, shunt the memory access request to a memory bus, so as to respond to the memory access request through the memory bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural diagram of a device cache consistency access system in the related art;

[0028] Figure 2 It is a structural diagram of a device cache consistency access system provided by an embodiment of the present application;

[0029] Figure 3 is a flowchart of a memory access method provided by an embodiment of the present application;

[0030] Figure 4 It is a structural diagram of another device cache consistency access system provided by an embodiment of the present application;

[0031] Figure 5It is a structural diagram of a device cache consistency access system provided by an embodiment of the present application;

[0032] Figure 6 It is a structural diagram of a device cache consistency access system provided by an embodiment of the present application;

[0033] Figure 7 It is a schematic diagram of the principle of a diversion module provided in an embodiment of the present application;

[0034] Figure 8 It is a structural diagram of a memory access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solution in the present application will be described clearly and in detail below in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0037] In a complex device cache coherent access system, one or more chips for computing are usually set up, and each chip is set up with one or more processors. The chip is also surrounded by memory and some peripheral devices, such as Peripheral Component Interconnect Express (PCIE) devices, Graphics Processing Unit (GPU) and Field-Programmable Gate Array (FPGA), but not limited to these.

[0038] See also Figure 1 , Figure 1 Schematic diagram of a device cache consistency access system in the related art. Figure 1As shown, the system is provided with a chip 11, and a memory 12 and at least one peripheral device 13 are provided on the periphery of the chip 11. A cache bus, a memory bus and at least one core 111 are provided on the chip 11. One or more clusters (Cluste) are provided in each core 111, and each cluster constitutes a processor. The processor includes at least one core (core), a sniffing filter (SnoopFilter) and a third-level cache (L3 Cache), etc. Each core includes a first-level cache (L1 Cache) and a second-level cache (L2Cache).

[0039] The cache bus is also called the Cache Coherent Interconnnect (CCI) bus. To ensure cache consistency between processors, the three-level cache in each processor is connected to the cache bus. The cache bus can realize cache consistency sharing between multiple processors, so that the data in the same memory row remains consistent in different three-level caches to achieve cache consistency between processors. Memory buses, such as the Advanced eXtensible Interface (AXI) bus, are used to connect memory and cache buses and provide data in memory to the cache bus.

[0040] like Figure 1 As shown, in order to improve the data access efficiency of peripheral devices, peripheral devices can be connected to the cache bus so that the peripheral devices can access the memory through direct memory access (DMA). When the peripheral device accesses the memory through the cache bus, the memory access request of the peripheral device will participate in the cache consistency sharing process between the processors, which may occupy part of the bandwidth of the processor to access the memory, thereby reducing the memory access efficiency of the processor, and further reducing the efficiency of the entire device cache consistency access system.

[0041] It should be noted that the chip in the embodiment of the present application may be a chip integrating multiple core particles, or may be a single core particle.

[0042] In order to solve the above technical problems, an embodiment of the present application provides a memory access method. In this method, when the chip receives a memory access request sent by a peripheral device, it first determines whether the memory access request participates in cache consistency sharing. If it does not participate in cache consistency sharing, the memory access request is diverted to the memory bus to respond to the memory access request through the memory bus.

[0043] In an embodiment of the present application, when a memory access request of a peripheral device does not participate in cache consistency sharing, the memory access request is diverted to the memory bus, and the memory access request is responded to through the memory bus. This can reduce the memory bandwidth occupied by the peripheral device, thereby improving the memory access efficiency of the processor, and further improving the efficiency of the device cache consistency access system.

[0044] The memory access request participating in cache coherence sharing means that the memory space accessed by the memory access request (hereinafter referred to as the first memory space) may overlap with the memory space accessed by the processor (hereinafter referred to as the second memory space). Peripheral devices generally access memory in units of rows, so the first memory space includes one or more memory rows, which may need to participate in the cache coherence sharing process between processors.

[0045] In actual applications, the processor accesses data in memory in units of bytes. When accessing data in memory, the processor reads all the data in the memory row where the byte data to be accessed is located and stores it in the corresponding cache row, and reads the byte data to be accessed from the cache row. At the same time, the processor can store data in one or more memory rows in the cache. The memory space composed of one or more memory rows in the cache where the data is read and stored is the second memory space. When the first memory space overlaps with the second memory space, one or more memory rows in the first memory space are memory rows in the second memory space. That is, when the first memory space overlaps with the second memory space, in order to keep the data in the same memory row consistent in different caches, the data in some or all memory rows in the first memory space may need to participate in the cache consistency sharing process between the processors.

[0046] In order to implement the memory access method provided in the embodiment of the present application, the embodiment of the present application also provides a chip, which includes multiple processors and a shunt module, the caches of the multiple processors are interconnected through a cache bus, and the cache bus is connected to the memory of the chip through a memory bus. The shunt module is connected to the cache bus and the memory bus respectively, and the shunt module is connected to the peripheral devices of the chip.

[0047] It should be noted that the cache in the embodiment of the present application refers to the cache in multiple processors that participates in cache coherence sharing. Figure 1 For example, the third-level caches of multiple processors are interconnected through a cache bus, and cache consistency sharing is achieved through the cache bus. Therefore, the memory access method and the cache in the memory access chip provided in this application refer to Figure 1 The device cache coherence shown accesses the third level cache in the system.

[0048] See also Figure 2 , Figure 2Schematic diagram of a device cache consistency access system provided by an embodiment of the present application. Figure 2 As shown, the system includes a chip 21, and a memory 22 and a peripheral device 23 arranged on the periphery of the chip 21. A core particle 211 and a diversion module 212 are arranged in the chip 21. The core particle 211 includes multiple clusters, and each cluster is provided with multiple cores, a sniffer filter and a three-level cache. Each cluster constitutes a processor, and the three-level cache in the processor has a cache interface, and the cache interface can be an Advanced eXtensible Interface Coherency Extensions (ACE) interface. The cache interface of each three-level cache is connected to the cache bus, so that the three-level caches in multiple processors can be interconnected through the cache bus. The cache bus is connected to the memory bus, and the memory bus is connected to the memory 22. When the processor accesses the data in the memory 22, it can access the data in the memory through the interconnected cache bus and memory bus.

[0049] like Figure 2 As shown, the diversion module 212 is connected to the memory bus and the cache bus respectively. The diversion module 212 is also connected to the peripheral device 23 outside the chip. The diversion module 212 can receive a memory access request sent by the peripheral device. After receiving the memory access request, the diversion module 212 first determines whether the memory access request participates in cache consistency sharing. If it does not participate in cache consistency sharing, the memory access request is diverted to the memory bus to respond to the memory access request through the memory bus.

[0050] like Figure 2 As shown, responding to a memory access request through a memory bus means shunting the memory access request to the memory bus, and directly reading data from the memory row accessed by the memory access request or writing data to the memory row accessed by the memory access request through the memory bus. Correspondingly, responding to a memory access request through a cache bus means shunting the memory access request to the cache bus, accessing the memory through the interconnected cache bus and memory bus, and reading data from the cache row accessed by the memory access request or writing data to the cache row accessed by the memory access request.

[0051] It should be noted that the memory access method provided in the embodiment of the present application can be Figure 2 The process is performed by the diversion module in the chip shown, and may also be performed by other parts in the chip, such as a cache bus, which is not limited in this embodiment.

[0052] See also Figure 3 , Figure 3is a flowchart of the steps of a memory access method provided by an embodiment of the present application. The method is applied to a chip having multiple processors, the chip including a shunt module and a cache, and the method can be executed by the shunt module, such as Figure 3 As shown, the method comprises the following steps:

[0053] Step 301: Receive a memory access request sent by a peripheral device.

[0054] In this embodiment, the peripheral device outside the chip is connected to the shunt module in the chip. When the peripheral device accesses the data in the memory, it can access the data in the memory in units of rows through direct memory access, accessing the data of one or more consecutive memory rows in the memory each time. In the process of accessing the memory, the peripheral device can first send a memory access request to the shunt module.

[0055] Step 302: Determine whether the memory access request participates in cache coherence sharing.

[0056] Step 303: If not, the memory access request is diverted to the memory bus to respond to the memory access request through the memory bus.

[0057] In this embodiment, after receiving a memory access request, the shunting module first determines whether the memory access request participates in cache consistency sharing. If it participates in cache consistency sharing, the memory access request is shunted to the cache bus, and the memory access request is responded to through the cache bus. If it does not participate in cache consistency sharing, the memory access request is shunted to the memory bus, and the memory access request is responded to through the memory bus.

[0058] Optionally, step 302 may include:

[0059] Determine a first memory space accessed by a memory access request and a second memory space currently accessed by a processor;

[0060] In a case where the first memory space overlaps with the second memory space, it is determined that the memory access request participates in cache coherence sharing.

[0061] In one embodiment, after receiving a memory access request, the diversion module can directly determine the first memory space accessed by the memory access request based on the memory access request. For example, when the memory access request is a write request and data in at least one memory row needs to be written into the memory, the memory access request includes a source address, a target address, a data length, and other information, the source address is the starting address of the data to be written into the memory in the peripheral device, the target address is the first address of at least one memory row in the memory for storing the data to be written, and the data length corresponds to the number of memory rows. After receiving the memory access request, the diversion module can determine the position of each memory row of the data to be written in the memory based on the target address and the data length, and the memory space composed of all memory rows of the data to be written is the first memory space.

[0062] Similarly, when the memory access request is a read request and data in at least one memory row needs to be read from the memory, the memory access request includes a source address, a target address, a data length, and other information. At this time, the source address is the starting address of at least one memory row to be read in the memory, the target address is the address in the peripheral device for storing data in at least one memory row to be read, and the data length corresponds to the number of memory rows to be read. After receiving the memory access request, the shunt module can determine the position of each memory row to be read in the memory based on the source address and the data length. The memory space composed of all memory rows to be read is the first memory space.

[0063] The shunt module can be connected to the cache interface of the cache included in each processor to monitor the memory lines stored in the cache. Each cache line in the cache is used to store data in the corresponding multiple memory lines. When the shunt module monitors that the data in a certain memory line is read and stored in the corresponding cache line, it determines that the memory line is a memory line in the second memory space, that is, the memory space composed of all memory lines where data is stored in the cache is the second memory space.

[0064] After determining the first memory space and the second memory space, the diversion module determines whether the first memory space and the second memory space include the same memory rows. If they include the same memory rows, it is determined that the first memory space and the second memory space overlap. If they do not include the same memory rows, it is determined that the first memory space and the second memory space do not overlap.

[0065] Further, when the first memory space and the second memory space do not overlap, it is determined that the memory access request does not participate in cache consistency sharing, the memory access request is shunted to the memory bus, and the memory access request is responded to through the memory bus. And, when the first memory space and the second memory space overlap, it is determined that the memory access request participates in cache consistency sharing, the memory access request is shunted to the cache bus, and the memory access request is responded to through the cache bus.

[0066] It should be noted that when determining that a memory access request participates in cache coherence sharing, it only means that the first memory space accessed by the memory access request may overlap with the second memory space accessed by the processor, and does not mean that the first memory space and the second memory space must overlap.

[0067] In the embodiment of the present application, when a memory access request sent by a peripheral device is received, it is first determined whether the memory access request participates in cache consistency sharing. When it is determined that the memory access request does not participate in cache consistency sharing, the memory access request is shunted to the memory bus, and the memory access request is responded to through the memory bus. In this way, the memory bandwidth occupied by the peripheral device can be reduced, thereby improving the memory access efficiency of the processor, and further improving the efficiency of the device cache consistency access system.

[0068] It should be noted that the memory access method provided in the embodiment of the present application is not only applicable to a single chip including multiple processors, but also to multiple chips connected through a cache bus.

[0069] See also Figure 4 , Figure 4 Schematic diagram of another device cache consistency access system provided by an embodiment of the present application. Figure 4 As shown, the device cache consistency access system includes two chips 21, each chip 21 is provided with a corresponding memory 22 and a peripheral device 23 at the periphery, and each chip 21 is provided with a core particle 211 and a diversion module 212.

[0070] In the device cache coherent access system, multiple chips can share one memory. Alternatively, when each chip is provided with a corresponding memory, multiple memories of multiple chips use a unified memory space, and the multiple memories are physically divided into multiple memories, but logically are one memory, so that each processor in the device cache coherent access system can access any memory in the device cache coherent access system.

[0071] like Figure 4As shown, when the shunt module in one of the chips 21 receives a memory access request, when the memory access request participates in cache coherence sharing, the memory access request can be shunted to the cache bus of the chip where it is located, and the cache bus of the chip where it is located is interconnected with the cache bus of other chips, and the memory access request can be responded to. When the memory access request does not participate in cache coherence sharing, the memory access request is shunted to the memory bus of the chip where it is located, and the memory access request is responded to through the memory bus of the chip where it is located.

[0072] Optionally, step 302 may include:

[0073] Acquire sharing attribute information; wherein the sharing attribute information indicates whether the memory access request participates in cache coherence sharing or does not participate in cache coherence sharing;

[0074] Whether the memory access request participates in cache coherence sharing is determined based on the sharing attribute information.

[0075] Exemplarily, a DMA controller is provided in the processor, and the DMA controller is connected to the peripheral device and is used to initiate a DMA request of the peripheral device. Before executing each task, the processor can initialize the DMA controller and configure corresponding sharing attribute information for each memory access request issued by the peripheral device during the task execution.

[0076] For example, for each memory access request issued by a peripheral device during task execution, the first memory space accessed by the memory access request can be determined, and it can be determined whether the first memory space overlaps with the second memory space accessed by the processor during task execution. For each memory access request, if the first memory space accessed by the memory access request overlaps with the second memory space, the sharing attribute information of the memory access request is set to the first sharing attribute information, and the memory access request during task execution is identified by the first sharing attribute information as participating in cache coherence sharing.

[0077] On the contrary, for each memory access request, if the first memory space accessed by the memory access request does not overlap with the second memory space, the sharing attribute information of the memory access request is set to the second sharing attribute information, and the second sharing attribute information is used to indicate that the memory access request does not participate in cache consistency sharing during task execution.

[0078] After the processor starts executing the task, the peripheral device sends a memory access request to the diversion module during the task execution process. The memory access request may include shared attribute information corresponding to the memory access request, and the shared attribute information is the pre-configured first shared attribute information or the second shared attribute information. After receiving the memory access request, the diversion module can obtain the shared attribute information from the memory access request. If the shared attribute information is the first shared attribute information, it is determined that the memory access request participates in cache consistency sharing, and the memory access request is diverted to the cache bus, and the memory access request is responded to through the cache bus. If the shared attribute information is the second shared attribute information, it is determined that the memory access request does not participate in cache consistency sharing, and the memory access request is diverted to the memory bus, and the memory access request is responded to through the memory bus.

[0079] In an embodiment of the present application, by determining whether a memory access request participates in cache consistency sharing through the sharing attribute information of the memory access request, it is possible to quickly and accurately determine whether the memory access request participates in cache consistency sharing, thereby quickly diverting the memory access request to the memory bus or the cache bus.

[0080] Optionally, before receiving the memory access request sent by the peripheral device, the method may further include:

[0081] If it is determined that a part of the memory access requests sent by the peripheral device participate in cache coherence sharing and another part of the memory access requests do not participate in cache coherence sharing, configuring the memory access mode to be the first memory access mode;

[0082] Alternatively, if it is determined that each memory access request sent by the peripheral device participates in cache coherence sharing, the memory access mode is configured as the second memory access mode, and the sharing attribute information configured for the peripheral device is the first sharing attribute information; wherein the first sharing attribute information is sharing attribute information indicating that the memory access request participates in cache coherence sharing;

[0083] Alternatively, if it is determined that each memory access request sent by the peripheral device does not participate in cache consistency sharing, the memory access mode is configured as a second memory access mode, and the sharing attribute information for the peripheral device is configured as second sharing attribute information; wherein the second sharing attribute information is sharing attribute information indicating that the memory access request does not participate in cache consistency sharing.

[0084] The multiple memory access requests sent by the peripheral device refer to the multiple memory access requests sent by the peripheral device when executing a task. There are two situations for the multiple memory access requests. The first situation is that some of the multiple memory access requests participate in cache consistency sharing, and the other memory access requests do not participate in cache consistency sharing. The second situation is that none of the multiple memory access requests participate in cache consistency sharing or all participate in cache consistency sharing.

[0085] In one embodiment, before starting to execute each task, the processor configures the memory access mode of the peripheral device to the first memory access mode for the first case above. At the same time, corresponding sharing attribute information is configured for each memory access request. When the memory access request participates in cache consistency sharing, the sharing attribute information is configured as the first sharing attribute information. When the memory access request does not participate in cache consistency sharing, the sharing attribute information is configured as the second sharing attribute information. In this way, when the peripheral device sends a memory access request, it can carry the corresponding sharing attribute information in the memory access request.

[0086] For the second case above, if all memory access requests participate in cache coherence sharing, unified sharing attribute information is configured for all memory access requests during task execution (i.e., sharing attribute information is configured for peripheral devices), and the sharing attribute information is the first sharing attribute information. If all memory access requests do not participate in cache coherence sharing, unified sharing attribute information is configured for all memory access requests during task execution, and the sharing attribute information is the second sharing attribute information. At the same time, the memory access mode of the peripheral device can be configured as the second memory access mode.

[0087] Exemplarily, a first register is provided in the shunt module, and the first register is used to store mode information of the memory access mode. When the memory access mode of the peripheral device is the first memory access mode, the first mode information can be stored in the first register, and the first mode information indicates that the memory access mode of the peripheral device is the first memory access mode. When the memory access mode of the peripheral device is the second memory access mode, the second mode information can be stored in the first register, and the second mode information indicates that the memory access mode of the peripheral device is the second memory access mode.

[0088] The diversion module also includes a second register, which is used to store shared attribute information corresponding to the second memory access mode. When the memory access mode is the second memory access mode, and the unified shared attribute information configured for all memory access requests is the first shared attribute information, the first shared attribute information can be stored in the second register. When the memory access mode is the second memory access mode, and the unified shared attribute information configured for all memory access requests is the second shared attribute information, the second shared attribute information can be stored in the second register.

[0089] Accordingly, the step of obtaining shared attribute information may include:

[0090] determining a memory access pattern pre-configured for a peripheral device;

[0091] When the memory access mode is the first memory access mode, obtaining sharing attribute information included in the memory access request;

[0092] When the memory access mode is the second memory access mode, shared attribute information pre-configured for the peripheral device is obtained.

[0093] The shared attribute information pre-configured for the peripheral device refers to the shared attribute information configured for all memory access requests sent by the peripheral device before the processor starts to execute the task, such as the shared attribute information stored in the second register in the above example.

[0094] Exemplarily, during task execution, the diversion mode can first obtain mode information from the first register. If the mode information is the first mode information, the memory access mode of the peripheral device is determined to be the first memory access mode. If the mode information is the second mode information, the memory access mode of the peripheral device is determined to be the second memory access mode.

[0095] For each memory access request, when the memory access mode is the first memory access mode, after receiving the memory access request, the diversion module can obtain the sharing attribute information included in the memory access request, and determine whether the memory access request participates in cache consistency sharing through the sharing attribute information included in the memory access request.

[0096] For each memory access request, when the memory access mode is the second memory access mode, after receiving the memory access request, the diversion module can obtain sharing attribute information from the second register, and then determine whether the memory access request participates in cache consistency sharing based on the sharing attribute information obtained from the second register.

[0097] In an embodiment of the present application, corresponding shared attribute information is obtained from the memory access request in the first memory access mode, so that multiple memory access requests of peripheral devices can be diverted individually. In the second memory access mode, multiple memory access requests of peripheral devices are uniformly diverted through unified shared attribute information, which not only can refine the diversion of memory access requests, but also reduce the difficulty of managing memory access requests.

[0098] Optionally, the diversion module includes a distributor and a splitter; the distributor is connected to the peripheral device and the memory bus respectively, and is used to divert the memory access request to the memory bus when the memory access request does not participate in cache consistency sharing; the distributor is also connected to the splitter, and is used to divert the memory access request to the splitter when the memory access request participates in cache consistency sharing; the splitter is connected to the cache bus, and is used to split the memory access request into at least one sub-memory access request, and send the sub-memory access request to the cache bus, each sub-memory access request corresponding to a memory row accessed by the memory access request.

[0099] See also Figure 5 , Figure 5 Schematic diagram of a device cache consistency access system provided by an embodiment of the present application. Figure 5 As shown, the shunt module 212 includes a distributor (also called an output distributor) and a splitter (also called a burst splitter), and the distributor is connected to the peripheral device and is used to receive the memory access request sent by the peripheral device. The distributor is connected to the memory bus and is used to shunt the received memory access request to the memory bus when the memory access request does not participate in cache consistency sharing. The distributor is also connected to the splitter and is used to shunt the memory access request to the splitter when the memory access request participates in cache consistency sharing.

[0100] Among them, the peripheral device accesses the memory in units of rows, and accesses N memory rows in the memory each time, where N is an integer greater than or equal to 1, and the cache bus usually only accesses the data of one memory row each time. After receiving the memory access request sent by the distributor, the splitter can split the memory access request into N sub-memory access requests, each sub-memory access request corresponding to a memory row accessed by the memory access request. After splitting the N sub-memory access requests, the splitter can send the sub-memory access request to the cache bus, and the cache bus responds to each sub-memory access request.

[0101] Specifically, if the memory access request is a read request, the splitter can split the memory access request into N sub-memory access requests, each of which is used to read data in a corresponding memory row from the memory. After the cache bus reads the data in a memory row corresponding to each sub-memory access request through the memory bus, it returns the read data to the splitter, and the splitter sends the read data to the peripheral device.

[0102] Similarly, if the memory access request is a write request, the splitter can split the memory access request into N sub-memory access requests, each of which is used to write data to a corresponding memory row in the memory. After the cache bus writes data to a memory row corresponding to each sub-memory access request through the memory bus, it sends a response message returned after writing the data to the splitter, and the splitter sends the response message to the peripheral device.

[0103] In the embodiment of the present application, the diversion module includes a distributor and a splitter, which can not only realize the rapid diversion of memory access requests, but also has a simple structure and low cost.

[0104] Optionally, the diversion module also includes a bit width converter; the bit width converter is connected to the distributor and the splitter respectively, and is used to convert the bit width of the memory access request output by the distributor when the bit width of the memory access request is larger than the bit width of the cache bus, so as to obtain and send the converted memory access request to the splitter; wherein the bit width of the converted memory access request matches the bit width of the cache bus.

[0105] In actual applications, the bit width of a memory access request is generally 512 bits or 256 bits, and the bit width of a cache bus is generally 128 bits or 256 bits. When the bit width of a memory access request is inconsistent with the bit width of the cache bus, a bit width converter is required to convert the bit width of the memory access request to match the cache bus.

[0106] See also Figure 6 , Figure 6 Schematic diagram of a device cache consistency access system provided by an embodiment of the present application. Figure 6 As shown, the shunt module 212 includes a distributor, a bit width converter and a splitter, the input end of the bit width converter is connected to the distributor, the output end of the bit width converter is connected to the splitter, and the distributor sends the memory access request to the bit width converter when determining that the memory access request needs to be shunted to the cache bus. After receiving the memory access request, the bit width converter converts the bit width of the memory access request and sends the converted memory access request to the splitter.

[0107] For example, if the bit width of the memory access request is 512 bits and the bit width of the cache bus is 128 bits, after receiving the memory access request sent by the distributor, the bit width converter can convert the bit width of the memory access request, convert the 512-bit memory access request into a 128-bit memory access request, and send the converted memory access request to the splitter.

[0108] In an embodiment of the present application, a bit width converter is provided in the diversion module, and the bit width of the memory access request can be converted by the bit width converter so that the bit width of the memory access request matches the bit width of the cache bus.

[0109] Optionally, the allocator includes a logic unit, a cache array, a first selector and a second selector; the cache array is used to store flag information corresponding to a memory access request, and the flag information is used to mark whether the memory access request participates in cache consistency sharing or does not participate in cache consistency sharing; the logic unit is respectively connected to the peripheral device, the cache array, the memory bus and the splitter, and is used to obtain the flag information corresponding to the memory access request from the cache array after receiving the memory access request, and to divert the memory access request to the memory bus or the splitter according to the flag information; the first selector is respectively connected to the splitter, the memory bus, the peripheral device and the cache array, and is used to send the data read by the memory access request returned by the splitter or the memory bus to the peripheral device based on the flag information corresponding to the memory access request stored in the cache array when the memory access request is a read request; the second selector is respectively connected to the splitter, the memory bus, the peripheral device and the cache array, and is used to send the response information of the memory access request returned by the splitter or the memory bus to the peripheral device based on the flag information corresponding to the memory access request stored in the cache array when the memory access request is a write request.

[0110] In this embodiment, the allocator can set corresponding flag information for the memory access request based on the shared attribute information corresponding to the acquired memory access request, and store the flag information, and the flag information corresponds to the shared attribute information. Exemplarily, for each memory access request, if the acquired shared attribute information is the first shared attribute information, the flag information can be set to 1, and the memory access request is marked to participate in cache consistency sharing through the flag information 1; if the acquired shared attribute information is the second shared attribute information, the flag information can be set to 0, and the memory access request is marked not to participate in cache consistency sharing through the flag information 0.

[0111] The buffer array may be a First Input First Output (FIFO) storage cell array. For multiple memory access requests in a task, flag information of each memory access request may be stored in sequence in a FIFO storage cell array corresponding to an ID of the FIFO storage cell array according to an identifier (Identity Document, ID) of the memory access request.

[0112] See also Figure 7 , Figure 7 Schematic diagram of the principle of a flow diversion module provided in an embodiment of the present application. Figure 7 As shown, the diversion module 70 includes a distributor 71 and a splitter / bit-width converter 72. When the bandwidth of the memory access request matches the bandwidth of the cache bus, the splitter / bit-width converter 72 only includes a splitter. When the bandwidth of the memory access request does not match the bandwidth of the cache bus, the splitter / bit-width converter 72 includes a splitter and a bit-width converter.

[0113] The distributor 71 includes a logic unit, a first selector, a second selector and a FIFO storage unit array. Figure 7 As shown, S1 is a memory access request diverted to the memory bus; S2 is a memory access request diverted to the cache bus; R1 is the read data returned from the memory bus when the memory access request is a read request; R2 is the read data returned from the cache bus when the memory access request is a read request; B1 is the response information returned from the memory bus when the memory access request is a write request; B2 is the response information returned from the cache bus when the memory access request is a write request.

[0114] The distributor 71 also includes a first buffer, a second buffer, a third buffer and a fourth buffer. The first buffer is arranged between the memory bus and the first selector, and is used to cache the data between the memory bus and the first selector; the second buffer is arranged between the splitter / bit width converter 72 and the second selector, and is used to cache the data between the splitter / bit width converter 72 and the second selector; the third buffer is arranged between the logic unit and the memory bus, and is used to cache the data between the logic unit and the memory bus; the third buffer is arranged between the logic unit and the splitter / bit width converter 72, and is used to cache the data between the logic unit and the splitter / bit width converter 72.

[0115] The logic unit is connected to the peripheral device and the FIFO storage unit array. After receiving the memory access request, the corresponding flag information can be obtained from the FIFO storage unit array according to the ID of the memory access request, and whether the memory access request participates in cache consistency sharing can be determined according to the flag information. If it participates in cache consistency sharing, the memory access request is shunted to the splitter / bit width converter 72, and the splitter / bit width converter 72 splits at least one sub-memory access request, and the sub-memory access request is shunted to the cache bus. If it does not participate in cache consistency sharing, the memory access request is shunted to the memory bus.

[0116] After the memory access request is shunted to the memory bus, when the memory access request is a read request, the returned data is transmitted to the first selector through the first buffer, and when the memory access request is a write request, the returned response information is transmitted to the second selector through the second buffer. After the memory access request is shunted to the cache bus, when the memory access request is a read request, the returned data is first transmitted to the splitter / bit width converter 72, and then returned to the first selector; when the memory access request is a write request, the returned response information is first transmitted to the splitter / bit width converter 72, and then returned to the second selector.

[0117] The first selector and the second selector are multiplexers. For each memory access request, when the memory access request is a read request, the first selector obtains the corresponding flag information from the FIFO storage unit array according to the ID of the memory access request, and then selects the data accessed by the memory access request from the data returned by the memory bus and the bit width converter according to the flag information, and then transmits the data to the peripheral device. Similarly, for each memory access request, when the memory access request is a write request, the second selector obtains the corresponding flag information from the FIFO storage unit array according to the ID of the memory access request, and then selects the response information corresponding to the memory access request from the response information returned by the memory bus and the bit width converter according to the flag information, and then transmits the response information to the peripheral device.

[0118] See also Figure 8 , Figure 8 Schematic diagram of a memory access device provided in an embodiment of the present application. Figure 8 As shown, the memory access device 800 includes:

[0119] The receiving module 801 is used to receive a memory access request sent by a peripheral device;

[0120] A determination module 802 is used to determine whether the memory access request participates in cache coherence sharing;

[0121] The shunting module 803 is configured to, if not, shunt the memory access request to a memory bus, so as to respond to the memory access request through the memory bus.

[0122] Optionally, the determination module 802 is specifically used to obtain sharing attribute information; wherein the sharing attribute information indicates whether the memory access request participates in cache consistency sharing or not; and determines whether the memory access request participates in cache consistency sharing based on the sharing attribute information.

[0123] Optionally, the determination module 802 is specifically used to determine a memory access mode pre-configured for the peripheral device; when the memory access mode is a first memory access mode, obtain the shared attribute information included in the memory access request; when the memory access mode is a second memory access mode, obtain the shared attribute information pre-configured for the peripheral device.

[0124] Optionally, the device 800 also includes a configuration module, which is used to configure the memory access mode to the first memory access mode if it is determined that a part of the memory access requests sent by the peripheral device participate in cache consistency sharing and another part of the memory access requests do not participate in cache consistency sharing; or, if it is determined that each of the memory access requests sent by the peripheral device participates in cache consistency sharing, configure the memory access mode to the second memory access mode, and configure the sharing attribute information for the peripheral device to the first sharing attribute information; wherein the first sharing attribute information is the sharing attribute information indicating that the memory access request participates in cache consistency sharing; or, if it is determined that each of the memory access requests sent by the peripheral device does not participate in cache consistency sharing, configure the memory access mode to the second memory access mode, and configure the sharing attribute information for the peripheral device to the second sharing attribute information; wherein the second sharing attribute information is the sharing attribute information indicating that the memory access request does not participate in cache consistency sharing.

[0125] Optionally, the determination module 802 is specifically used to determine a first memory space accessed by the memory access request and a second memory space currently accessed by the processor; when the first memory space overlaps with the second memory space, determine that the memory access request participates in cache consistency sharing.

[0126] Optionally, the diversion module 803 is further configured to divert the memory access request to a cache bus if the memory access request participates in cache coherence sharing, so as to respond to the memory access request through the cache bus.

[0127] It should be noted that the memory access device 800 is implemented in the form of a functional unit. The term "module" here can be implemented in the form of software and / or hardware, and is not specifically limited to this.

[0128] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, equivalent changes made according to the claims of the present disclosure are still within the scope covered by the present disclosure.

Claims

1. A memory access method, It is characterized in that The method comprises: Receive memory access requests sent by peripheral devices; Determining whether the memory access request participates in cache coherence sharing; If not, the memory access request is shunted to a memory bus so as to respond to the memory access request through the memory bus; if so, the memory access request is shunted to a cache bus so as to respond to the memory access request through the cache bus; The determining whether the memory access request participates in cache consistency sharing includes: determining a memory access mode pre-configured for the peripheral device; when the memory access mode is a first memory access mode, obtaining sharing attribute information included in the memory access request; when the memory access mode is a second memory access mode, obtaining the sharing attribute information pre-configured for the peripheral device; wherein the sharing attribute information indicates that the memory access request participates in cache consistency sharing or does not participate in cache consistency sharing; determining whether the memory access request participates in cache consistency sharing based on the sharing attribute information; wherein, before receiving the memory access request sent by the peripheral device, if it is determined that a part of the memory access requests sent by the peripheral device participates in cache consistency sharing and another part of the memory access requests do not participate in cache consistency sharing, then configuring the memory access mode to the first memory access mode; or, if it is determined that each of the memory access requests sent by the peripheral device participates in cache consistency sharing, then configuring the memory access mode to the second memory access mode, and configuring the peripheral device Set the sharing attribute information to the first sharing attribute information; wherein the first sharing attribute information is the sharing attribute information indicating that the memory access request participates in cache consistency sharing, indicating that the memory space accessed by the memory access request overlaps with the memory space accessed by the processor; or, if it is determined that each of the memory access requests sent by the peripheral device does not participate in cache consistency sharing, then configure the memory access mode to the second memory access mode, and configure the sharing attribute information for the peripheral device to the second sharing attribute information; wherein the second sharing attribute information is the sharing attribute information indicating that the memory access request does not participate in cache consistency sharing, indicating that the memory space accessed by the memory access request does not overlap with the memory space accessed by the processor; or, determining whether the memory access request participates in cache consistency sharing includes: determining the first memory space accessed by the memory access request, and the second memory space currently accessed by the processor; in the case where the first memory space overlaps with the second memory space, determining that the memory access request participates in cache consistency sharing.

2. A chip, It is characterized in that include: A plurality of processors, caches of the plurality of processors are interconnected via a cache bus, and the cache bus is connected to the memory of the chip via a memory bus; A shunt module, wherein the shunt module is connected to the cache bus and the memory bus respectively, and the shunt module is connected to the peripheral device of the chip, and the shunt module is used to execute the memory access method as claimed in claim 1.

3. The chip according to claim 2, It is characterized in that The diversion module includes a distributor and a splitter; The distributor is connected to the peripheral device and the memory bus respectively, and is used to shunt the memory access request to the memory bus when the memory access request does not participate in cache coherence sharing; The distributor is also connected to the splitter, and is used to shunt the memory access request to the splitter when the memory access request participates in cache coherence sharing; The splitter is connected to the cache bus and is used to split the memory access request into at least one sub-memory access request and send the sub-memory access request to the cache bus, each of the sub-memory access request corresponds to a memory row accessed by the memory access request.

4. The chip according to claim 3, It is characterized in that The shunt module also includes a bit width converter; The bit width converter is connected to the distributor and the splitter respectively, and is used to perform bit width conversion on the memory access request output by the distributor when the bit width of the memory access request is larger than the bit width of the cache bus, so as to obtain and send the converted memory access request to the splitter; wherein the bit width of the converted memory access request matches the bit width of the cache bus.

5. The chip according to claim 3, It is characterized in that The distributor includes a logic unit, a buffer array, a first selector, and a second selector; The cache array is used to store flag information corresponding to the memory access request, and the flag information is used to mark whether the memory access request participates in cache coherence sharing or does not participate in cache coherence sharing; The logic unit is connected to the peripheral device, the buffer array, the memory bus and the splitter respectively, and is used to obtain the flag information corresponding to the memory access request from the buffer array after receiving the memory access request, and to shunt the memory access request to the memory bus or the splitter according to the flag information; The first selector is connected to the splitter, the memory bus, the peripheral device and the buffer array respectively, and is used to send the data read by the memory access request returned by the splitter or the memory bus to the peripheral device based on the flag information corresponding to the memory access request stored in the buffer array when the memory access request is a read request; The second selector is respectively connected to the splitter, the memory bus, the peripheral device and the cache array, and is used to send the response information of the memory access request returned by the splitter or the memory bus to the peripheral device based on the flag information corresponding to the memory access request stored in the cache array when the memory access request is a write request.

6. A device cache consistency access system, It is characterized in that Comprising the chip as claimed in any one of claims 2 to 5.

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