A memory access method, device cache consistency filtering monitoring system and chip

Abstract

The present application provides a memory access method, a device cache consistency filtering monitoring system and a chip. The method includes: upon receiving a memory access request sent by a peripheral device, determining the target memory row accessed by the memory access request, determining a target cache group for storing data in the target memory row, and if some or all of the cache rows in the target cache group do not store data, providing the data in the target memory row to the peripheral device via the memory bus. In this way, when the data in the target memory row is not stored in the cache row or the probability of being stored in the cache row is low, the peripheral device's access to the target memory row can be diverted to the memory bus, thereby reducing the peripheral device's occupancy of the memory bandwidth, and further improving the processor's memory access efficiency.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and more specifically, to a memory access method, a device cache consistency filtering monitoring system and a chip. Background Art

[0002] At present, in order to improve computing efficiency, a large number of processors are set in the device cache consistency filtering monitoring system. In order to ensure cache consistency between processors, the caches of each processor in the device cache consistency filtering monitoring system are connected through a cache bus.

[0003] Some peripheral devices are usually set up in the device cache consistency filtering monitoring system. The peripheral devices can access the memory in the device cache consistency filtering monitoring system through direct memory access. In order to improve the data access efficiency of the peripheral devices, one method is to connect the peripheral devices to the cache bus so that the peripheral devices can quickly access the data in the memory through the cache bus. When the peripheral devices are connected to the cache bus, the memory access requests of the peripheral devices will participate in the cache consistency process between the processors, which may occupy part of the bandwidth of the processor to access the memory, thereby reducing the memory access efficiency of the processor. Summary of the invention

[0004] The present application provides a memory access method, a device cache consistency filtering monitoring system and a chip, which can reduce the memory bandwidth occupied by peripheral devices and improve the memory access efficiency of the processor.

[0005] In a first aspect, a memory access method is provided, the method comprising:

[0006] When receiving a memory access request sent by a peripheral device, determining a target memory row accessed by the memory access request;

[0007] determining a target cache group for storing data in the target memory row;

[0008] If some or all cache lines in the target cache group do not store data, the data in the target memory line is provided to the peripheral device via a memory bus.

[0009] In the embodiment of the present application, when the peripheral device accesses the data in the memory, it first determines the target memory row to be accessed, and determines the target cache group for storing the data in the target memory row. If some or all cache rows in the target cache group do not store data, the data in the target memory row is provided to the peripheral device through the memory bus. In this way, when the data in the target memory row is not stored in the cache row or the probability of being stored in the cache row is low, the peripheral device's access to the target memory row can be diverted to the memory bus, thereby reducing the peripheral device's occupation of the memory bandwidth, and further improving the processor's memory access efficiency.

[0010] Optionally, if some or all cache lines in the target cache group do not store data, providing the data in the target memory line to the peripheral device through a memory bus includes:

[0011] Obtain a pre-stored first count value; wherein, the multiple memory rows corresponding to the target cache group are divided into multiple groups, the first count value corresponds to a group of memory rows where the target memory row is located, and the first count value represents the number of memory rows in the group of memory rows whose data is written into the target cache group; if the first count value is less than a pre-designed value, the data in the target memory row is provided to the peripheral device through the memory bus.

[0012] Optionally, the multiple memory rows are divided into multiple groups according to the target bit in the address tag of each memory row; obtaining the pre-stored first count value includes: determining the cache index of the target cache group and the target bit in the address tag of the target memory row; based on the cache index and the target bit in the address tag of the target memory row, obtaining the first count value from the pre-stored multiple count values.

[0013] Optionally, the method further includes: if the first count value is greater than or equal to the pre-designed value, providing the data in the target memory row to the peripheral device via a cache bus.

[0014] Optionally, if some or all of the cache rows in the target cache group do not store data, the data in the target memory rows are provided to the peripheral device via the memory bus, including: obtaining a pre-stored second count value; wherein the second count value represents the number of cache rows in the target cache group that store data; if the second count value is less than a pre-designed value, the data in the target memory rows are provided to the peripheral device via the memory bus.

[0015] Optionally, the obtaining of a pre-stored second count value includes: determining a cache index of the target cache group; and obtaining the second count value from a plurality of pre-stored count values ​​based on the cache index.

[0016] Optionally, the method further includes: if the second count value is greater than or equal to the pre-designed value, providing the data in the target memory row to the peripheral device via a cache bus.

[0017] Optionally, providing the data in the target memory row to the peripheral device through the memory bus includes: constructing a first data request for the target memory row based on the address of the target memory row; and sending the first data request to the memory bus to provide the data in the target memory row to the peripheral device through the memory bus.

[0018] In a second aspect, a chip is provided, including:

[0019] A plurality of processors, caches of the plurality of processors are interconnected via a cache bus, and the cache bus is connected to the memory of the chip via a memory bus;

[0020] A monitoring module, wherein the monitoring module is connected to the cache bus, the memory bus and the cache respectively, and the monitoring module is connected to the peripheral device of the chip, and the monitoring module is used to execute the memory access method as claimed in claim 1.

[0021] In a third aspect, a device cache consistency filtering monitoring system is provided, comprising the chip as described in the second aspect above.

[0022] In a fourth aspect, a memory access device is provided, the device comprising:

[0023] A determination module, configured to determine a target memory row to be accessed by a memory access request when receiving the memory access request sent by the peripheral device;

[0024] The determination module is further used to determine a target cache group for storing data in the target memory row;

[0025] A module is provided, for providing the data in the target memory row to the peripheral device through a memory bus if some or all cache rows in the target cache group do not store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a structural diagram of a device cache consistency filtering monitoring system in the related art;

[0027] Figure 2 It is a structural diagram of a device cache consistency filtering monitoring system provided by an embodiment of the present application;

[0028] Figure 3 It is a logical schematic diagram of a cache provided in an embodiment of the present application;

[0029] Figure 4 It is a mapping relationship diagram between cache and memory provided in an embodiment of the present application;

[0030] Figure 5 It is a schematic diagram of the composition of address data provided in an embodiment of the present application;

[0031] Figure 6 is a flowchart of a memory access method provided by an embodiment of the present application;

[0032] Figure 7 This is a schematic diagram of storing a count value provided by an embodiment of the present application;

[0033] Figure 8 It is a schematic diagram of the principle of a monitoring module provided in an embodiment of the present application;

[0034] Fig. 9 It is a structural diagram of a memory access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solution in the present application will be described clearly and in detail below in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0037] In a complex device cache consistency filtering monitoring system, one or more chips for computing are usually set up, and each chip is set up with one or more processors. The chip is also surrounded by memory and some peripheral devices, such as peripheral component interconnect express (PCIE) devices, graphics processing units (GPUs) and field programmable gate arrays (FPGAs), but not limited to these.

[0038] See also Figure 1 , Figure 1Schematic diagram of a device cache consistency filtering monitoring system in the related art. Figure 1 As shown, a chip 11 is provided in the system, and a memory 12 and at least one peripheral device 13 are provided on the periphery of the chip 11. A cache bus, a memory bus and at least one core 111 are provided on the chip 11. One or more clusters (Cluste) are provided in each core 111, and each cluster constitutes a processor. The processor includes at least one core (core), a snoop filter (Snoop Filter) and a third-level cache (L3 Cache), etc. Each core includes a first-level cache (L1 Cache) and a second-level cache (L2 Cache).

[0039] The cache bus is also called the Cache Coherent Interconnnect (CCI) bus. To ensure cache consistency between processors, the three-level cache in each processor is connected to the cache bus. The cache bus can realize cache consistency sharing between multiple processors, so that the data in the same memory row remains consistent in different three-level caches to achieve cache consistency between processors. Memory buses, such as the Advanced eXtensible Interface (AXI) bus, are used to connect memory and cache buses and provide data in memory to the cache bus.

[0040] like Figure 1 As shown, in order to improve the data access efficiency of peripheral devices, the peripheral devices are connected to the cache bus so that the peripheral devices can access the memory through direct memory access (DMA). When the peripheral devices access the memory through the cache bus, the memory access request of the peripheral devices will participate in the cache consistency process between the processors, which may occupy part of the bandwidth of the processor to access the memory, thereby reducing the memory access efficiency of the processor, and further reducing the efficiency of the entire device cache consistency filtering monitoring system.

[0041] It should be noted that the chip in the embodiment of the present application may be a chip integrating multiple core particles, or may be a single core particle.

[0042] In order to solve the above technical problems, an embodiment of the present application provides a memory access method, in which, when a chip receives a memory access request sent by a peripheral device, it first determines the memory row accessed by the memory access request (hereinafter referred to as the target memory row), and determines from the cache a cache group for storing data in the target memory row (hereinafter referred to as the target cache group), and then, when some or all of the cache rows in the target cache group do not store data, the data in the target memory row is provided to the peripheral device through the memory bus.

[0043] Among them, when some or all of the cache rows in the target cache group do not store data, it indicates that the data in the target memory row is most likely not stored in the cache. At this time, the data in the target memory row is provided to the peripheral device through the memory bus, and the access of the peripheral device to the target memory row can be diverted to the memory bus. The data in the target memory row is provided to the peripheral device through the memory bus. This can reduce the peripheral device's occupancy of memory bandwidth, thereby improving the processor's memory access efficiency, and further improving the efficiency of the device cache consistency filtering monitoring system.

[0044] It should be noted that the cache in the embodiment of the present application refers to the cache used to achieve cache consistency sharing between multiple processors. Figure 1 For example, the third-level caches of multiple processors are interconnected through a cache bus, and cache consistency sharing is achieved through the cache bus. Therefore, the memory access method and the cache in the memory access chip provided in this application refer to Figure 1 The device cache coherency filter shown monitors the third level cache in the system.

[0045] The embodiment of the present application also provides a chip to implement the memory access method in the embodiment of the present application. The chip includes multiple processors and a monitoring module, and the caches of the multiple processors are interconnected through a cache bus, and the cache bus is connected to the memory of the chip through a memory bus. The monitoring module is connected to the cache bus, the memory bus and the cache respectively, and the monitoring module is connected to the peripheral device of the chip, and the monitoring module is used to execute the memory access method provided by the implementation of the present application.

[0046] See also Figure 2 , Figure 2 Schematic diagram of a device cache consistency filtering monitoring system provided by an embodiment of the present application. Figure 2 As shown, the system includes a chip 21, and a memory 22 and a peripheral device 23 arranged on the periphery of the chip 21. The chip 21 is provided with a core particle 211 and a monitoring module. The core particle 211 includes multiple clusters, and each cluster is provided with multiple cores, a sniffer filter and a three-level cache. Each cluster constitutes a processor, and the three-level cache in the processor has a cache interface, and the cache interface can be an Advanced eXtensible Interface Coherency Extensions (ACE) interface. Each three-level cache is connected to the cache bus through the cache interface, so that the three-level caches in multiple processors can be interconnected through the cache bus. The cache bus is connected to the memory bus, and the memory bus is connected to the memory. When the processor accesses the data in the memory, it can access the data in the memory through the interconnected cache bus and memory bus.

[0047] like Figure 2As shown, the monitoring module is connected to the cache interface of each L3 cache, and is also connected to the memory bus and the cache bus. The monitoring module is also connected to the peripheral devices outside the chip. The monitoring module can receive the memory access request sent by the peripheral device and determine one or more target memory rows accessed by the memory access request. For each target memory row, a target cache group for storing data in the target memory row is determined. If some or all cache rows in the target cache group do not store data, the data in the target memory row is provided to the peripheral device through the memory bus.

[0048] It should be noted that the memory access method provided in the embodiment of the present application can be Figure 2 The monitoring module in the chip shown is executed, and may also be executed by other parts in the chip, such as a cache bus, which is not limited in this embodiment.

[0049] Optionally, the cache may be a multi-way set-associative cache. In a multi-way set cache, the cache is divided into multiple ways, each way includes multiple cache lines, and each cache line can store data in a corresponding memory row.

[0050] See also Figure 3 , Figure 3 This is a logical schematic diagram of a cache provided in an embodiment of the present application. Figure 3 The cache shown is a 4-way 4-group cache, including 4-way cache lines, each way including 4 cache lines. At the same time, the cache is also divided into multiple groups, each group of cache lines includes a cache line in a different way, and each group of cache lines corresponds to a cache index, that is, each cache index corresponds to multiple cache lines. Figure 3 As shown, each cache line includes two parts of random access memory (Random Access Memory, RAM), one part is data random access memory (Data RAM), and the other part is tag random access memory (Tag RAM). The data random access memory is used to store the data in the memory line, and the tag random access memory is used to store the address tag (tag) of the memory line. The address tag corresponds to part of the address bits of the memory line in the memory.

[0051] like Figure 2 and Figure 3As shown, each processor has a third-level cache. In order to achieve cache consistency between multiple processors, the third-level caches of multiple processors are the same. Therefore, for the entire chip, the cache group corresponding to each cache index also includes cache lines in the third-level caches of different processors. For example, when the cache index index is 1, the cache index not only corresponds to the 4 cache lines with a cache index of 1 in the third-level cache of Cluster0, but also corresponds to the 4 cache lines with a cache index of 1 in the third-level cache of Cluster1, that is, the cache group corresponding to cache index 1 includes 8 cache lines, namely, 4 cache lines with a cache index of 1 in Cluster0 and 4 cache lines with a cache index of 1 in Cluster1.

[0052] It should be noted that Figure 3 This is just an example. The number of groups and ways in the cache can be set according to actual needs, including but not limited to Figure 3 shown.

[0053] See also Figure 4 , Figure 4 is a mapping relationship diagram between cache and memory provided by an embodiment of the present application. Figure 4 As shown, multiple cache lines in the same cache group are used to store data in the corresponding multiple memory lines in the memory. For ease of introduction, the embodiment of the present application refers to the multiple memory lines corresponding to the same cache group as a memory group, and the dotted arrows represent the correspondence between the memory lines and the cache lines. The multiple memory lines in the memory group Y correspond to the cache group X. When the processor accesses the data in the memory, when accessing the data in a certain memory line included in the memory group Y, the data in the memory line can be stored in one of the cache lines in the cache group X, and the data to be accessed can be obtained from the cache line.

[0054] Specifically, when the processor accesses a byte of data in the memory, it first sends a data request to the memory management unit (MMU) in the processor. The address data included in the data request is binary data. The address data is used to determine the specific location of the byte data accessed by the processor in the memory. Some of the binary bits in the address data are tag bits, some of the binary bits are offset bits, and the other binary bits are index bits.

[0055] See also Figure 5 , Figure 5 Schematic diagram of the composition of address data provided by the embodiment of the present application. Figure 5As shown, the address data is 32-bit binary data, bits 0 to 5 are offset bits, bits 6 to 11 are index bits, and bits 12 to 32 are tag bits. The tag bit stores the address tag of the memory row where the byte data accessed by the processor is located, the offset bit stores the address offset of the byte data accessed by the processor in the memory row, and the index bit stores the cache index of the cache group corresponding to the memory row.

[0056] When the processor accesses a certain byte of data in the memory, after receiving the data request sent by the processor, the memory management unit first determines a corresponding cache group from the cache according to the cache index in the index bit, and then traverses each cache line in the cache group to determine which cache line's tag random access memory stores the address tag in the tag bit. If the tag random access memory of a cache line stores the address tag in the tag bit, it is determined that the data in the memory line where the byte data is located is pre-stored in the cache line, and then the byte data can be read from the cache line according to the address offset in the offset bit.

[0057] On the contrary, if all cache lines in the cache group do not store the address tag in the tag bit, it is determined that the data in the memory line where the byte data is located is not stored in the cache. At this time, the data in the memory line where the byte data is located can be obtained from the memory, and then the obtained data of a memory line is stored in a free cache line in the corresponding cache group. If there is no free cache line in the cache group, the data in a cache line is kicked out of the cache according to the preset rules, so that the cache line is free, and then the obtained data in the memory line is stored in the cache line.

[0058] See also Figure 6 , Figure 6 is a flowchart of a memory access method provided in an embodiment of the present application. The method is applied to a chip of a specific plurality of processors, the chip including Figure 2 The monitoring module and cache shown in the figure can be Figure 2 The monitoring module shown is executed as Figure 6 As shown, the method comprises the following steps:

[0059] Step 601: upon receiving a memory access request sent by a peripheral device, determining a target memory row to be accessed by the memory access request.

[0060] In this embodiment, the peripheral device is connected to the monitoring module in the chip. When the peripheral device accesses the data in the memory, it can access the data in the memory in units of rows by direct memory access, and access the data of one or more consecutive memory rows in the memory each time. In the process of accessing the memory, the peripheral device can first send a memory access request to the monitoring module. The memory access request includes the first address and data length of at least one memory row to be accessed. The first address is the address of the first memory row in the memory of the at least one memory row (corresponding to the address label of the memory row), and the data length corresponds to the number of memory rows.

[0061] After receiving the memory access request, the monitoring module can determine each memory row to be accessed by the peripheral device based on the first address and the data length, and each memory row is a target memory row. For example, when there is one memory row to be accessed, the first address is the address of the target memory row; when there are multiple consecutive memory rows to be accessed, the first address is the address of the first memory row, the first address is offset by one memory row to be the address of the second memory row, the first address is offset by two memory rows to be the address of the third memory row, and so on, each target memory row to be accessed can be determined.

[0062] Step 602: Determine a target cache group for storing data in a target memory row.

[0063] Step 603: If some or all cache lines in the target cache group do not store data, the data in the target memory line is provided to the peripheral device via the memory bus.

[0064] In this embodiment, after determining one or more target memory rows to be accessed, the monitoring module can determine the target cache group corresponding to the target memory row for each target memory row, and the target cache group corresponding to the target memory row is the cache group corresponding to the memory group where the target memory row is located. Figure 4 As shown, if the target memory line is a memory line in memory group Y, the target cache group is cache group X.

[0065] When data is stored in a cache line in a cache group, it indicates that data in a memory line in a memory group corresponding to the cache group is stored in the cache line. The more cache lines storing data in the cache group, the more memory lines in the corresponding memory group have data stored in the cache. Since the cache lines in the cache group only store data in the corresponding memory lines, when no data is stored in all cache lines in the cache group, the probability that data in each memory line in the corresponding memory group is stored in the cache is 0.

[0066] Furthermore, the data stored in the cache line is data in one of the memory lines in the corresponding memory group, and the memory line may be any memory line in the memory group. Therefore, when data is stored in at least one cache line in the cache group, each memory line in the corresponding memory group has a certain probability of being stored in the cache. For each memory line in the memory group, the more cache lines that store data in the cache group, the greater the probability that the data in the memory line is stored in the cache.

[0067] like Figure 2-4 As shown in the figure, each cache group includes 8 cache lines, which are 4 cache lines in the third-level cache of Cluster0 and 4 cache lines in the third-level cache of Cluster1. If the memory group corresponding to the cache group includes N memory lines, when no data is stored in each of the 8 cache lines, the probability of each of the N memory lines being stored in the cache is 0. When only one cache line among the 8 cache lines stores data, the probability of each of the N memory lines being stored in the cache is , when all 8 cache lines store data, the probability that each of the N memory lines is stored in the cache is .

[0068] Based on this, in one embodiment, after determining the target cache group, the monitoring module can first determine whether all the multiple cache lines included in the target cache group store data. If it is determined that no data is stored in the multiple caches, it can be determined that the probability of the target memory line being stored in the cache is 0. At this time, the monitoring module can provide the data in the target memory line to the peripheral device through the memory bus. On the contrary, when it is determined that data is stored in one or more cache lines in the target cache group, it can be determined that the data in the target memory line has a certain probability of being stored in the cache. At this time, the monitoring module can provide the data in the target memory line to the peripheral device through the cache bus.

[0069] In another embodiment, after determining the target cache group, the monitoring module may first determine whether there are at least M cache lines storing data in the target cache group, where M is an integer greater than or equal to 1. For example, when M is 1, after determining the target cache group, the monitoring module first determines whether there is at least one cache line storing data in the target cache group. When there are one or more cache lines storing data, it can be determined that the target memory line has a certain probability of being stored in the cache, and at this time the monitoring module may provide the data in the target memory line to the peripheral device through the cache bus. On the contrary, when the number of cache lines storing data in the target cache group is less than M, that is, all cache lines in the target cache group do not store data, the monitoring module may provide the data in the target memory line to the peripheral device through the memory bus.

[0070] like Figure 2 As shown, when providing data in a target memory row to a peripheral device via a memory bus, the monitoring module may send a data request to the memory bus, and the data request may include an address tag of the target memory row. After receiving the data request, the memory management unit connected to the memory may obtain the data in the target memory row from the memory based on the address of the target memory row, and send the obtained data to the monitoring module via the memory bus, and the monitoring module may send the received data to the peripheral device.

[0071] Similarly, when providing data in the target memory row to the peripheral device via the cache bus, the monitoring module can send a data request to the cache bus, and the data request includes the address tag of the target memory row. At this time, upon receiving the data request, the cache bus first determines whether the data in the target memory row is stored in the cache according to the address tag of the target memory row. If the data in the target memory row is stored, the data in the target memory row is obtained from the cache, and the obtained data is sent to the monitoring module.

[0072] It should be noted that when the data in the target memory row is provided to the peripheral device via the cache bus, it only indicates that the data in the target memory row may be stored in the cache, but it does not indicate that the data in the target memory row must be stored in the cache. Therefore, when the data in the target memory row is provided to the peripheral device via the cache bus, if the data in the target memory row is not stored in the cache, the data in the target memory row can be obtained from the memory via the cache bus and the memory bus, and then the obtained data is sent to the peripheral device.

[0073] In actual applications, when a peripheral device accesses memory, part of the data in the memory accessed during initialization will be pre-stored in the cache. Therefore, although the number of memory lines corresponding to the cache group is large, since the probability that the data in the target memory line to be accessed is pre-stored in the cache is high, even if the number of cache lines in the target cache group is small, as long as the target cache group has one or more cache lines storing data, the probability that the data in the target memory line is stored in the cache is still high, and it is very likely that the data in the target memory line can be obtained from the cache through the cache bus.

[0074] When the data in the target memory row is provided to the peripheral device through the cache bus, the peripheral device's access to the target memory row participates in the cache consistency sharing process. When the data in the target memory row is provided to the peripheral device through the memory bus, the peripheral device's access to the target memory row does not participate in the cache consistency sharing process.

[0075] In the embodiment of the present application, when the peripheral device accesses the data in the memory, it first determines the target memory row to be accessed, and determines the target cache group for storing the data in the target memory row. If some or all cache rows in the target cache group do not store data, the data in the target memory row is provided to the peripheral device through the memory bus. In this way, when the data in the target memory row is not stored in the cache row or the probability of being stored in the cache row is low, the peripheral device's access to the target memory row can be diverted to the memory bus, thereby reducing the peripheral device's occupation of the memory bandwidth, and further improving the processor's memory access efficiency.

[0076] Optionally, the multiple memory rows corresponding to each cache group in the cache are divided into multiple groups, and the monitoring module can monitor the cache access requests corresponding to each group of memory rows in the memory, and obtain the count value corresponding to each group of memory rows based on the cache access requests corresponding to each group of memory rows, and the count value represents the number of memory rows in the corresponding group of memory rows whose data is written into the cache. In other words, the count value represents the sum of the number of times a group of memory rows is accessed, that is, the number of memory rows written into the cache group.

[0077] Correspondingly, when the monitoring module receives a memory access request sent by a peripheral device, it can obtain a first count value corresponding to a group of memory rows where the target memory row is located from multiple count values. Afterwards, it can be determined whether the first count value is less than a pre-designed value. If the first count value is less than the pre-designed value, the data in the target memory row is provided to the peripheral device through the memory bus. On the contrary, if the first count value is greater than or equal to the pre-designed value, the data in the target memory row is provided to the peripheral device through the cache bus.

[0078] The cache access request corresponding to each group of memory rows includes an access request for the processor to access data in any one of the memory rows in each group of memory rows, such as an address read request and an address write request. It also includes an access request for the cache bus to share the data in the memory row consistently, such as a snoop request. It should be understood that the cache access request includes but is not limited to the above examples.

[0079] In one implementation, for multiple memory rows corresponding to each cache group, the multiple memory rows may be grouped according to the target bits in the address tags of the memory rows. Figure 5 As shown, the target bit is, for example, the first bit in the address tag, that is, the multiple memory rows corresponding to the cache group are divided into two groups through the 12th bit in the address data. When the multiple memory rows corresponding to the cache group are grouped by the first bit in the address tag, the memory rows whose first bit in the address tag is 0 can be grouped into one group, and the memory rows whose first bit in the address tag is 1 can be grouped into one group. In total, the multiple memory rows corresponding to the cache group can be divided into two groups.

[0080] Of course, the target bit can also be multiple bits. For example, the first two bits in the address tag can be used to group multiple memory rows, and the first two bits are the 12th and 13th bits in the address data. At this time, the memory rows whose first two bits in the address tag are 00 can be divided into one group, the memory rows whose first two bits in the address tag are 01 can be divided into one group, the memory rows whose first two bits in the address tag are 10 can be divided into one group, and the memory rows whose first two bits in the address tag are 11 can be divided into one group. In total, the multiple memory rows corresponding to the cache group can be divided into four groups.

[0081] like Figure 2-4 As shown, when the target bit is the first bit in the address tag, the multiple memory lines corresponding to the cache group X can be divided into two groups. For each group of memory lines, the monitoring module can set the corresponding initial count value to 0, add 1 to the count value when monitoring an address read request from any processor to any memory line in the group of memory lines, subtract 1 from the count value when monitoring an address write request from any processor to any memory line in the group of memory lines, and subtract 1 from the count value when monitoring a snoop request from any processor to any memory line in the group of memory lines.

[0082] Thus, for the two groups of memory rows corresponding to cache group X, two count values ​​can be obtained. One count value corresponds to a group of memory rows whose first bit in the address tag is 0, and the other count value corresponds to a group of memory rows whose first bit in the address tag is 1. Figure 2-3 As shown, each cache group includes 8 cache lines, and the maximum count value corresponding to each group of memory lines is 8 and the minimum count value is 0.

[0083] In this embodiment, the monitoring module can store the count value corresponding to each group of memory rows. After receiving a memory access request and determining the target cache group, the count value corresponding to a group of memory rows where the target memory row is located (i.e., the first count value) can be determined from the pre-stored multiple count values.

[0084] Optionally, when the target bit in the address tag is used to group the memory rows, in the process of storing the count value, each count value may be stored in sequence based on the cache index of the cache group corresponding to each group of memory rows and the target bit in the address tag of the memory row. In this way, in the process of obtaining the first count value, the cache index of the target cache group and the target bit in the address tag of the target memory row may be determined first, and then the first count value may be determined from the pre-stored multiple count values ​​based on the cache index and the target bit in the address tag of the target memory row.

[0085] As described above, when the first bit in the address tag is used to group memory rows, two count values ​​can be obtained for cache group X, and two count indexes can be set for the two count values, respectively. One count index consists of the cache index of cache group X and "0", corresponding to the memory row with the first bit in the address tag being 0, and the other count index consists of the cache index of cache group X and "1", corresponding to the memory row with the first bit in the address tag being 1. Two count values ​​can be stored based on the two count indexes, and by analogy, the count value of each group of memory rows can be stored based on the count index corresponding to each group of memory rows.

[0086] In the process of obtaining the first count value, the count index corresponding to the target memory row can be determined based on the cache index of the target cache group and the first bit in the address tag of the target memory row, and then the first count value can be determined from multiple count values ​​according to the count index.

[0087] As mentioned above, the larger the first count value is, the more cache lines that store data in the target cache group. The preset count value can be set to 1. When the first count value is less than 1 (i.e., 0), it can be determined that no data is stored in multiple cache lines of the target cache group. At this time, the data in the target memory line can be provided to the peripheral device through the memory bus. On the contrary, when the first count value is greater than or equal to 1, it can be determined that at least one cache line in the target cache group stores data. At this time, the monitoring module can provide the data in the target memory line to the peripheral device through the cache bus.

[0088] In an embodiment of the present application, multiple memory rows corresponding to a cache group are divided into multiple groups, and a corresponding count value is set for each group of memory rows to represent the number of memory rows written to the cache in each group of memory rows. The probability of a memory row being written to the cache can be determined by the count value, so that it can be quickly determined whether it is necessary to provide data in the memory row to a peripheral device through a memory bus based on the count value.

[0089] Optionally, the monitoring module can monitor the cache access requests of each cache group in the cache, and count the cache access requests of each cache group to obtain a count value corresponding to each cache group; wherein the count value represents the number of cache rows storing data in the corresponding cache group.

[0090] Correspondingly, when the monitoring module receives a memory access request sent by a peripheral device, it can obtain a second count value corresponding to the target cache group from multiple count values. Afterwards, it can be determined whether the second count value is less than a pre-designed value. If the second count value is less than the pre-designed value, the data in the target memory row is provided to the peripheral device via the memory bus. If the second count value is greater than or equal to the pre-designed value, the data in the target memory row is provided to the peripheral device via the cache bus.

[0091] In another embodiment, the multiple memory rows corresponding to each cache group can be directly grouped together, and the multiple memory rows corresponding to each cache group can be counted to obtain the count value corresponding to the cache group, that is, the count value corresponding to the multiple memory rows corresponding to the cache group.

[0092] like Figure 2-4 As shown, for multiple memory lines corresponding to cache group X, the monitoring module can set the initial count value corresponding to cache group X to 0, and when monitoring an address read request from any processor to any memory line in memory group Y, add 1 to the count value, and when monitoring an address write request from any processor to any memory line in memory group Y, subtract 1 from the count value, and when monitoring a snoop request from any processor to any memory line in memory group Y, subtract 1 from the count value. In this way, a count value can be obtained for cache group X, and the larger the count value, the more cache lines storing data in cache group X.

[0093] In this embodiment, the monitoring module can store the count value corresponding to each cache group, and after receiving a memory access request and determining the target cache group, it can determine the count value corresponding to the target cache group (ie, the second count value) from multiple pre-stored count values.

[0094] Optionally, when multiple memory rows corresponding to each cache group are grouped together, in the process of storing the count value, each count value may be stored in sequence based on the cache index of the cache group. In this way, in the process of obtaining the second count value, the cache index of the target cache group may be determined first, and then the second count value may be determined from the pre-stored multiple count values ​​based on the cache index.

[0095] As mentioned above, the larger the second count value is, the more cache lines that store data in the target cache group. The preset count value can be set to 1. When the second count value is less than 1 (i.e., 0), it can be determined that no data is stored in multiple cache lines of the target cache group. At this time, the data in the target memory line can be provided to the peripheral device through the memory bus. On the contrary, when the second count value is greater than or equal to 1, it can be determined that at least one cache line in the target cache group stores data. At this time, the monitoring module can provide the data in the target memory line to the peripheral device through the cache bus.

[0096] In an embodiment of the present application, a corresponding count value is set for the multiple memory rows corresponding to each cache group to represent the number of memory rows written to the cache in each group of memory rows. The probability of the memory row being written to the cache can be determined by the count value, so that it can be quickly determined whether it is necessary to provide the data in the memory row to the peripheral device through the memory bus based on the count value.

[0097] In actual applications, when a peripheral device accesses data in memory by direct memory access, it usually accesses the data in memory in blocks, accessing the data in multiple consecutive memory rows in a memory block each time. Based on this, in the process of storing count values, the count values ​​corresponding to the multiple consecutive memory rows included in each memory block can be stored in sequence according to the address order of the memory rows in the memory. The count value corresponding to the memory row is the count value corresponding to a group of memory rows where the memory row is located or the count value corresponding to the cache group corresponding to the memory row. In this way, in the process of obtaining the count value, the count values ​​corresponding to all target memory rows can be obtained at one time according to the starting address.

[0098] Optionally, a static random access memory (SRAM) may be provided in the monitoring module to store each count value. Figure 7 As shown, Figure 7 The SRAM in the monitoring module can be divided into 64 banks, each bank includes index0 to index1023 storage spaces, and each storage space can store the count values ​​corresponding to all memory rows in a memory block.

[0099] For example, if the size of a memory block is 4 kilobytes (KB), including 64 memory rows, each storage space in the SRAM can store 64 count values ​​corresponding to 64 consecutive memory rows in a memory block. Specifically, if a count value is stored using a 6-bit binary number, the 64 count values ​​corresponding to 64 consecutive memory rows require a 384-bit binary number to store, and the size of each storage space in the SRAM can be set to 384 bits.

[0100] like Figure 7 As shown, for each memory block, the bank where the storage space corresponding to the memory block is located can be set, and the depth of the storage space corresponding to the memory block in the bank can be set. The depth refers to the position of the storage space in the bank. Each memory block corresponds to a storage space. In the process of storing count values, for the 64 consecutive memory rows included in each memory block, the count value corresponding to the first memory row can be stored in the 0th to 5th bits in the corresponding storage space, and the count value corresponding to the second memory row can be stored in the 6th to 11th bits. And so on, the count value corresponding to each memory row can be stored.

[0101] After receiving a memory access request, the first address in the address data included in the memory access request can be determined. The first address is the address data of the first memory row in the target memory block where the target memory row is located, and the first address corresponds to the storage space corresponding to the memory block. After that, the target bank where the storage space corresponding to the target memory block is located can be determined from multiple banks based on the first address, and the target storage space can be determined from the target bank according to the depth corresponding to the target memory block, and then 64 count values ​​corresponding to 64 consecutive memory rows can be obtained from the target storage space. After that, the count value corresponding to the target memory row (i.e., the first count value and the second count value in the above example) can be determined from the 64 count values ​​according to the offset of the target memory row in the consecutive 64 memory rows.

[0102] Optionally, the monitoring module includes a counting unit and a shunt unit, the counting unit is connected to the shunt unit and the cache respectively, and the shunt unit is connected to the memory bus. When the multiple memory rows corresponding to each cache group are divided into multiple groups, the counting unit can monitor the cache access requests corresponding to each group of memory rows in the memory, count based on the cache access requests corresponding to each group of memory rows, and obtain the count value corresponding to each group of memory rows. When receiving the memory access request, the counting unit obtains a first count value corresponding to a group of memory rows where the target memory row is located from the pre-stored multiple count values, and sends the relevant information of the first count value and the memory access request to the shunt unit. Based on the relevant information, the shunt unit can provide the data in the target memory row to the peripheral device through the memory bus when the first count value is less than the pre-designed value. When the first count value is greater than or equal to the pre-designed value, the data in the target memory row is provided to the peripheral device through the cache bus.

[0103] See also Figure 8 , Figure 8 Schematic diagram of the principle of a monitoring module provided in the embodiment of the present application. Figure 8 As shown, the monitoring module 80 includes a counting unit 81 and a diversion unit 82 which are interconnected. The counting unit 81 is connected to the cache interface of the cache in each processor and is also connected to the peripheral device. The counting unit 81 can monitor the cache access request through the cache interface. A first cache queue is provided in the counting unit 81, and the first cache queue is used to store the cache access request monitored from the cache interface. An arbitrator (ARB) and SRAM are also provided in the counting unit 81. The ARB can count the cache access requests corresponding to each group of memory rows stored in the first cache queue, obtain the count value corresponding to each group of memory rows, and store the count value in the SRAM.

[0104] The counting unit 81 is also connected to the peripheral device to receive the memory access request sent by the peripheral device. The counting unit 81 is also provided with a second cache queue, and the second cache queue is used to store the memory access request received from the peripheral device. The ARB can determine the target memory row and the target cache group based on the memory access request stored in the second cache queue, and obtain the count value (i.e., the first count value or the second count value) corresponding to the target memory row from the SRAM.

[0105] like Figure 8 As shown, the shunt unit 82 is connected to the counting unit 81, and is also connected to the cache bus and the memory bus. After obtaining the count value corresponding to the target memory row, the counting unit 81 can control the shunt unit 82 to provide the data in the target memory row to the peripheral device through the memory bus when the count value is less than the pre-designed value, or control the shunt unit 82 to provide the data in the target memory row to the peripheral device through the cache bus when the count value is greater than or equal to the pre-designed value.

[0106] Optionally, the relevant information may be a tag vector corresponding to the count value. For the count value corresponding to each memory row, when the count value is greater than or equal to a pre-designed value (for example, 1), the tag vector corresponding to the memory row may be set to 1, and when the count value is less than the pre-designed value, the tag vector corresponding to the memory row may be set to 0. A tag vector of 1 indicates that the data in the memory row is obtained through a cache bus, and a tag vector of 0 indicates that the data in the memory row is obtained through a memory bus.

[0107] As described above, in the process of obtaining the count value corresponding to the target memory row, the counting unit may first obtain 64 count values ​​corresponding to the memory block where the target memory row is located from the SRAM. After obtaining the 64 count values, for each count value, when the count value is greater than or equal to the pre-designed value, the corresponding marking vector may be determined to be 1, and when the count value is less than the pre-designed value, the corresponding marking vector may be determined to be 0, so that 64 marking vectors may be obtained. Afterwards, the 64 marking vectors may be sent to the shunt unit 82.

[0108] After the diversion unit 82 receives 64 tag vectors, for each target memory row to be accessed, it can determine the target tag vector corresponding to the target memory row from the 64 vectors. When the target tag vector is 1, the data in the target memory row is provided to the peripheral device through the cache bus. When the target tag vector is 0, the data in the target memory row is provided to the peripheral device through the memory bus.

[0109] Optionally, when the multiple memory rows corresponding to each cache group are taken as a group, the counting unit can monitor the cache access requests of each cache group in the cache, and obtain the count value corresponding to each cache group based on the cache access requests of each cache group; wherein the count value represents the number of cache rows storing data in the corresponding cache group. When receiving the memory access request, the counting unit can obtain the second count value corresponding to the target cache group from the multiple count values, and send the relevant information of the second count value and the memory access request to the diversion unit. Based on the relevant information, the diversion unit can provide the data in the target memory row to the peripheral device through the memory bus when the second count value is less than the pre-designed value. When the second count value is greater than or equal to the pre-designed value, the data in the target memory row is provided to the peripheral device through the cache bus.

[0110] Among them, the process of the counting unit obtaining the count value based on the cache access requests corresponding to each cache group and obtaining the count value from the SRAM can refer to the process of counting the cache access requests corresponding to each group of memory rows to obtain the count value and the process of obtaining the count value from the SRAM, which will not be elaborated in this embodiment.

[0111] Optionally, in the process of providing data in a target memory row to a peripheral device via a memory bus, a first data request for the target memory row can be constructed based on the address of the target memory row (i.e., the address tag), and then the first data request can be sent to the memory bus to provide the data in the target memory row to the peripheral device via the memory bus.

[0112] Similarly, in the process of providing data in a target memory row to a peripheral device via a cache bus, a second data request for the target memory row can be constructed based on the address of the target memory row, and then the second data request can be sent to the cache bus to provide data in the target memory row to the peripheral device via the cache bus.

[0113] As described above, the target memory row whose corresponding count value is less than the pre-designed value can be determined as the first target memory row, and the target memory row whose count value is greater than or equal to the pre-designed value can be determined as the second target memory row. For the first target memory row, the address (i.e., address tag) of the first target memory row can be determined based on the starting address included in the memory access request, and then the first data request for the first target memory row can be constructed based on the address tag, and the first data request can be forwarded to the memory bus. In this way, the data in the first target memory row returned by the memory bus can be obtained, and then the data in the first target memory row can be sent to the peripheral device.

[0114] Similarly, for the second target memory row, the address of the second target memory row can be determined based on the start address included in the memory access request, and then a second data request for the second target memory row is constructed based on the address tag, and the second data request is forwarded to the cache bus. In this way, the data in the second target memory row returned by the cache bus can be obtained, and then the data in the second target memory row can be sent to the peripheral device.

[0115] Optionally, the diversion unit includes a bit width converter, a splitter and an output distributor connected in sequence; the bit width converter is used to perform bit width conversion on the memory access request and send the converted memory access request to the splitter; when there are multiple target memory rows, the splitter creates a first data request for the first target memory row based on the converted memory access request, and / or creates a first data request for the second target memory row; the output distributor can send the first data request for the first target memory row to the memory bus to provide the data in the first target memory row to the peripheral device through the memory bus, and send the second data request for the second target memory row to the cache bus to provide the data in the second target memory row to the peripheral device through the cache bus.

[0116] like Figure 8 As shown, the diversion unit includes a bit width converter, which is used to convert the bit width of the memory access request. The bit width of the memory access request is generally 512 bits or 256 bits, and the bit width of the memory bus is generally 128 bits or 256 bits. For example, if the bit width of the memory access request is 512 bits and the bit width of the memory bus is 128 bits, after receiving the memory access request, the bit width converter can convert the bit width of the memory access request, convert the 512-bit memory access request into a 128-bit memory access request, and send the converted memory access request to the splitter.

[0117] The splitter may be a burst splitter, which may split the converted memory access request. For the converted memory access request, when there are multiple target memory rows, the splitter may split the memory access request into multiple data requests, each data request corresponding to a target memory row. Specifically, the address tag of each target memory row may be determined in turn based on the starting address and data length included in the memory access request. For each target memory row, a data request may be constructed based on the address tag to obtain a data request for each memory row. Afterwards, the splitter may send the split data request to the output distributor.

[0118] As described above, after receiving multiple data requests, the output distributor can determine the corresponding tag vector from 64 tag vectors for the data request corresponding to each target memory row. If the tag vector is 0, the data request is determined to be the first data request, and the first data request is sent to the memory bus. When the corresponding tag vector is 1, the data request is determined to be the second data request, and the second data request is sent to the cache bus. In this way, the peripheral device's access to multiple memory rows can be diverted to the memory bus and the cache bus, thereby reducing the peripheral device's occupancy of memory bandwidth, thereby improving the processor's memory access efficiency, and further improving the efficiency of the device cache consistency filtering monitoring system.

[0119] Optionally, after receiving the memory access request, the counting unit can also determine whether the processor is currently accessing the memory row accessed by the memory access request based on the address in the memory access request. If the processor is currently accessing the memory row accessed by the memory access request, a notification signal is output to the diversion unit to notify the diversion unit that the target memory row is being accessed. Correspondingly, after receiving the notification signal, the diversion unit stops providing the data in the target memory row to the peripheral device.

[0120] Afterwards, after determining that the processor has completed access to the target memory row, the counting unit may continue to execute the above steps, so that the diversion unit can provide the data in the target memory row to the peripheral device through the cache bus or the memory bus.

[0121] Combination of the above Figures 1 to 8 The memory access method provided by the embodiment of the present application is described in detail; Fig. 9 The device embodiments of the present application are described in detail. It should be understood that the device in the embodiments of the present application can execute the various methods of the aforementioned embodiments of the present application, that is, the specific working processes of the following various products can refer to the corresponding processes in the aforementioned method embodiments.

[0122] See also Fig. 9 , Fig. 9 Schematic diagram of a memory access device provided in an embodiment of the present application. Fig. 9 As shown, the memory access device 900 includes:

[0123] A determination module 901 is used to determine a target memory row to be accessed by a memory access request when receiving a memory access request sent by a peripheral device;

[0124] The determination module 901 is further used to determine a target cache group for storing data in the target memory row;

[0125] The providing module 902 is configured to provide the data in the target memory row to the peripheral device via a memory bus if some or all cache rows in the target cache group do not store data.

[0126] Optionally, the providing module 902 is specifically used to obtain a pre-stored first count value; wherein, the multiple memory rows corresponding to the target cache group are divided into multiple groups, the first count value corresponds to a group of memory rows where the target memory row is located, and the first count value represents the number of memory rows in the group of memory rows where data is written into the target cache group; if the first count value is less than a pre-designed value, the data in the target memory row is provided to the peripheral device through the memory bus.

[0127] Optionally, the providing module 902 is specifically used for obtaining the pre-stored first count value, including: determining the cache index of the target cache group and the target bit in the address tag of the target memory row; based on the cache index and the target bit in the address tag of the target memory row, obtaining the first count value from multiple pre-stored count values.

[0128] Optionally, the providing module 902 is further configured to provide the data in the target memory row to the peripheral device via a cache bus if the first count value is greater than or equal to the pre-designed value.

[0129] Optionally, the providing module 902 is specifically used to obtain a pre-stored second count value; wherein, the second count value represents the number of cache rows storing data in the target cache group; if the second count value is less than a pre-designed value, the data in the target memory row is provided to the peripheral device via the memory bus.

[0130] Optionally, the providing module 902 is specifically configured to determine a cache index of the target cache group; and based on the cache index, obtain the second count value from a plurality of pre-stored count values.

[0131] Optionally, the providing module 902 is further configured to provide the data in the target memory row to the peripheral device via a cache bus if the second count value is greater than or equal to the pre-designed value.

[0132] Optionally, the providing module 902 is specifically used to construct a first data request for the target memory row based on the address of the target memory row; and send the first data request to the memory bus to provide the data in the target memory row to the peripheral device through the memory bus.

[0133] It should be noted that the memory access device 900 is implemented in the form of a functional unit. The term "module" here can be implemented in the form of software and / or hardware, and is not specifically limited to this.

[0134] For example, a "module" may be a software program, a hardware circuit, or a combination of the two that implements the above functions. The hardware circuit may include an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor, or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit, and / or other suitable components that support the described functions.

[0135] Therefore, the units of each example described in the embodiments of the present application can be implemented by electronic hardware, or a combination of electronic equipment software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0136] In the description of the present disclosure, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances. In addition, in the description of the present disclosure, unless otherwise specified, "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previously associated objects are in an "or" relationship.

[0137] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, equivalent changes made according to the claims of the present disclosure are still within the scope covered by the present disclosure.

Claims

1. A memory access method, characterized in that: The method comprises: When receiving a memory access request sent by a peripheral device, determining a target memory row accessed by the memory access request; determining a target cache group for storing data in the target memory row; If some or all cache lines in the target cache group do not store data, providing the data in the target memory line to the peripheral device via a memory bus; Wherein, if some or all cache rows in the target cache group do not store data, the data in the target memory row is provided to the peripheral device through the memory bus, including: determining the cache index of the target cache group and the target bit in the address tag of the target memory row; based on the cache index and the target bit in the address tag of the target memory row, obtaining a first count value from a plurality of pre-stored count values; wherein the plurality of memory rows corresponding to the target cache group are divided into a plurality of groups according to the target bit in the address tag of each memory row, the first count value corresponds to a group of memory rows where the target memory row is located, and the first count value represents the number of memory rows in the group of memory rows whose data is written into the target cache group; if the first count value is less than a pre-designed value, the data in the target memory row is provided to the peripheral device through the memory bus. data; if the first count value is greater than or equal to the pre-designed value, providing the data in the target memory row to the peripheral device through the cache bus; or, if some or all of the cache rows in the target cache group do not store data, providing the data in the target memory row to the peripheral device through the memory bus, including: determining the cache index of the target cache group; based on the cache index, obtaining a second count value from a plurality of pre-stored count values; wherein the second count value represents the number of cache rows storing data in the target cache group; if the second count value is less than the pre-designed value, providing the data in the target memory row to the peripheral device through the memory bus; if the second count value is greater than or equal to the pre-designed value, providing the data in the target memory row to the peripheral device through the cache bus.

2. The method according to claim 1, characterized in that Providing the data in the target memory row to the peripheral device through the memory bus includes: Based on the address of the target memory row, construct a first data request for the target memory row; The first data request is sent to the memory bus to provide the data in the target memory row to the peripheral device through the memory bus.

3. The method according to claim 1 or 2, characterized in that Providing the data in the target memory row to the peripheral device through the cache bus includes: constructing a second data request for the target memory row based on the address of the target memory row; The second data request is sent to the cache bus to provide the data in the target memory row to the peripheral device through the cache bus.

4. A chip, characterized in that: include: A plurality of processors, caches of the plurality of processors are interconnected via a cache bus, and the cache bus is connected to the memory of the chip via a memory bus; A monitoring module, wherein the monitoring module is connected to the cache bus, the memory bus and the cache respectively, and the monitoring module is connected to the peripheral device of the chip, and the monitoring module is used to execute the memory access method as claimed in claim 1.

5. The chip according to claim 4, characterized in that: The plurality of memory rows corresponding to each cache group in the cache are divided into a plurality of groups, and the monitoring module includes a counting unit and a shunting unit; The counting unit is connected to the shunt unit and the cache, respectively, and is used to monitor the cache access request corresponding to each group of memory rows in the memory, and obtain the count value corresponding to each group of memory rows by counting the cache access request corresponding to each group of memory rows, respectively, and the count value represents the number of memory rows in the corresponding group of memory rows that are written into the cache; The counting unit is further configured to, upon receiving the memory access request, obtain a first counting value corresponding to a group of memory rows where the target memory row is located from the plurality of counting values, and send relevant information of the first counting value and the memory access request to the diversion unit; The shunt unit is connected to the memory bus, and is used to provide the data in the target memory row to the peripheral device through the memory bus based on the relevant information when the first count value is less than a pre-designed value.

6. The chip according to claim 4, characterized in that: The monitoring module includes a counting unit and a shunt unit; The counting unit is connected to the cache, and is used to monitor the cache access request of each cache group in the cache, and obtain the count value corresponding to each cache group by counting the cache access request of each cache group respectively; wherein the count value represents the number of cache lines storing data in the corresponding cache group; The counting unit is further configured to, upon receiving the memory access request, obtain a second counting value corresponding to the target cache group from the plurality of counting values, and send relevant information of the second counting value and the memory access request to the diversion unit; The shunt unit is connected to the memory bus, and is used to provide the data in the target memory row to the peripheral device through the memory bus based on the relevant information when the second count value is less than a pre-designed value.

7. The chip according to claim 5 or 6, characterized in that: The shunt unit includes a bit width converter, a splitter and an output distributor connected in sequence; The bit width converter is used to perform bit width conversion on the memory access request and send the converted memory access request to the splitter; The splitter is used to create a first data request for a first target memory row and / or a second data request for a second target memory row based on the memory access request obtained by conversion when there are multiple target memory rows; wherein the count value corresponding to the first target memory row is less than the target memory row of a pre-designed value, and the count value corresponding to the second target memory row is greater than or equal to the pre-designed value; The output distributor is used to send a first data request for the first target memory row to the memory bus to provide the data in the first target memory row to the peripheral device through the memory bus, and to send a second data request for the second target memory row to the cache bus to provide the data in the second target memory row to the peripheral device through the cache bus.

8. A device cache consistency filtering monitoring system, characterized in that: Comprising the chip as claimed in any one of claims 4 to 7.

Images