Display panel, display panel driving method, display device

Abstract

A display panel includes a pixel circuit, a gate of a first transistor of the pixel circuit is connected to a first gate signal line, a source is connected to a first data line, and a drain is connected to a first capacitor; a gate of a second transistor is connected to a second gate signal line, a source is connected to the first capacitor, and a drain is connected to a second capacitor. When high-frequency display is performed, the second transistor is turned off in a case where the first transistor is turned on, and a storage capacitor of the pixel circuit is the first capacitor; when low-frequency display is performed, the second transistor is turned on, and the storage capacitor of the pixel circuit is a sum of the first capacitor and the second capacitor. The display panel can be switched according to requirements of low-frequency display and high-frequency display, without increasing a size of the first transistor, thereby saving display power consumption of the display panel. A driving method of the display panel and a display device including the display panel are also provided.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel, a driving method for the display panel, and a display device. Background Technology

[0002] Some display panels typically employ both high-frequency and low-frequency display modes. To meet the requirements of low-frequency display, the storage capacitance of the sub-pixels is increased.

[0003] However, increasing the storage capacitor requires increasing the size of the first transistor for high-frequency displays, which in turn increases the load on the first gate signal line and the first data line, thereby increasing the display power consumption of the display panel.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to overcome the problem of increased power consumption in transflective display panels caused by increased storage capacitors, and to provide a display panel, a driving method for the display panel, and a display device.

[0006] According to one aspect of the present invention, a display panel is provided, the display panel including a substrate and a driving circuit layer, the driving circuit layer being disposed on one side of the substrate, the driving circuit layer including a first data line, a first gate signal line, a second gate signal line and a plurality of pixel circuits, the pixel circuit including a first transistor, a second transistor, a first capacitor and a second capacitor, the gate of the first transistor being connected to the first gate signal line, the source being connected to the first data line, and the drain being connected to the first capacitor, the gate of the second transistor being connected to the second gate signal line, the source being connected to the first capacitor, and the drain being connected to the second capacitor.

[0007] In one embodiment of the present invention, the display panel has a reflective area, and both the first capacitor and the second capacitor are located in the reflective area.

[0008] In one embodiment of the present invention, the display panel further has a transmissive area, and a first capacitor and a second capacitor are respectively disposed on both sides of the transmissive area along the column direction.

[0009] In one embodiment of the present invention, the orthogonal projection of the first capacitor on the substrate is greater than the orthogonal projection of the second capacitor on the substrate.

[0010] In one embodiment of the present invention, the driving circuit layer further includes a gate layer, an active layer, and a first conductive layer. The gate layer is disposed on one side of the substrate and has a first gate signal line and a second gate signal line. The gate layer also includes a first gate portion and a second gate portion. The first gate signal line and the second gate signal line extend in a row direction. The first gate signal line is connected to the first gate portion, and the second gate signal line is connected to the second gate portion. The active layer is disposed on the side of the gate layer away from the substrate and includes a first active portion and a second active portion. The orthographic projection of the first gate portion on the substrate overlaps with the orthographic projection of the channel region of the first active portion on the substrate to form the gate of the first transistor. The orthographic projection of the second gate portion on the substrate overlaps with the orthographic projection of the channel region of the second active portion on the substrate to form the gate of the second transistor. Gate; A first conductive layer is disposed on the side of the active layer away from the substrate. The first conductive layer includes a first conductive portion, a second conductive portion, a third conductive portion, a fourth conductive portion, and a first data line. The first conductive portion is connected to the first data line. The orthographic projection of the first conductive portion on the substrate overlaps with the orthographic projection of the source region of the first active portion on the substrate to form the source of the first transistor. The orthographic projection of the second conductive portion on the substrate overlaps with the orthographic projection of the drain region of the first active portion on the substrate to form the drain of the first transistor. The orthographic projection of the third conductive portion on the substrate overlaps with the orthographic projection of the source region of the second active portion on the substrate to form the source of the second transistor. The orthographic projection of the fourth conductive portion on the substrate overlaps with the orthographic projection of the drain region of the second active portion on the substrate to form the drain of the second transistor.

[0011] In one embodiment of the present invention, the first capacitor includes a first sub-capacitor, and the second capacitor includes a second sub-capacitor; the gate layer further includes a first common electrode and a second common electrode, wherein the orthographic projection of the first common electrode on the substrate and the orthographic projection of the second conductive portion on the substrate overlap each other to form the first sub-capacitor; and the orthographic projection of the second common electrode on the substrate and the orthographic projection of the fourth conductive portion on the substrate overlap each other to form the second sub-capacitor.

[0012] In one embodiment of the present invention, the display panel further includes a transmissive layer, the transmissive layer including transmissive pixel electrodes, the transmissive pixel electrodes being connected to a second conductive portion through vias.

[0013] In one embodiment of the present invention, the transmissive layer is a transparent conductive layer, and the display panel further includes an insulating layer and a reflective layer. The insulating layer is disposed on the side of the transmissive layer away from the substrate and has a transmissive opening. The reflective layer is disposed on the side of the insulating layer away from the substrate and includes a reflective pixel electrode. The reflective pixel electrode extends along the sidewall of the transmissive opening to connect with the transmissive pixel electrode.

[0014] In one embodiment of the present invention, the first capacitor includes a third sub-capacitor, and the second capacitor includes a fourth sub-capacitor; the transmissive layer further includes a third common electrode and a fourth common electrode, which are respectively disposed on both sides of the transmissive pixel electrode along the column direction. The orthographic projection of the third common electrode on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate to form a third sub-capacitor, and the orthographic projection of the fourth common electrode on the substrate overlaps with the orthographic projection of the fourth conductive portion on the substrate to form a fourth sub-capacitor.

[0015] In one embodiment of the present invention, the first capacitor includes a third sub-capacitor, the second capacitor includes a fourth sub-capacitor, and the display panel further includes a second conductive layer disposed between the transmissive layer and the first conductive layer. The orthographic projection of the second conductive layer on the substrate and the orthographic projection of the second conductive portion on the substrate overlap to form the third sub-capacitor, and the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the fourth conductive portion on the substrate overlap to form the fourth sub-capacitor.

[0016] In one embodiment of the present invention, the first capacitor further includes a fifth sub-capacitor, the second capacitor further includes a sixth sub-capacitor, the transmissive layer further includes a third common electrode and a fourth common electrode, the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third common electrode on the substrate overlap to form the fifth sub-capacitor, and the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the fourth common electrode on the substrate overlap to form the sixth sub-capacitor.

[0017] In one embodiment of the present invention, the display panel further includes a third transistor, a second data line, and a third gate signal line. The third transistor is located on the periphery of each row of pixel circuits along the row direction. The gate of the third transistor is connected to the third gate signal line, the source of the third transistor is connected to the second data line, and the drain of the third transistor is connected to the second gate signal line.

[0018] In one embodiment of the present invention, the first conductive layer is provided with a second data line and a third gate signal line. The gate layer further includes a third gate portion, which is disposed between the second data line and the second data line along the row direction. The third gate portion is connected to the third gate signal line through a via. The first conductive layer further includes a fifth conductive portion and a sixth conductive portion. The fifth conductive portion is connected to the second data line, and the sixth conductive portion is connected to the second gate signal line through a via.

[0019] In one embodiment of the present invention, the orthogonal projection of the reflective pixel electrode on the substrate covers the orthogonal projection of the first gate signal line on the substrate and the orthogonal projection of the second gate signal line on the substrate.

[0020] In one embodiment of the present invention, the width of the gate of the second transistor is smaller than the width of the gate of the first transistor.

[0021] According to another aspect of the present invention, a method for driving a display panel provided in one aspect of the present invention is provided, the method comprising:

[0022] When the first gate signal line is charged with a high level, the first transistor is turned on.

[0023] When performing high-frequency display, the second gate signal line is loaded with a low level, the second transistor is turned off, the second capacitor is 0, and the storage capacitor of the pixel circuit is the first capacitor.

[0024] When performing low-frequency display, the second gate signal line is loaded with a high level, the second transistor is turned on, and the storage capacitance of the pixel circuit is the sum of the first capacitance and the second capacitance.

[0025] In one embodiment of the present invention, when performing high-frequency display, the second gate signal line is loaded with a low level and the second transistor is turned off includes: when performing high-frequency display, the third gate signal line is loaded with a high level, the second data line is loaded with a low level, and all second transistors connected to the second data line are turned off.

[0026] When performing low-frequency display, the second gate signal line is loaded with a high level, and the second transistor is turned on, including: when performing low-frequency display, the second data line is loaded with a high level, all the second transistors connected to the second data line are turned on, and the storage capacitance of the pixel circuit is the sum of the first capacitance and the second capacitance.

[0027] According to another aspect of the present invention, a display device is provided, comprising a display panel provided in one aspect of the present invention.

[0028] The display panel of this invention includes a pixel circuit, which comprises a first transistor, a second transistor, a first capacitor, and a second capacitor. The gate of the first transistor is connected to a first gate signal line, the source is connected to a first data line, and the drain is connected to the first capacitor. The gate of the second transistor is connected to a second gate signal line, the source is connected to the first capacitor, and the drain is connected to the second capacitor. When the first transistor is on, during high-frequency display, the second transistor is off, the second capacitor is zero, and the storage capacitance of the pixel circuit is the first capacitor. During low-frequency display, the second transistor is on, and the storage capacitance of the pixel circuit is the sum of the first and second capacitors. Switching can be performed according to the needs of low-frequency and high-frequency display without increasing the size of the first transistor, thereby saving display power consumption of the display panel.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0031] Figure 1 This is a schematic diagram of the driving circuit layer in an embodiment of the present invention when the pixel circuit includes a first transistor and a first capacitor.

[0032] Figure 2 This is a layout of the gate layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0033] Figure 3 This is a layout of the active layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0034] Figure 4 This is a layout of the first conductive layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0035] Figure 5 This is a layout of the second conductive layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0036] Figure 6 This is a layout of the transmissive layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0037] Figure 7 This is a schematic diagram of the transmission opening on the insulating layer according to an embodiment of the present invention when the pixel circuit includes a first transistor and a first capacitor.

[0038] Figure 8 This is a layout of the reflective layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0039] Figure 9 This is a layout of the gate layer, active layer, and first conductive layer stacked together in an embodiment of the present invention when the pixel circuit includes a first transistor and a first capacitor.

[0040] Figure 10 This is a layout of the gate layer, active layer, first conductive layer and second conductive layer stacked together in an embodiment of the present invention when the pixel circuit includes a first transistor and a first capacitor.

[0041] Figure 11This is a layout of the gate layer, active layer, first conductive layer, second conductive layer and transmissive layer stacked together in an embodiment of the present invention when the pixel circuit includes a first transistor and a first capacitor.

[0042] Figure 12 This is a layout of the gate layer, active layer, first conductive layer, second conductive layer, transmissive layer, and insulating layer with their transmission openings stacked together, according to embodiments of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0043] Figure 13 This is a layout of the gate layer, active layer, first conductive layer, second conductive layer, transmissive layer, transmissive opening on the insulating layer, and reflective layer stacked together when the pixel circuit includes a first transistor and a first capacitor, according to embodiments of the present invention.

[0044] Figure 14 for Figure 13 A schematic diagram of the cross-section between A1 and A1.

[0045] Figure 15 for Figure 13 A schematic diagram of the cross-section between B1 and B1.

[0046] Figure 16 for Figure 13 A schematic diagram of the cross-section between C1 and C1.

[0047] Figure 17 for Figure 10 A schematic diagram of the cross-section between D1 and D1.

[0048] Figure 18 This is a layout of the driving backplane according to an embodiment of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0049] Figure 19 This refers to the layout of the peripheral area of ​​the display panel according to embodiments of the present invention, when the pixel circuit includes a first transistor and a first capacitor.

[0050] Figure 20 This is a schematic diagram of the driving circuit layer in an embodiment of the present invention when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0051] Figure 21 This is a layout of the gate layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0052] Figure 22 This is a layout of the active layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0053] Figure 23 This is a layout of the first conductive layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0054] Figure 24 This is a layout of the transmissive layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0055] Figure 25 This is a schematic diagram of the transmission opening on the insulating layer according to an embodiment of the present invention, when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0056] Figure 26 This is a layout of the reflective layer of the display panel according to an embodiment of the present invention, when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0057] Figure 27 This is a layout of the gate layer, active layer, and first conductive layer stacked together when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor, according to an embodiment of the present invention.

[0058] Figure 28 This is a layout of the gate layer, active layer, first conductive layer and transmissive layer stacked together when the pixel circuit includes a first transistor, a second transistor, a first capacitor and a second capacitor, according to an embodiment of the present invention.

[0059] Figure 29 This is a layout of the gate layer, active layer, first conductive layer, transmissive layer and reflective layer stacked together when the pixel circuit includes a first transistor, a second transistor, a first capacitor and a second capacitor, according to the embodiments of the present invention.

[0060] Figure 30 for Figure 29 A schematic diagram of the cross-section between A1 and A1.

[0061] Figure 31 for Figure 29 A schematic diagram of the cross-section between B1 and B1.

[0062] Figure 32 for Figure 29 A schematic diagram of the cross-section between C1 and C1.

[0063] Figure 33 for Figure 28 Schematic diagram of cross sections E1-E1 and F1-F1.

[0064] Figure 34This is the layout of the driving backplane in the embodiments of the present invention when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0065] Figure 35 This refers to the layout of the peripheral area of ​​the display panel in the embodiments of the present invention, when the pixel circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor.

[0066] Figure 36 The schematic diagram of the driving circuit layer in this embodiment of the invention is shown when the driving circuit layer also includes a third transistor.

[0067] Figure 37 The layout of the driving backplane in this embodiment of the invention is as follows: when the driving circuit layer also includes a third transistor.

[0068] Figure 38 This is a layout of the peripheral area of ​​the display panel according to an embodiment of the present invention, when the driving circuit layer also includes a third transistor.

[0069] Figure 39 This is the layout of the gate layer, active layer, and first conductive layer stacked together in the embodiments of the present invention when the driving circuit layer further includes a third transistor and a second conductive layer is disposed between the first conductive layer and the transmission layer.

[0070] Figure 40 The layout of the second conductive layer in this embodiment of the invention is as follows: when the driving circuit layer further includes a third transistor, and a second conductive layer is disposed between the first conductive layer and the transmissive layer.

[0071] Figure 41 This is the layout of the gate layer, active layer, first conductive layer and second conductive layer stacked together when the driving circuit layer further includes a third transistor and a second conductive layer is disposed between the first conductive layer and the transmission layer.

[0072] Figure 42 The layout of the gate layer, active layer, first conductive layer, second conductive layer and transmission layer stacked together in the embodiments of the present invention is as follows: when the driving circuit layer also includes a third transistor and a second conductive layer is disposed between the first conductive layer and the transmission layer.

[0073] Figure 43 This is the layout of the gate layer, active layer, first conductive layer, second conductive layer, transmission layer and insulating layer stacked together in the embodiments of the present invention when the driving circuit layer also includes a third transistor and a second conductive layer is disposed between the first conductive layer and the transmission layer.

[0074] Figure 44This is the layout of the gate layer, active layer, first conductive layer, second conductive layer, transmission layer, insulating layer and reflective layer stacked together in the embodiments of the present invention when the driving circuit layer also includes a third transistor and a second conductive layer is disposed between the first conductive layer and the transmission layer.

[0075] Figure 45 for Figure 44 A schematic diagram of the cross-section between A1 and A1.

[0076] Figure 46 for Figure 44 A schematic diagram of the cross-section between B1 and B1.

[0077] Figure 47 for Figure 44 A schematic diagram of the cross-section between C1 and C1.

[0078] Figure 48 for Figure 41 Schematic diagram of cross sections G1-G1 and H1-H1.

[0079] Figure 49 The layout of the driving backplane in this embodiment of the invention is as follows: when the driving circuit layer further includes a third transistor and a second conductive layer is disposed between the first conductive layer and the transmissive layer.

[0080] Figure 50 The layout of the peripheral area of ​​the display panel in this embodiment of the invention is as follows: when the driving circuit layer further includes a third transistor and a second conductive layer is disposed between the first conductive layer and the transmissive layer.

[0081] In the diagram: 1-Substrate, 2-Driver circuit layer, 21-Gate layer, 211-First gate portion, 212-Second gate portion, 213-First gate signal line, 214-Second gate signal line, 215-First common electrode, 216-Second common electrode, 217-First common signal line, 218-Second common signal line, 219-Third gate portion, 22-Active layer, 221-First active portion, 222-Second active portion, 23-Gate insulating layer, 24-First conductive layer, 241-First conductive portion, 242-Second conductive portion, 2421-First transition portion, 243-Third conductive portion, 244-Fourth conductive portion, 2441-Second transition portion, 245-First data line, 246-Third gate signal line, 247-Second data line, 248-Peripheral common signal line, 2401-Fifth gate layer Electrical section, 2402-Sixth conductive section, 25-Second conductive layer, 251-First opening, 2511-First sub-opening, 2512-Second sub-opening, 252-Second opening, 253-Third opening, 261-First protective layer, 262-Second protective layer, 27-Transmitting layer, 271-Transmitting pixel electrode, 272-Third common electrode, 273-Fourth common electrode, 274-Third common signal line, 275-Fourth common signal line, 28-Insulating layer, 281-Transmitting opening, 29-Reflective layer, 291-Reflective pixel electrode, TFT1-First transistor, TFT2-Second transistor, 200-Pixel circuit, 201-First via, 202-Second via, 203-Third via, 204-Fourth via, 205-Fifth via, 206-Sixth via, 207-Seventh via. Detailed Implementation

[0082] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted. Furthermore, the drawings are merely illustrative of the invention and are not necessarily drawn to scale.

[0083] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0084] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0085] Outdoor displays typically suffer from high ambient light, resulting in less clear images. Improving the display quality is usually achieved by adjusting the overall screen brightness, but this increases power consumption. Reflective displays can significantly reduce power consumption in high-brightness environments, but they fail to provide clear images in low-light conditions or at night. To reduce power consumption, reflective mode is used in high-brightness environments, while transmissive mode is used in low-brightness environments.

[0086] Transmissive displays typically operate at their highest frequency across different screen display modes. To further reduce power consumption, the display frequency can be switched according to the dynamic screen display, achieving clear display in various scenarios. When a transmissive display panel employs both high-frequency and low-frequency display modes, the storage capacitor of the sub-pixels is increased to meet the requirements of low-frequency display.

[0087] like Figures 1 to 16 As shown, the display panel includes a driving backplane, which generally includes a substrate 1 and a driving circuit layer 2. The driving circuit layer 2 is disposed on one side of the substrate 1. The driving circuit layer 2 includes a first gate signal line 213, a first data line 245, and a plurality of pixel circuits 200. The first gate signal line 213 is disposed between two adjacent rows of pixel circuits 200, and the first data line 245 is disposed between two adjacent columns of pixel circuits 200. The pixel circuit 200 includes a first transistor TFT1 and a first capacitor C1. The gate of the first transistor TFT1 is connected to the first gate signal line 213, the source is connected to the first data line 245, and the drain is connected to the first capacitor C1.

[0088] The driving circuit layer 2 includes a gate layer 21, which is disposed on one side of the substrate 1. The gate layer 21 has a first gate signal line 213, a plurality of first gate portions 211, a plurality of first common electrodes 215 and a first common signal line 217. The first gate signal line 213 and the first common signal line 217 extend in the row direction. The first gate signal line 213 is connected to the plurality of first gate portions 211 and the first common signal line 217 is connected to the plurality of first common electrodes 215.

[0089] The driving circuit layer 2 also includes a gate insulating layer 23 and an active layer 22. The gate insulating layer 23 is disposed on the side of the gate layer 21 away from the substrate 1, and the active layer 22 is disposed on the side of the gate insulating layer 23 away from the substrate 1. The active layer 22 includes a first active portion 221. The orthographic projection of the first gate portion 211 on the substrate 1 overlaps with the orthographic projection of the channel region of the first active portion 221 on the substrate 1 to form the gate of the first transistor TFT1.

[0090] The driving circuit layer 2 also includes a first conductive layer 24. The first conductive layer 24 is disposed on the side of the active layer 22 and the gate insulating layer 23 away from the substrate 1. The first conductive layer 24 includes a first conductive portion 241 and a second conductive portion 242. The orthographic projection of the first conductive portion 241 on the substrate 1 overlaps with the orthographic projection of the source region of the first active portion 221 on the substrate 1 to form the source of the first transistor TFT1. The orthographic projection of the second conductive portion 242 on the substrate 1 overlaps with the orthographic projection of the drain region of the first active portion 221 on the substrate 1 to form the drain of the first transistor TFT1.

[0091] The driving circuit layer 2 further includes a first protective layer 261 and a second conductive layer 25. The first protective layer 261 is disposed on the side of the first conductive layer 24 away from the substrate 1, and the second conductive layer 25 is disposed on the side of the first protective layer 261 away from the substrate 1. The second conductive layer 25 has a first opening 251 and a second opening 252. The driving circuit layer 2 also includes a second protective layer 262, which is disposed on the side of the second conductive layer 25 away from the substrate 1. The second protective layer 262 directly contacts the first protective layer 261 within the first opening 251 and the second opening 252. It should be noted that the areas with hexagonal patterns in each figure represent the second conductive layer 25.

[0092] The first opening 251 includes a first sub-opening 2511 and a second sub-opening 2512. The second sub-opening 2512 is located along the column direction on the side of the first sub-opening 2511 near the second conductive portion 242, and the second sub-opening 2512 communicates with the first sub-opening 2511. The orthographic projection of the second sub-opening 2512 on the substrate 1 overlaps with the orthographic projection of the second conductive portion 242 on the substrate 1. A first through-hole 201 is provided in the second sub-opening 2512, and the first through-hole 201 passes through the second protective layer 262 and the first protective layer 261.

[0093] The driving circuit layer 2 further includes a transmissive layer 27, which includes a transmissive pixel electrode 271. The orthographic projection of the transmissive pixel electrode 271 on the substrate 1 covers the orthographic projection of the first opening 251 on the substrate 1. The transmissive pixel electrode 271 is connected to the second conductive portion 242 through a first via 201. The driving circuit layer 2 also includes an insulating layer 28 and a reflective layer 29. The insulating layer 28 is disposed on the side of the transmissive layer 27 away from the substrate 1 and has a transmissive opening 281. The reflective layer 29 is disposed on the side of the insulating layer 28 away from the substrate 1 and includes a reflective pixel electrode 291. The reflective pixel electrode 291 extends from the side of the insulating layer away from the substrate 1 along the edge and sidewall of the transmissive opening 281 to connect with the transmissive pixel electrode 271.

[0094] The orthographic projection of the reflective layer 29 onto the substrate 1 covers the orthographic projections of the first gate signal line 213 and the first data line 245 onto the substrate 1. The overlapping locations of the orthographic projections of the reflective layer 29 and the first gate signal line 213, as well as the overlapping locations of the orthographic projections of the reflective layer 29 and the first data line 245 onto the substrate 1, form shielding portions. This prevents light leakage at the locations of the first data line 245 and the first gate signal line 213 during display. Since the linewidths of the first data line 245 and the first gate signal line 213 are relatively small, the width of the shielding portions formed here is typically smaller than the width of separately provided shielding portions, increasing the reflective area and thus improving the aperture ratio in the reflection mode.

[0095] To improve the reflective effect of the reflective layer 29, an uneven surface can be provided on the side of the insulating layer 28 away from the substrate 1, so that an uneven reflective surface is formed on the side of the reflective layer 29 away from the substrate 1, thereby increasing the reflective area of ​​the side of the reflective layer 29 away from the substrate 1 and thus improving the reflective effect of the reflective layer 29.

[0096] Figure 17 for Figure 10 A schematic diagram of the cross-section between D1 and D1 is shown below. Figure 10 and Figure 17As shown, the orthographic projection of the second conductive portion 242 on the substrate 1 overlaps with the orthographic projection of the first common electrode 215 on the substrate 1, forming a first capacitor, which includes only one sub-capacitor. To match low-frequency displays, the storage capacitor size is around 1pF. Therefore, the orthographic projection of the second conductive layer 25 on the substrate 1 overlaps with the orthographic projection of the second conductive portion 242 on the substrate 1, forming another sub-capacitor. This first capacitor includes two sub-capacitors, significantly increasing the storage capacitor. However, increasing the storage capacitor requires increasing the transistor size for high-frequency displays, thereby increasing the load on the first gate signal line 213 and the first data line 245, thus increasing the display power consumption of the transflective display panel.

[0097] like Figure 18 and Figure 19 As shown, multiple first common electrodes 215 are connected together via first common signal lines 217 extending along the row direction. The first common signal lines 217 extend from the display area AA to the peripheral area of ​​the display panel and are connected to the peripheral common signal line 248 via a second via 202. The second conductive layer 25 extends from the display area AA to the peripheral area of ​​the display panel and is connected to the peripheral common signal line 248 via a third via 203. It should be noted that the peripheral area is located outside the display area AA.

[0098] The manufacturing process of this display panel is as follows: A gate layer 21 is deposited on a substrate 1. A first gate signal line 213, a plurality of first gate portions 211, a plurality of first common electrodes 215, and a first common signal line 217 are formed using a first mask. A gate insulating layer 23 and an active layer 22 are deposited on the gate layer 21. A first active portion 221 is formed using a second mask. A first conductive layer 24 is deposited on the active layer 22. A first conductive portion 241, a second conductive portion 242, and a first data line 245 are formed in one step using a third mask. A first protective layer 261 is deposited on the first conductive layer 24. A second conductive layer 25 is formed on the first protective layer 261. A first opening 251 and a second opening 252 are formed on the second conductive layer 25 using a fourth mask. A second protective layer 262 is deposited on the second conductive layer 25. A first via 201 is formed within the second sub-opening 2512 using a fifth mask, passing through the second protective layer 262 and the first protective layer 261, exposing the second conductive portion 242 within the first via 201. A transmissive layer 27, made of dense indium tin oxide, is then deposited on the second protective layer 262. A transmissive pixel electrode 271 is formed on the transmissive layer 27 using a sixth mask. An insulating layer 28 is formed on the transmissive layer 27, and a transmissive opening 281 is formed on the insulating layer 28. Finally, a reflective layer 29 is formed on the insulating layer 28, including a reflective pixel electrode 291 that extends along the sidewall of the transmissive opening 281 to connect with the transmissive pixel electrode 271.

[0099] The display panel has the following film layers in the channel region of the first active portion 221: gate layer 21, gate insulating layer 23, active layer 22, first conductive layer 24, first protective layer 261, second protective layer 262, insulating layer 28, and reflective layer 29. The display panel has the following film layers in other reflective regions: gate layer 21, gate insulating layer 23, first conductive layer 24, first protective layer 261, second conductive layer 25, second protective layer 262, insulating layer 28, and reflective layer 29. The display panel has the following film layers in the transmissive region: gate insulating layer 23, first protective layer 261, second protective layer 262, and transmissive layer 27. The difference in film thickness between the transmissive and reflective regions is the difference between the sum of the thicknesses of the gate layer 21, first conductive layer 24, second conductive layer 25, insulating layer 28, and reflective layer 29 and the thickness of the transmissive layer 27. The cell thickness of the transmissive region is twice the cell thickness of the reflective region.

[0100] Based on this, embodiments of the present invention provide a display panel. For example... Figures 20 to 50 As shown, the display panel includes a substrate 1 and a driving circuit layer 2. The driving circuit layer 2 is disposed on one side of the substrate 1. The driving circuit layer 2 includes a first data line 245, a first gate signal line 213, a second gate signal line 214, and a plurality of pixel circuits 200. The pixel circuit 200 includes a first transistor TFT1, a second transistor TFT2, a first capacitor C1, and a second capacitor C2. The gate of the first transistor TFT1 is connected to the first gate signal line 213, the source is connected to the first data line 245, and the drain is connected to the first capacitor C1. The gate of the second transistor TFT2 is connected to the second gate signal line 214, the source is connected to the first capacitor C1, and the drain is connected to the second capacitor C2.

[0101] The display panel includes a pixel circuit 200, which includes a first transistor TFT1, a second transistor TFT2, a first capacitor, and a second capacitor C2. The drain of the first transistor TFT1 is connected to the first capacitor, and the source of the second transistor TFT2 is connected to the first capacitor, while its drain is connected to the second capacitor C2. When the first transistor TFT1 is on, for high-frequency display, the second transistor TFT2 is off, the second capacitor C2 is zero, and the storage capacitance of the pixel circuit 200 is the first capacitor. For low-frequency display, the second transistor TFT2 is on, and the storage capacitance of the pixel circuit 200 is the sum of the first capacitor C1 and the second capacitor C2. Switching can be performed according to the needs of low-frequency and high-frequency display without increasing the size of the first transistor TFT1, thus saving display power consumption of the display panel.

[0102] The display panel involved in the embodiments of the present invention will be described in detail below with reference to specific examples.

[0103] like Figures 20 to 32As shown, the display panel includes a driving backplane, which generally includes a substrate 1 and a driving circuit layer 2. The driving circuit layer 2 includes a first data line 245, a first gate signal line 213, a second gate signal line 214, and a plurality of pixel circuits 200. The first gate signal line 213 and the second gate signal line 214 extend along the row direction. Each row of pixel circuits 200 is disposed between the first gate signal line 213 and the second gate signal line 214. The first gate signal line 213 of the previous row of pixel circuits 200 is adjacent to the second gate signal line 214 of the current row of pixel circuits 200. The first data line 245 is disposed between two adjacent columns of pixel circuits 200.

[0104] The pixel circuit 200 includes a first transistor TFT1, a second transistor TFT2, a first capacitor C1, and a second capacitor C2. The gate of the first transistor TFT1 is connected to the first gate signal line 213, the source is connected to the first data line 245, and the drain is connected to the first capacitor C1. The gate of the second transistor TFT2 is connected to the second gate signal line 214, the source is connected to the first capacitor C1, and the drain is connected to the second capacitor C2.

[0105] The driving circuit layer 2 further includes a gate layer 21, which is disposed on one side of the substrate 1. The gate layer 21 includes a first gate portion 211, a second gate portion 212, a first gate signal line 213, and a second gate signal line 214. The first gate signal line 213, the second gate signal line 214, the first common signal line 217, and the second common signal line 218 extend along the row direction. The first gate signal line 213 is connected to the first gate portion 211, and the second gate signal line 214 is connected to the second gate portion 212. The first gate portion 211 and the second gate portion 212 are located between the first gate signal line 213 and the second gate signal line 214 along the column direction.

[0106] The gate layer 21 also includes a first common electrode 215, a second common electrode 216, a first common signal line 217, and a second common signal line 218. The first common signal line 217 is connected to the first common electrode 215, and the second common signal line 218 is connected to the second common electrode 216. The first common signal line 217 is disposed adjacent to the first gate signal line 213 along the column direction. The first common electrode 215 is disposed along the column direction on the side of the first common signal line 217 away from the first gate signal line 213. The second common signal line 218 is disposed adjacent to the second gate signal line 214 along the column direction. The second common electrode 216 is disposed along the column direction on the side of the second common signal line 218 away from the first gate signal line 213.

[0107] The driving circuit layer 2 further includes a gate insulating layer 23 and an active layer 22. The gate insulating layer 23 is disposed on the side of the gate layer 21 away from the substrate 1, and the active layer 22 is disposed on the side of the gate layer 21 away from the substrate 1. The active layer 22 includes a first active portion 221 and a second active portion 222. The orthographic projection of the first gate portion 211 on the substrate 1 overlaps with the orthographic projection of the channel region of the first active portion 221 on the substrate 1 to form the gate of the first transistor TFT1. The orthographic projection of the second gate portion 212 on the substrate 1 overlaps with the orthographic projection of the channel region of the second active portion 222 on the substrate 1 to form the gate of the second transistor TFT2. The width of the gate of the second transistor TFT2 is smaller than the width of the gate of the first transistor TFT1 to avoid increasing the display power consumption of the display panel.

[0108] The driving circuit layer 2 also includes a first conductive layer 24. The first conductive layer 24 is disposed on the side of the active layer 22 away from the substrate 1. The first conductive layer 24 includes a first conductive portion 241 and a second conductive portion 242. The orthographic projection of the first conductive portion 241 on the substrate 1 overlaps with the orthographic projection of the source region of the first active portion 221 on the substrate 1 to form the source of the first transistor TFT1. The orthographic projection of the second conductive portion 242 on the substrate 1 overlaps with the orthographic projection of the drain region of the first active portion 221 on the substrate 1 to form the drain of the first transistor TFT1.

[0109] The first conductive layer 24 further includes a third conductive portion 243 and a fourth conductive portion 244. The orthographic projection of the third conductive portion 243 on the substrate 1 overlaps with the orthographic projection of the source region of the second active portion 222 on the substrate 1 to form the source of the second transistor TFT2. The orthographic projection of the fourth conductive portion 244 on the substrate 1 overlaps with the orthographic projection of the drain region of the second active portion 222 on the substrate 1 to form the drain of the second transistor TFT2.

[0110] The driving circuit layer 2 further includes a protective layer 26 and a transmissive layer 27. The protective layer 26 is disposed on the side of the first conductive layer 24 away from the substrate 1, and the transmissive layer 27 is disposed on the side of the protective layer 26 away from the substrate 1. The transmissive layer 27 includes a transmissive pixel electrode 271. A first via 201 is provided on the protective layer 26, and a second conductive portion 242 includes a first adapter portion 2421. The transmissive pixel electrode 271 is connected to the first adapter portion 2421 through the first via 201. It should be noted that the protective layer 26 may include a first protective layer and a second protective layer. The first protective layer may be disposed on the side of the first conductive layer 24 away from the substrate 1, and the second protective layer may be disposed on the side of the first protective layer away from the substrate 1.

[0111] The fourth conductive part 244 includes a second transition part 2441. The orthographic projection of the first transition part 2421 on the substrate 1 overlaps with the orthographic projection of the first common electrode 215 on the substrate 1 to form a first sub-capacitor. The orthographic projection of the second transition part 2441 on the substrate 1 overlaps with the orthographic projection of the second common electrode 216 on the substrate 1 to form a second sub-capacitor.

[0112] The transmissive layer 27 also includes a third common electrode 272, a fourth common electrode 273, a third common signal line 274, and a fourth common signal line 275. The third common electrode 272 and the fourth common electrode 273 are respectively disposed on both sides of the transmissive pixel electrode 271 along the column direction. The third common signal line 274 is connected to the third common electrode 272 and is disposed on the side of the third common electrode 272 away from the transmissive pixel electrode 271. The fourth common signal line 275 is connected to the fourth common electrode 273 and is disposed on the side of the fourth common electrode away from the transmissive pixel electrode 271.

[0113] The driving circuit layer 2 also includes an insulating layer 28 and a reflective layer 29. The insulating layer 28 is disposed on the side of the transmissive layer 27 away from the substrate 1, and has a transmissive opening 281. The reflective layer 29 is disposed on the side of the insulating layer 28 away from the substrate 1, and includes a reflective pixel electrode 291. The reflective pixel electrode 291 extends along the sidewall of the transmissive opening 281 to connect with the transmissive pixel electrode 271. When the external light is weak, the display device provides a backlight, and the transmissive pixel electrode 271 and the common electrode form a pressure difference to drive the liquid crystal molecules to rotate, and the display panel is in transmissive mode. When the external light is strong, ambient light is used as the light source, and the reflective pixel electrode 291 and the common electrode form a pressure difference to drive the liquid crystal molecules to rotate, and the display panel is in reflective mode.

[0114] Figure 33 for Figure 28 Cross-sectional diagrams of E1-E1 and F1-F1 are shown below. Figure 28 and Figure 33 As shown, the orthographic projection of the third common electrode 272 on the substrate 1 overlaps with the orthographic projection of the second conductive portion 242 on the substrate 1 to form a third sub-capacitor. The orthographic projection of the fourth common electrode 273 on the substrate 1 overlaps with the orthographic projection of the fourth conductive portion 244 on the substrate 1 to form a fourth sub-capacitor. The first sub-capacitor and the third sub-capacitor together form the first capacitor, and the second sub-capacitor and the fourth sub-capacitor together form the second capacitor.

[0115] like Figure 34 and Figure 35As shown, multiple first common electrodes 215 are connected together via first common signal lines 217 extending along the row direction. The first common signal lines 217 extend to the peripheral area of ​​the display panel and are connected to the peripheral common signal line 248 via a second via 202. A second common signal line 218 extends to the peripheral area of ​​the display panel and is connected to the peripheral common signal line 248 via a fourth via 204. A second gate signal line 214 extends to the peripheral area of ​​the display panel and is connected to the second data line 247 via a fifth via 205.

[0116] The manufacturing process of this display panel is as follows: A gate layer 21 is deposited on a substrate 1. A first gate portion 211, a second gate portion 212, a first gate signal line 213, a second gate signal line 214, a first common electrode 215, a second common electrode 216, a first common signal line 217, and a second common signal line 218 are formed using a first mask. A gate insulating layer 23 and an active layer 22 are deposited on the gate layer 21. A first active portion 221 and a second active portion 222 are formed using a second mask. A first conductive layer 24 is deposited on the active layer 22. A first conductive portion 241, a second conductive portion 242, a third conductive portion 243, a fourth conductive portion 244, and a first data line 245 are formed in one pass using a third mask. A protective layer 26 is deposited on the first conductive layer 24. A first via 201 is formed through the protective layer 26 using a fifth mask, exposing the second conductive portion 242 within the first via 201. Next, a transmission layer 27 is deposited on the protective layer 26. The transmission layer 27 is made of dense indium tin oxide. A transmission pixel electrode 271, a third common electrode 272, and a fourth common electrode are formed on the transmission layer 27 using a sixth mask. An insulating layer 28 is formed on the transmission layer 27, and a transmission opening 281 is formed on the insulating layer 28. Finally, a reflective layer 29 is formed on the insulating layer 28. The reflective layer 29 includes a reflective pixel electrode 291, which extends along the sidewall of the transmission opening 281 to connect with the transmission pixel electrode 271.

[0117] like Figures 36 to 38 As shown, with Figures 20 to 35 In contrast, the display panel also includes a third transistor TFT3, a second data line 247 and a third gate signal line 246. The third transistor TFT3 is located on the periphery of each row pixel circuit 200 along the row direction. The gate of the third transistor TFT3 is connected to the third gate signal line 246, the source of the third transistor TFT3 is connected to the second data line 247, and the drain of the third transistor TFT3 is connected to the second gate signal line 214.

[0118] During high-frequency display, the third gate signal line 246 is at a high level, the third transistor TFT3 is turned on, the second data line 247 is at a low level, the second gate signal line 214 is at a low level, the second transistor TFT2 is turned off, the first gate signal line 213 is at a high level, the first transistor TFT1 is turned on, and the first capacitor C1 is charged. The storage capacitor of the pixel circuit 200 is the first capacitor C1. During low-frequency display, the third gate signal line 246 is at a high level, the third transistor TFT3 is turned on, the second data line 247 is at a high level, the second gate signal line 214 is at a high level, the second transistor TFT2 is turned on, the first gate signal line 213 is at a high level, the first transistor TFT1 is turned on, and the first capacitor C1 and the second capacitor C2 are charged. The storage capacitor of the pixel circuit 200 is the sum of the first capacitor and the second capacitor C2.

[0119] like Figure 37 and Figure 38 As shown, the first conductive layer 24 is provided with a second data line 247 and a third gate signal line 246. The gate layer 21 also includes a third gate portion 219, which is disposed between the second data line 247 and the third gate signal line 246 along the row direction. The third gate portion 219 is connected to the third gate signal line 246 through a seventh via 207. The first conductive layer 24 also includes a fifth conductive portion 2401 and a sixth conductive portion 2402. The fifth conductive portion 2401 is connected to the second data line 247, and the sixth conductive portion 2402 is connected to the third gate signal line 246 through a sixth via 206.

[0120] like Figures 39 to 50 As shown, with Figures 20 to 38 The difference is that the driving circuit layer 2 also includes a second conductive layer 25, which is disposed on the side of the first protective layer 261 away from the substrate 1. The second conductive layer 25 is provided with a first opening 251, a second opening 252 and a third opening 253. The driving circuit layer 2 also includes a second protective layer 262, which is disposed on the side of the second conductive layer 25 away from the substrate 1. The second protective layer 262 is in direct contact with the first protective layer 261 in the first opening 251, the second opening 252 and the third opening 253.

[0121] The first opening 251 includes a first sub-opening 2511 and a second sub-opening 2512. The second sub-opening 2512 is located along the column direction on the side of the first sub-opening 2511 near the second conductive portion 242, and the second sub-opening 2512 communicates with the first sub-opening 2511. The orthographic projection of the second sub-opening 2512 on the substrate 1 overlaps with the orthographic projection of the second conductive portion 242 on the substrate 1. A first through-hole 201 is provided in the second sub-opening 2512, and the first through-hole 201 passes through the second protective layer 262 and the first protective layer 261.

[0122] The driving circuit layer 2 also includes a second protective layer 262 and a transmissive layer 27. The second protective layer 262 is disposed on the side of the second conductive layer 25 away from the substrate 1, and the transmissive layer 27 is disposed on the side of the second protective layer 262 away from the substrate 1. The transmissive layer 27 includes a transmissive pixel electrode 271. A first via 201 is provided on the first protective layer 261, and the second conductive part 242 includes a first adapter part 2421. The transmissive pixel electrode 271 is connected to the first adapter part 2421 through the first via 201.

[0123] The fourth conductive part 244 includes a second transition part 2441. The orthographic projection of the first transition part 2421 on the substrate 1 overlaps with the orthographic projection of the first common electrode 215 on the substrate 1 to form a first sub-capacitor. The orthographic projection of the second transition part 2441 on the substrate 1 overlaps with the orthographic projection of the second common electrode 216 on the substrate 1 to form a second sub-capacitor.

[0124] The orthographic projection of the second conductive layer 25 on the substrate 1 overlaps with the orthographic projection of the second conductive portion 242 on the substrate 1 to form a third sub-capacitor. The orthographic projection of the second conductive layer 25 on the substrate 1 overlaps with the orthographic projection of the fourth conductive portion 244 on the substrate 1 to form a fourth sub-capacitor.

[0125] The transmissive layer 27 also includes a third common electrode 272, a fourth common electrode 273, a third common signal line 274, and a fourth common signal line 275. The third common electrode 272 and the fourth common electrode 273 are respectively disposed on both sides of the transmissive pixel electrode 271 along the column direction. The third common signal line 274 is connected to the third common electrode 272 and is disposed on the side of the third common electrode 272 away from the transmissive pixel electrode 271. The fourth common signal line 275 is connected to the fourth common electrode 273 and is disposed on the side of the fourth common electrode away from the transmissive pixel electrode 271.

[0126] Figure 48 for Figure 41 The cross-sectional diagrams of G1-G1 and H1-H1 show that the orthographic projection of the third common electrode 272 on the substrate 1 overlaps with the orthographic projection of the second conductive layer 25 on the substrate 1, forming a fifth sub-capacitor. Similarly, the orthographic projection of the fourth common electrode 273 on the substrate 1 overlaps with the orthographic projection of the second conductive layer 25 on the substrate 1, forming a sixth sub-capacitor. The first, third, and fifth sub-capacitors constitute the first capacitor, and the second, fourth, and sixth sub-capacitors constitute the second capacitor.

[0127] like Figure 49 and Figure 50 As shown, with Figure 37 and Figure 38The difference is that the driving circuit layer 2 also includes a second conductive layer 25, which extends to the peripheral area of ​​the display panel and is connected to the peripheral common signal line 248 through a third via 203.

[0128] The manufacturing process of this display panel is as follows: Figures 20 to 38 The difference in the manufacturing process of the display panel is that, after the formation of the first protective layer 261 and before the formation of the second protective layer 262, a second conductive layer 25 is formed, and a fourth mask is used to form a first opening 251 and a second opening 252 on the second conductive layer 25.

[0129] Since the first capacitor C1 and the second capacitor C2 being located in the transmission region will affect the transmission of light through the transmission pixel electrode 271, in the above embodiment, the first capacitor C1 and the second capacitor C2 are both located in the reflection region. The first capacitor C1 and the second capacitor C2 are respectively located on both sides of the transmission region along the column direction. The orthogonal projection of the first capacitor on the substrate 1 is greater than the orthogonal projection of the second capacitor on the substrate 1.

[0130] It should be noted that the row direction is the x-direction shown in the figure, and the column direction is the y-direction shown in the figure.

[0131] The present invention also provides a driving method for the display panel according to any of the above embodiments. The method includes:

[0132] In step S10, the first gate signal line 213 is loaded with a high level, and the first transistor TFT1 is turned on.

[0133] In step S20, when performing high-frequency display, the second gate signal line 214 is loaded with a low level, the second transistor TFT2 is turned off, the second capacitor is 0, and the storage capacitor of the pixel circuit 200 is the first capacitor.

[0134] In step S30, when performing low-frequency display, the second gate signal line 214 is loaded with a high level, the second transistor TFT2 is turned on, and the storage capacitance of the pixel circuit 200 is the sum of the first capacitor and the second capacitor.

[0135] In the case where the display panel also includes a third transistor, a second data line 247, and a third gate signal line 246:

[0136] When performing high-frequency display, the second gate signal line 214 is loaded with a low level, and the second transistor TFT2 is turned off, including:

[0137] When performing high-frequency display, the third gate signal line 246 is loaded with a high level, the second data line 247 is loaded with a low level, and the second transistor TFT2 connected to the second data line 247 is completely turned off.

[0138] When performing a low-frequency display, the second gate signal line 214 is loaded with a high level, and the second transistor TFT2 is turned on, including:

[0139] When performing low-frequency display, the second data line 247 is loaded with a high level, and all the second transistors TFT2 connected to the second data line 247 are turned on. The storage capacitor of the pixel circuit 200 is the sum of the first capacitor and the second capacitor.

[0140] This invention also provides a display device, which may include the display panel mentioned above in this invention. The specific structure and beneficial effects of the display panel have been described in detail above, and therefore will not be repeated here.

[0141] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts, such as the casing, circuit board, power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0142] Display devices can be traditional electronic devices, such as mobile phones, computers, televisions, and video recorders, or emerging wearable devices, such as virtual reality devices and augmented reality devices, which will not be listed here.

[0143] It should be noted that the above embodiments are interconnected and can be combined to form other solutions. The solutions of the present invention are not limited to those described in the above embodiments. Those skilled in the art will readily conceive of other embodiments of the invention upon considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate substrate; a driving circuit layer provided on one side of the substrate substrate, the driving circuit layer comprising a first data line, a first gate signal line, a second gate signal line and a plurality of pixel circuits, the pixel circuit comprising a first transistor, a second transistor, a first capacitor and a second capacitor, the gate of the first transistor being connected to the first gate signal line, the source being connected to the first data line, and the drain being connected to the first capacitor, the gate of the second transistor being connected to the second gate signal line, the source being connected to the first capacitor, and the drain being connected to the second capacitor.

2. The display panel of claim 1, wherein, The display panel has a reflection area, and the first capacitor and the second capacitor are located in the reflection area.

3. The display panel of claim 2, wherein, The display panel also has a transmission area, and the first capacitor and the second capacitor are respectively provided on both sides of the transmission area in the column direction.

4. The display panel of claim 3, wherein, The first capacitor has a larger orthographic projection on the substrate substrate than the second capacitor.

5. The display panel of claim 1, wherein, The driving circuit layer further comprises: a gate layer provided on one side of the substrate substrate, the gate layer being provided with the first gate signal line and the second gate signal line, the gate layer further comprising a first gate part and a second gate part, the first gate signal line and the second gate signal line extending in the row direction, the first gate signal line being connected to the first gate part, and the second gate signal line being connected to the second gate part; an active layer provided on the side of the gate layer away from the substrate substrate, the active layer comprising a first active part and a second active part, the orthographic projection of the first gate part on the substrate substrate and the orthographic projection of the channel region of the first active part on the substrate substrate overlap to form the gate of the first transistor, and the orthographic projection of the second gate part on the substrate substrate and the orthographic projection of the channel region of the second active part on the substrate substrate overlap to form the gate of the second transistor; a first conductive layer provided on the side of the active layer away from the substrate substrate, the first conductive layer comprising a first conductive part, a second conductive part, a third conductive part, a fourth conductive part and a first data line, the first conductive part being connected to the first data line, the orthographic projection of the first conductive part on the substrate substrate and the orthographic projection of the source region of the first active part on the substrate substrate overlap to form the source of the first transistor, the orthographic projection of the second conductive part on the substrate substrate and the orthographic projection of the drain region of the first active part on the substrate substrate overlap to form the drain of the first transistor, the orthographic projection of the third conductive part on the substrate substrate and the orthographic projection of the source region of the second active part on the substrate substrate overlap to form the source of the second transistor, and the orthographic projection of the fourth conductive part on the substrate substrate and the orthographic projection of the drain region of the second active part on the substrate substrate overlap to form the drain of the second transistor.

6. The display panel of claim 5, wherein, The first capacitor includes a first sub-capacitor, and the second capacitor includes a second sub-capacitor; the gate layer further includes a first common electrode and a second common electrode, a projection of the first common electrode on the substrate substrate overlaps with a projection of the second conductive part on the substrate substrate, forming the first sub-capacitor; a projection of the second common electrode on the substrate substrate overlaps with a projection of the fourth conductive part on the substrate substrate, forming the second sub-capacitor.

7. The display panel of claim 6, wherein, The display panel further includes a transmission layer, the transmission layer includes a transmission pixel electrode, the transmission pixel electrode is connected with the second conductive part through a via hole.

8. The display panel of claim 7, wherein, The transmission layer is a transparent conductive layer, and the display panel further includes: An insulating layer is arranged on the side of the transmission layer away from the substrate substrate, and the insulating layer is provided with a transmission opening; A reflective layer is arranged on the side of the insulating layer away from the substrate substrate, and the reflective layer includes a reflective pixel electrode, the reflective pixel electrode extends along the side wall of the transmission opening to be connected with the transmission pixel electrode.

9. The display panel of claim 7, wherein, The first capacitor includes a third sub-capacitor, and the second capacitor includes a fourth sub-capacitor; the transmission layer further includes a third common electrode and a fourth common electrode, the third common electrode and the fourth common electrode are respectively arranged on both sides of the transmission pixel electrode along the column direction, the third common electrode on the substrate substrate overlaps with the projection of the second conductive part on the substrate substrate, forming the third sub-capacitor, and the fourth common electrode on the substrate substrate overlaps with the projection of the fourth conductive part on the substrate substrate, forming the fourth sub-capacitor.

10. The display panel of claim 7, wherein, The first capacitor includes a third sub-capacitor, and the second capacitor includes a fourth sub-capacitor, and the display panel further includes a second conductive layer, the second conductive layer is arranged between the transmission layer and the first conductive layer, the projection of the second conductive layer on the substrate substrate overlaps with the projection of the second conductive part on the substrate substrate to form the third sub-capacitor, and the projection of the second conductive layer on the substrate substrate overlaps with the projection of the fourth conductive part on the substrate substrate to form the fourth sub-capacitor.

11. The display panel of claim 10, wherein, The first capacitor further includes a fifth sub-capacitor, and the second capacitor further includes a sixth sub-capacitor, the transmission layer further includes a third common electrode and a fourth common electrode, the projection of the second conductive layer on the substrate substrate overlaps with the projection of the third common electrode on the substrate substrate to form the fifth sub-capacitor, and the projection of the second conductive layer on the substrate substrate overlaps with the projection of the fourth common electrode on the substrate substrate to form the sixth sub-capacitor.

12. The display panel of claim 5, wherein, The display panel further includes a third transistor, a second data line and a third gate signal line, the third transistor is located in the periphery of each row of pixel circuits along the row direction, the gate of the third transistor is connected with the third gate signal line, the source of the third transistor is connected with the second data line, and the drain of the third transistor is connected with the second gate signal line.

13. The display panel of claim 12, wherein, The first conductive layer is provided with the second data line and the third gate signal line, the gate layer further comprises a third gate portion, the third gate portion is arranged between the second data line and the second data line along the row direction, the third gate portion is connected with the third gate signal line through a via hole, the first conductive layer further comprises a fifth conductive portion and a sixth conductive portion, the fifth conductive portion is connected with the second data line, and the sixth conductive portion is connected with the second gate signal line through a via hole.

14. The display panel of claim 8, wherein, The first gate signal line is arranged between the second data line and the second gate signal line along the row direction.

15. The display panel of claim 1, wherein, The width of the gate of the second transistor is less than the width of the gate of the first transistor.

16. A driving method of the display panel according to any one of claims 1 to 15, characterized by, The method comprises: The first gate signal line is loaded with a high level, and the first transistor is turned on. When high-frequency display is performed, the second gate signal line is loaded with a low level, the second transistor is turned off, the second capacitance is 0, and the storage capacitance of the pixel circuit is a first capacitance. When low-frequency display is performed, the second gate signal line is loaded with a high level, the second transistor is turned on, and the storage capacitance of the pixel circuit is a sum of the first capacitance and the second capacitance.

17. The driving method of the display panel according to claim 16, wherein The display panel is the display panel of claim 12, when high-frequency display is performed, the second gate signal line is loaded with a low level, and the second transistor is turned off, comprising: when high-frequency display is performed, the third gate signal line is loaded with a high level, the second data line is loaded with a low level, and all the second transistors connected with the second data line are turned off. When low-frequency display is performed, the second gate signal line is loaded with a high level, and the second transistor is turned on, comprising: when low-frequency display is performed, the second data line is loaded with a high level, all the second transistors connected with the second data line are turned on, and the storage capacitance of the pixel circuit is a sum of the first capacitance and the second capacitance.

18. A display device comprising: The display panel comprises the display panel of any one of claims 1 to 15. The display panel comprises the display panel of any one of claims 1 to 15.

Images