A SiC MOSFET resistant to single-particle gate breakdown and its fabrication method

Abstract

The application provides a SiC MOSFET and a preparation method of the SiC MOSFET, which comprises, from bottom to top, a drain metallization layer, an N+ substrate layer, an N-drift region, a current spreading region, a P-well region, a second N+ source region, a second P-base region, a first P-base region, a first N+ source region, a gate oxide, a polysilicon gate, an isolation oxide, and a source metallization layer; the first N+ source region, the second N+ source region, and the P-well region are in contact with the source metallization layer; the second N+ source region surrounds the bottom, two corners, and one sidewall of a trench gate oxide; the second N+ source region is shielded by the P-well region and the second P-base region, and is isolated from the current spreading region and the N-drift region. The application effectively suppresses a strong electric field of the gate oxide caused by high-energy charged particle radiation, and greatly improves the anti-single-particle gate punch-through capability of the trench type SiC MOSFET.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically relating to a SiC MOSFET resistant to single-event gate breakdown and its fabrication method. Background Technology

[0002] Trench-type SiC MOSFETs have advantages such as high breakdown voltage, fast switching speed, and low on-resistance, and their performance is superior to that of planar SiC MOSFETs, meeting the urgent need for high-voltage power devices in new aerospace power systems.

[0003] Space is filled with a large number of high-energy charged particles, which can cause permanent damage to power semiconductor devices when they enter. According to numerous ground-based accelerator simulations, trench-type SiC MOSFETs are generally not resistant to high-energy charged particle radiation, experiencing single-event gate breakdown (SEGR) at around 10% of their rated voltage, resulting in permanent device damage. Directly applying unhardened, conventional trench-type SiC MOSFETs to aerospace power systems would severely threaten the spacecraft's on-orbit lifespan.

[0004] Trench SiC MOSFETs are highly sensitive and vulnerable to single-event gate breakdown. This is because when high-energy charged particles enter the device, they collide and ionize, generating a large number of electron-hole pairs. Under the influence of a strong electric field, the holes rapidly accumulate at the gate oxide interface, creating a transient strong electric field. Once this transient strong electric field exceeds the critical breakdown electric field value, the gate oxide will break down, and a leakage current path will be formed.

[0005] Due to the geometric asymmetry of the trench corners, trench-type SiC MOSFETs exhibit a higher maximum electric field at the gate oxide corners than at the trench bottom when high-energy charged particles are incident. Suppressing or mitigating the instantaneous strong electric field at the gate oxide corners and bottom caused by hole accumulation is a key aspect of single-particle gate-breakdown hardening design for trench-type SiC MOSFETs.

[0006] like Figure 1 The diagram shown is a schematic of a conventional trench SiC MOSFET structure, which can be used as a comparative device of the present invention. It includes: a source metallization layer 101, isolation oxide 102, gate oxide 103, polysilicon gate 104, N+ source region 105, P-base region 106, P-well region 107, N-drift region 108, N+ substrate region 109, and drain metallization layer 110. Summary of the Invention

[0007] The technical problem solved by this application is to overcome the shortcomings of the prior art and provide a SiC MOSFET and its fabrication method that resist single-event gate breakdown, so as to solve the problem of single-event gate breakdown caused by high-energy charged particle radiation in space applications.

[0008] The technical solution provided in this application is as follows:

[0009] In a first aspect, a SiC MOSFET resistant to single-particle gate breakdown and its fabrication method are provided, including:

[0010] N+ substrate layer;

[0011] A drain metallization layer is located on the lower surface of the N+ substrate layer;

[0012] The N-drift region is located on the upper surface of the N+ substrate layer;

[0013] The current extension region is located on the upper surface of the portion of the N-drift region;

[0014] The first P-base region is located on the upper surface of the current extension region;

[0015] The first N+ source region is located on the upper surface of the first P-base region;

[0016] One side of the gate trench is in contact with the first N+ source region, the first P-base region, and the current spread region, and the gate oxide is located on the bottom and sidewall of the gate trench.

[0017] The polysilicon gate is located on the upper surface of the gate oxide, and its top is flush with the top of the N+ source region.

[0018] Oxygen is isolated and located on the upper surface of the polysilicon gate and part of the first N+ source region;

[0019] The P-well region is located on the upper surface of the partial N-drift region and is in contact with the current extension region;

[0020] The second N+ source region is located on the upper surface of the partial P-well region, surrounding the bottom, two corners, and one sidewall of the trench gate oxide;

[0021] The second P-base region is located on the upper surface of part of the second N+ source region and part of the P-well region, and is in contact with the gate oxide sidewall and the current spread region.

[0022] The source metallization layer is located on the upper surface of the oxygen isolation region, the first N+ source region, a portion of the second N+ source region, and a portion of the P-well region.

[0023] The second N+ source region is shielded by the P-well region and the second P-base region, and is isolated from the current spread region and the N-drift region.

[0024] Preferably, the first N+ source region is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm-3 The thickness is 0.1μm to 0.5μm and the width is 1μm to 5μm.

[0025] Preferably, the material of the second N+ source region is N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness ranges from 1.0 μm to 4.0 μm, and the width ranges from 0.8 μm to 3.0 μm.

[0026] Preferably, the material of the first P-base region is P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 The thickness is 0.1μm to 0.6μm and the width is 1.0μm to 5.0μm.

[0027] Preferably, the material of the second P-base region is P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 The thickness is 0.1μm to 0.6μm and the width is 0.4μm to 1.5μm.

[0028] Preferably, the material of the P-well region is P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~5×10 19 cm -3 The thickness is 1.5μm to 5.0μm and the width is 1.0μm to 6.0μm.

[0029] Preferably, the current-spreading region is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness ranges from 1.0 μm to 4.0 μm, and the width ranges from 0.8 μm to 3.0 μm.

[0030] Preferably, the gate oxide material is SiO2, HfO2 or Al2O3, and the thickness is 40nm to 150nm.

[0031] Preferably, the oxygen-isolating material is SiO2, HfO2 or Al2O3, with a thickness of 0.1μm to 2.0μm.

[0032] Preferably, the polysilicon gate is made of N-type polysilicon, and the doping element is phosphorus with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm-3 The thickness is 1.0μm to 3.0μm and the width is 0.5μm to 1.5μm.

[0033] Preferably, the N-drift region is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 13 ~5×10 16 cm -3 The thickness is 5μm to 50μm.

[0034] Preferably, the N+ substrate is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 5 × 10⁻⁶. 18 ~1×10 20 cm -3 The thickness ranges from 50μm to 400μm.

[0035] Secondly, a SiC MOSFET resistant to single-particle gate breakdown and its fabrication method are provided, the fabrication method including but not limited to the following steps:

[0036] ① An N- drift region is epitaxially grown on a heavily doped SiC N+ substrate;

[0037] ②A high-concentration N-type epitaxial layer is grown on the N-drift region;

[0038] ③ Fabricate a mask to block part of the upper surface of the N-type epitaxial layer, and form a partial P-well region by ion implantation;

[0039] ④ Based on the previous step, grow another N-type epitaxial layer of the same concentration;

[0040] ⑤ By fabricating different photomasks and using multiple photolithography steps and controlling ion implantation energy, a portion of the P-well region and a second N+ source region are formed on the newly grown epitaxial layer;

[0041] ⑥ Based on the previous step, another N-type epitaxial layer of the same concentration is grown epitaxially. Multiple sets of different masks are made. Then, by using multiple photolithography and controlling the ion implantation energy, a partial P-well region, a second N+ source region and a second P-base region are formed on the newly grown epitaxial layer.

[0042] ⑦ Based on the previous step, grow another N-type epitaxial layer of the same concentration. Use ion implantation to form the remaining P-well region, the second N+ source region, and the first N+ source region and the first P-base region in the middle part of the epitaxial layer on the newly grown epitaxial layer.

[0043] ⑧ A trench is etched on the surface of the epitaxial layer grown in the previous step ⑦ by dry etching. One side of the gate trench is in contact with the first N+ source region, the first P-base region, the current extension region, the second P-base region, and the second N+ source region. The other side of the trench is only in contact with the second N+ source region. The bottom of the trench is in contact with the second N+ source region.

[0044] ⑨ A uniform and dense gate oxide layer is grown at the bottom and sidewalls of the trench, a conductive dielectric polysilicon gate is deposited and photolithography and etching are performed to form the gate electrode, and a thick oxide layer is deposited on the upper surface of the trench to form oxygen isolation.

[0045] ⑩ Perform back-side thinning and metal sputtering to form a drain metallization layer on the surface of the SiC N+ substrate; perform front-side metal deposition to form a source metallization layer on the upper surface of the device structure.

[0046] In summary, this application includes at least the following beneficial technical effects:

[0047] When a trench-type SiC MOSFET is in the blocking state, a large number of holes generated by the collisional ionization of high-energy charged particles move towards the gate and source under the influence of a strong electric field. A highly doped N-type second N+ source region is connected to the source. A large number of electrons in this region can recombine with holes moving towards the gate oxide. Simultaneously, the second N+ source region absorbs holes, causing them to move rapidly towards the source, reducing the hole density accumulated at the gate oxide interface. Furthermore, a highly doped P-well region is also connected to the source, surrounding and shielding the second N+ source region. The P-well region can rapidly absorb holes, causing them to move towards the source, further reducing the number of holes moving towards the second N+ source region. Under the combined effect of the second N+ source region and the P-well region, the number of holes accumulated at the gate oxide interface is significantly reduced, and the instantaneous electric field strength is effectively lowered.

[0048] When the trench SiC MOSFET is in the forward conduction state, the first N+ source region injects electrons into the current extension region through the first P-base region; in addition, the second N+ source region injects electrons into the current extension region through the second P-base region. The combination of the second N+ source region and the second P-base region increases the effective channel area without increasing the chip area, doubling the conduction current and further reducing the on-resistance of the trench SiC MOSFET. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of a traditional trench-type SiC MOSFET structure;

[0050] Figure 2 This is a schematic diagram of the trench SiC MOSFET structure reinforced against single-particle gate penetration according to the present invention;

[0051] Figure 3 This is a schematic flowchart of the fabrication method of the trench SiC MOSFET structure reinforced against single-particle gate penetration according to the present invention;

[0052] Figure 4 This is a schematic diagram of the movement trajectory of electron and hole pairs during high-energy charged particle radiation, which is a traditional trench-type SiC MOSFET structure.

[0053] Figure 5 This is a schematic diagram of the movement trajectory of electron and hole pairs in the trench SiC MOSFET structure reinforced against single-particle gate penetration according to the present invention, under high-energy charged particle radiation.

[0054] Figure 6 This is a comparison diagram of the breakdown characteristics of the trench SiC MOSFET structure reinforced against single-particle gate breakdown of the present invention and the traditional trench SiC MOSFET structure;

[0055] Figure 7 This is a TCAD simulation diagram showing the change in electric field intensity at the gate oxide position when a high-energy charged particle with a linear energy conversion value of 0.52 pC / μm is incident on the most sensitive location in the trench SiC MOSFET structure with single-particle gate penetration reinforcement of the present invention and the traditional trench SiC MOSFET structure. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments disclosed in the present invention will be described in further detail below with reference to the accompanying drawings.

[0057] This application discloses a schematic diagram of a SiC MOSFET resistant to single-particle gate breakdown and its fabrication method, as shown in the embodiment. Figure 2 As shown, it includes multiple parallel cells, each cell including: a source metallization layer 201, an isolation oxide layer 202, a gate oxide layer 203, a polysilicon gate layer 204, a first N+ source region 205, a first P-base region 206, a second N+ source region 207, a P-well region 208, a second P-base region 209, a current extension region 210, an N-drift region 211, an N+ substrate layer 212, and a drain metallization layer 213.

[0058] Drain metallization layer 213 is located on the lower surface of N+ substrate layer 212; N- drift region 211 is located on the upper surface of N+ substrate layer 212; current extension region 210 is located on the upper surface of N- drift region 211 at the middle position; first P-base region 206 is located on the upper surface of current extension region 210; first N+ source region 205 is located on the upper surface of first P-base region 206, and the width of first N+ source region 205 is the same as the width of first P-base region 206.

[0059] P-well region 208 is located on the upper surface of a portion of the N-drift region 211, in contact with the current extension region 210. P-well region 208 comprises two parts, each located on one side of the current extension region 210. Each part of P-well region 208 has a first protrusion on the side closer to the current extension region 210 and a second protrusion on the side farther from the current extension region 210. The height of the second protrusion is greater than that of the first protrusion, forming a groove between the first and second protrusions. A second N+ source region 207 is located within the groove on the surface of the portion of the P-well region 208. A gate trench is formed within the second N+ source region 207, located in the middle of the second N+ source region 207, causing a third protrusion and a fourth protrusion to form on both sides of the gate trench. The gate trench has a third protrusion located on the side of the gate trench near the current extension region 210, and a fourth protrusion located on the side of the gate trench away from the current extension region 210. The end of the third protrusion away from the N-drift region 211 is flush with the first protrusion, and the end of the fourth protrusion away from the N-drift region 211 is flush with the second protrusion. This makes one side of the gate trench contact the second P-base region 209, the current extension region 210, the first N+ source region 205, and the first P-base region 206, while the other side and bottom of the gate trench contact the second N+ source region 207. The gate oxide 203 is located on the bottom and sidewalls of the gate trench. The polysilicon gate 204 is located on the upper surface of the gate oxide 203, and its top is flush with the top of the N+ source region 205. The second N+ source region 207 surrounds the bottom, two corners, and one sidewall of the trench gate oxide 203.

[0060] The second P-base region 209 is located on the upper surface of the second N+ source region 207 and the P-well region 208 on the side of the trench gate oxide 203 near the current extension region 210. That is, the second P-base region 209 is located on the side of the first protrusion and the third protrusion away from the N-drift region 211, and the width of the second P-base region 209 is equal to the sum of the widths of the first protrusion and the third protrusion. The side of the second P-base region 209 away from the N-drift region 211 is successively the current extension region 210, the first P-base region 206, and the first N+ source region 205, and the ends of the second P-base region 209, the current extension region 210, the first P-base region 206, and the first N+ source region 205 are flush. The second P-base region 209 is in contact with the sidewall of the gate oxide 203 and the current extension region 210.

[0061] Isolation oxide 202 is located on top of the polysilicon gate 204 and the gate oxide 203 outside the polysilicon gate 204. The width direction along the direction from the polysilicon gate 204 to the current extension region 210 is greater than the total width of the gate oxide 203, so that the two ends of the isolation oxide 202 exceed the gate oxide 203 and cover part of the upper surface of the first N+ source region 205; the source metallization layer 201 is located on the upper surface of the isolation oxide 202, the first N+ source region 205, the second N+ source region 207, and the P-well region 208.

[0062] The first N+ source region 205, the second N+ source region 207, and the P-well region 208 are in contact with the source metallization layer 201; the second N+ source region 207 surrounds the bottom, two corners, and one sidewall of the trench gate oxide 203; the second N+ source region 207 is shielded by the P-well region 208 and the second P-base region 209, and is isolated from the current spread region 210 and the N-drift region 211.

[0063] The first N+ source region 205 is made of N-type SiC, and the doping element is either nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 0.1μm to 0.5μm and the width is 1μm to 5μm.

[0064] The second N+ source region 207 is made of N-type SiC, and the doping element is either nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness ranges from 1.0 μm to 4.0 μm, and the width ranges from 0.8 μm to 3.0 μm.

[0065] The first P-base region 206 is made of P-type SiC, with aluminum or boron as the doping element and a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 The thickness is 0.1μm to 0.6μm and the width is 1μm to 5μm.

[0066] The second P-base region 209 is made of P-type SiC, with aluminum or boron as the doping element and a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 The thickness is 0.1μm to 0.6μm and the width is 0.4μm to 1.5μm.

[0067] The P-well region 208 is made of P-type SiC, with aluminum or boron as the doping element and a doping concentration of 1×10⁻⁶. 18 ~5×1019 cm -3 The thickness is 1.5μm to 5μm and the width is 1μm to 6μm.

[0068] The current extension region 210 is made of N-type SiC, and the doping element is either nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness ranges from 1.0 μm to 4.0 μm, and the width ranges from 0.8 μm to 3.0 μm.

[0069] The gate oxide 203 is made of SiO2, HfO2 or Al2O3 and has a thickness of 40nm to 150nm.

[0070] The material of the oxygen isolation 202 is SiO2, HfO2 or Al2O3, and the thickness is 0.1μm to 2μm.

[0071] The polysilicon gate 204 is made of N-type polysilicon, doped with phosphorus at a concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 1μm to 3μm and the width is 0.5μm to 1.5μm.

[0072] The N-drift region 211 is made of N-type SiC, and the doping element is either nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 13 ~5×10 16 cm -3 The thickness is 5μm to 50μm.

[0073] The N+ substrate 212 is made of N-type SiC, and the doping element is either nitrogen or phosphorus, with a doping concentration of 5 × 10⁻⁶. 18 ~1×10 20 cm -3 The thickness ranges from 50μm to 400μm.

[0074] Figure 3 This is a schematic diagram of the fabrication process of a SiC MOSFET resistant to single-particle gate breakdown and its fabrication method, as described in this invention. The specific fabrication process includes:

[0075] Step 1: Epitaxially grow an N- drift region 211 on a heavily doped SiC N+ substrate 212 with a doping concentration of 1×10⁻⁶. 13 ~5×10 16 cm -3 The thickness is 5μm to 50μm;

[0076] Step 2: A high-concentration N-type epitaxial layer is grown on the N-drift region 211, with a doping concentration of 1×10⁻⁶.16 ~5×10 17 cm -3 The thickness is 0.5μm to 1.0μm;

[0077] Step 3: Fabricate a mask to partially block the upper surface of the N-type epitaxial layer, and perform aluminum or boron ion implantation to form a partial P-well region 208 with a doping concentration of 1×10⁻⁶. 18 ~5×10 19 cm -3 ;

[0078] Step 4: Based on Step 3, grow another N-type epitaxial layer with the same doping concentration as the epitaxial layer grown in Step 3, which is 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness is 0.5μm to 1.5μm;

[0079] Step 5: Fabricate different photomasks and use multiple photolithography and controlled ion implantation energy to form a partial P-well region 208 and a second N+ source region 207 on the newly grown epitaxial layer;

[0080] Step 6: Based on step 5, grow another N-type epitaxial layer with the same doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness is 0.1μm to 0.6μm. Multiple sets of different masks are fabricated, and then P-well regions 208, second N+ source regions 207 and second P-base regions 209 are sequentially formed on the newly grown epitaxial layer by multiple photolithography and controlled ion implantation energy. The width of the second P-base region 209 is 0.4μm to 1.5μm. The boundary of the second P-base region 209 near the current extension region 210 is aligned with the P-well region 208 below it.

[0081] Step 7: Based on step 6, grow another N-type epitaxial layer with the same doping concentration, still 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness is 0.5μm to 3.0μm. Then, by using multiple photolithography and controlling the ion implantation energy, the remaining P-well region 208 and the second N+ source region 207 are formed on the newly grown epitaxial layer. The first N+ source region 205 and the first P-base region 206 are located in the middle part of the epitaxial layer surface, with the first N+ source region above the first P-base region.

[0082] Step 8: Etch trenches on the upper surface of the epitaxial layer grown in step 7 using dry etching. One side of the gate trench is in contact with the first N+ source region 205, the first P-base region 206, the current extension region 210, the second P-base region 209, and the second N+ source region 207. The other side of the trench is only in contact with the second N+ source region 207. The bottom of the trench is in contact with the second N+ source region 207.

[0083] Step 9: Grow a uniform and dense gate oxide layer (i.e., gate oxide 203) at the bottom and sidewalls of the trench, deposit a conductive dielectric polysilicon gate 204 and perform photolithography and etching to form a gate electrode, and deposit a thick oxide layer on the upper surface of the trench to form isolation oxide 202.

[0084] Step 10: Perform back-side thinning and metal sputtering to form a drain metallization layer 213 on the surface of the SiC N+ substrate 212; perform front-side metal deposition to form a source metallization layer 201 on the upper surface of the device structure.

[0085] The working principle of the trench SiC MOSFET with single-particle gate-penetration hardening according to the present invention is as follows:

[0086] When the trench-type SiC MOSFET of the present invention is in the on state, a certain positive voltage needs to be applied to the polysilicon gate 204 (i.e., the gate). At this time, the device channel is turned on, forming two conduction paths: one is sequentially composed of drain metallization layer 213, N+ substrate layer 212, N- drift region 211, current extension region 210, first P-base region 206, first N+ source region 205, and source metallization layer 201; the other is sequentially composed of drain metallization layer 213, N+ substrate layer 212, N- drift region 211, current extension region 210, second P-base region 209, second N+ source region 207, and source metallization layer 201. The combination of the second N+ source region 207 and the second P-base region 209 increases the effective channel area without increasing the chip area, and doubles the conduction current, thereby further reducing the on-resistance of the trench-type SiC MOSFET of the present invention.

[0087] When the trench-type SiC MOSFET of this invention is in the blocking state, a zero voltage or a negative voltage needs to be applied to the gate. At this time, the channel is closed and there is no conduction path. When high-energy charged particles enter the device at this time, a large number of holes generated by the collision ionization of high-energy charged particles move towards the gate and source (i.e., the source metallization layer 201) under the action of a strong electric field. The highly doped N-type second N+ source region 207 is connected to the source. A large number of electrons in it can recombine with the holes moving towards the gate oxide 203. At the same time, the second N+ source region 207 absorbs holes. Due to the high doping concentration of the second N+ source region 207, the holes move rapidly towards the source, reducing the hole density accumulated at the gate oxide 203 interface. In addition, the highly doped P-well region 208 is also connected to the source, surrounding and shielding the second N+ source region 207. The P-well region 208 can quickly absorb holes, and the holes move towards the source, reducing the number of holes moving towards the second N+ source region 207. Under the combined effect of the second N+ source region 207 and the P-well region 208, the number of holes accumulated at the gate oxide 203 interface is greatly reduced, and the instantaneous electric field intensity is effectively reduced. Figure 4 and Figure 5 These are schematic diagrams showing the movement trajectories of electron and hole pairs under high-energy charged particle radiation, respectively, for a traditional trench SiC MOSFET and the single-particle gate-penetration-resistant hardened structure proposed in this invention.

[0088] To further illustrate the performance of the trench SiC MOSFET with single-particle gate-through hardening of the present invention, this embodiment uses the simulation tool TCAD to perform device simulation and performance comparison between the present invention and the traditional trench SiC MOSFET.

[0089] Figure 6 This indicates that through simulation... Figure 1 and Figure 2 By comparing the breakdown characteristics of the medium structure, it can be seen that the breakdown voltage of the trench SiC MOSFET reinforced with single-particle gate breakdown resistance of the present invention and the traditional trench SiC MOSFET are both around 650V, which is equivalent to a device with a rated voltage of 600V.

[0090] Figure 7 The linear energy conversion value (LET) is 0.52 pC / μm, equivalent to 78.7 MeV / (mg / cm²). 2 The simulation graph shows the change of the gate oxide electric field intensity over time when Ta ions are incident at the most sensitive location of a trench SiC MOSFET. For a conventional trench SiC MOSFET, with a drain bias voltage V... DS At a voltage of 100V, the maximum electric field of the gate oxide reaches 10MeV / cm, far exceeding the critical breakdown electric field value of the gate oxide (6MeV / cm). However, the trench-type SiC MOSFET with single-particle gate breakdown hardening of this invention, at a drain bias voltage of V...DS At 600V, the maximum electric field strength remains below 3MeV / cm, not exceeding the critical breakdown electric field of the gate oxide. It can be seen that this invention effectively improves the threshold voltage for single-particle gate breakdown.

[0091] The contents not described in detail in this application specification are common knowledge to those skilled in the art.

[0092] The present application has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present application. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present application without departing from the spirit and scope of the present application, and all such modifications and improvements fall within the scope of the present application. The scope of protection of the present application is determined by the appended claims.

Claims

1. A SiC MOSFET resistant to single-particle gate breakdown, characterized in that, It includes multiple parallel cells, each cell comprising: A drain metallization layer (213), an N+ substrate layer (212), and an N- drift region (211) are sequentially arranged; The current extension region (210) is located in the middle of the N- drift region (211) away from the surface of the N+ substrate layer (212); The first P-base region (206) is located on the surface of the current extension region (210) away from the N-drift region (211); The first N+ source region (205) is located on the surface of the first P-base region (206) away from the current extension region (210); The P-well region (208) is located on the surface of the N-drift region (211) away from the N+ substrate layer (212). The P-well region (208) includes two parts. The two parts of the P-well region (208) are located on both sides of the current extension region (210) and are in contact with the current extension region (210). Each part of the P-well region (208) has a first protrusion on the side close to the current extension region (210) and a second protrusion on the side away from the current extension region (210). The height of the second protrusion is greater than that of the first protrusion, so as to form a groove between the first protrusion and the second protrusion. The second N+ source region (207) is located in a groove on the surface of the P-well region (208); a gate trench is formed in the second N+ source region (207) so that a third protrusion and a fourth protrusion are formed on both sides of the gate trench. The third protrusion is located on the side of the gate trench closer to the current extension region (210), and the fourth protrusion is located on the side of the gate trench away from the current extension region (210). Gate oxide (203) is located at the bottom and sidewall of the gate trench. One sidewall of the gate trench is in contact with the current extension region (210), the first N+ source region (205), and the first P-base region (206). The other sidewall and bottom of the gate trench are in contact with the second N+ source region (207). The polysilicon gate (204) is located on the surface of the gate oxide (203) away from the second N+ source region (207), and the surface of the polysilicon gate (204) away from the N- drift region (211) is flush with the first N+ source region (205); Oxygen isolation (202) is located on the surface of the polysilicon gate (204) and gate oxide (203) away from the N-drift region (211); The source metallization layer (201) is located on the surface of the isolated oxygen (202), the first N+ source region (205), a portion of the second N+ source region (207), and a portion of the P-well region (208).

2. A SiC MOSFET resistant to single-particle gate breakdown according to claim 1, characterized in that, Each cell also includes: a second P-base region (209) located on the surface of the first and third protrusions away from the N-drift region (211), the second P-base region (209) being in contact with the sidewall of the gate oxide (203) and the current spread region (210); the side of the second P-base region (209) away from the first protrusion is successively the current spread region (210), the first P-base region (206), and the first N+ source region (205); The second N+ source region (207) is shielded by the P-well region (208) and the second P-base region (209) and isolated from the current extension region (210) and the N-drift region (211).

3. A SiC MOSFET with single-particle gate breakdown protection according to claim 1, characterized in that: The first N+ source region (205) is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 0.1μm to 0.5μm, and the width is 1μm to 5μm; The second N+ source region (207) is made of N-type SiC, and the doping element is either nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness ranges from 1.0 μm to 4.0 μm, and the width ranges from 0.8 μm to 3.0 μm.

4. A SiC MOSFET with single-particle gate breakdown protection according to claim 1, characterized in that: The first P-base region (206) is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 The thickness is 0.1μm to 0.6μm, and the width is 1μm to 5μm; The second P-base region (209) is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 The thickness is 0.1μm to 0.6μm and the width is 0.4μm to 1.5μm.

5. A SiC MOSFET with single-particle gate breakdown protection according to claim 1, characterized in that: The P-well region (208) is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~5×10 19 cm -3 The thickness is 1.5μm to 5.0μm and the width is 1.0μm to 6.0μm.

6. A SiC MOSFET resistant to single-particle gate breakdown according to claim 1, characterized in that: The current extension region (210) is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness ranges from 1.0 μm to 4.0 μm, and the width ranges from 0.8 μm to 3.0 μm.

7. A SiC MOSFET with single-particle gate breakdown protection according to claim 1, characterized in that: The polysilicon gate (204) is made of N-type polysilicon, doped with phosphorus at a concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 1.0μm to 3.0μm and the width is 0.5μm to 1.5μm.

8. A SiC MOSFET resistant to single-particle gate breakdown according to claim 1, characterized in that: The gate oxide (203) is made of SiO2, HfO2 or Al2O3 and has a thickness of 40nm to 150nm; the oxygen isolation material is made of SiO2, HfO2 or Al2O3 and has a thickness of 0.1μm to 2.0μm.

9. A SiC MOSFET with single-particle gate breakdown protection according to claim 1, characterized in that: The N-drift region (211) is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 13 ~5×10 16 cm -3 The thickness is 5μm to 50μm; The N+ substrate (212) is made of N-type SiC, and the doping element is either nitrogen or phosphorus, with a doping concentration of 5 × 10⁻⁶. 18 ~1×10 20 cm -3 The thickness ranges from 50μm to 400μm.

10. A method for fabricating a SiC MOSFET resistant to single-particle gate breakdown according to any one of claims 1-9, characterized in that, include: S1: An N- drift region (211) is epitaxially grown on a heavily doped SiC N+ substrate (212); S2: A high-concentration N-type epitaxial layer is grown on the surface of the N-drift region (211) away from the N+ substrate layer (212), with a doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness is 0.5μm to 1.0μm; S3: Fabricate a mask to block the middle part of the surface of the N-type epitaxial layer, and perform aluminum or boron ion implantation to form a partial P-well region (208). The mask blockage position forms a current extension region (210). S4: Based on step S3, grow another N-type epitaxial layer. The thickness and doping concentration of the N-type epitaxial layer are the same as those of the epitaxial layer grown previously. S5: Fabricate different photomasks, and then use multiple photolithography and controlled ion implantation energy to form part of the P-well region (208) and part of the second N+ source region (207) on the newly grown epitaxial layer; S6: Based on step S5, grow another N-type epitaxial layer with a doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness is 0.1μm to 0.6μm. Then, by using multiple photolithography and controlling the ion implantation energy, a partial P-well region (208), a second N+ source region (207), and a second P-base region (209) are sequentially formed on the newly grown N-type epitaxial layer in this step. S7: Based on step S6, grow another N-type epitaxial layer with the same doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness is 0.5μm to 3.0μm. Then, by using multiple photolithography and controlling the ion implantation energy, the remaining P-well region (208) and the second N+ source region (207) are formed sequentially on the newly grown epitaxial layer, and the first N+ source region (205) and the first P-base region (206) are formed in the middle part of the epitaxial layer surface. S8: A gate trench is etched on the surface of the second N+ source region (207) by dry etching. One side of the gate trench is in contact with the first N+ source region (205), the first P-base region (206), the current extension region (210), the second P-base region (209), and the second N+ source region (207). The other side and bottom of the gate trench are only in contact with the second N+ source region (207). S9: A uniform and dense gate oxide layer (203) is grown at the bottom and sidewalls of the gate trench, a conductive dielectric polysilicon gate (204) is deposited and photolithography and etching are performed to form the gate electrode, and a thick oxide layer is deposited on the upper surface of the trench to form isolation oxide (202). S10: Perform back-side thinning and metal sputtering to form a drain metallization layer (213) on the surface of the SiC N+ substrate (212); perform front-side metal deposition to form a source metallization layer (201) on the upper surface of the device structure.

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