Cascade H-bridge unit capacitor voltage enhancement balancing method, device and computer equipment

Abstract

The present application relates to a method, device and computer equipment for enhancing the balance of capacitor voltage of cascaded H-bridge units. The method includes: determining the average value of the capacitor voltage of each H-bridge unit in the bridge arm; performing an enhanced balancing step on each H-bridge unit in the bridge arm, and the enhanced balancing step includes: determining the state priority information of the current H-bridge unit according to the capacitor voltage, average value and bridge arm current of the current H-bridge unit, and determining the control state of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit; wherein the state priority information includes: the states with the highest priority from the highest to the lowest are: capacitor positive series state, capacitor bypass state, capacitor negative series state, or capacitor negative series state, capacitor bypass state, capacitor positive series state.

Description

Technical Field

[0001] The present application relates to the technical field of energy storage power supply, and in particular to a method, device and computer equipment for enhancing the voltage balance of cascaded H-bridge unit capacitors. Background Art

[0002] The Cascaded H-Bridge (CHB) converter is a multi-level topology that relies on connecting multiple H-bridge units in series to increase the voltage level. Each H-bridge unit contains a capacitor, and the combination of capacitor voltages in different H-bridge units forms the output voltage of the bridge arm. The balance of capacitor voltages is crucial for the stable and efficient operation of this type of converter. The cascaded H-bridge capacitor voltage balance algorithm is designed to make the actual output of the bridge arm voltage track the bridge arm voltage reference signal and minimize the voltage deviation of all H-bridge capacitors in a bridge arm.

[0003] Under the control of the existing voltage balancing algorithm, multiple H-bridge unit capacitors are in bypass state and cannot participate in energy exchange. In addition, the H-bridge capacitors themselves are sensitive to aging and temperature, which will affect their capacity and voltage holding ability, making balancing control more difficult. Especially in the case of rapid load changes or grid failures, it may not be possible to quickly compensate for capacitor voltage deviations, which will have an adverse effect on the stability and efficiency of the system. Summary of the invention

[0004] Based on this, it is necessary to provide a cascaded H-bridge unit capacitor voltage enhanced balancing method, device, computer equipment, computer readable storage medium and computer program product that can quickly compensate for capacitor voltage deviation in order to address the above technical problems.

[0005] In a first aspect, the present application provides a cascaded H-bridge unit capacitor voltage enhancement balancing method, comprising:

[0006] Determine the average value of the capacitor voltage of each H-bridge unit in the bridge arm;

[0007] Performing an enhanced balancing step on each H-bridge unit in the bridge arm, the enhanced balancing step comprising:

[0008] Determine the state priority information of the current H-bridge unit according to the capacitor voltage, the average value and the bridge arm current of the current H-bridge unit, and determine the control state of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit;

[0009] Among them, the state priority information includes: the states with priorities from large to small are: capacitor forward series state, capacitor bypass state, capacitor negative series state, or the capacitor negative series state, the capacitor bypass state, and the capacitor forward series state.

[0010] In one embodiment, determining the state priority information of the current H-bridge unit according to the capacitor voltage of the current H-bridge unit, the average value and the bridge arm current includes:

[0011] Determining a voltage deviation of the current H-bridge unit according to the capacitor voltage of the current H-bridge unit and the average value;

[0012] The state priority information of the current H-bridge unit is determined according to the voltage deviation and the bridge arm current.

[0013] In one embodiment, determining the state priority information of the current H-bridge unit according to the voltage deviation and the bridge arm current includes:

[0014] If the product of the voltage deviation and the bridge arm current is less than or equal to 0, the first state priority information of the current H-bridge unit is determined, and the first state priority information includes: the states with the highest priority from the highest priority to the lowest priority are: the capacitor forward series state, the capacitor bypass state, and the capacitor negative series state;

[0015] If the product of the voltage deviation and the bridge arm current is greater than 0, the second state priority information of the current H-bridge unit is determined, and the second state priority information includes: the states with priorities from large to small are: the negative series state of the capacitor, the bypass state of the capacitor, and the forward series state of the capacitor.

[0016] In one embodiment, determining the control state of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit includes:

[0017] Determine a target state based on the state priority information of the current H-bridge unit, the expected output voltage of the H-bridge unit in an undetermined state, and the output voltage that can be provided by the H-bridge unit in an undetermined state, wherein the target state is one of the capacitor negative series state, the capacitor bypass state, and the capacitor forward series state;

[0018] Based on the target state, the control states of all switch sub-units in the current H-bridge unit are determined.

[0019] In one embodiment, determining the target state based on the state priority information of the current H-bridge unit, the expected output voltage of the H-bridge unit in an undetermined state, and the available output voltage of the H-bridge unit in an undetermined state includes:

[0020] Based on the state priority information of the current H-bridge unit, a first state is selected, wherein the first state includes: a state where the capacitors are connected in a forward direction in series, or a state where the capacitors are connected in a negative direction in series;

[0021] In the first state, if the output voltage that can be provided meets the expected output voltage, the first state is determined as the target state, and if the output voltage that can be provided does not meet the expected output voltage, the capacitor bypass state is selected based on the state priority information of the current H-bridge unit;

[0022] In the capacitor bypass state, if the output voltage that can be provided meets the expected output voltage, the capacitor bypass is determined as the target state; if the output voltage that can be provided does not meet the expected output voltage, the third state is selected as the target state based on the state priority information of the current H-bridge unit.

[0023] Among them, the first state is the forward series state of the capacitor, the third state is the negative series state of the capacitor, the first state is the negative series state of the capacitor, and the third state is the forward series state of the capacitor.

[0024] In one embodiment, the method further comprises:

[0025] Determining voltage deviations of n H-bridge units in the bridge arm according to the capacitor voltages of each H-bridge unit in the bridge arm and the average value;

[0026] According to the order of the voltage deviation of each H-bridge unit in the bridge arm from large to small, each H-bridge unit performs the capacitor voltage enhancement balancing step.

[0027] In a second aspect, the present application also provides a cascaded H-bridge unit capacitor voltage enhancement balancing device, comprising:

[0028] A determination module, used to determine the average value of the capacitor voltage of each H-bridge unit in the bridge arm;

[0029] The enhanced balancing module is used to perform an enhanced balancing step on each H-bridge unit in the bridge arm, and the enhanced balancing step includes:

[0030] Determine the state priority information of the current H-bridge unit according to the capacitor voltage, the average value and the bridge arm current of the current H-bridge unit, and determine the control state of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit;

[0031] Among them, the state priority information includes: the states with priorities from large to small are: capacitor forward series state, capacitor bypass state, capacitor negative series state, or the capacitor negative series state, the capacitor bypass state, and the capacitor forward series state.

[0032] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method described in the first aspect or any one of its embodiments is implemented.

[0033] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method as described in the first aspect or any one of its embodiments.

[0034] In a fifth aspect, the present application further provides a computer program product, including a computer program, which, when executed by a processor, implements the method described in the first aspect or any one of its embodiments.

[0035] The above-mentioned cascaded H-bridge unit capacitor voltage enhanced balancing method, device, computer equipment, storage medium and computer program product. In this method, the average value of the capacitor voltage of each H-bridge unit in the bridge arm can be determined; and the enhanced balancing step is performed on each H-bridge unit in the bridge arm, and the enhanced balancing step includes: according to the capacitor voltage, average value and bridge arm current of the current H-bridge unit, the state priority information of the current H-bridge unit is determined, and based on the state priority information of the current H-bridge unit, the control state of all switch subunits in the current H-bridge unit is determined; wherein the state priority information includes: the states with the highest priority from the highest to the lowest are: capacitor positive series state, capacitor bypass state, capacitor negative series state, or capacitor negative series state, capacitor bypass state, capacitor positive series state. Since in the state priority information of the current H-bridge unit determined in the enhanced balancing step, the priority of the capacitor forward series state is greater than the priority of the capacitor bypass state, or the priority of the capacitor negative series state is greater than the priority of the capacitor bypass state, therefore when determining the control state of all switch sub-units in the current H-bridge unit based on the state priority information of the current H-bridge unit, the capacitor forward series state is preferentially selected, or the capacitor negative series state is preferentially selected, so that more H-bridge unit capacitors can participate in energy exchange, thereby quickly compensating for capacitor voltage deviations and improving system stability and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 is a schematic diagram of a cascaded H-bridge arm formed by cascading n H-bridge units in one embodiment;

[0038] Figure 2 A control block diagram of a cascaded H-bridge capacitor voltage balancing algorithm in the prior art;

[0039] Figure 3 It is a schematic diagram of a typical H-bridge unit topology;

[0040] Figure 4 for Figure 3 Schematic diagram of the three common states of the H-bridge unit;

[0041] Figure 5 A schematic diagram of a flow chart of a cascaded H-bridge unit capacitor voltage enhancement balancing method;

[0042] Figure 6 A schematic diagram of another method for enhancing the balancing of capacitor voltages of cascaded H-bridge units;

[0043] Figure 7 A schematic diagram and an equivalent circuit diagram of each switch state in a bridge arm when the capacitor voltage balancing method provided in the prior art is used;

[0044] Figure 8 A schematic diagram and an equivalent circuit diagram of each switch state in a bridge arm when the capacitor voltage enhancement balancing method provided by an embodiment of the present application is used;

[0045] Fig. 9 A structural block diagram of a cascaded H-bridge unit capacitor voltage enhancement balancing device in one embodiment;

[0046] Fig.10 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] As a multi-level topology, the cascaded H-Bridge (CHB) converter is very popular in high-voltage and high-power applications such as renewable energy systems, electric vehicle charging stations, high-voltage DC transmission and active power filters (APF). Figure 1 is a schematic diagram of a cascaded H-bridge arm consisting of n cascaded H-bridge units. Figure 1The structure shown in the figure increases the voltage level by connecting multiple H-bridge units in series. Each H-bridge unit has a capacitor, and the combination of capacitor voltages in different H-bridge units forms the output voltage of the bridge arm. Among them, the balance of capacitor voltages is the key problem for the stable and efficient operation of this converter.

[0049] The voltage balancing algorithm of the cascaded H-bridge capacitors in the prior art aims to make the actual output of the bridge arm voltage track the bridge arm voltage reference signal and minimize the voltage deviation of all H-bridge capacitors in one bridge arm. The prior art usually achieves this by periodically connecting or bypassing the H-bridge capacitors in series. Figure 2 The control block diagram of a cascaded H-bridge capacitor voltage balancing algorithm in the prior art. The input of the controller includes: a bridge arm voltage reference signal, n capacitor voltages in a bridge arm, and a bridge arm current. The bridge arm voltage reference signal is divided by the average value of the n capacitor voltages to obtain a modulation index (Nref). The n capacitor voltages in a bridge arm are sorted from low to high, and then the sequence value of the capacitor connected in series to the main circuit is updated according to the direction of the bridge arm current. The sequence value of the capacitor connected in series to the main circuit is compared with Nref, and the state of each H-bridge unit can be easily obtained by using the nearest level modulation or pulse width modulation. The Nref H-bridge unit capacitors are connected in series to the main circuit in a positive or negative direction, and n - Nref capacitors are bypassed. Finally, the drive signal of each switch unit in all H-bridge units in a bridge arm is obtained by looking up the table.

[0050] The multiple H-bridge unit capacitors under the control of the voltage balancing algorithm in the above-mentioned prior art are in a bypass state and do not participate in energy exchange. The aging and temperature sensitivity of the H-bridge capacitors themselves will affect their capacity and voltage holding ability, resulting in increased difficulty in balancing control. In particular, in the case of rapid load changes or grid failures, it may not be possible to quickly compensate for capacitor voltage deviations, affecting system stability and efficiency.

[0051] The cascaded H-bridge unit capacitor voltage enhancement balancing method provided in the embodiment of the present application can enable more H-bridge unit capacitors to participate in energy exchange, thereby quickly compensating for capacitor voltage deviations and improving system stability and efficiency.

[0052] Figure 3 Schematic diagram of a typical H-bridge unit topology structure, in which the H-bridge unit includes four switch units and one capacitor unit. The four switch units are Figure 3The switch unit 1, switch unit 2, switch unit 3 and switch unit 4 are shown in FIG. Among them, the connection point between switch unit 1 and switch unit 2 is port 1, and the connection point between switch unit 3 and switch unit 4 is port 2. The direction in which the bridge arm current Is flows from port 1 can be defined as the current reference positive direction, denoted as Is>0; the voltage drop from port 1 to port 2 is defined as the positive direction of the H-bridge unit voltage Vh, denoted as Vh>0.

[0053] Figure 4 for Figure 3 Schematic diagram of the three common states of the H-bridge unit. Figure 3 The switch unit and Figure 4 The voltage of the capacitor unit is defined as Vc, Vc>=0.

[0054] When switch units 1 and 3 are turned on and switch units 2 and 4 are turned off, the capacitor unit is bypassed, corresponding to Figure 4 The capacitor bypass state in (a) is shown in the figure. At this time, Vh=0 and there is no energy exchange between the capacitor and the main circuit.

[0055] When switch units 1 and 4 are turned on and switch units 2 and 3 are turned off, the capacitor unit is connected in series with the main circuit in the forward direction, corresponding to Figure 4 The capacitor in (c) shown in the figure is in the forward series state. At this time, Vh=Vc, and there is energy exchange between the capacitor and the main circuit: if Is>0, Is flows into the positive electrode of the capacitor unit and Vc rises; if Is<0, Is flows into the negative electrode of the capacitor unit and Vc decreases.

[0056] When switch units 2 and 3 are turned on and 1 and 4 are turned off, the capacitor unit is connected in series with the main circuit in the negative direction, corresponding to Figure 4 The capacitor in (c) shown in the figure is in the forward series state. At this time, Vh=-Vc, and there is energy exchange between the capacitor and the main circuit: if Is>0, Is flows into the negative electrode of the capacitor unit and Vc decreases; if Is<0, Is flows into the positive electrode of the capacitor unit and Vc increases.

[0057] from Figure 4 It can be seen that in different states of the H-bridge unit, the control state of the switch unit will be different. The corresponding relationship between the state of the H-bridge unit and the control state of the switch unit can be shown in Table 1 below.

[0058] Table 1

[0059]

[0060] Figure 5 FIG. 1 is a flow chart of a method for enhancing the voltage balance of cascaded H-bridge unit capacitors. Figure 5 The method may include but is not limited to the following steps:

[0061] 501. Determine an average value of the capacitor voltages of each H-bridge unit in a bridge arm.

[0062] The capacitor voltages of the H-bridge units in the bridge arm may be first obtained, and then the average value of the capacitor voltages of the H-bridge units in the bridge arm may be determined by averaging.

[0063] 502. Perform an enhanced balancing step on each H-bridge unit in the bridge arm, the enhanced balancing step comprising: determining the state priority information of the current H-bridge unit according to the capacitor voltage, average value and bridge arm current of the current H-bridge unit, and determining the control state of all switch sub-units in the current H-bridge unit based on the state priority information of the current H-bridge unit.

[0064] In some embodiments, the enhanced balancing step may be performed sequentially on each H-bridge unit in the bridge arm in any order to determine the control state of all switch sub-units in each H-bridge unit.

[0065] In some embodiments, the state priority information includes: the states with the highest priority in descending order are: capacitor positive series state, capacitor bypass state, capacitor negative series state.

[0066] In some embodiments, the state priority information includes: capacitor negative series state, capacitor bypass state, and capacitor positive series state.

[0067] In the above-mentioned enhanced balancing step, the voltage deviation of the current H-bridge capacitor can be determined first according to the capacitor voltage and average value of the current H-bridge unit, and then the state priority information of the current H-bridge unit can be determined according to the voltage deviation and the bridge arm current; then based on the state priority information of the current H-bridge unit, the control state of all switch sub-units in the current H-bridge unit is determined, that is, based on the state priority information of the current H-bridge unit, the state of the current H-bridge unit is selected, and the control state of all switch sub-units in the current H-bridge unit is determined based on the selected state of the current H-bridge unit.

[0068] The voltage deviation may be a difference between the capacitor voltage of the H-bridge unit and the average value, and may be a positive value or a negative value.

[0069] In some embodiments, determining the state priority information of the current H-bridge unit according to the voltage deviation and the bridge arm current may include but is not limited to the following situations:

[0070] (1) If the product of the voltage deviation and the bridge arm current is less than or equal to 0, the first state priority information of the current H-bridge unit is determined, and the first state priority information includes: the states with the highest priority from the highest to the lowest are: the capacitor forward series state, the capacitor bypass state, and the capacitor negative series state.

[0071] In some embodiments, when the voltage deviation is positive and the bridge arm current is negative, the product of the voltage deviation and the bridge arm current is less than or equal to 0. At this time, it means that the capacitor voltage of the H-bridge unit is greater than the average value, indicating that the capacitor voltage needs to be reduced. At this time, the bridge arm current is negative. Therefore, the first state priority information can be determined, and the current H-bridge unit is preferentially placed in the capacitor forward series state for discharge to reduce the capacitor voltage. Secondly, the H-bridge unit is placed in the capacitor bypass state without discharging or charging. At the very least, the current H-bridge unit is placed in the capacitor negative series state for charging to increase the capacitor voltage.

[0072] In some embodiments, when the voltage deviation is negative and the bridge arm current is positive, the product of the voltage deviation and the bridge arm current is less than or equal to 0. This indicates that the capacitor voltage of the H-bridge unit is less than the average value, indicating that the capacitor voltage needs to be increased, and the bridge arm current is positive at this time, so the first state priority information can be determined, and the current H-bridge unit is preferentially placed in a capacitor forward series state for charging to increase the capacitor voltage, and secondly, the H-bridge unit is placed in a capacitor bypass state without discharging or charging, and finally, the current H-bridge unit is placed in a capacitor negative series state for charging to reduce the capacitor voltage.

[0073] (2) If the product of the voltage deviation and the bridge arm current is greater than 0, the second state priority information of the current H-bridge unit is determined, and the second state priority information includes: the states with the highest priority from the highest to the lowest are: the capacitor negative series state, the capacitor bypass state, and the capacitor positive series state.

[0074] In some embodiments, when the voltage deviation is positive and the bridge arm current is positive, the product of the voltage deviation and the bridge arm current is greater than 0. At this time, it means that the capacitor voltage of the H-bridge unit is greater than the average value, indicating that the capacitor voltage needs to be reduced. At this time, the bridge arm current is positive. Therefore, the second state priority information can be determined, and the current H-bridge unit is preferentially placed in a capacitor negative series state for discharge to reduce the capacitor voltage. Secondly, the H-bridge unit is placed in a capacitor bypass state without discharging or charging. At the very least, the current H-bridge unit is placed in a capacitor positive series state for charging to increase the capacitor voltage.

[0075] In some embodiments, when the voltage deviation is negative and the bridge arm current is negative, the product of the voltage deviation and the bridge arm current is greater than 0. This indicates that the capacitor voltage of the H-bridge unit is less than the average value, indicating that the capacitor voltage needs to be increased, and the bridge arm current is negative at this time, so the second state priority information can be determined, and the current H-bridge unit is preferentially placed in a capacitor negative series state for charging to increase the capacitor voltage, and secondly, the H-bridge unit is placed in a capacitor bypass state without discharging or charging, and finally, the current H-bridge unit is placed in a capacitor positive series state for charging to reduce the capacitor voltage.

[0076] The above-mentioned cascaded H-bridge unit capacitor voltage enhanced balancing method can determine the average value of the capacitor voltage of each H-bridge unit in the bridge arm; and perform an enhanced balancing step on each H-bridge unit in the bridge arm, the enhanced balancing step including: determining the state priority information of the current H-bridge unit according to the capacitor voltage, average value and bridge arm current of the current H-bridge unit, and determining the control state of all switch sub-units in the current H-bridge unit based on the state priority information of the current H-bridge unit; wherein the state priority information includes: the states with the highest priority from the highest to the lowest are: capacitor positive series state, capacitor bypass state, capacitor negative series state, or capacitor negative series state, capacitor bypass state, capacitor positive series state. Since in the state priority information of the current H-bridge unit determined in the enhanced balancing step, the priority of the capacitor forward series state is greater than the priority of the capacitor bypass state, or the priority of the capacitor negative series state is greater than the priority of the capacitor bypass state, therefore when determining the control state of all switch sub-units in the current H-bridge unit based on the state priority information of the current H-bridge unit, the capacitor forward series state is preferentially selected, or the capacitor negative series state is preferentially selected, so that more H-bridge unit capacitors can participate in energy exchange, thereby quickly compensating for capacitor voltage deviations and improving system stability and efficiency.

[0077] In some embodiments, based on the state priority information of the current H-bridge unit, determining the control state of all switch sub-units in the current H-bridge unit may include but is not limited to: determining the target state based on the state priority information of the current H-bridge unit, the expected output voltage of the H-bridge unit in an undetermined state, and the output voltage that can be provided by the H-bridge unit in an undetermined state, the target state is one of the capacitor negative series state, the capacitor bypass state, and the capacitor positive series state; based on the target state, determining the control state of all switch sub-units in the current H-bridge unit.

[0078] In some embodiments, based on the state priority information of the current H-bridge unit, the expected output voltage of the H-bridge unit in an undetermined state, and the available output voltage of the H-bridge unit in an undetermined state, determining the target state may include but is not limited to: based on the state priority information of the current H-bridge unit, selecting the first state, the first state including: the capacitor forward series state, or the capacitor negative series state; in the first state, if the available output voltage meets the expected output voltage, the first state is determined as the target state, if the available output voltage does not meet the expected output voltage, based on the state priority information of the current H-bridge unit, the capacitor bypass state is selected; in the capacitor bypass state, if the available output voltage meets the expected output voltage, the capacitor bypass is determined as the target state, if the available output voltage does not meet the expected output voltage, based on the state priority information of the current H-bridge unit, the third state is selected as the target state.

[0079] Among them, the first state is the capacitor forward series state, the third state is the capacitor negative series state, the first state is the capacitor negative series state, and the third state is the capacitor forward series state.

[0080] In the above embodiment, after the state priority information of the current H-bridge unit is known, the expected output voltage of the H-bridge unit in the undetermined state and the output voltage that can be provided by the H-bridge unit in the undetermined state can be considered, and the target state with the highest priority that can provide an output voltage that meets the expected output voltage is selected, and the control state of all switch sub-units in the current H-bridge unit is determined based on the target state. In this way, the optimal connection state can be selected to determine the control state of all switch sub-units in the current H-bridge unit while making the output voltage meet the expected output voltage.

[0081] In some embodiments, the voltage deviation of n H-bridge units in the bridge arm can be determined based on the capacitor voltage and the average value of each H-bridge unit in the bridge arm; and the enhanced balancing step is performed on each of the n H-bridge units in the bridge arm in the order of the voltage deviation of each H-bridge unit in the bridge arm from large to small.

[0082] In the above embodiment, the enhanced balancing step is performed on each of the n H-bridge units in the bridge arm in the order of the voltage deviation of each H-bridge unit in the bridge arm from large to small, so that the enhanced balancing step can be performed on the H-bridge unit with a large voltage deviation first, and then the enhanced balancing step can be performed on the H-bridge unit with a small voltage deviation. In this way, the capacitor voltage deviation can be compensated more quickly and the system stability and efficiency can be improved.

[0083] Figure 6 FIG. 1 is a flow chart of another method for enhancing the voltage balance of capacitors in cascaded H-bridge units. Figure 6 The method may include but is not limited to the following steps:

[0084] 601. Obtain an n-dimensional array Vcs consisting of a bridge arm voltage reference value Vs*, a bridge arm current Is, and capacitor voltages of n H-bridge units in one bridge arm.

[0085] Wherein, Vcs={Vc1, Vc2, ..., Vcn}, the kth element Vcs[k]=Vck(k=1, ..., n) in Vcs represents the capacitor voltage of the kth H-bridge unit. The above k is greater than or equal to 1 and less than or equal to n, k = 1, ..., n.

[0086] 602. Calculate an average value Vc0 of capacitor voltages of n H-bridge units in one bridge arm and an n-dimensional voltage deviation array dVcs.

[0087] Among them, dVcs = {|Vc1-Vc0|, |Vc2-Vc0|, ..., |Vcn-Vc0|}, the kth element dVcs[k] in dVcs = |Vck - Vc0|, which represents the absolute value of the difference between the capacitor voltage of the kth H-bridge unit and the average capacitor voltage.

[0088] 603. Sort the elements in the n-dimensional voltage deviation array dVcs from large to small to obtain an n-dimensional sorted array Rs.

[0089] Where Rs = {Rs[1], Rs[2], ..., Rs[n]}, and the array elements include n positive integers from 1 to n. Rs makes dVcs[Rs[k]] monotonically decrease as k increases from 1 to n, with dVcs[Rs[1]] being the largest and dVcs[Rs[n]] being the smallest.

[0090] For example, assuming n=3, Vcs={1,3,8} indicates that the capacitor voltages of the three H-bridge units in one bridge arm are 1V, 3V, and 8V, respectively. Vc0=(1+3+8)÷3=4V, corresponding dVcs = {|1-4|, |3-4|, |8-4|} = {3,1,4}; corresponding Rs={3,1,2}, that is, the difference between the capacitor voltage of H-bridge unit 3 and the average capacitor voltage is the largest, followed by H-bridge unit 1, and the difference between the capacitor voltage of H-bridge unit 2 and the average capacitor voltage is the smallest.

[0091] 604. Initialize parameter j, n-dimensional array Vref and n-dimensional array Vavail.

[0092] Wherein, Vref represents the expected output voltage of the H-bridge unit in an undetermined state of Vavail, and Vavail represents the available output voltage of the H-bridge unit in an undetermined state.

[0093] Let j = 1, Vref[j] = Vs*, Vavail[j] = n × Vc0.

[0094] 605. Determine the status priority information of the H-bridge unit Rs[j].

[0095] If (Vcs[Rs[j]] - Vc0) × Is is less than or equal to 0, the state priority information of the H-bridge unit j includes: the preferred states are the capacitor forward series state, the capacitor bypass state, and the capacitor negative series state.

[0096] If (Vcs[Rs[j]] - Vc0) × Is is greater than 0, the state priority information of the H-bridge unit j includes: the preferred states are the capacitor negative series state, the capacitor bypass state, and the capacitor positive series state.

[0097] 606. Select the best state from the remaining preferred states.

[0098] 607. Determine whether the current selection state of the H-bridge unit Rs[j] is feasible.

[0099] For the case where the preferred states are capacitor positive series state, capacitor bypass state, and capacitor negative series state:

[0100] When the current selection state is the capacitor forward series state, if |Vref[j] - Vcs[ Rs[j] ]| <= Vavail[j] - Vcs[ Rs[j] ] ÷ 2, then the state is feasible and the following step 608 is executed; otherwise, the current selection state is discarded and the process returns to the above step 606 to reselect the capacitor bypass state of the next priority.

[0101] When the current selected state is the capacitor bypass state, if |Vref[j]| <= Vavail[j] - Vcs[ Rs[j]] ÷ 2, the state is feasible and the following step 608 is executed; otherwise, the current selected state is discarded and the process returns to the above step 606 to reselect the capacitor negative series state.

[0102] For the case where the preferred states are capacitor negative series state, capacitor bypass state, and capacitor positive series state:

[0103] When the current selection state is the capacitor negative series state, if |Vref[j] + Vcs[ Rs[j] ]| <= Vavail[j] - Vcs[ Rs[j] ] ÷ 2, then the state is feasible and the following step 608 is executed; otherwise, the current selection state is discarded and the process returns to the above step 606 to reselect the capacitor bypass state of the next priority.

[0104] When the current selected state is the capacitor bypass state, if |Vref[j]| <= Vavail[j] - Vcs[ Rs[j]] ÷ 2, the state is feasible and the following step 608 is executed; otherwise, the current selected state is discarded and the process returns to the above step 606 to reselect the capacitor forward series state.

[0105] 608. Update parameters j, Vref[j+1] and Vavail[j+1] according to the feasible state of the H-bridge unit Rs[j].

[0106] If the feasible state of the H-bridge unit Rs[j] is the capacitor forward series connection state, then Vref[j+1] = Vref[j] -Vcs[ Rs[j] ].

[0107] If the feasible state of the H-bridge unit Rs[j] is the capacitor bypass state, then Vref[j+1] = Vref[j].

[0108] If the feasible state of the H-bridge unit Rs[j] is the negative series connection state of the capacitor, then Vref[j+1] = Vref[j] +Vcs[ Rs[j] ].

[0109] Update parameters: Vavail[j+1] = Vavail[j] - Vcs[ Rs[j] ]; j=j+1.

[0110] 609. Determine whether the parameter j is greater than the number n of H-bridge units.

[0111] If the parameter j is greater than the number n of H-bridge units, then continue to execute step 610 ; if the parameter j is less than or equal to the number n of H-bridge units, then return to execute step 605 .

[0112] 610. According to the feasible state of each H-bridge unit, obtain the control state of all switch units.

[0113] The control states of all switch units can be obtained by querying Table 1 according to the feasible state of each H-bridge unit.

[0114] In the above-mentioned cascaded H-bridge unit capacitor voltage enhanced balancing method, since in the state priority information of the current H-bridge unit determined in the enhanced balancing step, the priority of the capacitor forward series state is greater than the priority of the capacitor bypass state, or the priority of the capacitor negative series state is greater than the priority of the capacitor bypass state, therefore when determining the control state of all switch sub-units in the current H-bridge unit based on the state priority information of the current H-bridge unit, the capacitor forward series state is preferentially selected, or the capacitor negative series state is preferentially selected, so that more H-bridge unit capacitors can participate in energy exchange, thereby quickly compensating for capacitor voltage deviations and improving system stability and efficiency.

[0115] In the above embodiment, after the state priority information of the current H-bridge unit is known, the expected output voltage of the H-bridge unit in the undetermined state and the available output voltage of the H-bridge unit in the undetermined state can be considered, and the target state with the highest priority (i.e., the above feasible state) that can provide an output voltage that meets the expected output voltage is selected, and the control state of all switch sub-units in the current H-bridge unit is determined based on the target state. In this way, the optimal connection state can be selected to determine the control state of all switch sub-units in the current H-bridge unit while making the output voltage meet the expected output voltage.

[0116] In the above embodiment, the enhanced balancing step is performed on each of the n H-bridge units in the bridge arm in the order of the voltage deviation of each H-bridge unit in the bridge arm from large to small, so that the enhanced balancing step can be performed on the H-bridge unit with a large voltage deviation first, and then the enhanced balancing step can be performed on the H-bridge unit with a small voltage deviation. In this way, the capacitor voltage deviation can be compensated more quickly and the system stability and efficiency can be improved.

[0117] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0118] For example, when a bridge arm has three H-bridge units and the bridge arm voltage reference is an H-bridge capacitor voltage, when the capacitor voltage balancing method provided in the prior art is adopted, the schematic diagram and equivalent circuit diagram of each switch state in the bridge arm are as follows: Figure 7 As shown in Figure 7 As shown, only one H-bridge unit capacitor participates in energy exchange. When the capacitor voltage enhancement balancing method provided in the embodiment of the present application is adopted, the schematic diagram and equivalent circuit diagram of each switch state in the bridge arm are as follows Figure 8 As shown, Figure 8 All H-bridge unit capacitors participate in energy exchange. The cascaded H-bridge unit capacitor voltage enhancement balancing algorithm proposed in this patent can enable most H-bridge unit capacitors to participate in energy exchange during operation, quickly compensate for capacitor voltage deviations, and improve the response speed and stability of the cascaded H-bridge converter.

[0119] Based on the same inventive concept, the embodiment of the present application also provides a cascaded H-bridge unit capacitor voltage enhancement balancing device for implementing the above-mentioned cascaded H-bridge unit capacitor voltage enhancement balancing method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above-mentioned method, so the specific limitations in the embodiments of one or more cascaded H-bridge unit capacitor voltage enhancement balancing devices provided below can refer to the limitations of the cascaded H-bridge unit capacitor voltage enhancement balancing method above, and will not be repeated here.

[0120] In an exemplary embodiment, Fig. 9As shown, a cascaded H-bridge unit capacitor voltage enhancement balancing device is provided, comprising:

[0121] A determination module 901 is used to determine the average value of the capacitor voltage of each H-bridge unit in the bridge arm;

[0122] The enhanced balancing module 902 is used to perform an enhanced balancing step on each H-bridge unit in the bridge arm, and the enhanced balancing step includes:

[0123] Determine the state priority information of the current H-bridge unit according to the capacitor voltage, the average value and the bridge arm current of the current H-bridge unit, and determine the control state of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit;

[0124] Among them, the state priority information includes: the states with priorities from large to small are: capacitor forward series state, capacitor bypass state, capacitor negative series state, or the capacitor negative series state, the capacitor bypass state, and the capacitor forward series state.

[0125] In one embodiment, the enhanced balancing module 902 is specifically used to: determine the voltage deviation of the current H-bridge unit according to the capacitor voltage of the current H-bridge unit and the average value;

[0126] The state priority information of the current H-bridge unit is determined according to the voltage deviation and the bridge arm current.

[0127] In one embodiment, the enhanced balancing module 902 is specifically used to: if the product of the voltage deviation and the bridge arm current is less than or equal to 0, determine the first state priority information of the current H-bridge unit, and the first state priority information includes: the states with priorities from large to small are: the capacitor forward series state, the capacitor bypass state, and the capacitor negative series state; if the product of the voltage deviation and the bridge arm current is greater than 0, determine the second state priority information of the current H-bridge unit, and the second state priority information includes: the states with priorities from large to small are: the capacitor negative series state, the capacitor bypass state, and the capacitor forward series state.

[0128] In one embodiment, the enhanced balancing module 902 is specifically used to: determine a target state based on the state priority information of the current H-bridge unit, the expected output voltage of the H-bridge unit in an undetermined state, and the available output voltage of the H-bridge unit in an undetermined state, wherein the target state is one of the negative series state of the capacitor, the bypass state of the capacitor, and the forward series state of the capacitor; and determine the control state of all switch sub-units in the current H-bridge unit based on the target state.

[0129] In one embodiment, the enhanced balancing module 902 is specifically used to: select a first state based on the state priority information of the current H-bridge unit, the first state including: the capacitor forward series state, or the capacitor negative series state; in the first state, if the available output voltage meets the expected output voltage, the first state is determined as the target state, if the available output voltage does not meet the expected output voltage, the capacitor bypass state is selected based on the state priority information of the current H-bridge unit; in the capacitor bypass state, if the available output voltage meets the expected output voltage, the capacitor bypass is determined as the target state, if the available output voltage does not meet the expected output voltage, based on the state priority information of the current H-bridge unit, a third state is selected as the target state, wherein the first state is the capacitor forward series state, the third state is the capacitor negative series state, the first state is the capacitor negative series state, and the third state is the capacitor forward series state.

[0130] In one embodiment, the determination module 901 is further used to determine the voltage deviation of n H-bridge units in the bridge arm according to the capacitor voltage of each H-bridge unit in the bridge arm and the average value;

[0131] The enhanced balancing module 902 is specifically used to: in the order of the voltage deviation of each H-bridge unit in the bridge arm from large to small, each H-bridge unit performs the capacitor voltage enhanced balancing step.

[0132] Each module in the above-mentioned cascaded H-bridge unit capacitor voltage enhancement balancing device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each of the above modules.

[0133] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Fig.10As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a cascaded H-bridge unit capacitor voltage enhancement balancing method is implemented.

[0134] Those skilled in the art will understand that Fig.10 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0135] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and each step in the above method embodiment is implemented when the processor executes the computer program.

[0136] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0137] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for enhancing the voltage balance of capacitors of cascaded H-bridge units, characterized in that: include: Determine the average value of the capacitor voltage of each H-bridge unit in the bridge arm; Performing an enhanced balancing step on each H-bridge unit in the bridge arm, the enhanced balancing step comprising: determining the state priority information of the current H-bridge unit according to the capacitor voltage of the current H-bridge unit, the average value and the bridge arm current, and determining the control state of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit; The state priority information includes: the states with the highest priority from the highest to the lowest are: the capacitor forward series state, the capacitor bypass state, the capacitor negative series state, or the capacitor negative series state, the capacitor bypass state, the capacitor forward series state; The determining the state priority information of the current H-bridge unit according to the capacitor voltage of the current H-bridge unit, the average value and the bridge arm current includes: Determining a voltage deviation of the current H-bridge unit according to the capacitor voltage of the current H-bridge unit and the average value; If the product of the voltage deviation and the bridge arm current is less than or equal to 0, the first state priority information of the current H-bridge unit is determined, and the first state priority information includes: the states with the highest priority from the highest priority to the lowest priority are: the capacitor forward series state, the capacitor bypass state, and the capacitor negative series state; If the product of the voltage deviation and the bridge arm current is greater than 0, the second state priority information of the current H-bridge unit is determined, and the second state priority information includes: the states with priorities from large to small are: the negative series state of the capacitor, the bypass state of the capacitor, and the forward series state of the capacitor.

2. The method according to claim 1, characterized in that The determining the control states of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit includes: Determine a target state based on the state priority information of the current H-bridge unit, the expected output voltage of the H-bridge unit in an undetermined state, and the output voltage that can be provided by the H-bridge unit in an undetermined state, wherein the target state is one of the capacitor negative series state, the capacitor bypass state, and the capacitor forward series state; Based on the target state, the control states of all switch sub-units in the current H-bridge unit are determined.

3. The method according to claim 2, characterized in that The determining of the target state based on the state priority information of the current H-bridge unit, the expected output voltage of the H-bridge unit in an undetermined state, and the available output voltage of the H-bridge unit in an undetermined state includes: Based on the state priority information of the current H-bridge unit, a first state is selected, wherein the first state includes: a state where the capacitors are connected in a forward direction in series, or a state where the capacitors are connected in a negative direction in series; In the first state, if the output voltage that can be provided meets the expected output voltage, the first state is determined as the target state, and if the output voltage that can be provided does not meet the expected output voltage, the capacitor bypass state is selected based on the state priority information of the current H-bridge unit; In the capacitor bypass state, if the output voltage that can be provided meets the expected output voltage, the capacitor bypass is determined as the target state; if the output voltage that can be provided does not meet the expected output voltage, the third state is selected as the target state based on the state priority information of the current H-bridge unit. Among them, the first state is the forward series state of the capacitor, the third state is the negative series state of the capacitor, the first state is the negative series state of the capacitor, and the third state is the forward series state of the capacitor.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Determining voltage deviations of n H-bridge units in the bridge arm according to the capacitor voltages of each H-bridge unit in the bridge arm and the average value; The enhanced balancing step is performed on each H-bridge unit in the bridge arm in the order of the voltage deviation of each H-bridge unit from large to small.

5. A cascaded H-bridge unit capacitor voltage enhancement balancing device, characterized in that: include: A determination module, used to determine the average value of the capacitor voltage of each H-bridge unit in the bridge arm; The enhanced balancing module is used to perform an enhanced balancing step on each H-bridge unit in the bridge arm, and the enhanced balancing step includes: Determine the state priority information of the current H-bridge unit according to the capacitor voltage, the average value and the bridge arm current of the current H-bridge unit, and determine the control state of all switch subunits in the current H-bridge unit based on the state priority information of the current H-bridge unit; The state priority information includes: the states with the highest priority from the highest to the lowest are: the capacitor forward series state, the capacitor bypass state, the capacitor negative series state, or the capacitor negative series state, the capacitor bypass state, the capacitor forward series state; The enhanced balancing module is specifically used for: Determining a voltage deviation of the current H-bridge unit according to the capacitor voltage of the current H-bridge unit and the average value; If the product of the voltage deviation and the bridge arm current is less than or equal to 0, the first state priority information of the current H-bridge unit is determined, and the first state priority information includes: the states with the highest priority from the highest priority to the lowest priority are: the capacitor forward series state, the capacitor bypass state, and the capacitor negative series state; If the product of the voltage deviation and the bridge arm current is greater than 0, the second state priority information of the current H-bridge unit is determined, and the second state priority information includes: the states with priorities from large to small are: the negative series state of the capacitor, the bypass state of the capacitor, and the forward series state of the capacitor.

6. A computer device, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 4 when executing the computer program.

7. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

8. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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