A message pre-classification processor and method

Abstract

A message pre-classification processor and method, wherein the message pre-classification processor comprises: a plurality of micro-engines; the micro-engines comprise a micro-engine pipeline and a micro-engine state machine; the micro-engine pipeline comprises: an instruction fetch stage for fetching instructions from an instruction storage; a decoding stage for parsing the instructions fetched by the instruction fetch stage, obtaining an operand pointer and a packet pointer; a register file reading stage for obtaining the operand from the register file according to the operand pointer, and obtaining corresponding packet data from the packet data register file according to the packet pointer, and transmitting the same to the execution stage; the register file reading stage comprises at least one packet data register file; the packet data register file can cache packet data; the execution stage performs operations according to the operand and the packet data. The present invention improves the performance of the micro-engine while reducing the probability of invalid pre-fetching and controlling power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a message pre-classification processor and method. Background Art

[0002] With the rapid development of network technology, the energy consumption ratio of network processors has received more and more attention. The message pre-classification processor is a key component used to classify messages in network communications. Its main function is to classify messages according to predefined rules during the message transmission process before the message enters the network core processing flow, and use the classification results for subsequent routing, forwarding, priority processing, etc. The message pre-classification processor is responsible for pre-parsing incoming messages, classifying and forwarding traffic based on message characteristics, which often requires a large number of message reading and parsing operations.

[0003] The network processor microengine is the core data processing unit in the network processor (NP), and it plays a vital role in network data processing. The network processor microengine is a hardware-based static multi-threaded scheduling unit that is mainly responsible for data-level processing, such as data packet classification, processing, and forwarding. The design of the microengine aims to improve the data processing capability and efficiency of the network processor to meet the needs of modern networks for high performance and programmability. When the traditional network processor microengine needs to obtain the message data to be processed, it requests data from the message storage unit through a dedicated packet data load / store instruction, and the microengine pipeline is suspended and resumed after the packet data is returned. However, in some scenarios where packet data is used frequently, this method will increase the number of business microcodes, increase the processing delay of the microengine, and affect the overall performance of the processor.

[0004] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above content has been disclosed on the filing date of this patent application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0005] To this end, the message pre-classification processor and method provided by the present invention saves instruction space for accessing packet data storage and shortens memory access delay by automatically acquiring and pre-fetching packet data. By dynamically controlling pre-fetching through microinstructions, the performance of the micro-engine is improved while reducing the probability of invalid pre-fetching and controlling power consumption.

[0006] In a first aspect, the present invention provides a message pre-classification processor, characterized in that it comprises: a plurality of micro-engines; each of the micro-engines comprises a micro-engine pipeline;

[0007] The microengine pipeline includes an instruction fetch stage, a decode stage, a register file read stage, and an execute stage;

[0008] Wherein, the instruction fetch stage is used to fetch instructions from the instruction storage;

[0009] The decoding stage is used to parse the instruction fetched by the instruction fetch stage, and obtain an operand pointer and a packet pointer; wherein the packet pointer identifies the byte number of the packet data to be obtained; and the operand pointer identifies the address of the operand in the register file;

[0010] The register file reading stage obtains the corresponding operand from the register file according to the operand pointer, obtains the corresponding packet data from the packet data register file according to the packet pointer, and transmits the packet data to the execution stage; the register file reading stage includes at least one packet data register file; the packet data register file can cache packet data;

[0011] The execution stage performs operations according to operands and packet data obtained by the register file read stage.

[0012] Optionally, the message pre-classification processor is characterized in that when a microengine is assigned to process a message, the packet data register file loads part of the data in the packet cache and provides it to the execution stage.

[0013] Optionally, the message pre-classification processor is characterized in that the packet data register file issues a packet data request, pauses the microengine pipeline, and after receiving the packet data, loads the packet data into the packet data register file, and the register file provides the packet data to the execution stage and resumes the microengine pipeline.

[0014] Optionally, the message pre-classification processor is characterized in that if the packet data in the pre-fetch window is not in the packet data register file, the packet data register file initiates pre-fetch and stores the packet data in the packet data register file.

[0015] Optionally, the message pre-classification processor is characterized in that when the packet data register file initiates pre-fetching, the micro-engine pipeline is not paused.

[0016] Optionally, the message pre-classification processor is characterized in that when the pre-fetch instruction needs to be revoked after being issued, a cancel pre-fetch request is issued; if the cancel pre-fetch request is unsuccessful, the packet data returned according to the pre-fetch instruction is discarded.

[0017] Optionally, the message pre-classification processor is characterized in that the packet data register file includes multiple storage slices; each of the storage slices can independently initiate reading and pre-fetching of packet data.

[0018] Optionally, the message pre-classification processor is characterized in that the storage slice comprises: an input data selection and recording module, a data storage module, an output data selection module, a storage slice state machine, and an acquisition and pre-fetch detection module;

[0019] The input data selection and recording module is used to receive initial packet data and packet data return, send corresponding records to the storage slice state machine, and send the data to be stored to the data storage module;

[0020] The data storage module is used to store package data;

[0021] The output data selection module is used to select the data to be output from the data storage module for output;

[0022] The storage slice state machine is used to control the operation state of the storage slice;

[0023] The acquisition and pre-fetch detection module is used to acquire packet pointers and control information, detect stored data records, send acquisition or pre-fetch signals, and send pipeline stop signals.

[0024] Optionally, the message pre-classification processor is characterized in that the micro-engine supports pre-fetch control instructions to dynamically modify the pre-fetch configuration.

[0025] Optionally, the message pre-classification processor is characterized in that if the data packet needs to be used continuously, the pre-fetch control instruction is used to configure a larger pre-fetch window; if the data packet does not need to be used continuously, the pre-fetch control instruction is used to configure a smaller pre-fetch window.

[0026] Optionally, the message pre-classification processor is characterized in that each of the microengines further includes a microengine state machine;

[0027] The micro-engine state machine is used to control the working state of the micro-engine pipeline to switch between idle, running and end;

[0028] When the microengine state machine is idle, it indicates that the microengine pipeline can receive messages;

[0029] When the micro-engine state machine is in operation, it indicates that the micro-engine pipeline is running;

[0030] When the micro-engine state machine is at the end, it indicates that the micro-engine pipeline is waiting for the execution result to be taken away.

[0031] In a first aspect, the present invention provides a message pre-classification method, characterized in that it includes:

[0032] Step S1: fetching instructions from instruction storage;

[0033] Step S2: parsing the instruction to obtain an operand pointer and a packet pointer; wherein the packet pointer identifies the byte number of the packet data to be obtained; and the operand pointer identifies the address of the operand;

[0034] Step S3: acquiring a corresponding operand according to the operand pointer, and acquiring corresponding packet data from the packet data register file according to the packet pointer; wherein the packet data register file can cache packet data;

[0035] Step S4: Execute an operation according to the acquired operand and the packet data.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The micro-engine pipeline of the present invention realizes parallel processing of instructions and improves the execution efficiency and performance of the processor by decomposing the instruction execution process into multiple stages such as instruction fetching, decoding, register file reading and execution. Each stage has clear responsibilities and functions, and each stage is connected by the micro-engine pipeline to realize continuous and efficient execution of instructions.

[0038] The register file read stage in the present invention can load data in the packet cache, and can pre-fetch data so that the micro-engine pipeline does not need to be paused when requesting data to the packet cache, thereby reducing the number of business microcodes, reducing the processing delay of the micro-engine, and improving the overall performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings in the following descriptions are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more obvious:

[0040] Figure 1 A schematic diagram of the structure of a message pre-classification processor according to an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of a processing flow of a message pre-classification processor in an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of the working state of a micro-engine state machine in an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of the organization of a packet data register file in an embodiment of the present invention;

[0044] Figure 5 A storage slice data flow graph in an embodiment of the present invention;

[0045] Figure 6 A state transition diagram of a storage slice state machine in an embodiment of the present invention;

[0046] Figure 7 A schematic diagram of a cyclic redundancy check instruction in an embodiment of the present invention;

[0047] Figure 8 The present invention is a flowchart of a method for pre-classifying messages according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0049] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein, for example, can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] A message pre-classification processor provided in an embodiment of the present invention is intended to solve the problems existing in the prior art.

[0051] In order to make it easier for those skilled in the art to understand and implement the scheme of the present invention, some contents are described in this specification using fixed size or quantity as an example. For example, the instruction length is 128 bits, the size of the byte packet data is 48 bytes, and the storage slices are 3 or 4. However, this does not mean that this description is only applicable to the application scenarios of the above numbers. It can be understood by those skilled in the art that the numbers in this specification are only described in as much detail as possible to enable those skilled in the art to better understand and implement the present invention, and the number required for the actual implementation of this scheme can be set according to various application scenarios. Therefore, under the enlightenment of the present invention, any size of instruction length, byte packet data, number of storage slices or the number of other components and changes caused by changes in the corresponding quantities are within the protection scope of the present invention.

[0052] The following specific embodiments are used to describe in detail the technical solutions of the present invention and how the technical solutions of the present application solve the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0053] The message pre-classification processor provided by the present invention saves instruction space for accessing packet data storage and shortens memory access delay by automatically acquiring and pre-fetching packet data. It can also reduce invalid pre-fetching probability and control power consumption while improving micro-engine performance through dynamic control of pre-fetching by micro-instructions.

[0054] Figure 1 FIG. 1 is a schematic diagram of the structure of a message pre-classification processor according to an embodiment of the present invention. Figure 1 As shown, a message pre-classification processor in an embodiment of the present invention includes: multiple micro-engines; each of the micro-engines includes a micro-engine pipeline.

[0055] Specifically, the microengine is the basic processing unit in the message pre-classification processor and is also the core component, responsible for executing a series of instructions and operations to complete specific data processing tasks. The microengine is universal and programmable. Multiple microengines form a microengine pool. They are highly parallel and programmable and can process multiple data streams or instruction sets at the same time. Each microengine is an independent processor that can execute different tasks in parallel.

[0056] The microengine pipeline is divided into the instruction fetch stage (fetch), the decode stage (decode), the register file read stage (register file read), and the execution stage (execute).

[0057] Specifically, each microengine is equipped with a microengine pipeline to improve the speed and efficiency of data processing. Microengine pipeline is a technology that breaks down the instruction execution process into multiple consecutive stages, each stage is handled by a different part of the microengine. This design can significantly improve the throughput and efficiency of instruction execution.

[0058] The instruction fetch stage is used to fetch instructions from the instruction store. The instruction fetch stage is the first stage of the microengine pipeline and is responsible for fetching instructions to be executed from the instruction store. The instruction store is a high-speed memory that stores instructions and can quickly provide instructions to the microengine to reduce access delays to the main memory.

[0059] The decoding stage is used to parse the instructions fetched by the instruction fetch stage, and obtain the operand pointer and the packet pointer; wherein the packet pointer identifies the byte number of the packet data to be obtained; and the operand pointer identifies the address of the operand in the register file. The decoding stage is the second stage in the microengine pipeline, responsible for parsing the instructions fetched by the instruction fetch stage, and identifying information such as the operation type and the operand address.

[0060] The register file reading stage obtains the corresponding operand from the register file according to the operand pointer, obtains the corresponding packet data from the packet data register file according to the packet pointer, and transmits it to the execution stage. The register file reading stage is the third stage of the microengine pipeline. It should be noted that in this specification, the register file and the packet data register file are two independent memories. The register file is a high-speed memory for storing operands, and the packet data register file is a high-speed memory for storing packet data.

[0061] The register file reading level includes at least one packet data register file; the packet data register file can cache packet data. The packet data register file is a fast storage unit set for storing packet data to be processed. Since the processing of network data packets has extremely high speed requirements, the design goal of the packet data register file is to provide the fastest access speed to ensure that there is no delay in the data processing process due to waiting for data. The packet data register file is usually implemented by a fast static random access memory (SRAM), which has a dedicated read port and a write port, and can access different registers in multiple ways. Through such a design, the message pre-classification processor can quickly obtain the required operands and packet data at the execution level, thereby efficiently completing the data processing tasks required by various instructions. This high-speed cache mechanism greatly improves the overall performance of the processor, and simplifies and accelerates complex data processing processes.

[0062] The execution stage performs operations based on the operands and packet data obtained by the register file reading stage. The execution stage is the last stage of the microengine pipeline. At this stage, the microengine processes the data according to the requirements of the instruction, such as performing logical operations, fetching instructions, table lookups, termination, etc.

[0063] Figure 2 FIG. 1 is a schematic diagram of a processing flow of a message pre-classification processor according to an embodiment of the present invention. Figure 2 In the figure, "state machine" refers to the microengine state machine. The microengine state machine is used to control the working state of the microengine pipeline. The working state of the microengine state machine is as follows: Figure 3 As shown. The microengine state machine is in the idle state by default, indicating that it can receive messages. When the microengine is selected by the message scheduling logic outside the pre-classification processor, the microengine state machine detects that there is a message input, and it will jump from the default IDLE state to the running state. The microengine pipeline clock is turned on and the microengine pipeline starts running. The instruction fetch stage fetches instructions from the instruction storage (Instruction MEM) according to the instruction fetch information of the input message, and returns 128-bit data each time. Since each instruction is variable in length, the returned instruction entry is also not fixed. The instruction fetch stage selects the instruction that needs to be executed from the returned instruction data and outputs it to the decoding stage. The decoding stage parses the instruction to obtain the operand pointer and the packet pointer, and then the register file read stage obtains the operand from the register file according to the operand pointer, and obtains the corresponding packet data from the packet data register file according to the packet pointer, and then transmits the operand and packet data to the execution stage. At the execution stage, the operand and packet data are used as inputs of the arithmetic logic unit (ALU) to execute the instruction operation. Different types of instructions will produce different actions. If it is an operation logic instruction, the operation result is written back to the register file; if it is an instruction fetch instruction, the execution level returns the instruction fetch information to the instruction fetch level and continues to fetch instructions; if it is a table lookup instruction, the execution level will initiate an external table search; if it is a termination instruction, the execution level outputs an end signal, controls the micro-engine state machine to jump to the end (FINISHED) state, notifies the processor peripheral circuit to read the execution result, and waits until the result is taken away. The micro-engine state machine jumps back to the idle (IDLE) state, indicating that the next message can be received. It should be noted that the instruction types listed in this embodiment are not all the instruction types that can be processed by this embodiment, and all types that can be processed by the processor can be processed by this embodiment. The types listed in this embodiment are only used to enable those skilled in the art to better understand the present invention, and are not a limitation of this embodiment. Those skilled in the art can understand that any instruction that can be executed by the processor can be implemented by this embodiment and does not depart from the scope of protection of the present invention.

[0064] In some embodiments, when the processor starts to process a message, the packet data to be processed is stored in a packet cache; when a microengine is assigned to process a message, the packet data register file loads part of the data in the packet cache and provides it to the execution level. The packet cache is a fast-access storage area where data is pre-stored so that it can be quickly retrieved and used when needed. By caching data, access speed is accelerated and system performance is optimized. The microengine can process messages independently and read part of the data from the packet cache, thereby accelerating the processing speed. Through the independent processing of multiple microengines, the parallel processing efficiency of the processor can be improved.

[0065] In some embodiments, the packet data register file issues a packet data request, pauses the microengine pipeline, and after receiving the packet data, loads the packet data into the packet data register file. The packet data register file has the ability to self-sensing and automatically obtain packet data. When the microengine executes certain instructions, it needs to obtain specific packet data. When the packet data register file detects this situation, it will automatically issue a packet data request and pause the microengine pipeline. The packet data request includes the starting byte number, the number of bytes, the microengine identifier that issued the request, and the storage slice identifier of the packet data register file. After the packet cache receives the request, the packet data of the read request is returned to the microengine that initiated the request, and then loaded into the packet data register file of the microengine. The packet data register file provides the data required by the execution level, and resumes the operation of the microengine pipeline to complete the execution of the instructions that depend on the packet data.

[0066] Figure 4 FIG. 1 is a schematic diagram of the organization of a packet data register file in an embodiment of the present invention. Figure 4 As shown, the packet data register file includes multiple storage slices; each of the storage slices can independently initiate the reading and pre-fetching of packet data. The size and structure of each storage slice are exactly the same. The storage slices store different bytes of the packet data according to certain byte order rules. For example, if the packet data register file contains 4 storage slices, the first storage slice S0 stores packet data with byte order 0, 4, 8..., the second storage slice S1 stores packet data with byte order 1, 5, 9..., the third storage slice S2 stores packet data with byte order 2, 6, 10..., and the fourth storage slice S3 stores packet data with byte order 3, 7, 11... The byte order here can also be sorted in byte blocks composed of multiple bytes, and the byte order is consistent with the byte order in the packet cache. The size of each storage slice is fixed, and it can only store a number of bytes belonging to it, and the storage record will be maintained separately.

[0067] When an execution-level instruction requires package data, each storage slice will independently determine whether it needs to provide the data, and then determine whether it has already stored the data. If the storage slice finds that not all the required data is stored, it will independently initiate the reading of the package data. After the package data is returned, it will be stored in the corresponding storage slice according to the byte order rule.

[0068] In addition, each storage slice independently supports the prefetch mechanism in other embodiments. Prefetch enable refers to enabling a function that allows the processor to predict and load data from the packet cache to the register file read level in advance, so as to reduce the delay caused by waiting for data when the processor executes instructions, thereby improving the overall computing efficiency. If the current prefetch enable is turned on, the storage slice determines that the packet data in the prefetch window belongs to its own storage part and is not stored, the storage slice initiates data prefetch, and the data returned by the prefetch is loaded into the storage slice that initiated the prefetch. The prefetch of each storage slice is independent of each other. When outputting packet data, the data output by the packet data register file as a whole is aligned with the data required by the execution level through their respective shift and mask operations.

[0069] like Figure 4 As shown, the byte packet data input externally is stored in the packet data register file. This embodiment takes 48 bytes of packet data as an example. The packet data register file is divided into three storage slices, such as Figure 4 As shown, the first 16 bytes of the 48-byte packet data are loaded into the storage slice S0, and S0 updates the storage slice record number to 0. The second 16 bytes are loaded into the storage slice S1, and S1 updates the storage slice record number to 1. The third 16 bytes are loaded into the storage slice S2, and S2 updates the storage slice record number to 2. The subsequent data from the external packet cache is also stored in the order of S0, S1, S2, S0, S1... with 16 bytes as the granularity, so the record number of S0 is switched in the order of 0, 3, 6..., the record number of S1 is switched in the order of 1, 4, 7..., and the record number of S2 is switched in the order of 2, 5, 8... If the packet data required for instruction execution is in the packet data register file, the required packet data is selected from the three storage slices and transmitted to the execution level; if the packet data required for instruction execution is not in the packet data register file, the packet data register file outputs a stop signal, and the micro-engine pipeline is suspended through the micro-engine state machine. The storage slice that needs to store the packet data issues a packet data request. The requests of the three storage slices are arbitrated by the request scheduling. The authorized request can continue to participate in the scheduling between external micro-engines and finally reach the packet cache. After the data in the packet cache is returned to the packet data register file that initiated the request, the packet data required by the execution level is selected for output, and the stop signal is canceled to resume the operation of the micro-engine pipeline. The data output by each storage slice is processed by shift alignment, and the output data of the three storage slices are finally merged into the data required by the execution level.

[0070] Figure 5 This is a storage slice data flow diagram in an embodiment of the present invention. Figure 5 As shown in the figure, the structure of each storage slice is consistent, including modules such as input data selection and recording, data storage, output data selection, storage slice state machine, acquisition and pre-fetch detection. Figure 5 In the description, "state machine" means the storage slice state machine. The input data selection and recording module is used to receive the initial packet data and the packet data return, send the corresponding record to the storage slice state machine, and send the data to be stored to the data storage module; the data storage module is used to store the packet data; the output data selection module is used to select the data to be output from the data storage module for output; the storage slice state machine is used to control the operation state of the storage slice, including sending a packet data request, acquiring a new packet, receiving an acquisition or pre-fetch signal, receiving a data return signal, sending a data discard signal, sending a cancel stop signal, etc. The acquisition and pre-fetch detection module is used to acquire the packet pointer and control information, detect the stored data record, send an acquisition or pre-fetch signal, and send a stop pipeline signal.

[0071] This embodiment is explained by taking each storage slice processing 16 bytes of packet data as an example. The initial packet data selects 16 bytes for storage in the input data selection and recording module according to the storage rules described above, and records the position code of the 16 bytes in the whole packet. During the processing of the data packet, the packet pointer will be dynamically updated to the position of the next packet data to be processed. The control information is generated by instruction parsing and is used as the input of the storage slice, including the starting byte of the operation, the operation length, the prefetch enable and the prefetch window size. If the prefetch enable is turned on, each storage slice will determine whether the packet data in the prefetch window should be stored by itself based on the current packet pointer and the stored data record; if it should be stored but has not been obtained, the storage slice will initiate a packet data prefetch request, which includes the starting byte number, the number of bytes requested, the micro-engine mark and the storage slice mark. After multi-level scheduling, the authorized request obtains the required packet data from the packet cache and returns 16 bytes of data to the storage slice that initiated the request. Because it is a prefetch, the micro-engine pipeline stop signal will not be pulled up during the period from the initiation of the request to the return of the data, and the micro-engine pipeline continues to execute. When the subsequent instructions being executed need this part of the packet data, since this part of the packet data has been retrieved from the packet cache by the storage slice, it can be used directly. Finally, the output data selection module selects the correct data to output to the execution level based on the starting byte of the control information and the operation length. When the prefetch instruction needs to be canceled after it is issued, a cancel prefetch request is issued; if the cancel prefetch request is unsuccessful, the packet data returned according to the prefetch instruction is discarded. Figure 5The packet data request in the process includes a packet data pre-fetch request and a packet data acquisition request. The uninterrupted operation of the micro-engine in this process improves the overall performance of the processor.

[0072] Figure 6 FIG. 1 is a state transition diagram of a storage slice state machine in an embodiment of the present invention. Figure 6 As shown, the storage slice state machine is in the READY state by default, indicating that the storage unit has the packet data required for instruction execution. When the packet acquisition and prefetch module detects that the packet data to be stored has not been acquired, it notifies the storage slice state machine to switch to the REQUESTING state and initiates a data acquisition request. At the same time, the packet acquisition and prefetch detection module sends a micro-engine pipeline stop signal; when the issued data acquisition request obtains the scheduling authorization between storage slices, the storage slice state machine jumps from the REQUESTING state to the WAITING DATA state. When the packet data is finally retrieved from the packet cache and loaded into the storage unit, the storage slice state machine jumps back to the READY state and notifies the acquisition and prefetch module to cancel the stop signal. When the prefetch enable of the control information is turned on, the acquisition and prefetch detection module determines whether there is data that it needs to store based on the current storage data record, packet pointer and prefetch window. If there is but it has not been acquired, it only sends a prefetch command to the storage slice state machine, and does not issue a micro-engine pipeline stop signal. After receiving the prefetch command, the storage slice state machine jumps to the REQUESTING state and initiates a data fetch request. When the request obtains the scheduling authorization between storage slices, the storage slice state machine jumps from the REQUESTING state to the WAITING DATA state. When the packet data is finally retrieved from the packet cache and loaded into the storage unit, the storage slice state machine jumps back to the READY state.

[0073] Since prefetching is based on the current instruction execution site and stored data, it predicts the packet data required for subsequent instructions and obtains it in advance. Therefore, it is inevitable that the retrieved data may not be actually used by subsequent instructions. For these situations, the storage slice state machine can make a correct response. For example, when the storage slice state machine is in the REQUESTING state, the processing of the current packet has been terminated, and a new packet has entered. The storage slice state machine jumps to the REQUESTING BUT TERMINATED state and cancels the prefetch request. If the prefetch data request has not been authorized at this time, the storage slice state machine continues to jump back to the READY state. If the prefetch data request has been authorized at this time, it means that the cancellation of the prefetch request is unsuccessful, and the storage slice state machine jumps to the DISCARDING state. After the prefetched data is returned, the storage slice state machine controls the input data selection module to discard the data and jump back to the READY state to start responding to the processing requirements of the new packet; when the storage slice state machine is in the REQUESTING state, a new packet enters and the prefetch data request is authorized, and the storage slice state machine directly jumps to the DISCARDING state; when the storage slice state machine is in the WAITING state, the storage slice state machine directly jumps to the DISCARDING state. When a new packet enters the DATA state and the packet data has not been returned from the packet cache, the storage slice state machine also jumps to the DISCARDING state. After the data is returned, the storage slice state machine controls the input data selection module to discard the data and jump back to the READY state.

[0074] In some embodiments, if the packet data in the pre-fetch window is not in the packet data register file, the packet data register file initiates pre-fetching and stores the packet data in the packet data register file. When the micro-engine needs to process the packet data, it first checks whether the packet data is already in the packet data register file. This process is crucial to improving the efficiency and response speed of the micro-engine in processing packet data. Through the pre-fetch mechanism, the time waiting for data loading can be reduced, thereby speeding up the overall processing speed.

[0075] In some embodiments, when the packet data register file initiates prefetching, the microengine pipeline is not paused. The packet data register file supports prefetching of packet data. When the prefetching enable is turned on, the packet data register file determines whether to initiate prefetching based on the packet pointer and the prefetching window. The packet data register file maintains a record of the currently stored data. If the packet data in the prefetching window is not in the packet data register file, the packet data register file initiates prefetching, and the microengine pipeline will not be paused. When the packet data read from the packet cache is returned, the packet data register file will store all the packet data in the prefetching window, and the packet data required by the execution-level instruction can be found in the packet data register file, and the microengine will not stop running due to obtaining packet data from the external packet cache.

[0076] In some embodiments, the microengine supports prefetch control instructions to dynamically modify the prefetch configuration. The configuration information includes prefetch enable and prefetch window size. The execution of these instructions can change the prefetch enable and prefetch window size. For example, after a certain instruction is executed, the packet pointer changes, which would cause packet data prefetching, but because the prefetch enable bit in the instruction is not turned on, the execution of the instruction does not trigger prefetching. The size of the prefetch enable bit is 1 bit.

[0077] For prefetching of packet data that is not required by subsequent instructions, in addition to the correct response of the storage slice state machine to avoid errors, it also supports dynamic control of prefetch operations through instructions to reduce redundant packet cache access. OPCODE, the full name of which is Operation Code, is also called instruction code or machine code, which is used to specify the operation performed by the computer. Figure 7 As shown, this is an instruction to perform a cyclic redundancy check (CRC) on the 16-bit packet data of the instruction. The execution of this instruction will cause the value of the packet pointer register to change, and the control information of the packet data file register storage slice will be updated with the prefetch enable and prefetch window size carried by the instruction. If the prefetch enable is turned on, the storage slice will use the updated prefetch window and packet pointer to decide whether to initiate packet prefetch. A larger prefetch window will make prefetch more active. In some scenarios where data packets are not used continuously, the prefetch window can be appropriately reduced to reduce invalid prefetching; if the prefetch enable is turned off, no prefetching will occur directly. If the data packet needs to be used continuously, use the prefetch control instruction to configure a larger prefetch window; if the data packet does not need to be used continuously, use the prefetch control instruction to configure a smaller prefetch window. When developing business microcode, programmers can flexibly adjust the microcode according to the business characteristics, while improving the overall performance of the microengine through packet data prefetching, reducing the probability of invalid prefetching and saving power consumption.

[0078] Figure 8 FIG. 1 is a flow chart of the steps of a message pre-classification method in an embodiment of the present invention. Figure 8 As shown, a message pre-classification method in an embodiment of the present invention includes:

[0079] Step S1: fetch instructions from the instruction storage.

[0080] In this step, the instructions are usually stored in the instruction storage in a certain order (such as the order specified by the program counter) and are ready to be executed. The present embodiment first determines the storage location of the next instruction to be executed. The binary representation of the instruction is read from this location.

[0081] Step S2: Parse the instruction to obtain an operand pointer and a packet pointer.

[0082] In this step, the packet pointer identifies the byte number of the packet data to be obtained; the operand pointer identifies the address of the operand. After obtaining the instruction, the binary format of the decoded instruction is used to identify the type of instruction, the required operands (if any), and any special flags or parameters. In this step, it is particularly important to parse the operand pointer and the packet pointer. When identifying the operand pointer, the field in the instruction that specifies the location of the operand is identified. This field may be a direct address, an offset, or some form of index. The packet pointer indicates which packet or data structure the data needs to be extracted from.

[0083] Step S3: acquiring a corresponding operand according to the operand pointer, and acquiring corresponding packet data from the packet data register file according to the packet pointer.

[0084] In this step, the packet data register file is capable of caching packet data. Using the operand pointer, the value of the operand is retrieved from the register file. The operand may be any type of data, such as an integer, a floating point number, a string, or a more complex data structure. Using the packet pointer, the specified packet data is retrieved from the packet data register file. This usually involves parsing the data packet to find and extract the required specific fields or data blocks. The packet data register file in this step has functions such as automatic acquisition and pre-fetching. The packet data register file in this step is the same as that in the previous embodiment and will not be repeated here.

[0085] Step S4: Execute an operation according to the acquired operand and the packet data.

[0086] In this step, the operands and packet data obtained from the operand pointer and packet pointer parsed from the instruction are used to perform the actual operation. Depending on the type of instruction, the corresponding operation is performed. This may include arithmetic operations (such as addition, subtraction, multiplication, and division), logical operations (such as AND, OR, and NOT), comparison operations, data movement, control flow operations (such as jumps, conditional branches), etc. During execution, the operands and packet data obtained in step S3 are used as input.

[0087] This embodiment saves instruction space for accessing packet data storage and shortens memory access latency by automatically acquiring and prefetching packet data. By dynamically controlling prefetching through microinstructions, the performance of the microengine is improved while reducing the probability of invalid prefetching and controlling power consumption.

[0088] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. The above description of the disclosed embodiments enables professionals and technicians in this field to implement or use the present invention. Various modifications to these embodiments will be obvious to professionals and technicians in this field, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in this article, but will comply with the widest range consistent with the principles and novel features disclosed herein.

[0089] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A message pre-classification processor, characterized in that: include: Multiple micro-engines; Each of the microengines includes a microengine pipeline; The microengine pipeline includes an instruction fetch stage, a decode stage, a register file read stage, and an execute stage; Wherein, the instruction fetch stage is used to fetch instructions from the instruction storage; The decoding stage is used to parse the instruction fetched by the instruction fetch stage, and obtain an operand pointer and a packet pointer; wherein the packet pointer identifies the byte number of the packet data to be obtained; and the operand pointer identifies the address of the operand in the register file; The register file reading stage obtains the corresponding operand from the register file according to the operand pointer, obtains the corresponding packet data from the packet data register file according to the packet pointer, and transmits the packet data to the execution stage; the register file reading stage includes at least one packet data register file; the packet data register file can cache packet data; the packet data register file issues a packet data request, suspends the microengine pipeline, and after receiving the packet data, loads the packet data into the packet data register file, and the register file provides the packet data to the execution stage, and resumes the microengine pipeline; The execution stage performs operations according to operands and packet data obtained by the register file read stage.

2. A message pre-classification processor according to claim 1, characterized in that: When a micro-engine is assigned to process a message, the packet data register file loads part of the data in the packet cache and provides it to the execution stage.

3. A message pre-classification processor according to claim 1, characterized in that: If the packet data within the pre-fetch window is not in the packet data register file, the packet data register file initiates pre-fetching and stores the packet data in the packet data register file.

4. A message pre-classification processor according to claim 3, characterized in that: When the packet data register file initiates prefetching, the microengine pipeline is not paused.

5. A message pre-classification processor according to claim 3, characterized in that: When a prefetch instruction needs to be canceled after being issued, a cancel prefetch request is issued; if the cancel prefetch request is unsuccessful, the packet data returned according to the prefetch instruction is discarded.

6. A message pre-classification processor according to claim 1, characterized in that: The packet data register file includes a plurality of storage slices; each of the storage slices can independently initiate reading and pre-fetching of packet data.

7. A message pre-classification processor according to claim 6, characterized in that: The storage slice includes: an input data selection and recording module, a data storage module, an output data selection module, a storage slice state machine, and an acquisition and pre-fetch detection module; The input data selection and recording module is used to receive initial packet data and packet data return, send corresponding records to the storage slice state machine, and send the data to be stored to the data storage module; The data storage module is used to store package data; The output data selection module is used to select the data to be output from the data storage module for output; The storage slice state machine is used to control the operation state of the storage slice; The acquisition and pre-fetch detection module is used to acquire packet pointers and control information, detect stored data records, send acquisition or pre-fetch signals, and send pipeline stop signals.

8. The message pre-classification processor according to claim 1, characterized in that: The microengine supports prefetch control instructions to dynamically modify the prefetch configuration.

9. A message pre-classification processor according to claim 8, characterized in that: If the data packet needs to be used continuously, the pre-fetch control instruction is used to configure a larger pre-fetch window; if the data packet does not need to be used continuously, the pre-fetch control instruction is used to configure a smaller pre-fetch window.

10. The message pre-classification processor according to claim 1, characterized in that: Each of the microengines also includes a microengine state machine; The micro-engine state machine is used to control the working state of the micro-engine pipeline to switch between idle, running and end; When the microengine state machine is idle, it indicates that the microengine pipeline can receive messages; When the micro-engine state machine is in operation, it indicates that the micro-engine pipeline is running; When the micro-engine state machine is at the end, it indicates that the micro-engine pipeline is waiting for the execution result to be taken away.

11. A message pre-classification method, characterized in that: Applicable to the message pre-classification processor of claim 1; the message pre-classification method comprises: Step S1: fetching instructions from instruction storage; Step S2: parsing the instruction to obtain an operand pointer and a packet pointer; wherein the packet pointer identifies the byte number of the packet data to be obtained; and the operand pointer identifies the address of the operand; Step S3: acquiring a corresponding operand according to the operand pointer, and acquiring corresponding packet data from the packet data register file according to the packet pointer; wherein the packet data register file can cache packet data; Step S4: Execute an operation according to the acquired operand and the packet data.

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